Semiconductor equipment

Abstract

This invention provides a highly reliable semiconductor device by suppressing unintended leakage of adhesive used in stacking multiple semiconductor chips. [Solution] The semiconductor device according to this embodiment includes a wiring board having a recess on its first surface. A first semiconductor chip is placed on the bottom surface of the recess. A first insulating material fills the recess and is provided around the first semiconductor chip. At least one second semiconductor chip is stacked on top of the first semiconductor chip.

Description

Technical Field

[0001] This embodiment relates to a semiconductor device.

Background Art

[0002] In semiconductor devices such as NAND-type flash memories, a plurality of semiconductor chips may be stacked on the same wiring substrate from the viewpoints of miniaturization and high speed. In this case, the plurality of semiconductor chips are adhered by a DAF (Die Attach Film) provided therebetween, and a FOD (Film Over Die) structure in which they are stacked is known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Summary of the Invention

Problems to be Solved by the Invention

[0004] To provide a highly reliable semiconductor device by suppressing the unintentional protrusion of an adhesive used for stacking a plurality of semiconductor chips.

Means for Solving the Problems

[0005] The semiconductor device according to this embodiment includes a wiring substrate having a recess on a first surface. The first semiconductor chip is disposed on the bottom surface of the recess. The first insulating material fills the recess and is provided around the first semiconductor chip. At least one second semiconductor chip is stacked above the first semiconductor chip. [Brief explanation of the drawing]

[0006] [Figure 1] A plan view showing an example of the configuration of a semiconductor device according to the first embodiment. [Figure 2] A cross-sectional view showing an example of the configuration of a semiconductor device according to the first embodiment. [Figure 3] A cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 4] A cross-sectional view showing an example of a semiconductor device manufacturing method, following Figure 3. [Figure 5] A cross-sectional view showing an example of a semiconductor device manufacturing method, following Figure 4. [Figure 6] A cross-sectional view showing an example of a semiconductor device manufacturing method, following Figure 5. [Figure 7] A plan view showing an example of the configuration of a semiconductor device according to the second embodiment. [Figure 8] A cross-sectional view showing an example of the configuration of a semiconductor device according to the second embodiment. [Figure 9] A cross-sectional view showing an example of the configuration of a semiconductor device according to the second embodiment. [Figure 10] A cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the second embodiment. [Figure 11] A cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the second embodiment. [Figure 12] A plan view showing an example configuration of a semiconductor device according to the third embodiment. [Figure 13] A cross-sectional view showing an example configuration of a semiconductor device according to the third embodiment. [Figure 14] A cross-sectional view showing an example of a method for manufacturing a semiconductor device package according to the third embodiment. [Figure 15] A cross-sectional view showing an example of a semiconductor device manufacturing method, following Figure 14. [Figure 16] Figure 15 is followed by a cross-sectional view showing an example of a semiconductor device manufacturing method. [Figure 17] A cross-sectional view showing an example of a semiconductor device manufacturing method, following Figure 16.

Best Mode for Carrying Out the Invention

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. This embodiment does not limit the present invention. The drawings are schematic or conceptual. In the specification and the drawings, the same elements are denoted by the same reference numerals.

[0008] (First Embodiment) FIG. 1 is a plan view showing a configuration example of a semiconductor device 1 according to the first embodiment. FIG. 2 is a cross-sectional view showing a configuration example of the semiconductor device 1 according to the first embodiment.

[0009] As shown in FIG. 2, the semiconductor device 1 according to this embodiment is a semiconductor package including a wiring substrate SUB1, semiconductor chips CH1 to CH3, insulating materials D1 to D3, bonding wires BW, and a sealing resin MR.

[0010] The wiring substrate SUB1 includes a resin material 10, solder resists 11a and 11b, wirings 12, and electrode pads 13a and 13b. The wiring substrate SUB1 is a substrate including a wiring layer formed of the wirings 12. The wiring substrate SUB1 electrically connects between the semiconductor chips CH1 to CH3 via the wirings 12, or electrically connects the semiconductor chips CH1 to CH3 and the outside. The wiring substrate SUB1 has a first surface F1 and a second surface F2 on the opposite side of the first surface F1.

[0011] The resin material 10 is, for example, a glass epoxy resin. The resin material 10 is provided around the wirings 12 and electrically separates between the wirings 12.

[0012] The solder resist 11a is provided on the first surface F1 side of the wiring substrate SUB1. The solder resist 11a exposes a part of the surface of the electrode pad 13a.

[0013] The solder resist 11b is provided on the second surface F2 side of the wiring substrate SUB1. The solder resist 11b exposes a part of the surface of the electrode pad 13b.

[0014] The wiring 12 is provided within the resin material 10 or within the solder resist 11a, 11b. The wiring 12 includes, for example, a metallic material such as copper, tungsten, or aluminum.

[0015] The electrode pad 13a, which serves as the second electrode, is provided on the first side F1 of the wiring board SUB1 and is exposed from the solder resist 11a. The electrode pad 13a functions as a bonding pad for connecting the bonding wire BW. A portion of the electrode pad 13a is also provided at the bottom of the recess CAV.

[0016] The electrode pad 13b is located on the second side F2 of the wiring board SUB1 and is exposed from the solder resist 11b. The electrode pad 13b functions as a pad or bump for electrical connection to an external device.

[0017] The wiring board SUB1 has a recess CAV on the first surface F1 side. The recess CAV is sized to accommodate a semiconductor chip CH1 and is filled with insulating material D2. The recess CAV extends to the resin material 10 and is formed by recessing the resin material 10. An electrode pad 13a is provided on the bottom surface of the recess CAV. The semiconductor chip CH1 is also positioned on the bottom surface of the recess CAV.

[0018] The depth of the recess CAV is greater than the thickness of the semiconductor chip CH1. Furthermore, in a plan view from the first surface F1 (viewed from the Z direction), as shown in Figure 1, the outer edge of the opening OP1 of the recess CAV is outside the outer edge of the semiconductor chip CH1. This allows the semiconductor chip CH1 to be housed within the recess CAV and positioned on the bottom surface of the recess CAV.

[0019] As shown in Figure 1, the recess CAV is located approximately in the center of the wiring board SUB1 in a plan view from the Z direction. However, the planar position of the recess CAV relative to the wiring board SUB1 is arbitrary and may be off-center in the X and / or Y directions.

[0020] The semiconductor chip CH1 is bonded to the bottom surface of the recess CAV by an insulating material D1. The semiconductor chip CH1 is a controller chip that controls semiconductor chips CH2 and CH3, which are memory chips, for example. The semiconductor chip CH1 is electrically connected to an electrode pad 13a provided on the bottom surface of the recess CAV via a bonding wire BW. The semiconductor chip CH1 is an example of a first semiconductor chip. The semiconductor chips CH2 and CH3 are examples of second semiconductor chips.

[0021] The thickness of the semiconductor chip CH1 is less than the depth of the recess CAV. Also, the outer edge of the semiconductor chip CH1 is smaller than the outer edge of the opening OP1 of the recess CAV. Therefore, as described above, the semiconductor chip CH1 can be housed within the recess CAV.

[0022] The insulating material D1 is pre-attached to the back surface of the semiconductor chip CH1. In the die bonding process, the insulating material D1 is placed together with the semiconductor chip CH1 at the bottom surface of the recess CAV and cured. This causes the insulating material D1 to bond the semiconductor chip CH1 to the bottom surface of the recess CAV.

[0023] The insulating material D2 fills the recess CAV and is provided around the semiconductor chip CH1. This protects the semiconductor chip CH1 and the bonding wire BW. Furthermore, the thickness of the insulating material D2 after curing is approximately equal to the depth of the recess CAV. As a result, the surface of the semiconductor chip CH2, which is placed on the insulating material D2, is positioned above (+Z direction) the first surface F1.

[0024] The insulating material D2 is pre-attached to the back surface of the semiconductor chip CH2. During the die bonding process, the insulating material D2 is positioned together with the semiconductor chip CH2 to cover the semiconductor chip CH1 in the recess CAV, and then cured. This allows the insulating material D2 to cover the semiconductor chip CH1 and the bonding wire BW, and to bond the semiconductor chip CH2 to the top of the semiconductor chip CH1. The insulating material D2 can also fill the inside of the recess CAV. In a plan view from the Z direction, the insulating material D2 is approximately the same size as the back surface of the semiconductor chip CH2 before curing, but after curing it is approximately the same size as the opening OP1 of the recess CAV. The volume of the insulating material D2 is approximately the same as the volume of the recess CAV.

[0025] The semiconductor chip CH2 is provided on an insulating material D2 and is stacked above the semiconductor chip CH1. The semiconductor chip CH2 is a memory chip, for example, that includes a memory cell array of a NAND flash memory. The semiconductor chip CH2 is electrically connected to an electrode pad 13a provided on the first surface F1 of the wiring board SUB1 via bonding wires BW.

[0026] The outer edge of the semiconductor chip CH2 is somewhat smaller than the outer edge of the opening OP1 of the recess CAV. That is, in a plan view from the Z direction, the outer edge of the opening OP1 of the recess CAV is outside the outer edge of the semiconductor chip CH2. Therefore, as described above, the uncured insulating material D2 attached to the semiconductor chip CH2 can be contained within the recess CAV. It is preferable that the sum of the volumes of the semiconductor chip CH1, the insulating material D1, the bonding wire BW connected to the semiconductor chip CH1, and the insulating material D2 is equal to the volume of the recess CAV. For this reason, the thickness of the uncured insulating material D2 attached to the semiconductor chip CH2 is slightly thicker than the depth of the recess CAV. This makes it possible to make the volume of the insulating material D2 approximately the same as the volume of the recess CAV, and to fill the inside of the recess CAV with the insulating material D2.

[0027] The semiconductor chip CH3 is bonded to the surface of the semiconductor chip CH2 by an insulating material D3. The semiconductor chip CH3, like the semiconductor chip CH2, is, for example, a memory chip for NAND flash memory. The semiconductor chip CH3 is electrically connected to an electrode pad 13a provided on the first surface F1 of the wiring board SUB1 via bonding wires BW.

[0028] The semiconductor chip CH3 is stacked above the semiconductor chip CH1, offset so that the electrode pads of the semiconductor chip CH2 are exposed. This allows the semiconductor chip CH3 and the electrode pad 13a to be connected by a bonding wire BW. Further semiconductor chips (not shown) may be stacked on top of the semiconductor chip CH3.

[0029] The insulating material D3 is pre-attached to the back surface of the semiconductor chip CH3. During the die bonding process, the insulating material D3 is placed on the semiconductor chip CH2 together with the semiconductor chip CH3 and cured. This causes the insulating material D3 to bond the semiconductor chip CH3 to the semiconductor chip CH2.

[0030] The encapsulating resin MR is provided on the first surface F1 of the wiring board SUB1 and covers the semiconductor chips CH2, CH3 and bonding wires BW. This allows the encapsulating resin MR to protect the semiconductor chips CH2, CH3 and bonding wires BW.

[0031] The insulating materials D1 to D3 are, for example, insulating adhesives such as DAF. In this embodiment, insulating material D2 embeds the semiconductor chip CH1. That is, the thickness of insulating material D2 is greater than the thickness of insulating materials D1 and D3.

[0032] In the comparative example of the FOD structure, the DAF attached to the back surface of the lower semiconductor chip sometimes crawled up from the back surface to the side surface during curing. In this case, the upper semiconductor chip stacked on top of the lower semiconductor chip may unintentionally be lifted by the DAF, or the bonding wires may come into contact with the DAF. Furthermore, the DAF sometimes protruded in the planar direction of the wiring board and reached the electrode pads on the wiring board. This can reduce the reliability of the semiconductor device.

[0033] In contrast, according to this embodiment, a recess CAV is provided in the wiring board SUB1, and a semiconductor chip CH1 is placed inside the recess CAV. The insulating material D2 covers the semiconductor chip CH1 and fills the inside of the recess CAV. Since the insulating material D2 has approximately the same volume as the recess CAV, it does not bleed out of the recess CAV during die bonding and prevents it from creeping up the side of the semiconductor chip CH2 to the surface. Therefore, it is possible to prevent the semiconductor chip CH3 from unintentionally lifting off the surface of the semiconductor chip CH2, and to prevent the insulating material D2 from unintentionally coming into contact with the bonding wire BW.

[0034] Furthermore, filling the recessed CAV with insulating material D2 eliminates any gaps. This prevents cracks caused by moisture entering the gaps, thereby improving the reliability of the semiconductor device.

[0035] Next, a method for manufacturing the semiconductor device 1 according to the first embodiment will be described.

[0036] Figures 3 to 6 are cross-sectional views showing an example of a method for manufacturing a semiconductor device 1 according to the first embodiment.

[0037] As shown in Figure 3, a wiring board SUB1 having a recess CAV on the first surface F1 is created. The thickness of the wiring board SUB1 in the Z direction is, for example, about 195 μm in the area other than the recess CAV, and for example, about 90 μm in the area of ​​the recess CAV. Therefore, the depth of the recess CAV is, for example, about 105 μm.

[0038] Next, as shown in Figure 4, the semiconductor chip CH1 and insulating material D1 are placed on the bottom surface of the recess CAV. The insulating material D1 is pre-attached to the back surface of the semiconductor chip CH1. Therefore, by curing the insulating material D1, the insulating material D1 adheres the semiconductor chip CH1 to the bottom surface of the recess CAV. Next, the electrode pads of the semiconductor chip CH1 and the electrode pads 13a on the bottom surface of the recess CAV are connected with bonding wires BW.

[0039] Next, as shown in Figure 5, the semiconductor chip CH2 and insulating material D2 are positioned to cover the semiconductor chip CH1 in the recess CAV. The insulating material D2 is pre-attached to the back surface of the semiconductor chip CH2. Therefore, by curing the insulating material D2, the insulating material D2 adheres the semiconductor chip CH1 and semiconductor chip CH2 in the recess CAV. The insulating material D2 also fills the recess CAV and supports the back surface of the semiconductor chip CH2 at approximately the same height level as the solder resist 11a on the first surface F1. Next, the electrode pads of the semiconductor chip CH2 and the electrode pads 13a on the first surface F1 are connected with bonding wires BW.

[0040] Next, as shown in Figure 6, the semiconductor chip CH3 and insulating material D3 are placed on the semiconductor chip CH2. The insulating material D3 is pre-attached to the back surface of the semiconductor chip CH3. Therefore, by curing the insulating material D3, the insulating material D3 adheres to the semiconductor chip CH2 and the semiconductor chip CH3. Next, the electrode pads of the semiconductor chip CH3 and the electrode pads of the semiconductor chip CH2 are connected with bonding wire BW.

[0041] Next, if necessary, other semiconductor chips are stacked on semiconductor chip CH3 and wire bonding is performed. Then, a sealing resin MR is formed on the first surface F1 to cover the semiconductor chip stack and bonding wire BW. Note that, for efficiency, the bonding process for the bonding wire BW may be performed all at once after all semiconductor chips have been stacked.

[0042] This completes the semiconductor device 1 according to the first embodiment shown in Figure 2.

[0043] According to this embodiment, the insulating material D2 covers the semiconductor chip CH1 and fills the recess CAV. Since the insulating material D2 has approximately the same volume as the recess CAV, bleeding from the recess CAV during curing can be suppressed. Therefore, the insulating material D2 does not creep up to the surface of the semiconductor chip CH2, and the semiconductor chip CH3 does not lift off the surface of the semiconductor chip CH2. Furthermore, bleeding of the insulating material D2 to the electrode pad 13a on the first surface F1 can also be suppressed.

[0044] (Second Embodiment) Figure 7 is a plan view showing an example configuration of the semiconductor device 1 according to the second embodiment. Figures 8 and 9 are cross-sectional views showing an example configuration of the semiconductor device 1 according to the second embodiment. Figure 8 shows a cross-section along line AA in Figure 7. Figure 9 shows a cross-section along line BB in Figure 7.

[0045] As shown in Figure 7, the second embodiment differs from the first embodiment in that, in a plan view from the Z direction, the planar shape of the opening OP1 of the recessed CAV is different. Furthermore, the second embodiment differs from the first embodiment in that the material filled in the recessed CAV is a sealing resin MR.

[0046] The planar shape of the opening OP1 is a roughly rectangular opening OP5, with four protrusions OP10 projecting in the ±X and ±Y directions from each side. In a plan view from the Z direction, the outer edge of the opening OP5 is significantly further outward than the outer edge of the semiconductor chip CH1, but smaller inward than the outer edge of the semiconductor chip CH2.

[0047] On the other hand, the protruding portion OP10 extends outward beyond the outer edge of the semiconductor chip CH2. Therefore, as shown in Figure 8, in the cross-section AA of the region of the protruding portion OP10, there is a gap GP between the semiconductor chip CH2 and the wiring substrate SUB1. The sealing resin MR enters the recess CAV from the gap GP and fills the recess CAV.

[0048] In a plan view from the Z direction, the protrusions OP10 protrude almost uniformly from each side of the opening OP5. Furthermore, each protrusion OP10 has approximately the same width and length. This allows the sealing resin MR to enter and fill the recess CAV almost uniformly.

[0049] The outer edge of the opening OP5 is smaller and located inward than the outer edge of the semiconductor chip CH2. Therefore, as shown in Figure 9, in the BB cross-section of the region of the opening OP5, the semiconductor chip CH2 is bonded to the solder resist 11a of the wiring substrate SUB1 by the insulating material D2.

[0050] Thus, in the second embodiment, the planar shape of the opening OP1 of the recess CAV has a protruding portion OP10, and as shown in Figure 8, a gap GP is created between the semiconductor chip CH2 and the wiring substrate SUB1. As a result, after stacking semiconductor chips CH2 and CH3 on top of semiconductor chip CH1, the sealing resin MR can be filled into the space formed between semiconductor chip CH2 and the recess CAV through the gap GP. The sealing resin MR is also provided on the semiconductor chips CH2 and CH3 and is formed on the first surface F1. Therefore, the sealing resin MR fills the inside of the recess CAV and covers the periphery of the semiconductor chips CH2 and CH3 and the bonding wire BW. The sealing resin MR is integrally formed from inside the recess CAV to the top of the semiconductor chips CH2 and CH3 and is continuous in the gap GP.

[0051] In the second embodiment, the insulating material D2 may have the same thickness as the insulating materials D1 and D3. Therefore, the insulating material D2 cannot fill the recessed CAV. However, by providing the protruding portion OP10, the sealing resin MR can enter the recessed CAV from the gap GP and fill the recessed CAV.

[0052] Furthermore, since the opening OP5 is smaller than the outer edge of the semiconductor chip CH2, the wiring substrate SUB1 can support the semiconductor chips CH2 and CH3, as shown in Figure 9.

[0053] The other components of the second embodiment may be the same as those of the first embodiment. Therefore, the second embodiment can obtain the same effects as the first embodiment.

[0054] Next, a method for manufacturing the semiconductor device 1 according to the second embodiment will be described.

[0055] Figures 10 and 11 are cross-sectional views showing an example of a method for manufacturing a semiconductor device 1 according to the second embodiment. Figure 10 corresponds to a cross-section along line AA. Figure 11 corresponds to a cross-section along line BB.

[0056] The process is described with reference to Figures 3 and 4. Although the planar shape of the recessed CAV is different, the cross-section at this time can be the same as the cross-section shown in Figures 3 and 4.

[0057] Next, as shown in Figures 10 and 11, the semiconductor chip CH2 is laminated on the wiring board SUB1. An insulating material D2 is pre-attached to the back surface of the semiconductor chip CH2. The thickness of the insulating material D2 is thinner than that of the first embodiment and can be the same thickness as the insulating materials D1 and D3. By curing the insulating material D2, the insulating material D2 adheres the semiconductor chip CH2 to the solder resist 11a of the wiring board SUB1.

[0058] Here, as shown in Figure 10, a gap GP is generated between the semiconductor chip CH2 and the wiring substrate SUB1 in the region of the protruding portion OP10. Also, as shown in Figure 11, in the region of the opening portion OP5, the semiconductor chip CH2 is bonded to the solder resist 11a of the wiring substrate SUB1 by the insulating material D2. A space SP is formed between the semiconductor chip CH2 and the wiring substrate SUB1.

[0059] Next, a bonding wire BW is used to connect the electrode pad of the semiconductor chip CH2 to the electrode pad 13a on the first surface F1.

[0060] Next, as shown in Figures 8 and 9, the semiconductor chip CH3 and insulating material D3 are placed on the semiconductor chip CH2. The insulating material D3 is pre-attached to the back surface of the semiconductor chip CH3. Therefore, by curing the insulating material D3, the insulating material D3 adheres to the semiconductor chip CH2 and the semiconductor chip CH3. Next, the electrode pads of the semiconductor chip CH3 and the electrode pads of the semiconductor chip CH2 are connected with bonding wire BW.

[0061] Next, if necessary, other semiconductor chips are stacked on semiconductor chip CH3 and wire bonding is performed. Note that, for efficiency, the bonding wire BW process may be performed all at once after all semiconductor chips have been stacked.

[0062] Next, a sealing resin MR is formed on the first surface F1 to cover the semiconductor chip stack and bonding wires BW. At this time, the sealing resin MR also fills the space SP through the gap GP. This results in the structure shown in Figures 8 and 9.

[0063] According to the second embodiment, the sealing resin MR fills the recessed CAV and coats the semiconductor chips CH2 and CH3. Therefore, the sealing resin MR is integrally formed in the recessed CAV and on the semiconductor chips CH2 and CH3. This allows the insulating material D2 to be the same type as the insulating materials D1 and D3, leading to cost reduction.

[0064] Other manufacturing steps in the second embodiment may be the same as those in the first embodiment. Therefore, the second embodiment can obtain the same effects as the first embodiment.

[0065] (Third embodiment) Figure 12 is a plan view showing an example configuration of the semiconductor device 1 according to the third embodiment. Figure 13 is a cross-sectional view showing an example configuration of the semiconductor device 1 according to the third embodiment.

[0066] As shown in Figure 12, in the third embodiment, in a plan view from the Z direction, the outer edge of the opening OP1 of the recess CAV is smaller and inward than the outer edge of the semiconductor chip CH2. Therefore, the semiconductor chip CH2 is provided so as to cover the opening OP1 of the recess CAV, and is also provided on the wiring board SUB1.

[0067] Furthermore, as shown in Figure 13, in the third embodiment, a plurality of metal bumps BMP as first electrodes are provided on the back surface of the semiconductor chip CH1 facing the bottom surface of the recess CAV. The wiring board SUB1 has a plurality of second electrodes 14 corresponding to the metal bumps BMP on the bottom surface of the recess CAV. As a result, the plurality of metal bumps BMP are connected to the plurality of second electrodes 14 during die bonding. That is, the semiconductor chip CH1 is flip-chip bonded to the plurality of second electrodes 14 of the wiring board SUB1. This eliminates the need to connect bonding wires BW between the semiconductor chip CH1 and the wiring board SUB1.

[0068] Material A1 is provided around the metal bump BMP and the second electrode 14. Material A1 is, for example, an anisotropic conductive film (ACF) in which conductive particles are dispersed in a thermosetting resin. Material A1 is conductive in the direction in which the semiconductor chip CH1 is bonded (Z direction) and insulating in the X and Y directions. That is, during the thermocompression bonding when the semiconductor chip CH1 is bonded to the bottom surface of the recess CAV, the conductive particles contained in material A1 come into contact with the metal bump BMP and the second electrode 14, and a conductive path is formed between the metal bump BMP and the second electrode 14. On the other hand, between adjacent metal bump BMPs or between adjacent second electrodes 14, the conductive particles remain dispersed in the thermosetting resin, thus maintaining insulation. This ensures electrical connection between the corresponding metal bump BMP and the second electrode 14, and maintains electrical insulation between adjacent metal bump BMPs or between adjacent second electrodes 14.

[0069] Furthermore, the semiconductor chip CH1 has a thickness such that when die-bonded into the recess CAV, its surface is at approximately the same height level as the first surface F1 of the wiring board SUB1. That is, it is preferable that the surface of the semiconductor chip CH1 is approximately flush with the first surface F1. This eliminates the need to fill the recess CAV with insulating material D2. The insulating material D2 may have the same thickness as insulating material D3.

[0070] An insulating material P1 is provided between the side surface of the semiconductor chip CH1 and the inner wall of the recess CAV. The insulating material P1 is, for example, a potting resin used to fill gaps. The potting resin is usually in a liquid state and solidifies through heat treatment or ultraviolet treatment. The potting resin used has a relatively low coefficient of thermal expansion. This reduces stress and suppresses cracks in the wiring board SUB1, etc. The semiconductor chip CH1 is fixed in the recess CAV by material A1 and insulating material P1. Furthermore, the gaps in the recess CAV are eliminated, improving the reliability of the semiconductor device 1.

[0071] The semiconductor chip CH2 is stacked on the first surface F1 of the wiring board SUB1 and on semiconductor chip CH1. Furthermore, semiconductor chip CH3 is stacked on semiconductor chip CH2. In addition, other semiconductor chips may be stacked on semiconductor chip CH3.

[0072] Other configurations of the third embodiment may be the same as those of the first embodiment. Therefore, the third embodiment can obtain the same effects as the first embodiment.

[0073] Next, a method for manufacturing the semiconductor device 1 according to the third embodiment will be described.

[0074] Figures 14 to 17 are cross-sectional views showing an example of a method for manufacturing the semiconductor device 1 according to the third embodiment.

[0075] As shown in Figure 14, a plurality of second electrodes 14 are provided on the bottom surface of the recessed CAV. The second electrodes 14 are electrically connected to one of the wirings 12. The second electrodes 14 protrude from the bottom surface of the recessed CAV. The other configurations of the wiring board SUB1 of the third embodiment may be the same as those of the wiring board SUB1 of the first embodiment.

[0076] Next, as shown in Figure 15, the semiconductor chip CH1 is placed on the bottom surface of the recess CAV. Metal bumps BMP are provided on the back surface of the semiconductor chip CH1. In addition, material A1 is pre-applied around the second electrode 14. Therefore, by die bonding the semiconductor chip CH1 to the bottom of the recess CAV, the metal bumps BMP provided on the back surface of the semiconductor chip CH1 are connected to their respective second electrodes 14. Furthermore, by curing material A1, material A1 adheres to the bottom surface of the recess CAV and the semiconductor chip CH1.

[0077] Next, as shown in Figure 16, insulating material P1 is poured into the gap between the side surface of the semiconductor chip CH1 and the side wall of the recess CAV. Then, the insulating material P1 is solidified by heat treatment or ultraviolet treatment. This fills the recess CAV with the semiconductor chip CH1 and the insulating material P1.

[0078] Next, as shown in Figure 17, semiconductor chip CH2 is laminated onto the first surface F1 of the wiring board SUB1 and semiconductor chip CH1. Insulating material D2 is pre-attached to the back surface of semiconductor chip CH2. The thickness of insulating material D2 may be the same as insulating material D3. By curing insulating material D2, insulating material D2 adheres to solder resist 11a, insulating material P1, and semiconductor chip CH1 and semiconductor chip CH2. Next, the electrode pads of semiconductor chip CH2 and the electrode pads 13a on the first surface F1 are connected with bonding wire BW.

[0079] Next, as shown in Figure 13, the semiconductor chip CH3 and insulating material D3 are placed on the semiconductor chip CH2. The insulating material D3 is pre-attached to the back surface of the semiconductor chip CH3. Therefore, by curing the insulating material D3, the insulating material D3 adheres to the semiconductor chip CH2 and the semiconductor chip CH3. Next, the electrode pads of the semiconductor chip CH3 and the electrode pads of the semiconductor chip CH2 are connected with bonding wire BW.

[0080] Next, if necessary, other semiconductor chips are stacked on semiconductor chip CH3 and wire bonding is performed. Note that, for efficiency, the bonding wire BW process may be performed all at once after all semiconductor chips have been stacked.

[0081] Next, a sealing resin MR is formed on the first surface F1 to cover the semiconductor chip stack and bonding wire BW. This results in the structure shown in Figure 13.

[0082] According to the third embodiment, the semiconductor chip CH1 is flip-chip bonded within the recess CAV. Therefore, there is no need to wire bond the semiconductor chip CH1 and the second electrode 14 within the recess CAV. Thus, the manufacturing of the semiconductor device 1 becomes easier.

[0083] Furthermore, the surface of semiconductor chip CH1 is at approximately the same height level as the first surface F1 of wiring board SUB1. This allows semiconductor chip CH2 to be bonded to semiconductor chip CH1 and wiring board SUB1.

[0084] Other manufacturing steps in the third embodiment may be the same as those in the first embodiment. Therefore, the third embodiment can achieve the same effects as the first embodiment.

[0085] Furthermore, an insulating material P1 may be present between the surface of semiconductor chip CH1 and the back surface of semiconductor chip CH2 or insulating material D2. Even in this case, if the surface of insulating material P1 is at approximately the same height level as the first surface F1 of the wiring board SUB1, semiconductor chip CH2 can be stacked on top of semiconductor chip CH1.

[0086] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0087] 1 Semiconductor device SUB1 Wiring board CH1~CH3 Semiconductor Chips D1-D3 Insulating Materials BW Bonding Wire MR sealing resin 10 Resin materials 11a, 11b Solder Resist 12 Wiring 13a, 13b electrode pads

Claims

1. A wiring board having a recess on the first surface, A first semiconductor chip is disposed on the bottom surface of the recess, The recess is filled with a first insulating material provided around the first semiconductor chip, A semiconductor device comprising at least one second semiconductor chip stacked on top of the first semiconductor chip.

2. The semiconductor device according to claim 1, wherein the depth of the recess is greater than the thickness of the first semiconductor chip.

3. The semiconductor device according to claim 1, wherein the depth of the recess is substantially equal to the thickness of the first insulating material.

4. The semiconductor device according to claim 1, wherein, in a plan view from the first surface, the outer edge of the opening of the recess is located outside the outer edge of the first semiconductor chip.

5. The semiconductor device according to claim 1, wherein the second semiconductor chip is provided on the first insulating material.

6. The semiconductor device according to claim 5, wherein, in a plan view from the first surface, the outer edge of the opening of the recess is located outside the outer edge of the second semiconductor chip.

7. The semiconductor device according to claim 1, wherein the first insulating material fills the recess and covers the periphery of the second semiconductor chip.

8. In a plan view from the first surface, the entire outer edge of the opening of the recess is located outside the outer edge of the first semiconductor chip. A portion of the outer edge of the opening of the recess is located outside the outer edge of the second semiconductor chip. The semiconductor device according to claim 7, wherein the other part of the outer edge of the opening of the recess is located inside the outer edge of the second semiconductor chip.

9. The semiconductor device according to claim 1, wherein the surface of the first semiconductor chip is substantially flush with the first surface.

10. The first semiconductor chip includes a plurality of first electrodes on a surface facing the bottom surface of the recess, The semiconductor device according to claim 9, wherein the plurality of first electrodes are each connected to a plurality of second electrodes provided on the bottom surface of the recess.

11. The semiconductor device according to claim 9, wherein the second semiconductor chip is provided on the first semiconductor chip and the first surface of the wiring substrate.

12. The semiconductor device according to claim 1, wherein a plurality of the second semiconductor chips are stacked on top of the first semiconductor chip.

13. The wiring board includes a second electrode provided on the bottom surface of the recess, The semiconductor device according to claim 1, wherein the first semiconductor chip is electrically connected to the second electrode by a bonding wire.

14. The second semiconductor chip is a memory chip equipped with a memory cell array, The semiconductor device according to claim 1, wherein the first semiconductor chip is a controller chip equipped with a control circuit for controlling the memory chip.

15. The semiconductor device according to claim 1, wherein the first insulating material is provided to cover the first semiconductor chip.

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