Method and apparatus relating to a package substrate having a stack of glass layers including an interconnect bridge.

Abstract

The embodiments provide a system, apparatus, manufactured product, and method relating to a package substrate having a stack of glass layers including an interconnect bridge. [Solution] An example of a substrate for an integrated circuit package includes a first glass layer in which a cavity is defined, a second glass layer different from the first glass layer, and an interconnect bridge at least partially located within the cavity. The interconnect bridge electrically couples a first semiconductor die to a second semiconductor die.

Description

Background Art

[0001] Integrated circuit (IC) chips and / or semiconductor dies are typically connected via a package substrate to a larger circuit board such as, for example, a motherboard and other types of printed circuit boards (PCBs). As the size of IC chips and / or dies decreases and the interconnect density increases, alternatives to traditional substrate layers have been developed to provide stable transmission of high-frequency data signals and / or increased power delivery between different circuits. One option being pursued is the implementation of package substrates with glass cores. Generally, glass core implementations offer several advantages including higher plated through hole (PTH) density, lower signal loss, and lower total thickness variation compared to implementations using conventional epoxy cores.

Brief Description of the Drawings

[0002] [Figure 1] An example of an integrated circuit (IC) package constructed in accordance with the teachings disclosed herein is shown. [Figure 2] An example of a package substrate that can be used to implement the example substrate core of FIG. 1 is shown. [Figure 3] FIGS. 3-10 show various stages in an example manufacturing process for manufacturing the example package substrate of FIG. 2. [Figure 4] FIGS. 3-10 show various stages in an example manufacturing process for manufacturing the example package substrate of FIG. 2. [Figure 5] FIGS. 3-10 show various stages in an example manufacturing process for manufacturing the example package substrate of FIG. 2. [Figure 6] FIGS. 3-10 show various stages in an example manufacturing process for manufacturing the example package substrate of FIG. 2. [Figure 7] FIGS. 3-10 show various stages in an example manufacturing process for manufacturing the example package substrate of FIG. 2. [Figure 8]Figures 3-10 show various steps in an example manufacturing process for producing the package substrate example shown in Figure 2. [Figure 9] Figures 3-10 show various steps in an example manufacturing process for producing the package substrate example shown in Figure 2. [Figure 10] Figures 3-10 show various steps in an example manufacturing process for producing the package substrate example shown in Figure 2. [Figure 11] Other examples of package substrates that can be used to mount the example package substrate in Figure 1 are shown. [Figure 12] This flowchart shows an example of a method that may be used to manufacture one of the package substrate examples shown in Figures 1-11. [Figure 13] This is a top view of a wafer containing a die that may be included in an IC package constructed according to the teachings disclosed herein. [Figure 14] This is a side cross-sectional view of an IC device that may be included in an IC package constructed according to the teachings disclosed herein. [Figure 15] This is a side cross-sectional view of an IC device assembly that may be included in an IC package constructed according to the teachings disclosed herein. [Figure 16] This is a block diagram of an example of electrical equipment that may be included in an IC package constructed according to the teachings disclosed herein.

[0003] Generally, throughout the drawings and accompanying descriptions, the same or similar parts are referred to using the same reference numerals. Drawings are not necessarily to scale. Rather, the thickness of layers or areas may be enlarged in the drawings. Drawings show layers and areas with clear lines and boundaries, but some or all of these lines and / or boundaries may be idealized. In reality, boundaries and / or lines may be unobservable, blended, and / or uneven. [Modes for carrying out the invention]

[0004] Figure 1 shows an example integrated circuit (IC) package 100 constructed according to the teachings disclosed herein. In the illustrated example, the IC package 100 is electrically coupled to a circuit board 102 via an array of contacts 104 on the package mounting surface 105 (e.g., bottom, outer surface) of the package. In the illustrated example, the contacts 104 are represented as pads or lands. However, in some examples, the IC package 100 may include, in addition to or instead of, the pads or lands shown, balls, pins, and / or any other type of contacts to enable the electrical coupling of the IC package 100 to the circuit board 102. In this example, the IC package 100 includes two semiconductor (e.g., silicon) dies 106, 108 (sometimes referred to as chips or chiplets) mounted on a package substrate 110 and surrounded by a package lid 112 (e.g., a mold compound, an integrated heat spreader, IHS, etc.). Thus, the package substrate 110 is an example of means for supporting the semiconductor dies. The IC package example 100 in Figure 1 includes two dies 106 and 108, but in other examples, the IC package 100 may have only one die or three or more dies. In some examples, one of the dies 106 and 108 (or separate dies) is embedded in the package substrate 110. The dies 106 and 108 can provide any preferred type of function (e.g., data processing, memory storage, etc.).

[0005] As shown in the illustrated example, each of the dies 106 and 108 is electrically and mechanically coupled to the package substrate 110 via a corresponding array of interconnects 114. In Figure 1, the interconnects are shown as bumps. However, the interconnects 114 may be any (one or more) other types of electrical connections (e.g., balls, pins, pads, wire bonding, etc.) in addition to or instead of the bumps shown. The electrical connections between the dies 106 and 108 and the package substrate 110 (e.g., interconnects 114) may be referred to as first-level interconnects. In contrast, the electrical connections between the IC package 100 and the circuit board 102 (e.g., contacts 104) may be referred to as second-level interconnects. In some examples, one or both of the dies 106 and 108 may be stacked on top of one or more other dies and / or interposers. In such an example, dies 106, 108 may be coupled to a lower die and / or interposer via a first set of first-level interconnects, and the lower die and / or interposer may be connected to the package substrate 110 via another set of first-level interconnects associated with the lower die and / or interposer. Thus, as used herein, the first-level interconnect refers to an interconnect (e.g., ball, bump, pin, pad, wire bonding, etc.) between the die and the package substrate, or between the die and the lower die and / or interposer.

[0006] As shown in Figure 1, the interconnect 114 of the first level interconnect includes two different types of bumps corresponding to core bumps 116 and bridge bumps 118. When used here, the core bump 116 is a bump on the dies 106, 108 through which electrical signals pass between the dies 106, 108 and external components of the IC package 100. More specifically, as shown in the illustrated example, when the dies 106, 108 are mounted on the package substrate 110, the core bump 116 is physically connected and electrically coupled to contacts 120 (e.g., pads, bumps, etc.) on the die mounting surface 122 of the package substrate 110 (e.g., top surface, inner surface, inner surface, top surface, etc.). Contacts 120 on the die mounting surface 122 of the package substrate 110 are electrically coupled to contacts 104 on the package mounting surface 105 of the package substrate 110 (e.g., the bottom, outer surface) (e.g., the surface opposite to the die mounting surface 122) via an internal interconnect 124 within the package substrate 110. As a result, a continuous electrical signal path exists between the core bumps 116 of the dies 106, 108 and the contacts 104 mounted on the circuit board 102, through the contacts 120 and interconnect 124 provided between them. As shown in the figure, the package mounting surface 105 and the die mounting surface 122 define the opposite outer surfaces of the package substrate 110. Although both surfaces are outer surfaces of the package substrate 110, the die mounting surface 122 may here be referred to as the inner surface or inner surface with respect to the entire IC package 100. In contrast, in this example, the package mounting surface 105 is the outer surface or outer surface of the IC package 100.

[0007] When used here, the bridge bump 118 is a bump on dies 106, 108 through which electrical signals pass between different dies 106, 108 within the IC package 100. Thus, as shown in the illustrated example, the bridge bump 118 of the first die 106 is electrically coupled to the bridge bump 118 of the second die 108 via an interconnect bridge 126 (e.g., a silicon-based interconnect bridge, interconnect die, embedded interconnect bridge (EMIB)) embedded in the package substrate 110. As shown in Figure 1, the core bump 116 is typically larger than the bridge bump 118. In some examples, the bridge bump 118 being smaller than the core bump allows for interconnects with finer pitches or line spaces within the interconnect bridge 126 than is possible with known organic interconnects in the package substrate. In some examples, as shown in Figure 1, the interconnect bridge is embedded within the substrate core 128 (e.g., within the first glass core 132). In some examples, the interconnect bridge 126 includes through-silicon vias (TSVs) for electrically coupling with some of the contacts 104 on the package mounting surface 105 of the package substrate 110 (e.g., via some of the interconnect 124).

[0008] In some examples, underfill material 119 is provided between dies 106, 108 and the package substrate 110, around and / or between the first level interconnect 114 (for example, around and / or between the core bump 116 and / or bridge bump 118). In the illustrated example, only the first die 106 is accompanied by underfill material 119. However, in other examples, both dies 106 and 108 are accompanied by underfill material 119. In other examples, the underfill material 119 is omitted. In some examples, the mold compound used for the package lid 112 is used as the underfill material surrounding the first level interconnect 114.

[0009] In some examples, the IC package 100 includes additional passive components, such as surface-mount resistors, capacitors, and / or inductors, which are located on the package mounting surface 105 and / or the die mounting surface 122 of the package substrate 110.

[0010] In Figure 1, the substrate 110 of the IC package example 100 includes a substrate core 128 (e.g., main core, overall core) between two separate build-up layers or regions 130, 131 (e.g., redistribution layers or regions). As shown in the illustrated example, the substrate core 128 includes a plurality of separate glass cores (e.g., a plurality of glass layers, a plurality of glass core layers, etc.), namely, a top glass core example 132 (e.g., a first glass core), an intermediate glass core example 134 (e.g., a second glass core), and a bottom glass core example 136 (e.g., a third glass core). In the illustrated example of Figure 1, the glass cores 132, 134, and 136 (e.g., subcores, glass substrates, glass layers, glass sheets) are stacked on top of each other.

[0011] In some examples, cores 132, 134, and 136 contain at least one of aluminosilicate, borosilicate, aluminoborosilicate, silica, and / or fused silica. In some examples, cores 132, 134, and 136 contain one or more additives including aluminum oxide (Al2O3), boron trioxide (B2O3), magnesium oxide (MgO), calcium oxide (CaO), stoichiometric silicon oxide (SrO), barium oxide (BaO), tin oxide (SnO2), nickel alloy (Na2O), potassium oxide (K2O), phosphorus trioxide (P2O3), zirconium dioxide (ZrO2), lithium oxide (Li2O), titanium (Ti), and / or zinc (Zn). In some examples, cores 132, 134, and 136 contain silicon and oxygen. In some examples, cores 132, 134, and 136 contain one or more of silicon, oxygen, and / or aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, and / or zinc. In some examples, cores 132, 134, and 136 contain at least 23 weight percent silicon and at least 26 weight percent oxygen. In some examples, glass cores 132, 134, and 136 are separate layers of glass containing silicon, oxygen, and aluminum. In some examples, cores 132, 134, and 136 contain at least 23 weight percent silicon, at least 26 weight percent oxygen, and at least 5 weight percent aluminum. In some examples, as further described below, different glass cores among glass cores 132, 134, and 136 contain different materials or different compositions of materials such that different glass cores 132, 134, and 136 are associated with different coefficients of thermal expansion (CTE). In some cases, the CTE is altered between different glass cores 132, 134, and 136 by varying the amount of alkali dopant (e.g., Na2O, K2O) contained in the glass. Generally, lower alkali content results in lower CTE. Therefore, for a CTE of 3 ppm / °C, the alkali content can be less than 0.1%. In contrast, for a CTE of 9 ppm / °C, the alkali content can reach 20%.

[0012] In some examples, cores 132, 134, and 136 are amorphous solid glass layers. In some examples, cores 132, 134, and 136 are glass layers that do not contain organic adhesives or organic materials. In some examples, cores 132, 134, and 136 are solid glass layers that have a rectangular shape in plan view. In some examples, cores 132, 134, and 136 include at least one glass layer as a glass substrate, but do not contain epoxy or glass fibers (e.g., they do not contain an epoxy prepreg layer with glass cloth). In some examples, cores 132, 134, and 136 correspond to a single piece of glass extending across the total height / thickness of each corresponding core.

[0013] In some examples, cores 132, 134, and 136 have a rectangular shape in plan view, having substantially the same extent as the layers above and / or below the core. In some examples, cores 132, 134, and 136 have a thickness ranging from approximately 25 micrometers (μm) to approximately 400 μm (with the total thickness of the substrate core 128 ranging from approximately 50 μm to approximately 1.4 millimeters (mm)). In some examples, cores 132, 134, and 136 can have dimensions ranging from approximately 10 mm to approximately 250 mm on each side (e.g., 10 mm × 10 mm to 250 mm × 250 mm). In some examples, cores 132, 134, and 136 correspond to rectangular prism volumes from which sections (e.g., vias) have been removed and filled with other materials (e.g., metal).

[0014] In Figure 1, the build-up regions 130, 131 are represented as lumps / blocks having internal interconnects 124 extending linearly through the build-up regions 130, 131 (and the glass cores 132, 134, 136). However, Figure 1 is simplified for clarity and illustrative purposes. In reality, the interconnects are not necessarily linear. More specifically, in some examples, the build-up regions 130, 131 are defined by alternating layers of dielectric material and layers of conductive material (e.g., metal such as copper). The conductive (metal) layers serve as the basis for the internal interconnects 124, which are represented in a simplified linear form as shown in Figure 1. In some examples, the metal layers are patterned to define electrical wiring or conductive traces that are electrically coupled between different metal layers by conductive (e.g., metal) vias extending through the intervening dielectric layers. Furthermore, electrical wiring or traces on either side of the substrate core 128 may be electrically coupled by through-glass vias (TGVs) (e.g., copper-plated vias) extending through the glass cores 132, 134, and 136.

[0015] In some examples, one or both of the build-up regions 130, 131 may be omitted. That is, in some examples, the stack of glass cores 132, 134, 136 defines most (e.g., all or substantially all) of the thickness of the package substrate 110 (e.g., all except the outer solder resist layer, all except a reduced set of metallization layers within the build-up regions 130, 131, etc.). In some such examples, the stack of glass cores 132, 134, 136 includes four or more glass layers, and parallel to those glass layers, redistribution of the electrical paths defined by the interconnects 124 is achieved by traces or wirings running between adjacent glass layers among those glass layers. Further, in some examples, as shown in FIG. 1, an interconnect bridge 126 is embedded in the topmost glass core 132 to provide die-to-die connection, thereby reducing and / or eliminating the need for the upper build-up region 130. That is, in some examples, embedding the interconnect bridge 126 in the topmost glass core 132 results in fewer metallization layers with intervening dielectric layers required within the upper build-up region 130 than would otherwise be possible. In some examples, the upper build-up region 130 can be completely omitted.

[0016] In particular, glass is harder and thus provides greater mechanical support or strength to the package substrate, so the glass core is more advantageous than an epoxy-based core. Thus, the substrate core 128, more specifically the individual glass cores 132, 134, 136, are examples of means for strengthening the package substrate. In addition to the mechanical benefits, the glass cores also offer other advantages including higher plated through hole (PTH) density, lower signal loss, and lower total thickness variation.

[0017] While the above advantages can be realized in the disclosed examples, glass cores also present challenges due to the fragile (e.g., brittle) nature of glass and the potential for defects to develop into cracks propagating through the glass. A common type of failure of known glass cores is called seware failure. Seware results in the separation of the glass core along a crack propagating from the edge of the glass core along its length and width between the main outer surfaces of the glass core (e.g., top and bottom, front and back). That is, seware is characterized by the glass core splitting into two separate glass sheets along a line extending generally parallel to the main surface of the glass core.

[0018] Factors contributing to seware include defects on the edges of the glass core resulting from fragmentation, and internal stresses induced by the mismatch between the coefficient of thermal expansion (CTE) of the glass core (e.g., CTE of approximately 3 ppm / °C to 10 ppm / °C) and the CTE of the build-up region material (e.g., approximately 39 ppm / °C for the organic dielectric layer, approximately 17 ppm / °C for copper, and approximately 2.6 ppm / °C for silicon) during the thermal cycling of the package substrate 110 (either during the manufacturing process or during subsequent use). More specifically, package substrates, such as the package substrate 110 in Figure 1, are often manufactured on large panels that are later fragmented or cut into individual units with a saw. Accordingly, in the example shown in Figure 1, the package substrate 110, including the substrate core 128 (and associated subcores 132, 134, 136) and build-up regions 130, 131, includes an opposite edge 138 created by sawing. Such sawing can lead to the growth of defects at the edges of the glass core (e.g., the edges 138 of the glass cores 132, 134, 136 in Figure 1), which can cause cracks to propagate across the center of the glass core, splitting it into two main pieces. Such crack growth and propagation are exacerbated by stresses induced by temperature fluctuations and the difference in CTE between the glass core and the build-up regions. Generally, the materials of the build-up regions 130, 131 have a higher CTE than the glass. As a result, the materials of the build-up regions 130, 131 expand and contract more than the glass core in response to thermal fluctuations, thereby creating internal stresses within the glass core that can promote crack propagation.

[0019] The examples disclosed herein reduce (e.g., minimize) concerns of sewering by implementing a substrate core 128 of a substrate with a plurality of separate (e.g., discrete) glass cores (e.g., glass cores 132, 134, 136) stacked on top of each other, as shown in FIG. 1. More specifically, in the examples disclosed herein, different laminated cores are implemented with different materials (or different compositions of the same material) associated with different CTEs. That is, in some examples, by adjusting (e.g., changing, varying, etc.) the relative ratios of Al2O3, B2O3, Li2O, Na2O, K2O, Sb2O3, and / or other additives in each layer and / or by process variations (e.g., lamination coating, heat treatment, etc.), the different CTEs of the different glass cores 132, 134, 136 can be adjusted. In some examples, the glass cores closer to the build-up regions 130, 131 are manufactured to have a CTE closer to the CTE of the build-up regions 130, 131 than the CTE of the glass cores farther from the build-up regions 130, 131 (e.g., closer to the center of the stack of glass cores). Thus, the substrate core 128 is defined by a gradual change or a progressive change in CTE values (e.g., across the glass cores 132, 134, 136 in the stack) to provide a smooth transition between different layers within the package substrate 110, thereby reducing the stress at any given location.

[0020] For example, in some cases, the intermediate glass core 134 has a lower CTE than the top glass core 132 and a lower CTE than the bottom glass core 136. In some cases, the CTEs of the top glass core 132 and the bottom glass core 136 are the same. Thus, in some cases, the different CTEs of the glass cores 132, 134, and 136 are symmetrical across the entire thickness of the substrate core 128. That is, the stack of glass cores 132, 134, and 136 and the arrangement or order of their associated CTEs define a symmetrical sequence of CTEs (e.g., a symmetrical CTE gradient) from the bottom glass core (e.g., the third glass core 136) to the top glass core (e.g., the first glass core 132). In some such cases, the lowest CTE value in the symmetrical CTE gradient is closer to the center of the stack of glass cores than the highest CTE value in the symmetrical CTE gradient (closer to the top and bottom of the stack). In other examples, different CTEs do not have to be symmetrical. For example, in some cases, the top glass core 132 (e.g., the glass core closest to dies 106, 108) has the highest CTE in the stack, the bottom glass core 136 (e.g., the glass core furthest from dies 106, 108) has the lowest CTE, and the intermediate glass core 134 has a CTE between the other two. In other cases, the top glass core 132 (e.g., the glass core closest to dies 106, 108) has the lowest CTE in the stack, and the bottom glass core 136 has the highest CTE in the stack. Any other preferred configuration of making the CTE values ​​different across any preferred number of stacked glass cores can be implemented, in addition or alternatively, to achieve any preferred CTE gradient across the entire substrate core 128. In some cases, the highest CTE for the glass cores is approximately 7 ppm / °C to 9 ppm / °C, the lowest CTE is approximately 3 ppm / °C to 5 ppm / °C, and one or more intervening glass cores have CTEs at different gradual points between these outer limits.

[0021] In addition to implementing multiple glass cores with different CTEs (e.g., glass cores 132, 134, and 136) to reduce stress, in some examples, as already mentioned above, one or both of the build-up regions 130 and 131 are omitted or their thickness is significantly reduced (e.g., the number of metallization layers contained within them is reduced). As a result, the stress generated on glass cores 132, 134, and 136 due to the mismatch in CTEs between the glass and the build-up regions 130 and 131 is reduced.

[0022] Furthermore, in some examples, a buffer material 140 (e.g., buffer layer, adhesive resin / material / layer) is placed between adjacent glass cores 132, 134, and 136 to hold the glass cores together. In some such examples, the buffer material 140 has a relatively low modulus of elasticity to absorb thermal fluctuations and stresses arising from the different CTEs of the different glass cores 132, 134, and 136, thereby further reducing the stress inside the substrate core 128. In some examples, the buffer material 140 is an organic dielectric material (e.g., polyimide, parylene, etc.). In some examples, the buffer material 140 is an inorganic dielectric material (e.g., silicon oxide (SiO2)). x ), silicon nitride (SiN x )) In some examples, the buffer material 140 includes a carbon-doped oxide (CDO). In some examples, the buffer material 140 includes the same or similar dielectric material used in the build-up regions 130 and 131. In some examples, the layer of buffer material 140 includes a conductive material that facilitates the redistribution of electrical paths between the glass cores 132, 134, and 136. Thus, the material between the glass cores is also referred to here as the redistribution material. The redistribution material may include one or more redistribution layers within the package substrate 110. Similarly, in such examples, the stack of glass cores 132, 134, and 136 may be referred here as the redistribution region or redistribution layer.

[0023] Three different glass cores (e.g., glass cores 132, 134, and 136) are shown in example substrate core 128 of Figure 1, but any other suitable number of glass cores may be mounted having corresponding CTEs such that they define a particular CTE gradient across the entire thickness of the substrate core 128. Thus, in some examples, only two glass cores, each having a different CTE, are used. In other examples, more than three glass cores are used. In some such examples, each glass core is different from all the other glass cores in the core stack. In other examples, two or more of the glass cores may have the same CTE (e.g., made from the same material of the same composition), and at least one glass core may have a different CTE from the others.

[0024] In the example shown in Figure 1, the glass cores 132, 134, and 136 are shown as having the same thickness (e.g., approximately equal thickness). However, in some examples, the thicknesses of the glass cores 132, 134, and 136 may differ from each other. For example, in some examples, the intermediate glass core 134 is thicker than the top glass core 132 and thicker than the bottom glass core 136. In other examples, the intermediate glass core 134 is thinner than the top glass core 132 and thinner than the bottom glass core 136. Any preferred thickness of the glass cores can be implemented to provide sufficient rigidity to the package substrate while achieving a suitable CTE gradient for reducing stress to mitigate sewerage.

[0025] Figure 2 shows an example package substrate 200 that may be used to mount the example package substrate 110 of Figure 1. In this example, the package substrate 200 includes a substrate core 202 and an upper build-up region 204 corresponding to the package substrate 128 and upper build-up region 130 shown in Figure 1. In particular, there is no lower build-up region in this example. Similar to Figure 1, the example substrate core 202 in Figure 2 includes a stack of multiple different (e.g., separate) glass cores (e.g., multiple glass layers, multiple glass core layers, etc.). However, in this example, there are a total of five glass cores, including a first glass core 206 (e.g., top glass core, uppermost glass core), a second glass core 208, a third glass core 210 (e.g., middle glass core), a fourth glass core 212, and a fifth glass core 214 (e.g., bottom glass core, lowermost glass core). In this example, the outermost surfaces of the outermost glass cores 206, 214 define the first outer surface 216 and the second outer surface 218 of the entire substrate core 202. In some examples, the glass cores 206, 208, 210, 212, 214 are covered and / or coated with a liner. In such examples, the liner on the outermost glass cores 206, 214 defines the first and second outer surfaces 216, 218 of the substrate core 202.

[0026] In the illustrated example, the different glass cores 206, 208, 210, 212, and 214 correspond to the different glass cores among glass cores 132, 134, and 136 in Figure 1. Thus, the glass cores 206, 208, 210, 212, and 214 contain different CTEs as described above. In this example, each of the glass cores 206, 208, 210, 212, and 214 has approximately the same thickness. In some examples, the different glass cores among glass cores 206, 208, 210, 212, and 214 may have different thicknesses. Furthermore, although five glass cores are shown, in some examples any other preferred number of glass cores (e.g., 2, 3, 4, 6, 7, 8, 10, 12, 15, etc.) may be used. In such examples, the stack of glass cores can define any preferred CTE gradient based on the difference in CTEs of each glass core in the stack. In some examples, the CTE gradient is symmetrical across the entire thickness of the substrate core 202. In other examples, the CTE gradient is not symmetrical.

[0027] In the illustrated example, the different glass cores 206, 208, 210, 212, and 214 are separated by an intervening layer of dielectric material 220 (e.g., adhesive material, adhesive resin) corresponding to the buffer material 140 described above in relation to Figure 1. In some examples, the dielectric material 220 includes an organic epoxy dielectric. However, any other suitable dielectric may be used in addition or in place. In some examples, the dielectric material 220 has a relatively low modulus of elasticity to absorb thermal fluctuations and stresses arising from the different CTEs of the different glass cores 206, 208, 210, 212, and 214.

[0028] In the illustrated example in Figure 2, the glass cores 206, 208, 210, 212, and 214 include glass through-vias (TGVs) 222 electrically coupled by additional conductive material 224 extending through the intervening layer of dielectric material 220. In some examples, the additional conductive material 224 corresponds to metal vias plated into openings (e.g., holes) in the dielectric material 220. In other examples, the additional conductive material 224 is dispensed into the openings or holes as a liquid metal and / or paste (e.g., copper paste and / or other suitable metals (e.g., aluminum, nickel, tin, etc.)). In some examples, the TGVs 222 are plated with the same material used for the additional conductive material 224 (e.g., copper, aluminum, nickel, tin, etc.). In some examples, at least a portion of the additional conductive material 224 includes a different material from the TGVs 222. Furthermore, as shown in the illustrated example, contact pads 226 are positioned at one end of each TGV222 (for example, adjacent to the surfaces on both sides of the corresponding glass cores 206, 208, 210, 212, 214). In some examples, the contact pads 226 are integral extensions of the TGV222 within the glass cores 206, 208, 210, 212, 214. Thus, as shown in the illustrated example, the contact pads 226 electrically couple the TGV222 with the additional conductive material 224. In this example, the outermost contact pads 226 (for example, along the first and second outer surfaces 216, 218) define both ends of an interconnect (for example, portion of interconnect 124 in Figure 1) that extends through the entire thickness of the substrate core 202. In some examples, the layers of dielectric material 220 between the glass cores 206, 208, 210, 212, and 214 function as redistribution layers having a metallization layer (e.g., accompanied by conductive material 224 and contact pads 226) that provides traces or wiring extending between the glass cores (e.g., substantially parallel to the main surface of the glass cores) for defining or rerouting electrical paths through the substrate core 202.In some examples, any suitable number of TGV222s can be mounted within each of the glass cores 206, 208, 210, 212, and 214, positioned in any suitable arrangement, and electrically coupled in any suitable manner (via additional conductive material 224 and / or other metals for the purpose of rewiring).

[0029] In this example, the first glass core 206 includes a cavity 228 containing an interconnect bridge 230 embedded therein. In this example, the interconnect bridge 230 corresponds to the interconnect bridge 126 in Figure 1. In some examples, as shown, the interconnect bridge 230 has a thickness approximately equal to the thickness of the first glass core 206. In other examples, the thickness of the interconnect bridge 230 is less than the thickness of the first glass core 206. In other examples, the thickness of the interconnect bridge 230 is greater than the thickness of the first glass core 206. For example, in some examples, the glass cores 206, 208, 210, 212, and 214 are thinner than the interconnect bridge 230, and the interconnect bridge 230 is embedded in a cavity extending through two or more of the glass cores 206, 208, 210, 212, and 214. In some examples, regardless of the thickness of the interconnect bridge 230 relative to the thickness of the glass cores 206, 208, 210, 212, and 214, the interconnect bridge 230 is positioned such that its upper surface is substantially coplanar with the outer surface 216 of the substrate core 202. As used here, substantially coplanar means coplanar within + / - 5 μm. In some examples, the thickness of the interconnect bridge 230 is greater than the thickness of the upper build-up region 204. In the past, interconnect bridges have been embedded within the build-up region of the package substrate, which allows this. However, by embedding the interconnect bridge 230 within the substrate core 202, the build-up region 204 can be significantly thinner than in other known package substrates. Furthermore, embedding the interconnect bridge 230 within the substrate core 202 and providing a redistribution layer function within the dielectric material 220 layers between the glass cores 206, 208, 210, 212, and 214 also reduces the number of dielectric and metal layers required within the build-up region 204. Thus, in some examples, as shown in the illustrated examples, only a single dielectric material layer (between two metal layers) is present. In other examples, multiple dielectric material layers between multiple metal layers may still be present.

[0030] As shown in the illustrated example, a first solder resist layer 232 is added on the build-up region 204. In this example, the first solder resist layer 232 defines the first outer surface 234 (e.g., the top surface) of the package substrate 200. That is, the solder resist layer 232 defines the die mounting surface 122 of the package substrate 110 in Figure 1. In some examples, the upper build-up region 204 can be completely omitted, and as a result, the uppermost glass core 206 can be adjacent to the first solder resist layer 232, similar to the one shown on the bottom surface of the package substrate 200. That is, in this example, a second solder resist layer 236 is provided adjacent to the fifth glass core 214 to define the second outer surface 238 of the package substrate 200 (e.g., corresponding to the package mounting surface 105 of the package substrate 110 in Figure 1).

[0031] In some examples, a first contact 240 and a second contact 242 are provided along the first solder resist layer 232 and the second solder resist layer 236, and are electrically coupled to the TGV 222. In this example, the first contact 240 along the first solder resist layer 232 corresponds to contact 120 in Figure 1, and the second contact 242 along the second solder resist layer 236 corresponds to contact 104 in Figure 1. Thus, the first contact 240 and the second contact 242 in Figure 2 represent the corresponding ends of the internal interconnects of the internal interconnect 124 that extends through the package substrate as described above in Figure 1. Furthermore, in this example, a third contact 244 is provided along the first solder resist layer 232 and is electrically coupled to the interconnect bridge 230. Thus, in this example, the third contact 244 corresponds to the location of the bridge bump 118 in Figure 1.

[0032] Figures 3-10 illustrate various stages in an example manufacturing process for producing the package substrate example 200 of Figure 2. Figure 3 shows a glass panel 300 corresponding to one of the initial states of the glass cores 206, 208, 210, 212, and 214. For illustrative purposes, the glass panel 300 is illustrated and described as corresponding to the third glass core 210 (for example, the intermediate glass core in the substrate core 202 of Figure 2). In some examples, the glass panel 300 is manufactured to a thickness corresponding to the final thickness of the third glass core 210. However, in some examples, the glass panel 300 is initially slightly thicker than the final thickness of the third glass core 210 to allow some amount of glass to be removed during subsequent polishing or planarization processes, which will be described further later.

[0033] Figure 4 shows the manufacturing stage after the TGV222 has been added to the third glass core 210 of Figure 3. In some examples, the TGV222 is added by first creating corresponding openings (e.g., holes) in the glass core through a laser-induced deep etching (LIDE) process. Once the openings are created, metal 402 (e.g., copper, aluminum, nickel, tin, etc.) is plated into the openings to define the TGV222. In this example, the TGV222 has a cross-sectional profile that generally corresponds to an hourglass shape, and the width (e.g., diameter) of the TGV222 is narrower near the midpoint of the opening between the first and second surfaces 404, 406 on both sides of the glass core 210. In other examples, one or more of the TGV222s may have different cross-sectional shapes. For example, in some examples, one or more of the TGV222 may be generally conical or tapered in shape, with the width (e.g., diameter) being smallest on one of the two surfaces 404, 406 of the glass core 210 and the width (e.g., diameter) being largest on the opposite surface 404, 406. In other examples, the width (e.g., diameter) of one or more of the openings in the TGV222 is substantially constant along the entire length of the TGV222 between both surfaces 404, 406 of the glass core 210.

[0034] Figure 4 also illustrates the manufacturing stage after the addition of contact pads 226 to both ends of the TGV 222 (for example, adjacent to each of the outer surfaces 404 and 406 of the glass core 210). In some examples, the contact pads 226 are made of the same metal 402 as the TGV and are added during the same process. That is, in some examples, the metal 402 is deposited by an electroplating process, which then provides the contact pads 226. In some such examples, excess portions of the metal 402 can be removed (for example, by selective etching using photolithography) to define the final shape of the contact pads 226. In some examples, the contact pads 226 are provided in a separate process from the TGV 222 (for example, by plating). In some examples, the contact pads 226 are omitted. In some examples, the metal 402 is plated after the deposition of a metal seed layer on the surface of the glass core 210 (for example, on the inner walls of the openings and / or on the outer surfaces 404 and 406). In other examples, TGV222 is plated from bottom to top without a seed layer. In some such examples, the glass core 210 in Figure 4 is first mounted on a conductive carrier to provide metal at the bottom of the opening in which the TGV222 is placed, enabling the start of the plating process. The manufacturing steps shown in Figure 4 are also after a polishing process (e.g., a CMP process) to flatten or planarize the metal 402 on the outer surfaces 404, 406 of the glass core 210 (e.g., to planarize the contact pad 226).

[0035] Figure 5 illustrates the manufacturing steps following the application of dielectric material 220 to both sides of the third glass core 2410 of Figure 4 (e.g., by lamination). Furthermore, Figure 5 illustrates the manufacturing steps after the addition of additional conductive material 224 (e.g., conductive vias) into the dielectric material 220. In some examples, the process of adding the additional conductive material 224 involves drilling holes through the dielectric material (e.g., laser drilling) to expose the contact pads 226 beneath, and then depositing more metal 402 into the holes (e.g., plating). In other examples, the additional conductive material 224 is dispensed into such holes as a liquid metal and / or paste, and then made curable or solidifiable. In some examples, any excess amount of additional conductive material 224 (e.g., extending beyond and / or above the outer surface of the dielectric material 220) is removed through a polishing process (e.g., a CMP process) so that the layers of dielectric material 220 and additional conductive material 224 are coplanar with each other.

[0036] Figure 6 shows the manufacturing steps in which each of the glass cores (e.g., the three internal glass cores 208, 210, and 212 of the substrate core 202 in Figure 2), excluding the outermost (e.g., top and bottom) glass cores, is assembled or stacked together by combining or joining the respective glass core assemblies 602, 604, and 606. In this example, the glass core assemblies 602, 604, and 606 in Figure 6 are the result of processing the corresponding second, third, and fourth glass cores 208, 210, and 212 through the manufacturing steps shown in Figures 3-10. That is, in this example, the glass core assemblies 602, 604, and 606 in Figure 6 are the result of processing the corresponding glass cores 208, 210, and 212 through the manufacturing steps shown in Figures 3-5. Therefore, the third glass core 210, processed up to the point shown in Figure 5 as described above, corresponds to the second glass core assembly 604 shown in Figure 6.

[0037] As shown in Figure 6, the first glass core assembly 602 is similar to the second glass core assembly 604, except for the presence of different glass cores with different CTEs (e.g., a second glass core 208 instead of a second glass core 210). Also, as shown in Figure 6, the dielectric material 220 added to the first glass core assembly 602 is thinner on the bottom side (e.g., the side facing the second glass core assembly 604). In this example, the dielectric material 220 is thinner on the bottom side because the bottom side does not contain additional conductive material 224. That is, in this example, only the contact pad 226 is provided on the bottom side of the first glass core assembly 602. Another difference between the first glass core assembly 602 and the second glass core assembly 604 is the position of the TGV 222 and the associated contact pad 226. In the example shown in Figure 6, the third glass core assembly 606 is manufactured similarly to the first glass core assembly 602, except that it has a different glass core 212 (having a different CTE) and a thinner layer of dielectric material 220 on the upper side (for example, the side facing the second glass core assembly 604).

[0038] In some examples, when different glass core assemblies 602, 604, and 606 are brought together (as shown in Figure 6), the stacks are pressed together (e.g., subjected to compression). In some examples, the dielectric material 220 is an adhesive resin and undergoes a curing process (e.g., by heating) during this compression process to firmly bond the assemblies 602, 604, and 606. The final result of combining or bonding the different glass core assemblies 602, 604, and 606 produces the internal glass core stacked assembly 700 shown in Figure 7. The dielectric material 220 is illustrated and described as being applied to both interfaces of the glass cores 208, 210, and 212 before assembly, however, in some examples, the dielectric material 220 is applied to only one of the two interfaces. In some examples, the second and third glass core assemblies 604 and 606 are combined with the first glass core assembly 602 before additional conductive material 224 is applied to the second and third glass core assemblies 604 and 606. In other words, in some examples, the outermost dielectric material 220 layer and associated additional conductive material 224 shown in Figure 7 can be added after the three glass cores 208, 210, and 212 are joined together.

[0039] Figure 8 shows the manufacturing stage after processing additional glass panels related to the first glass core 206 and the fifth glass core 214 through a process similar to that detailed above in relation to Figures 3-5 to produce additional glass core assemblies 802, 804. Furthermore, Figure 8 shows combining or bonding these glass core assemblies 802, 804 with the internal glass core laminated assembly 700 of Figure 7. As shown in Figure 8, dielectric material 220 is added to only one side of each of the additional glass core assemblies 802, 804 (for example, the side facing the internal glass core laminated assembly 700).

[0040] In this example, the first glass core 206 of the uppermost glass core assembly 802 in Figure 8 is manufactured with a relatively large cavity (e.g., cavity 228) closed at the bottom end by a relatively large conductive pad 806. In some examples, cavity 228 is manufactured during the same LIDE process used to manufacture the opening for TGV222. In other examples, cavity 228 is manufactured in a different process.

[0041] In some cases, when different glass core assemblies 700, 802, and 804 are brought together (as shown in Figure 7), the stacks are pressed together (e.g., subjected to compression), and the dielectric material 220 (e.g., adhesive resin) undergoes a curing process (e.g., by heating) to firmly bond the assemblies 700, 802, and 804. The final result of combining or bonding the different glass core assemblies 700, 802, and 804 is to produce the complete package substrate 200 shown in Figure 2.

[0042] Figure 9 shows the manufacturing stage after the interconnect bridge 230 has been embedded in the substrate core 202 of the stack of glass cores 206, 208, 210, 212, and 214, which are joined together as shown in Figure 8. More specifically, as shown in the illustrated example, the interconnect bridge 230 is located in the cavity 228 of the first glass core 206. In some examples, the interconnect bridge 230 is located within the first glass core 206 before it is combined with the other glass cores. That is, in some examples, the uppermost glass core assembly 802 in Figure 8 may already include the interconnect bridge 230 embedded within it.

[0043] The manufacturing stage shown in Figure 9 is also after the addition of the build-up region 204 on the first glass core 206 and the interconnect bridge 230. In this example, the build-up region 204 includes a single dielectric layer 902 that separates the contact pad 226 associated with the TGV 222 in the first glass core 206 from the additional contact pad 904 on the outer surface of the assembly. In some examples, the build-up region 204 includes two or more dielectric layers with an intervening metal layer. In this example, an additional contact 906 is added so as to extend through the build-up region 204 and electrically couple with the interconnect bridge 230.

[0044] In some examples, the dielectric layer 902 is added through a lamination process. Subsequently, contact pads 904 and additional contacts 906 are added by drilling holes through the dielectric layer 902, then filling the holes with metal, and adding additional metal on the outer surface of the dielectric layer 902. In some examples, the lamination of the dielectric layer 902 results in the filling of the gap surrounding the interconnect bridge 230 in the cavity 228. That is, in some examples, the same material used for the dielectric layer 902 surrounds (e.g., at least partially surrounds) the interconnect bridge 230 laterally. In some examples, before the addition of the dielectric layer 902 that spans over the interconnect bridge 230, another dielectric material is added to fill the cavity 228 around the interconnect bridge 230. In some such examples, the dielectric material in the cavity 228 is the same material used for the dielectric layer 902 over the interconnect bridge 230. In other examples, different dielectric materials can be used in the cavity 228 and on the interconnect bridge 230. Furthermore, in some examples, one or both of the dielectric material surrounding the interconnect bridge 230 in the cavity and the dielectric material on the interconnect bridge in the dielectric layer 902 can be the same as the dielectric material 220 between the glass cores 206, 208, 210, 212, and 214. In other examples, the dielectric material 220 between the glass cores 206, 208, 210, 212, and 214 is different from the dielectric material in contact with the sides and top surfaces of the interconnect bridge 230.

[0045] Figure 10 shows the manufacturing stage after the addition of solder resist layers 232, 236 and associated contacts 240, 242, 244 for the first level interconnect (along the first outer surface 234) and the second level interconnect (along the second surface 238). Figure 10 represents the completion of the manufacturing process. Thus, as shown in the figure, Figure 10 is the same as the package substrate 200 shown in Figure 2.

[0046] Figure 11 shows another package substrate example 1100 that may be used to mount the package substrate example 110 of Figure 1. The package substrate example 1100 of Figure 11 is substantially the same as the package substrate example 200 of Figure 2, except as described below or otherwise evident from the context. Thus, features shown in Figure 11 that are the same or similar as the corresponding features in Figure 2 (and related Figures 3-10) are identified by the same reference numerals. Also, the feature descriptions described above in relation to Figure 2 (and related Figures 3-10) apply similarly to the corresponding features in Figure 11. The difference between the package substrate example 1100 of Figure 11 and the package substrate example 200 of Figure 2 is that it includes a different interconnect bridge example 1102. More specifically, as shown in Figure 11, the interconnect bridge example 1102 includes through-silicon vias (TSVs) 1104 that extend through the bridge and are electrically coupled to TGVs 222 in the glass cores 206, 208, 210, 212, and 214 of the substrate core 202 located below. In some examples, the TSVs 1104 can be connected to the power supply of the associated IC package (e.g., IC package 100 in Figure 1) to improve the power supply to the interconnect bridge 230 shown in Figure 2.

[0047] Figure 12 is a flowchart illustrating an example method for manufacturing one of the package substrate examples 110, 200, and 1100 shown in Figures 1, 2, and 11. In some examples, some or all of the operations outlined in the example method in Figure 12 are performed automatically by manufacturing equipment programmed to perform those operations. While the example manufacturing method is described with reference to the flowchart shown in Figure 12, numerous other methods may be used instead. For example, the execution order of blocks may be changed, and / or some of the blocks described may be combined, divided, rearranged, omitted, removed, and / or implemented in some other way. Also, in some examples, additional processing operations may be performed before, between, and / or after any of the blocks shown in the illustrated example.

[0048] The method example in Figure 12 begins in block 1202 by preparing a glass core (e.g., one of glass core examples 206, 208, 210, 212, 214) having a given coefficient of thermal expansion (CTE) (as described in relation to Figure 3, for example). In some examples, the composition of the material used for the glass core is selected to achieve the intended CTE for a particular glass layer within an entire substrate core (e.g., substrate core 202) containing multiple glass cores that are laminated together.

[0049] In block 1204, the method example includes determining whether to embed an interconnect bridge within the glass core. If so, the method proceeds to block 1206, where a cavity is provided within the glass core (for example, as described above in relation to Figure 8). The method then proceeds to block 1208. If there is no interconnect bridge to be embedded within the glass core (as determined in block 1204), the method proceeds directly to block 1208.

[0050] In block 1208, the example method includes adding a TGV (e.g., TGV222) that penetrates the glass core (as described, for example, in relation to Figure 4). In some examples, adding the TGV222 includes adding a contact pad 226 to the end of the TGV222.

[0051] In block 1210, the example method includes depositing an adhesive resin (e.g., dielectric material 220) on one or both of the outer surfaces of the glass core (as described, for example, in relation to Figures 5 and 6). In block 1212, the example method includes providing an additional conductive material (e.g., conductive material 224) that penetrates the adhesive resin to electrically couple with the TGV 220 (as described, for example, again in relation to Figures 5 and 6). In some examples, the additional conductive material is a liquid metal or paste that is dispensed into holes drilled through the dielectric resin. In other examples, the additional conductive material is plated into such holes.

[0052] In block 1214, the example method includes determining whether another glass core should be manufactured. If so, the method returns to block 1202 and repeats the process for the different glass core. In some examples, the different glass cores may consist of different CTEs. In some examples, the next glass core is manufactured independently of the glass cores manufactured up to that point. Thus, in some examples, separate iterations through the example process may be performed in parallel rather than sequentially.

[0053] When there are no more glass cores to manufacture, the method example proceeds to block 1216, which involves assembling the glass cores. In some examples, an adhesive resin (added in block 1210) is used to attach different glass cores together (as described, for example, in relation to Figures 6 and 8). In some examples, two or more glass cores are assembled (in block 1216) before it is decided (decided in block 1214) to manufacture additional glass cores. In some examples, at least some of the conductive material added in block 1212 can be added after the glass cores have been assembled in block 1216.

[0054] In block 1218, the method example includes placing an interconnect within a cavity (e.g., a cavity created within at least one glass core in block 1206). In block 1220, the method example includes determining whether build-up regions (e.g., build-up regions 130, 131, 204 in Figure 1 and / or Figure 2) should be added. If so, the method proceeds to block 1222, where (one or more) build-up regions are added (e.g., as described in relation to Figure 9). In some examples, the build-up regions are added by adding (e.g., laminating) one or more layers of dielectric material between layers of metal. In some examples, the dielectric layers are organic epoxy dielectrics laminated onto the glass core. The method then proceeds to block 1224. Returning to block 1220, if (one or more) build-up regions are not added, the method proceeds directly to block 1224.

[0055] In block 1224, the method example includes completing the package substrate. In some examples, this includes adding a solder resist layer (e.g., solder resist layers 232, 236 as described in relation to Figure 10). In addition, or alternatively, in some examples, completing the package substrate includes adding contacts (e.g., contacts 240, 242, 244) to the outer surface of the package substrate. The method example in Figure 12 then concludes.

[0056] The IC package example 100 disclosed herein (including any one of the package substrate examples 110, 200, and 1100) can be incorporated into any suitable electronic component. Figures 13–16 show various examples of devices that include or may include the IC package 100 disclosed herein.

[0057] Figure 13 is a top view of a wafer 1300 and die 1302 that may be included in the IC package 100 of Figure 1 (for example, as any preferred die among dies 106, 108). The wafer 1300 comprises a semiconductor material and one or more dies 1302 having circuits. Each die 1302 may be a repeating unit of a semiconductor product. After the manufacturing of the semiconductor product is complete, the wafer 1300 may undergo a fragmentation process in which the dies 1302 are separated from each other to provide individual “chips”. The die 1302 includes one or more transistors (for example, some of the transistors 1440 in Figure 14 described below), support circuits for routing electrical signals to the transistors, passive components (for example, traces, resistors, capacitors, inductors, and / or other circuits), and / or any other components. In some examples, die 1302 may include and / or implement memory devices (e.g., random access memory (RAM) devices such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM®) devices, conductive bridging RAM (CBRAM) devices, etc.), logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuits or electronics. Multiple of these devices may be combined on a single die 1302. For example, a memory array of multiple memory circuits may be formed on the same die 1302 as a programmable circuit (e.g., processor circuit 1602 in Figure 16) and / or other logic circuits. Such memory may store information for use by the programmable circuit. The IC package example 100 disclosed herein may be manufactured using die-to-wafer assembly technology, in which some dies are mounted on a wafer 1300 containing other dies, and then the wafer 1300 is sectionalized.

[0058] Figure 14 is a side cross-sectional view of an IC device 1400 that may be included in one of the IC package examples 100 disclosed herein (e.g., any of dies 106 or 108). One or more of the IC devices 1400 may be included in one or more dies 1302 (Figure 13). The IC device 1400 may be formed on a die substrate 1402 (e.g., wafer 1300 in Figure 13) and may be included in a die (e.g., die 1302 in Figure 13). The die substrate 1402 may be a semiconductor substrate containing a semiconductor material including, for example, an n-type or p-type material system (or a combination of both). The die substrate 1402 may include, for example, a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In some examples, the die substrate 1402 may be formed using alternative materials that may or may not be combined with silicon, and such alternative materials may include, but are not limited to, germanium, indium antimony, lead telluride, indium arsenide, indium phosphorus, gallium arsenide, or gallium antimony. Further materials classified as Group II-VI, Group III-V, or Group IV may also be used to form the die substrate 1402. A few examples of materials on which the die substrate 1402 can be formed are described here, but any material that can function as the basis for the IC device 1400 may be used. The die substrate 1402 may be part of a detached die (e.g., die 1302 in Figure 13) or a wafer (e.g., wafer 1300 in Figure 13).

[0059] The IC device 1400 may include one or more device layers 1404 disposed on and / or on the die substrate 1402. The device layer 1404 may include features of one or more transistors 1440 (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)) formed on the die substrate 1402. The device layer 1404 may include, for example, one or more source and / or drain (S / D) regions 1420, a gate 1422 for controlling the current between the S / D regions 1420, and one or more S / D contacts 1424 for routing electrical signals to and from the S / D regions 1420. The transistor 1440 may include further features not shown for clarity, such as element isolation regions and gate contacts. The transistor 1440 is not limited to the type and configuration shown in Figure 14 and may include a wide variety of other types and / or configurations, such as planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include, for example, FinFET transistors such as double-gate transistors or tri-gate transistors, as well as wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors.

[0060] Each transistor 1440 may include a gate 1422 comprising a gate dielectric and a gate electrode. The gate dielectric may include one or more layers in a stack. These one or more layers may include silicon oxide, silicon dioxide, silicon carbide, and / or high-k dielectric material. High-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and / or zinc. Examples of high-k materials that can be used for the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, aluminum lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and / or lead zinc niobate. In some cases, when high-k materials are used, an annealing process may be performed on the gate dielectric to improve its quality.

[0061] The gate electrode can be formed on the gate dielectric and may include at least one p-type work function metal or an n-type work function metal, depending on whether the transistor 1440 is a p-type metal-oxide-semiconductor (PMOS) transistor or an n-type metal-oxide-semiconductor (NMOS) transistor. In some implementations, the gate electrode may include a stack of two or more metal layers, one or more of which are work function metal layers and at least one which is a filler metal layer. Further metal layers, such as a barrier layer, may also be included. In PMOS transistors, the metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and / or any of the metals described later with reference to NMOS transistors (e.g., with respect to work function tuning). In NMOS transistors, the metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and / or aluminum carbide), and / or any of the metals mentioned above with reference to PMOS transistors (e.g., with respect to work function tuning).

[0062] In some examples, when viewed as a cross-section of transistor 1440 along the source-channel-drain direction, the gate electrode may include a U-shaped structure comprising a bottom substantially parallel to the surface of the die substrate 1402 and two sidewalls substantially perpendicular to the top surface of the die substrate 1402. In other examples, at least one of the metal layers forming the gate electrode may be a planar layer substantially parallel to the top surface of the die substrate 1402 and not comprising sidewalls substantially perpendicular to the top surface of the die substrate 1402. In other examples, the gate electrode may include a combination of a U-shaped structure and / or a planar non-U-shaped structure. For example, the gate electrode may include one or more U-shaped metal layers formed on one or more planar non-U-shaped layers.

[0063] In some examples, a pair of sidewall spacers may be formed on the sides of the gate stack, flanking the gate stack. The sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and / or silicon oxynitride. The process for forming the sidewall spacers is well known in the art and generally involves deposition and etching processes. In some examples, multiple pairs of spacers may be used; for example, two, three, or four pairs of sidewall spacers may be formed on both sides of the gate stack.

[0064] The S / D region 1420 may be formed in the die substrate 1402 adjacent to the gate 1422 of the corresponding (one or more) transistors 1440. The S / D region 1420 may be formed, for example, using an ion implantation / diffusion process or an etching / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic may be ion-implanted into the die substrate 1402 to form the S / D region 1420. An annealing process may follow the ion implantation process to activate the dopants and further diffuse them into the die substrate 1402. In the latter process, the die substrate 1402 may first be etched to form a recess at the location of the S / D region 1420. Then, an epitaxial deposition process may be performed to fill the recess with the material used to manufacture the S / D region 1420. In some implementations, the S / D region 1420 may be manufactured using a silicon alloy such as silicon germanium or silicon carbide. In some examples, the epitaxially deposited silicon alloy may be in situ doped with dopants such as boron, arsenic, or phosphorus. In some examples, the S / D region 1420 may be formed using one or more alternative semiconductor materials such as germanium or III-V material or alloy. In further examples, one or more layers of metal and / or metallic alloy may be used to form the S / D region 1420.

[0065] For example, electrical signals such as power and / or input / output (I / O) signals can be routed to and from devices on device layer 1404 (e.g., transistor 1440) through one or more interconnect layers (shown as interconnect layers 1406-1410 in Figure 14) located on device layer 1404. For example, conductive features on device layer 1404 (e.g., gate 1422 and S / D contact 1424) can be electrically coupled to interconnect structures 1428 of interconnect layers 1406-1410. One or more interconnect layers 1406-1410 can form a metallization stack (also referred to as an "ILD stack") 1419 of IC device 1400.

[0066] The interconnect structure 1428 can be configured within the interconnect layers 1406-1410 to route electrical signals according to a wide variety of designs (in particular, its configuration is not limited to the interconnect structure 1428 in the specific configuration depicted in Figure 14). Although Figure 14 depicts a specific number of interconnect layers 1406-1410, examples of the present disclosure include IC devices with more or fewer interconnect layers than those depicted.

[0067] In some examples, the interconnect structure 1428 may include lines 1428a and / or vias 1428b filled with a conductive material, such as metal. Lines 1428a may be configured to route electrical signals in a plane substantially parallel to the surface of the die substrate 1402 on which the device layer 1404 is formed. For example, lines 1428a may route electrical signals in and / or out of the plane of the paper from the viewpoint of Figure 14. Vias 1428b may be configured to route electrical signals in a plane substantially perpendicular to the surface of the die substrate 1402 on which the device layer 1404 is formed. In some examples, vias 1428b may electrically couple lines 1428a of different interconnect layers 1406-1410 together.

[0068] The interconnect layers 1406-1410 may include dielectric material 1426 disposed between interconnect structures 1428, as shown in Figure 14. In some examples, the dielectric material 1426 disposed between interconnect structures 1428 in different layers of the interconnect layers 1406-1410 may have different compositions, while in other examples, the composition of the dielectric material 1426 between different interconnect layers 1406-1410 may be the same.

[0069] The first interconnect layer 1406 (referred to as metal 1 or “M1”) may be formed directly on the device layer 1404. In some examples, the first interconnect layer 1406 may include lines 1428a and / or vias 1428b, as shown in the figure. Lines 1428a of the first interconnect layer 1406 may be coupled to contacts of the device layer 1404 (e.g., S / D contacts 1424).

[0070] The second interconnect layer 1408 (referred to as Metal 2 or “M2”) may be formed directly on the first interconnect layer 1406. In some examples, the second interconnect layer 1408 may include vias 1428b for connecting lines 1428a of the second interconnect layer 1408 to lines 1428a of the first interconnect layer 1406. For clarity, lines 1428a and vias 1428b are structurally contoured by lines within each interconnect layer (e.g., within the second interconnect layer 1408), although lines 1428a and vias 1428b may, in some examples, be structurally and / or materially continuous (e.g., filled simultaneously during a dual damascene process).

[0071] A third interconnect layer 1410 (referred to as metal 3 or “M3”) (and, if applicable, additional interconnect layers) may be formed successively on the second interconnect layer 1408, in accordance with the same techniques and / or configurations described in relation to the second interconnect layer 1408 or the first interconnect layer 1406. In some examples, “higher” interconnect layers (i.e., further away from device layer 1404) in the metallization stack 1419 within the IC device 1400 can be thicker.

[0072] The IC device 1400 may include a solder resist material 1434 (e.g., polyimide or similar material) formed on interconnect layers 1406-1410 and one or more conductive contacts 1436. In Figure 14, the conductive contacts 1436 are shown as bond pads. The conductive contacts 1436 may be electrically coupled to the interconnect structure 1428 and configured to route electrical signals from (one or more) transistors 1440 to other external devices. For example, solder bonds may be formed on one or more conductive contacts 1436 to mechanically and / or electrically couple a chip containing the IC device 1400 to another component (e.g., a circuit board). The IC device 1400 may include additional or alternative structures for routing electrical signals from the interconnect layers 1406-1410; for example, the conductive contacts 1436 may include other similar features (e.g., posts) for routing electrical signals to external components.

[0073] Figure 15 is a side cross-sectional view of an IC device assembly 1500 which may include the IC package 100 disclosed herein. In some examples, the IC device assembly corresponds to the IC package 100. The IC device assembly 1500 includes a number of components arranged on a circuit board 1502 (which may be, for example, a motherboard). The IC device assembly 1500 includes components arranged on a first surface 1540 of the circuit board 1502 and a second opposite surface 1542 of the circuit board 1502, and generally, components may be arranged on one or both of surfaces 1540 and 1542. Any of the IC packages described later with reference to the IC device assembly 1500 may take the form of the IC package example 100 shown in Figure 1.

[0074] In some examples, the circuit board 1502 may be a printed circuit board (PCB) comprising multiple metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. One or more of the metal layers may be formed with a desired circuit pattern for routing electrical signals (optionally together with other metal layers) between components coupled to the circuit board 1502. In other examples, the circuit board 1502 may be a non-PCB package substrate.

[0075] The IC device assembly 1500 shown in Figure 15 may include a package-on-interposer structure 1536 coupled to a first surface 1540 of a circuit board 1502 by a coupling component 1516. The coupling component 1516 can electrically and mechanically couple the package-on-interposer structure 1536 to the circuit board 1502 and may also include solder balls (as shown in Figure 15), male and female sockets, adhesive, underfill material, and / or any other suitable electrical and / or mechanical coupling structures.

[0076] The package-on-interposer structure 1536 may include an IC package 1520 coupled to an interposer 1504 by a coupling component 1518. The coupling component 1518 can take any form suitable for the application, such as the form described above with reference to coupling component 1516. Although one IC package 1520 is shown in Figure 15, multiple IC packages may be coupled to the interposer 1504, and in fact, additional interposers may be coupled to the interposer 1504. The interposer 1504 can provide an intervening substrate used to bridge the circuit board 1502 and the IC package 1520. The IC package 1520 may be, for example, a die (die 1302 in Figure 13), an IC device (e.g., IC device 1400 in Figure 14), or any other suitable component, or may include such a component. Generally, the interposer 1504 can spread connections to a wider pitch or reroute connections to different connections. For example, the interposer 1504 may couple an IC package 1520 (e.g., a die) to a set of BGA conductive contacts of a coupling component 1516 for coupling to a circuit board 1502. In the example shown in Figure 15, the IC package 1520 and the circuit board 1502 are mounted on opposite sides of the interposer 1504, while in other examples, the IC package 1520 and the circuit board 1502 may be mounted on the same side of the interposer 1504. In some examples, three or more components may be interconnected by the interposer 1504.

[0077] In some examples, the interposer 1504 may be formed as a PCB comprising multiple metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. In some examples, the interposer 1504 may be formed of epoxy resin, glass fiber reinforced epoxy resin, epoxy resin with inorganic fillers, ceramic material, or polymer material such as polyimide. In some examples, the interposer 1504 may be formed of another rigid or flexible material, which may include the same materials used for semiconductor substrates as described above, such as silicon, germanium, other Group IV materials, and Group III-V materials. The interposer 1504 may include, but is not limited to, metal interconnects 1508 and vias 1510, including through-silicon vias (TSVs) 1506. The interposer 1504 may further include embedded devices 1514, which may include both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices, such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and micro-electromechanical systems (MEMS) devices, may also be formed on the interposer 1504. The package-on-interposer structure 1536 may take any form of package-on-interposer structure known in the art.

[0078] The IC device assembly 1500 may include an IC package 1524 coupled to the first surface 1540 of the circuit board 1502 by a coupling component 1522. The coupling component 1522 can take any form of the examples described above with reference to the coupling component 1516, and the IC package 1524 can take any form of the examples described above with reference to the IC package 1520.

[0079] The IC device assembly 1500 shown in Figure 15 includes a package-on-package structure 1534 coupled to a second surface 1542 of a circuit board 1502 by a coupling component 1528. The package-on-package structure 1534 may include a first IC package 1526 and a second IC package 1532 coupled together by a coupling component 1530 such that the first IC package 1526 is positioned between the circuit board 1502 and the second IC package 1532. The coupling components 1528 and 1530 can take any form of the examples of coupling components 1516 described above, and the IC packages 1526 and 1532 can take any form of the examples of IC packages 1520 described above. The package-on-package structure 1534 may be configured according to any package-on-package structure known in the art.

[0080] Figure 16 is a block diagram of an example electrical device 1600 which may include one or more of the example IC packages 100. For example, any preferred components of the electrical device 1600 may include one or more of the device assemblies 1500, IC devices 1400, or dies 1302 disclosed herein, which may be placed within an example IC package 100. Although several components are shown to be included in the electrical device 1600, one or more of these components may be omitted or repeated as appropriate for the application. In some examples, some or all of the components included in the electrical device 1600 may be mounted on one or more motherboards. In some examples, some or all of these components are manufactured on a single system-on-a-chip (SOC) die.

[0081] Furthermore, in various embodiments, the electrical device 1600 may not include one or more of the components shown in Figure 16, but may include interface circuits for coupling to such one or more components. For example, the electrical device 1600 may not include the display 1606, but may include a display interface circuit (e.g., a connector and a drive circuit) to which the display 1606 can be coupled. In another set of examples, the electrical device 1600 may not include the audio input device 1618 (e.g., a microphone) or the audio output device 1608 (e.g., a speaker, headset, earphone, etc.), but may include an audio input or output device interface circuit (e.g., a connector and a support circuit) to which the audio input device 1618 or the audio output device 1608 can be coupled.

[0082] The electrical device 1600 may include a programmable circuit 1602 (e.g., one or more processing devices). The programmable circuit 1602 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (special processors that execute cryptographic algorithms in hardware), server processors, or other suitable processing devices. The electrical device 1600 may include a memory 1604 which itself may include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or hard drives. In some examples, the memory 1604 may include memory that shares a die with the programmable circuit 1602. This memory can be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin-transfer torque magnetic random access memory (STT-MRAM).

[0083] In some examples, the electrical device 1600 may include a communication chip 1612 (e.g., one or more communication chips). For example, the communication chip 1612 may be configured to manage wireless communication for the transmission of data to and from the electrical device 1600. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can transmit data over a non-solid medium using modulated electromagnetic radiation. This term does not mean that the devices in question do not include any wires, although in some examples they may not include any wires.

[0084] The communication chip 1612 may implement any of the many wireless standards or protocols. These wireless standards or protocols include, but are not limited to, WiFi (IEEE 802.11 family), IEEE standards including the IEEE 802.16 standard (e.g., IEEE 802.16-2005 amendment), the Long-Term Evolution (LTE) project and its amendments, updates and / or revisions (e.g., the Advanced LTE project), the Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc. Broadband wireless access (BWA) networks compliant with IEEE 802.16 are commonly referred to as WiMAX networks, an acronym for Worldwide Interoperability for Microwave Access, which is a certification mark for products that have passed conformity and interoperability testing of the IEEE 802.16 standard. The communication chip 1612 may operate in accordance with Global System for Mobile Communications (GSM; registered trademark), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High-Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE networks. The communication chip 1612 may also operate in accordance with Enhanced Data Rate for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Telescopic Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 1612 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO), and their derivatives, as well as other radio protocols designated as 3G, 4G, 5G, and later. In other examples, the communication chip 1612 may operate in accordance with other radio protocols.The electrical device 1600 may include an antenna 1622 for supporting and / or receiving other wireless communications (e.g., AM or FM radio transmissions).

[0085] In some examples, the communication chip 1612 may manage wired communication, such as electrical, optical, or other suitable communication protocols (e.g., Ethernet®). As described above, the communication chip 1612 may include multiple communication chips. For example, a first communication chip 1612 may be used for shorter-range wireless communication, such as Wi-Fi® and / or Bluetooth®, and a second communication chip 1612 may be used for longer-range wireless communication, such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, or others. In some examples, the first communication chip 1612 may be used for wireless communication and the second communication chip 1612 for wired communication.

[0086] The electrical device 1600 may include a battery / power circuit 1614. The battery / power circuit 1614 may include a circuit for connecting components of the electrical device 1600 to one or more energy storage devices (e.g., batteries or capacitors) and / or an energy source separate from the electrical device 1600 (e.g., AC line power).

[0087] The electrical device 1600 may include a display 1606 (or, as described above, a corresponding interface circuit). The display 1606 may include any visual indicator, such as a head-up display, computer monitor, projector, touchscreen display, liquid crystal display (LCD), light-emitting diode display, or flat panel display.

[0088] The electrical device 1600 may include an audio output device 1608 (or, as described above, a corresponding interface circuit). The audio output device 1608 may include any device that generates an audible indicator, such as a speaker, headphones, or earphones.

[0089] The electrical device 1600 may include an audio input device 1618 (or, as described above, a corresponding interface circuit). The audio input device 1618 may include any device that generates a sound signal representation, such as a microphone, a microphone array, or a digital instrument (e.g., an instrument with a MIDI (musical instrument digital interface; MIDI) output).

[0090] The electrical device 1600 may include a GPS circuit 1616. The GPS circuit 1616 is capable of communicating with a satellite-based system and can receive the position of the electrical device 1600 as is technically known.

[0091] The electrical device 1600 may include any other output device 1610 (or, as described above, a corresponding interface circuit). Examples of other output devices 1610 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or further storage devices.

[0092] The electrical device 1600 may include any other input device 1620 (or, as described above, a corresponding interface circuit). Examples of other input devices 1620 may include an accelerometer, gyroscope, compass, image capture device, keyboard, cursor control device such as a mouse, stylus, touchpad, barcode reader, quick response (QR) code reader, any sensor, or radio frequency identification (RFID) reader.

[0093] The electrical device 1600 may have any desired form factor, such as a handheld or mobile electrical device (e.g., a mobile phone, smartphone, mobile internet device, music player, tablet computer, laptop computer, netbook computer, ultrabook computer, personal digital assistant (PDA), ultramobile personal computer, etc.), a desktop electrical device, a server or other networked computing component, a printer, scanner, monitor, set-top box, entertainment control unit, vehicle control unit, digital camera, digital video recorder, or wearable electrical device. In some examples, the electrical device 1600 may also be any other computing device that processes data.

[0094] The terms “contain” and “have” (and all their forms and tenses) are used here as open-ended terms. Therefore, whenever a claim uses any form of “contain” or “have” (e.g., have, contain, possess, contained, had, etc.) as a preamble to or within any kind of claim statement, it should be understood that additional elements, clauses, etc., may exist without deviating from the scope of the corresponding claim or statement. When used here, the phrase “at least” is open-ended, for example, when used as a transitional clause in the claim preamble, just as the terms “have” and “contain” are open-ended. For example, the term “and / or” when used in the form A, B, and / or C refers to any combination or subset of A, B, and C, such as (1) A alone, (2) B alone, (3) C alone, (4) A and B, (5) A and C, (6) B and C, or (7) A, B, and C. When used herein in a context describing a structure, component, item, object, and / or thing, the phrase “at least one of A and B” is intended to refer to an implementation that includes (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, when used herein in a context describing a structure, component, item, object, and / or thing, the phrase “at least one of A or B” is intended to refer to an implementation that includes (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. When used herein in a context describing a process, instruction, action, activity, etc., or the execution thereof, the phrase “at least one of A and B” is intended to refer to an implementation that includes (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.Similarly, when used herein in a context describing the performance or execution of a process, command, action, activity, etc., the phrase “at least one of A or B” is intended to refer to an implementation that includes (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.

[0095] Where used herein, singular references (e.g., “a,” “an,” “first,” “second,” etc.) do not exclude plurals. Where used herein, the term “a” or “an” object refers to one or more of those objects. The terms “a” (or “an”), “one or more,” and “at least one” are used interchangeably here. Furthermore, even if listed individually, multiple means, elements, or actions may be implemented, for example, by the same entity or object. In addition, individual features may be included in different examples or claims, but these may be combined in some cases, and inclusion in different examples or claims does not mean that the combination of features is not feasible and / or advantageous.

[0096] As used herein, unless otherwise specified, the term “above” describes the relationship between the two parts to the Earth. The first part is above the second part if the second part has at least one part between the Earth and the first part. Similarly, as used herein, the first part is “below” the second part if the first part is closer to the Earth than the second part. As described above, the first part can be above or below the second part in one or more of the following conditions: there is another part between them, there is no other part between them, the first and second parts are in contact, or the first and second parts are not in direct contact with each other.

[0097] Notwithstanding the foregoing, when referring to semiconductor devices under construction or production (e.g., transistors), semiconductor dies containing semiconductor devices, and / or integrated circuit (IC) packages containing semiconductor dies, “on” is not relative to the earth, but rather to the substrate on which the components in question are fabricated, assembled, mounted, supported, or otherwise provided. Thus, as used herein, unless otherwise noted or indicated by the context, a first component in a semiconductor die (e.g., a transistor or other semiconductor device) is “on” a second component in a semiconductor die when, during manufacturing / production, the first component is further from the substrate (e.g., a semiconductor wafer) on which the two components are fabricated or otherwise provided than the second component. Similarly, unless otherwise noted or indicated by the context, a first component in an IC package (e.g., a semiconductor die) is “on” a second component in an IC package when, during manufacturing / production, the first component is further from the printed circuit board (PCB) on which the IC package is mounted or attached. It should be understood that semiconductor devices are often used in a orientation different from the orientation in which they were manufactured. Therefore, when referring to semiconductor devices (e.g., transistors), semiconductor dies containing semiconductor devices, and / or integrated circuit (IC) packages containing semiconductor dies in use, the definition of “above” in the previous paragraph (i.e., that the term “above” describes the relationship between two parts relative to the earth) may be governed by the context of use.

[0098] When used in this patent, any statement that any part (e.g., a layer, film, area, region, or plate) is in any way on another part (e.g., positioned on, located on, placed on, or formed on) indicates either that the part in question is in contact with the other part, or that the part in question is above the other part and one or more intermediate parts are located between them.

[0099] When used herein, references to connections (e.g., attached, joined, connected, and joined) may include intermediate members between the elements referred to by the reference to connections and / or relative movement between those elements, unless otherwise specified. Thus, a reference to a connection does not necessarily mean that two elements are directly connected and / or are in a fixed relationship with one another. When used herein, the statement that any part is "in contact" with another part is defined to mean that there is no intermediate part between those two parts.

[0100] Unless otherwise specified, descriptors such as “first,” “second,” and “third” are used here without any implication or indication of any meaning of priority, physical order, placement in a list, and / or ordering, but merely as labels and / or arbitrary names to distinguish elements for the sake of clarity in the disclosed examples. In some examples, the descriptor “first” may be used to refer to an element in the detailed description, but the same element may be referred to in the claims using different descriptors such as “second” or “third.”

[0101] When used herein, “approximately” and “about” modify the subject / value to acknowledge the potential existence of variations that may occur in real-world applications. For example, “approximately” and “about” may modify dimensions that may not be precise due to manufacturing tolerances and / or other real-world imperfections, as understood by those skilled in the art. For example, “approximately” and “about” may indicate that such dimensions may be within a tolerance of + / - 10%, unless otherwise specified herein.

[0102] When used here, "virtually real-time" refers to an event occurring in a nearly instantaneous manner, acknowledging that real-world delays such as computation time and transmission may exist. Therefore, unless otherwise specified, "virtually real-time" means real-time plus 1 second.

[0103] As used herein, the phrase “communicate,” including its variations, encompasses direct communication and / or indirect communication via one or more intermediate components, and does not require direct physical (e.g., wired) communication and / or continuous communication, but rather further includes selective communication at periodic intervals, scheduled intervals, aperiodic intervals, and / or one-off events.

[0104] As used herein, “programmable circuit” is defined to include (i) one or more dedicated electrical circuits (e.g., application-specific circuits (ASICs)) configured to perform a specific (one or more) operation and comprising one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), and / or (ii) one or more general-purpose semiconductor-based electrical circuits that are programmable with instructions to perform a specific (one or more) function and / or (one or more) operation and comprising one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuits include, for example, a programmable microprocessor such as a central processor unit (CPU) capable of executing a first instruction to perform one or more operations and / or functions; a field-programmable gate array (FPGA) that can be programmed with a second instruction to produce an FPGA configuration and / or structuring to instantiate one or more operations and / or functions corresponding to a first instruction; a graphics processor unit (GPU) capable of executing a first instruction to perform one or more operations and / or functions; a digital signal processor (DSP), XPU, network processing unit (NPU) capable of executing a first instruction to perform one or more operations and / or functions; one or more microcontrollers capable of executing a first instruction to perform one or more operations and / or functions; and / or integrated circuits such as application-specific integrated circuits (ASICs). For example, an XPU may be implemented by a heterogeneous computing system that includes multiple types of programmable circuits (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, and / or any combination thereof) and orchestration techniques (e.g., one or more application programming interfaces (APIs)) that allow one or more computing tasks to be assigned to one or more of the multiple types of programmable circuits that are suitable and available for performing said computing tasks.

[0105] As used herein, an integrated circuit (circuit / circuitry) is defined as one or more semiconductor packages containing one or more circuit elements, such as transistors, capacitors, inductors, resistors, current paths, and diodes. For example, an integrated circuit can be implemented as one or more of the following: an ASIC, FPGA, chip, microchip, programmable circuit, semiconductor substrate combining multiple circuit elements, or a system-on-a-chip (SoC).

[0106] From the above, it can be understood that examples of systems, apparatus, products, and methods are disclosed that include a package substrate containing a substrate core comprising a substrate core comprising a stack of individual glass layers or glass cores having different CTEs. These different CTEs define a CTE gradient that reduces stress within the package substrate, and in particular mitigates seware known to occur in substrates having a single solid glass core with a single CTE. As a result, the examples disclosed herein improve yield losses in the manufacture of package substrates and improve the reliability and / or useful life of IC packages compared to known techniques. Furthermore, the examples disclosed herein include an interconnect bridge embedded within such a substrate core (e.g., within one or more glass layers in a stack of glass cores). Embedding the interconnect bridge with the glass core can provide die interconnects without the need for a thick build-up area on top of the package substrate. Reducing and / or eliminating the need for a build-up area outside the substrate core is achieved by metallization between different layers in the stack of glass cores, which acts as a redistribution layer for the package substrate.

[0107] Further examples and combinations thereof include the following:

[0108] Example 1 includes a substrate for an integrated circuit package, the substrate having a first glass layer in which a cavity is defined, a second glass layer different from the first glass layer, and an interconnect bridge at least partially located within the cavity for electrically coupling a first semiconductor die to a second semiconductor die.

[0109] Example 2 includes the substrate of Example 1, wherein the first glass layer has a first coefficient of thermal expansion (CTE), and the second glass layer has a second CTE, the second CTE being different from the first CTE.

[0110] Example 3 includes the substrate of Example 2, further comprising a third glass layer having a third CTE.

[0111] Example 4 includes a substrate according to any one of Examples 1 to 3, wherein the interconnect bridge contains silicon.

[0112] Example 5 includes a substrate according to any one of Examples 1 to 4, wherein the first glass layer is closer to the first semiconductor die than the second glass layer, and the interconnect bridge includes a silicon through-via for electrically connecting the first semiconductor die to a glass through-via in the second glass layer.

[0113] Example 6 includes a substrate according to any one of Examples 1 to 5, wherein the first glass layer has a first surface facing the first semiconductor die, and the interconnect bridge has a second surface facing the first semiconductor die, the second surface being substantially coplanar with the first surface.

[0114] Example 7 includes a substrate according to any one of Examples 1 to 6, wherein the first glass layer has a first thickness, and the interconnect bridge has a second thickness, the second thickness being approximately equal to the first thickness.

[0115] Example 8 includes a substrate according to any one of Examples 1 to 6, wherein the first glass layer has a first thickness and the interconnect bridge has a second thickness, the second thickness being smaller than the first thickness.

[0116] Example 9 includes a substrate according to any one of Examples 1 to 6, wherein the first glass layer has a first thickness, and the interconnect bridge has a second thickness, the second thickness being greater than the first thickness.

[0117] Example 10 includes a substrate according to any one of Examples 1 to 9, wherein the first glass layer is separated from the second glass layer.

[0118] Example 11 includes any one of the substrates from Examples 1 to 10, further comprising a dielectric material between the first glass layer and the second glass layer.

[0119] Example 12 includes the substrate of Example 11, wherein the dielectric material has a lower modulus of elasticity than the first glass layer.

[0120] Example 13 includes any one of Examples 11 to 12, further comprising a redistribution layer containing a metal within the dielectric material.

[0121] Example 14 further includes a substrate from any one of Examples 1 to 13, wherein the substrate further includes a dielectric material in the cavity, the dielectric material at least partially surrounding the interconnect bridge.

[0122] Example 15 is an integrated circuit (IC) package comprising: a first semiconductor die; a second semiconductor die adjacent to the first semiconductor die; a package substrate including a stack of a plurality of glass layers; and an interconnect die in at least one of the plurality of glass layers, the first semiconductor die being electrically coupled to the second semiconductor die via the interconnect die.

[0123] Example 16 includes the IC package of Example 15, wherein different glass layers among the plurality of glass layers have different coefficients of thermal expansion (CTE).

[0124] Example 17 includes the IC package of Example 16, wherein the difference in the different CTEs corresponds to a gradual change in the CTE over a larger span of CTE values.

[0125] Example 18 includes an apparatus comprising: a first semiconductor chip; a second semiconductor chip; and a package substrate on which the first semiconductor chip and the second semiconductor chip are mounted, the package substrate including a separate glass sheet and a silicon-based bridge in an opening in at least the first glass sheet of the glass sheet, which electrically couples the first semiconductor chip and the second semiconductor chip.

[0126] Example 19 includes the apparatus of Example 18, wherein the first glass sheet among the glass sheets has a different coefficient of thermal expansion (CTE) than the second glass sheet among the glass sheets.

[0127] Example 20 includes the apparatus of either Example 18 or 19, wherein the first glass sheet among the glass sheets is separated from the second glass sheet among the glass sheets by an intervening layer of dielectric material.

[0128] The following claims are incorporated by this reference into this detailed description. While specific systems, apparatus, articles, and methods are disclosed herein, the scope of this patent is not limited to them. Rather, this patent extends to all systems, apparatus, articles, and methods that fairly fall within the scope of the claims herein.

Claims

1. A substrate for integrated circuit packages, A first glass layer with a cavity defined inside, A second glass layer different from the first glass layer, An interconnect bridge located at least partially within the cavity, which electrically couples the first semiconductor die to the second semiconductor die, A substrate.

2. The substrate according to claim 1, wherein the first glass layer has a first coefficient of thermal expansion (CTE), and the second glass layer has a second CTE, the second CTE being different from the first CTE.

3. The substrate according to claim 2, further comprising a third glass layer having a third CTE.

4. The substrate according to any one of claims 1 to 3, wherein the interconnect bridge comprises silicon.

5. The substrate according to any one of claims 1 to 3, wherein the first glass layer is closer to the first semiconductor die than the second glass layer, and the interconnect bridge includes through-silicon vias for electrically connecting the first semiconductor die to through-glass vias in the second glass layer.

6. The substrate according to any one of claims 1 to 3, wherein the first glass layer has a first surface facing the first semiconductor die, and the interconnect bridge has a second surface facing the first semiconductor die, the second surface being substantially coplanar with the first surface.

7. The substrate according to any one of claims 1 to 3, wherein the first glass layer has a first thickness, and the interconnect bridge has a second thickness, the second thickness being substantially equal to the first thickness.

8. The substrate according to any one of claims 1 to 3, wherein the first glass layer has a first thickness, and the interconnect bridge has a second thickness, the second thickness being smaller than the first thickness.

9. The substrate according to any one of claims 1 to 3, wherein the first glass layer has a first thickness, and the interconnect bridge has a second thickness, the second thickness being greater than the first thickness.

10. The substrate according to any one of claims 1 to 3, wherein the first glass layer is separated from the second glass layer.

11. The substrate according to any one of claims 1 to 3, further comprising a dielectric material between the first glass layer and the second glass layer.

12. The substrate according to claim 11, wherein the dielectric material has a lower elastic modulus than the first glass layer.

13. The substrate according to claim 11, further comprising a redistribution layer containing a metal within the dielectric material.

14. The substrate according to any one of claims 1 to 3, further comprising a dielectric material in the cavity, wherein the dielectric material at least partially surrounds the interconnect bridge.

15. An integrated circuit (IC) package, The first semiconductor die, A second semiconductor die adjacent to the first semiconductor die, A package substrate including a stack of multiple glass layers, An interconnect die located in at least one of the plurality of glass layers, wherein the first semiconductor die is electrically coupled to the second semiconductor die via the interconnect die, A large IC package.

16. The IC package according to claim 15, wherein different glass layers among the plurality of glass layers have different coefficients of thermal expansion (CTE).

17. The IC package according to claim 16, wherein the difference in the different CTEs corresponds to a gradual change in the CTE over a larger span of CTE values.

18. The first semiconductor chip, The second semiconductor chip, A package substrate on which the first semiconductor chip and the second semiconductor chip are mounted, A separate glass sheet, and A silicon-based bridge in an opening of at least the first glass sheet among the glass sheets, which electrically connects the first semiconductor chip and the second semiconductor chip. A package substrate including, A device having.

19. The apparatus according to claim 18, wherein the first glass sheet among the glass sheets has a different coefficient of thermal expansion (CTE) than the second glass sheet among the glass sheets.

20. The apparatus according to claim 18 or 19, wherein the first glass sheet among the glass sheets is separated from the second glass sheet among the glass sheets by an intervening layer of dielectric material.

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