Manufacturing process for silicon carbide power electronics devices with improved input capacitance definition

Abstract

This prevents oscillation in parallel configurations of MOSFET devices (vertically conductive power devices). [Solution] The power device 1 includes forming a body region 5 having a second electrical conductivity opposite to the first electrical conductivity within a body 2 containing a semiconductor material and having a first electrical conductivity, forming a source region 7 having a first electrical conductivity within the corresponding body region, forming a gate structure 4 consisting of an insulating gate region 41, a conductive gate region 42, and a passivation gate region 43, wherein the conductive gate region overlaps the source region of the corresponding adjacent body region, and forming a source metallization region 6 on the body and gate structure between adjacent gate structures, including a contact portion 61 with the corresponding source region. Forming the contact portion includes forming a spacer portion 44 on the gate structure and body.

Description

[Technical Field]

[0001] (Cross-reference of related applications) This application claims the benefit of priority of Italian Patent Application No. 102024000020143, filed on September 10, 2024, titled "PROCESSO DI FABBRICAZIONE PER DISPOSITIVI ELETTRONICI DI POTENZA IN CARBURO DI SILICIO AVENTE UNA MIGLIORATA DEFINIZIONE DELLA CAPACITA' DI INGRESSO DEGLI STESSI", which is incorporated herein by reference to the maximum extent permitted by law.

[0002] This disclosure relates to a manufacturing process for silicon carbide power electronics devices having an improved input capacitance definition. [Background technology]

[0003] As is well known, semiconductor materials having, for example, a wide bandgap greater than 1.1 eV, low on-state resistance, high thermal conductivity, high operating frequency, and high charge carrier saturation rate make it possible to obtain electronic devices such as diodes and transistors that have higher performance than silicon electronic devices, specifically with respect to power applications (i.e., with respect to operating voltages included between 600V and 1300V, or under specific operating conditions such as high temperature).

[0004] More specifically, it is well known that such electronic devices are obtained starting from wafers made of one of the polytypes of silicon carbide (SiC), distinguished by the properties listed above, such as 3C-SiC, 4H-SiC, and 6H-SiC. Power electronic devices that can be obtained using SiC-type semiconductors may be, for example, vertical conduction MOSFETs or JFET transistors.

[0005] In MOSFET devices, the input capacitance is primarily defined by the sum of the capacitance between the device's gate and source terminals (also called "gate-source capacitance") and the capacitance between the device's gate and drain terminals (also called "gate-drain capacitance"). The input capacitance dictates the device's dynamic behavior and affects its efficiency in a particular application. The achievable input capacitance value for a given device is primarily determined by the device's basic cell structure and onboard structure.

[0006] MOSFET devices for high-power applications, particularly SiC technology power devices such as power inverters, have multiple base cells, which are typically assembled in parallel to reduce the on-resistance of each inverter stage. Such configurations can cause ringing effects in the gate-source and drain-source waveforms during the device's switching phase (especially at power-up), mainly due to gate-source coupling.

[0007] To prevent oscillation in parallel configurations of MOSFET devices, a series of capacitors (e.g., one or more individual capacitors mounted on an electronic circuit board for a specific application) can be inserted in parallel into the gate-source capacitance and / or gate-drain capacitance of the device, with the aim of increasing its input capacitance. However, the introduction of such individual capacitors can have several drawbacks, including higher manufacturing costs, loss of efficiency, and increased complexity in managing the drive circuit. [Overview of the project]

[0008] Therefore, the purpose of this disclosure is to overcome, or at least partially mitigate, the shortcomings and limitations of the prior art.

[0009] According to this disclosure, a manufacturing process for silicon carbide power electronics devices is provided.

[0010] In one exemplary embodiment, a process for manufacturing a vertical conductive power device includes forming a body region having a second electrical conductivity opposite to a first electrical conductivity within a body containing a semiconductor material and having the first electrical conductivity, forming a source region having the first electrical conductivity within a corresponding body region, and forming a gate structure including an insulating gate region on the body, a conductive gate region on the insulating gate region, and a passivation gate region on the conductive gate region, wherein the conductive gate region is partially overlapped with the source region of a corresponding adjacent body region, forming a source metallization region on the body and on the gate structure, wherein the source metallization region includes a contact portion with a corresponding source region between adjacent gate structures, and forming the contact portion includes conformally forming a spacer dielectric layer on the gate structure and on the body, and anisotropically etching the spacer dielectric layer to the source region, forming a source metallization region.

[0011] In various embodiments, etching the spacer dielectric layer includes performing maskless etching.

[0012] In various embodiments, the passivation gate region of each gate structure is formed by a first dielectric selected from oxides, oxynitrides, or a combination of oxides or nitrides and oxynitrides.

[0013] In various embodiments, the spacer dielectric layer is formed by a second dielectric selected from oxides, oxynitrides, or a combination of oxides or nitrides and oxynitrides.

[0014] In various embodiments, the spacer dielectric layer has a minimum thickness equal to 0.2 μm and laterally covers the gate structure.

[0015] In various embodiments, forming the gate structure includes forming a gate conductive layer and patterning the gate conductive layer such that each resulting conductive gate region overlaps over a corresponding source region within a corresponding overlap region along a first direction, and the conductive gate regions of adjacent gate structures are separated by a distance along a second direction perpendicular to the first direction, and patterning the gate conductive layer such that the ratio of the distance to the pitch of the power device exhibits a value included between 0.4 and 0.9.

[0016] In various embodiments, etching the spacer dielectric layer includes defining a pair of spacer portions on the side surfaces of each gate structure.

[0017] In various embodiments, the pair of spacer portions seals the conductive gate region of each gate structure.

[0018] In various embodiments, the source region includes a corresponding body contact region, and each body contact region extends to a corresponding body region.

[0019] In various embodiments, the body includes a substrate and an epitaxial layer, the body region and the source region are formed within the epitaxial layer, and the semiconductor material contains silicon carbide.

[0020] In various embodiments, the substrate has a rear surface, and the process further includes forming a drain metallization region on the rear surface.

[0021] In one exemplary embodiment, a vertically conducting power device includes a body containing a semiconductor material and having a first electrical conductivity; a body region extending within the body and having a second electrical conductivity opposite to the first electrical conductivity; a source region extending within the corresponding body region and having the first electrical conductivity; a gate structure each including an insulated gate region on the body, a conductive gate region on the insulated gate region, and a passivation gate region on the conductive gate region, wherein the conductive gate region is partially overlapped along a first direction on the source region of a corresponding adjacent body region; and source metallization regions on the body and on the gate structure, including a contact portion with the corresponding source region between adjacent gate structures, wherein each gate structure includes a plurality of lateral spacer portions that contact the body and define the extent of the corresponding contact portion.

[0022] In various embodiments, each conductive gate region is superimposed on the corresponding source region within a corresponding overlapping region along a first direction, and the conductive gate regions of adjacent gate structures are separated by a certain distance along a second direction perpendicular to the first direction, the ratio of which distance to the pitch of the power device is a value between 0.4 and 0.9.

[0023] In various embodiments, a vertically conducting power device further comprises a source terminal electrically connected to a source metallization region and gate terminals electrically connected to each conductive gate region of a gate structure, wherein the power device has capacitance between the gate terminals and the source terminals that depends on the ratio of the distance to the pitch of the power device.

[0024] In various embodiments, the semiconductor material contains silicon carbide. [Brief explanation of the drawing]

[0025] To further understand this disclosure, preferred embodiments are provided as non-limiting examples with reference to the accompanying drawings. [Figure 1] A schematic cross-section of a power device according to one embodiment of this disclosure is shown. [Figure 2A] Figure 1 schematically shows a cross-section of the power device in a continuous manufacturing step of a manufacturing process according to one embodiment of the present disclosure. [Figure 2B] Figure 1 schematically shows a cross-section of the power device in a continuous manufacturing step of a manufacturing process according to one embodiment of the present disclosure. [Figure 2C] Figure 1 schematically shows a cross-section of the power device in a continuous manufacturing step of a manufacturing process according to one embodiment of the present disclosure. [Figure 2D] Figure 1 schematically shows a cross-section of the power device in a continuous manufacturing step of a manufacturing process according to one embodiment of the present disclosure. [Figure 2E] Figure 1 schematically shows a cross-section of the power device in a continuous manufacturing step of a manufacturing process according to one embodiment of the present disclosure. [Figure 3] These are simplified block diagrams related to the processes shown in Figures 2A to 2E. [Modes for carrying out the invention]

[0026] The following explanation refers to the arrangement shown in the drawing, and therefore, terms such as "upper," "lower," "top," "bottom," "summit," "bottom," "right," and "left" refer to the attached drawing and should not be interpreted restrictively.

[0027] A power device manufactured according to one embodiment of the present disclosure is partially shown in Figure 1, indicated by the number 1. Power device 1 is, for example, a MOSFET, more specifically a power MOSFET, and more specifically a vertical conduction MOSFET fabricated using silicon carbide (SiC) technology, and is housed in a die not shown in the accompanying figures. Therefore, hereafter, power device 1 will also be referred to as "MOSFET" interchangeably and without loss of generality.

[0028] Figure 1 shows MOSFET1 in cross-section in a reference frame of orthogonal axes X, Y, and Z.

[0029] MOSFET1 comprises multiple identical base cells (only one of which is shown in the attached diagram), which are arranged within the same die such that they share a drain terminal D, a gate terminal G, and a source terminal S; in other words, they are electrically connected in parallel with one another.

[0030] The MOSFET 1 is formed within a semiconductor material body 2. The body 2 is defined at the top by a front surface 2a and at the bottom by a rear surface 2b, on opposite sides along the Z-axis. The body 2 may include a substrate, i.e., a substrate on which one or more epitaxial layers are grown, and is made of silicon carbide, one of its polytypes, for example, 4H-SiC polytype. In one embodiment, specifically, the body 2 includes a substrate 21, at the bottom by a rear surface 2b, and an epitaxial layer 22 extending on the substrate 21 and at the top by a front surface 2a.

[0031] A drift region 3, a plurality of body regions 5 (two are shown in FIG. 1), and a plurality of source regions 7 (two are shown in FIG. 1) are formed in the epitaxial layer 22. The body 2 made of a semiconductor material, that is, the substrate 21, the drift region 3, and the source region 7 have a first electrical conductivity, for example, of the N type. The body regions 5 have a second electrical conductivity of the P type, which is opposite to the first electrical conductivity. Each body region 5 has a doping level, for example, included between 1·10 17 atoms / cm 3 ~1·10 20 atoms / cm 3 . Each source region 7 has a doping level, for example, included between 1·10 18 atoms / cm 3 ~1·10 20 atoms / cm 3 .

[0032] The body regions 5 extend into the body 2 starting from the front surface 2a and are separated from each other along the X axis by the surface portion 31 of the drift region 3. Each source region 7 extends into the body 2 starting from the front surface 2a and is embedded in the corresponding body region 5. Each basic cell of the MOSFET 1 includes at least one body contact region 51, which has the second electrical conductivity and extends from the front surface 2a to one of the body regions 5 through the corresponding source region 7. A channel region 52 is defined in the body region 5 between the corresponding source region 7 and the surface portion 31 of the drift region 3.

[0033] The body regions 5, the source regions 7, and the body contact regions 51 also extend along the Y axis and have, for example, a strip or ring shape in a top view (not shown here).

[0034] In the epitaxial layer 22 of the MOSFET 1, during use, that is, when the voltage (V GS ) between the gate terminal G and the source terminal S is the threshold voltage (V THWhen the current is greater than ), current can flow between the source terminal S and the drain terminal D through each channel region 52 and the drift region 3. The drift region 3 actually forms a drift layer of charge carriers during use.

[0035] MOSFET1 also includes a plurality of gate structures 4 positioned above the front surface 2a of the body 2. Each gate structure 4 includes an insulated gate region 41 (e.g., silicon oxide) in contact with the front surface 2a of the body 2, a conductive gate region 42 (e.g., made of polysilicon) directly superimposed on the insulated gate region 41, and a passivation gate region 43 (e.g., oxide) covering the conductive gate region 42 and sealing the conductive gate region 42 together with the insulated gate region 41. The conductive gate regions 42 of the gate structures 4 are electrically connected in parallel in a manner not shown herein to form the gate terminal G of MOSFET1. In one embodiment, specifically, with respect to each gate structure 4, the width (along the X axis) of the conductive gate region 42 (hereinafter referred to as the gate strip width L) substantially coincides with the width (along the X axis) of the insulated gate region 41.

[0036] The conductive gate region 42 of each gate structure 4 extends between the source regions 7 of a pair of adjacent body regions 5. More specifically, the conductive gate region 42 partially overlaps the source regions 7 of the two adjacent body regions 5 and extends over the channel region 52 and over the surface portion 31 of the drift region 3 contained between the source regions 7. More specifically, referring to a single basic cell shown in Figure 1, the projection (along the Z-axis) of the conductive gate region 42 onto the corresponding source region 7 present below defines a corresponding overlapping region 71 having a dimension along the X-axis, hereafter referred to as the overlap width s. The gate strip width L is greater than the overlap width s. Furthermore, the gate strip width L is, as a first-order approximation, equal to the sum of twice the overlap width s, twice the width of the corresponding channel region 52, and the width of the surface portion 31 of the drift region 3.

[0037] MOSFET1 also includes a source metallization region 6, made of, for example, a metallic material and / or metal silicide, which forms the source terminal S of MOSFET1 and extends onto the front surface 2a of body 2, in direct electrical contact with the source region 7 and the body contact region 51. The body contact region 51 is actually used to bias the body region 5 at the potential of the source terminal S.

[0038] Adjacent gate structures 4 within MOSFET 1 are separated by corresponding contact portions 61 of the source metallization region 6. More specifically, each contact portion 61 of the source metallization region 6 is in contact with and interposed between the passivation gate regions 43 of two adjacent gate structures 4. Furthermore, the contact portions 61 form electrical contacts with the corresponding source region 7 and body contact region 51. Hereafter, the width of each contact portion 61 along the X-axis at the interface with the corresponding source region 7 will be referred to as the contact width C, and is intended to be measured between the corresponding passivation gate regions 43 of the two adjacent gate structures 4 near the front surface 2a of the body 2.

[0039] As expected, the passivation gate region 43 of each gate structure 4 covers the corresponding conductive gate region 42 at its top and sides. More specifically, the passivation gate region 43 includes a spacer portion 44 that extends onto the sides of the corresponding insulated gate region 41 and conductive gate region 42, defining the extent of the corresponding contact portion 61 in the direction of the X axis. In other words, the spacer portion 44 is located on both sides (along the X axis) of the conductive gate region 42 of the gate structure 4. As will be described below, the spacer portion 44 may be of a different material (e.g., a different type of oxide) than the corresponding passivation gate region 43. The width of each spacer portion 44 along the X axis will hereafter be referred to as the spacer width t and is intended to be measured near the front surface 2a of the body 2.

[0040] Therefore, in MOSFET1, conductive gate regions 42 belonging to adjacent gate structures 4 are separated by a gate strip distance T that is equal to the sum of the spacer width t (referring to the spacer portion 44 of the gate structure 4), the contact width C of the intervening contact portion 61, and the spacer width t (referring to the spacer portion 44 of the other gate structure 4). More specifically, the sum of the gate strip width L and the gate strip distance T defines the pitch PT of MOSFET1, which is greater than 4 μm in current devices. The pitch PT represents the (along the X-axis) dimension of the basic cell of MOSFET1.

[0041] Finally, the MOSFET 1 includes a drain metallization region 8 made of a conductive material, such as metal or silicide, which is in direct electrical contact with the substrate 21 and extends onto the rear surface 2b of the body 2 (in the opposite direction to the source metallization region 6), forming the drain terminal D of the MOSFET 1.

[0042] The capacitance between the gate terminal G and source terminal S of MOSFET1 (also called "gate-source capacitance"), C GS The input capacitance (C) of the MOSFET1 is determined by the overlap width s of the overlap region 71 between the conductive gate region 42 and the corresponding source region 7. More specifically, the overlap width s is determined according to design preferences, based on the input capacitance (C) of the MOSFET1. IN ) are selected to define precisely and flexibly in relation to the desired target parameters and / or desired application. In MOSFET1, the larger the overlap width s, the greater the gate-source capacitance C GSThe value of becomes higher. Instead, the capacitance between the gate terminal G and the drain terminal D (also called the "gate-drain capacitance") is independent of the overlap width s. Furthermore, the overlap width s is selected for a given width (along the X axis) of the source region 7 without changing the pitch PT of MOSFET1, or more specifically, without changing the contact width C of the contact portion 61 of the source metallization region 6, as described below. In MOSFET1, reliable control of the device's dynamic behavior is achieved through the precise definition of the input capacitance, thereby preventing undesirable phenomena such as oscillation during the switching phase.

[0043] In fact, without changing the pitch PT of the MOSFET 1 and the contact width C of the contact portion 61 of the source metallization region 6, the present disclosure makes it possible to change the gate strip distance T between conductive gate regions 42 belonging to adjacent gate structures 4 according to design preferences in order to change the overlap width s with respect to a conventional device. More specifically, the gate-source capacitance C GS To increase the value of , given the pitch PT of MOSFET1, the gate strip width L of the conductive gate region 42 can be increased, and as a result the overlap width s can be increased. Consequently, in MOSFET1, the overlap width s changes by inversely changing the spacer width t of the spacer portion 44 of the corresponding passivation gate region 43. Therefore, if the contact width C of the contact portion 61 remains the same, when the overlap width s is maximized, the spacer width t is minimized accordingly.

[0044] More specifically, the gate-source capacitance C GS , and finally the input capacitance C of MOSFET1 IN This correlates with the difference between the pitch PT and the gate strip distance T between adjacent conductive gate regions 42 belonging to the gate structure 4. When the gate strip distance T approaches zero in the limit, the input capacitance C IN The maximum limit value C IN TThe effective minimum value C is obtained by selecting the corresponding value of the overlap width s of the overlapping region 71. IN MIN and effective maximum value C IN MAX Between, input capacitance C IN You can choose this option.

[0045] Therefore, the input capacitance C of MOSFET1 IN The value of is obtained as a function of the ratio of the gate strip distance T to the pitch PT of MOSFET1, and this ratio, in the case of MOSFET1, exhibits a value that falls between 0.4 and 0.9. Specifically, C IN MIN and C IN MAX The value of is given by: C IN MIN =40%·C IN T , and C IN MAX =90%·C IN T .

[0046] The applicant has provided an input capacitance C that is 20% larger than that of a MOSFET having the same contact width C as the contact portion 61 of the source metallization region 6. IN We verified that it is possible to obtain the maximum effective value.

[0047] MOSFET1 in Figure 1 can be obtained by the manufacturing process described below with reference to Figures 2A to 2E and the flowchart in Figure 3.

[0048] Figure 2A shows a cross-section of a silicon carbide wafer 100 (e.g., 4H-SiC polytype) having a first electrical conductivity (N-type). The wafer 100 is defined at the top by the front surface 2a and at the bottom by the rear surface 2b, and initially contains a substrate 21 on which an epitaxial layer 22 is formed by epitaxial growth, having a thickness along the Z axis that is, for example, between 1 μm and 100 μm (first step S1).

[0049] Body regions 5, body contact regions 51, and source regions 7 are formed within the epitaxial layer 22 of the wafer 100 using a specific mask (not shown) on the front surface 2a (second step S2). Each body region 5 extends from the front surface 2a to a depth of, for example, 1 μm and has a width (along the X-axis) of, for example, 3 μm. Each source region 7 extends from the front surface 2a into the corresponding body region 5 to a depth of, for example, 0.4 μm and has a width (along the X-axis) of, for example, 2.4 μm, the width of which is set according to a design preference for the power performance of the MOSFET 1, for example. Each body contact region 51 extends from the front surface 2a into the corresponding body region 5 to a depth greater than or equal to the depth of the source region 7, for example, 0.4 μm and has a width (along the X-axis) of, for example, 1 μm. The N+ type source regions 7 typically have a doping higher than the doping of the wafer 100. The P+ type body contact region 51 typically has higher doping than the body region 5.

[0050] In this way, the basic cell of MOSFET1 (one is shown in Figures 2A to 2E) is completed. As a result, the drift region 3 is also defined within the portion of the epitaxial layer 22 that is not occupied by the body region 5. Finally, the entire body 2 of MOSFET1 is also completed.

[0051] Next, in Figure 2B, a gate insulating layer 141 (e.g., silicon oxide), a gate conductive layer 142 (e.g., made of polysilicon), and a gate passivation layer (or "intermediate dielectric layer") 143 are continuously formed on the body 2 (third step S3). Specifically, the gate insulating layer 141 is formed on the front surface 2a of the body 2, for example, by an oxidation process of the body 2; the gate conductive layer 142 is formed on the gate insulating layer 141, for example, by deposition or epitaxial reactor growth from a seed layer (not shown); and the gate passivation layer 143 is formed on the gate conductive layer 142, for example, by deposition. The gate passivation layer 143 is formed by an intermediate dielectric, for example, an oxide, an oxynitride, or a combination of an oxide or nitride and an oxynitride.

[0052] Next, as shown in Figure 2C, the gate insulating layer 141, the gate conductive layer 142, and the gate passivation layer 143 are patterned by etching using a mask (not shown) at the location corresponding to the source region 7 to form the first opening 140 and the corresponding intermediate gate structure 145 (fourth step S4). Specifically, the first opening 140 extends (along the Z-axis) to the front surface 2a of the body 2, leaving the source region 7 and the body contact region 51 at least partially exposed. Furthermore, the first opening 140 has an extension along the X-axis corresponding to the gate strip distance T, and this extension, as expected, provides the gate-source capacitance C of the MOSFET 1. GS These are design parameters related to the definition. Therefore, the resulting intermediate gate structure 145 has dimensions along the X-axis that correspond to the final gate strip width L of the conductive gate region 42 of the MOSFET 1.

[0053] Referring to Figure 2D, the spacer dielectric layer 144 is then conformally formed on the body 2 and the intermediate gate structure 145, for example, by deposition (fifth step S5). Specifically, the spacer dielectric layer 144 has a thickness substantially corresponding to the spacer width t and covers the remaining portion of the gate passivation layer 143 and the front surface 2a of the body 2 exposed within the first opening 140, and laterally covers the side surface of the intermediate gate structure 145. Thus, the gate conductive layer 142 of each preliminary gate structure 145 is sealed. The spacer dielectric layer 144 may be different from the dielectric of the gate passivation layer 143, but is still compatible with their dielectrics in terms of adhesion, and is formed of a dielectric such as oxide, or oxynitride, or a combination of oxide or nitride and oxynitride. Furthermore, the spacer width t may have a minimum value equal to, for example, 0.2 μm.

[0054] Next, referring to Figure 2E, vertical etching of the spacer dielectric layer 144, for example, time etching and / or selective etching, is performed. This vertical etching is anisotropic etching ("blanket etching"), for example, performed in a CF4 environment without the help of a mask. Such etching forms a second opening 150 by completely removing a portion of the spacer dielectric layer 144 parallel to the front surface 2a of the body 2 (sixth step S6). The portion of the spacer dielectric layer 144 covering the side of the intermediate gate structure 145 remains substantially unchanged and forms the corresponding spacer portion 44. More specifically, the second opening 150 extends (along the Z axis) to the front surface 2a of the body 2, leaving the source region 7 and the body contact region 51 at least partially exposed. Furthermore, the dimension of the second opening 150 along the X-axis defines the aforementioned contact width C, and is determined according to design preferences by the dimension of the first opening 140 along the X-axis and by the thickness of the spacer dielectric layer 144.

[0055] Finally (step 7, S7), a source metallization layer is formed, for example, by deposition, which completely fills the second opening 150 and forms the source metallization region 6 of the MOSFET 1, specifically the contact portion 61. A drain metallization region 8 is also formed on the rear surface 2b of the body 2, so that the MOSFET 1 shown in Figure 1 is finally obtained.

[0056] Therefore, the manufacturing process of the present disclosure allows for greater freedom in varying the gate strip distance T between conductive gate regions 42 belonging to two adjacent gate structures 4, with respect to a given contact width C of the contact portion 61 of the source metallization region 6, compared to a photolithography process performed using a dedicated mask. Specifically, the spacer dielectric layer 144 allows for minimizing the spacer width t with respect to a given contact width C, and therefore also allows for minimizing the gate strip distance T. Thus, for the same pitch PT, the gate strip width L of the conductive gate region 42 becomes larger, and therefore also the overlap width s and the input capacitance C of the MOSFET 1. IN This also increases. More generally, the spacer width t of the spacer portion 44 can be selected as a function of the desired overlap width s of the overlap region 71 between the conductive gate region 42 and the corresponding source region 7. Furthermore, the manufacturing process of the present disclosure makes it possible to avoid the use of a mask for patterning the contact portion 61 of the source metallization region 6, thereby giving the MOSFET 1 higher overall reliability.

[0057] Finally, it is evident that modifications and alterations can be made to those described and illustrated herein without departing from the scope of this disclosure, as defined in the attached claims.

[0058] For example, in some cases, the body contact region may not exist within the source region of a MOSFET.

[0059] The spacer portion of the gate structure may have a profile on the side facing the contact portion of the source metallization area that is positioned at an angle to the front of the body, i.e., a profile that is positioned at an inclination different from the vertical one shown in the figure.

[0060] In one embodiment of the manufacturing process not shown, the etching shown in Figure 2C, which forms the first opening, is stopped on the gate insulating layer, and therefore, the spacer portion of the gate structure obtained following the formation of the second opening (Figure 2E), includes a portion near the front surface of the body, which is formed of the same material as the gate insulating layer. In other words, in such an embodiment, the insulating gate region of the gate structure has an extent along the X-axis equal to the sum of the gate strip width L and twice the spacer width t.

[0061] In an alternative embodiment having the same advantages as described above, the MOSFET further comprises a deep body region located in contact with the lower part of the corresponding body region, a first current diffusion layer (CSL) region located in contact with the lower part of the corresponding deep body region, and a second current diffusion layer region located within the drift region between two adjacent body regions and extending from the front of the body to at least the first current diffusion layer region.

[0062] More generally, the MOSFETs of this disclosure may have body and source regions that differ in shape and dopant distribution from those described and illustrated. For example, some body regions may include portions having a dopant concentration higher than the average dopant concentration of those body regions.

Claims

1. A process for manufacturing vertical conduction power devices, A body containing a semiconductor material and having a first electrical conductivity is formed within a body region having a second electrical conductivity opposite to the first electrical conductivity, A first electrically conductive source region is formed within the corresponding body region, A gate structure is formed, each including an insulated gate region on the body, a conductive gate region on the insulated gate region, and a passivation gate region on the conductive gate region, wherein the conductive gate region is partially superimposed on the source region of a corresponding adjacent body region. Forming source metallization regions on the body and the gate structure, wherein the source metallization regions include contact portions with corresponding source regions between adjacent gate structures. Forming the aforementioned contact portion Conformally form a spacer dielectric layer on the gate structure and on the body, Forming a source metallization region, which includes anisotropically etching the spacer dielectric layer down to the source region, A process that includes this.

2. A process for manufacturing a vertical conduction power device according to claim 1, wherein etching the spacer dielectric layer includes performing maskless etching.

3. A process for manufacturing a vertical conduction power device according to claim 1, wherein the passivation gate region of each gate structure is formed of a first dielectric selected from oxides, oxynitrides, or a combination of oxides or nitrides and oxynitrides.

4. A process for manufacturing a vertical conduction power device according to claim 1, wherein the spacer dielectric layer is formed of a second dielectric selected from an oxide, an oxynitride, or a combination of an oxide or nitride and an oxynitride.

5. A process for manufacturing a vertical conduction power device according to claim 1, wherein the spacer dielectric layer has a minimum thickness equal to 0.2 μm and covers the gate structure laterally.

6. Forming the gate structure involves forming a gate conductive layer and patterning the gate conductive layer, wherein each resulting conductive gate region is superimposed on the corresponding source region within a corresponding overlapping region along a first direction. A process for manufacturing a vertically conductive power device according to claim 1, comprising: patterning the gate conductive layer such that conductive gate regions of adjacent gate structures are separated by a certain distance along a second direction perpendicular to the first direction, and the ratio of the distance to the pitch of the power device is a value between 0.4 and 0.

9.

7. A process for manufacturing a vertical conduction power device according to claim 1, wherein etching the spacer dielectric layer defines a pair of spacer portions on the side surface of each gate structure.

8. A process for manufacturing a vertically conductive power device according to claim 1, wherein the pair of spacer portions seal the conductive gate region of each gate structure.

9. A process for manufacturing a vertical conduction power device according to claim 1, wherein the source region includes a corresponding body contact region, and each body contact region extends to the corresponding body region.

10. A process for manufacturing a vertical conduction power device according to claim 1, wherein the body comprises a substrate and an epitaxial layer, the body region and the source region are formed within the epitaxial layer, and the semiconductor material contains silicon carbide.

11. A process for manufacturing a vertical conduction power device according to claim 1, wherein the substrate has a rear surface of the body, and the process further comprises forming a drain metallization region on the rear surface.

12. A vertically conductive power device, A body containing a semiconductor material and having a first electrical conductivity, One or more body regions extending within the body and having a second electrical conductivity opposite to the first electrical conductivity, One or more source regions extending within the corresponding body region and having the first electrical conductivity, One or more gate structures, each including an insulated gate region on the body, a conductive gate region on the insulated gate region, and a passivation gate region on the conductive gate region, wherein the conductive gate region is partially superimposed on the source region of a corresponding adjacent body region along a first direction, Source metallization regions on the body and the gate structure, including a contact portion between adjacent gate structures and a corresponding source region, Equipped with, A vertically conductive power device in which each gate structure includes a plurality of spacer portions laterally that contact the body and define the range of the corresponding contact portion.

13. Each conductive gate region is superimposed on the corresponding source region within the corresponding overlapping region along the first direction, The vertical conduction power device according to claim 12, wherein the conductive gate regions of adjacent gate structures are separated by a certain distance along a second direction perpendicular to the first direction, and the ratio of the distance to the pitch of the power device is a value between 0.4 and 0.

9.

14. A vertical conduction power device according to claim 13, comprising a source terminal electrically connected to the source metallization region and gate terminals electrically connected to each conductive gate region of the gate structure, wherein the power device has a capacitance between the gate terminal and the source terminal that depends on the ratio of the distance to the pitch of the power device.

15. The vertical conduction power device according to claim 12, wherein the semiconductor material contains silicon carbide.

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