Semiconductor equipment

Abstract

To provide a semiconductor device that can improve short-circuit withstand capability and reduce feedback capacitance. [Solution] The semiconductor device 1 includes an n-type SiC semiconductor layer 2 (semiconductor layer) having a first main surface 3, a trench gate structure 10 (first trench structure) formed on the first main surface 3, a trench source structure 11 (second trench structure) formed deeper on the first main surface 3 than the trench gate structure 10, with a depth ratio of 1.5 to 4.0 for the trench gate structure 10, and a p-type deep well region 21 (well region) formed along the trench source structure 11 in the surface layer of the first main surface 3.

Description

[Technical Field]

[0001] This invention relates to a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device comprising a gate trench and a source trench. The gate trench and the source trench are formed on the surface of an n-type semiconductor layer to approximately equal depths. A p-type body region is formed in the area between the gate trench and the source trench in the surface layer of the semiconductor layer.

[0003] The surface layer of the p-type body region is n + A p-type source region is formed. In the semiconductor layer, a p-type breakdown voltage holding region (deep well region) is formed along the source trench.

[0004] The gate trench contains the gate electrode via a gate insulating layer. The source trench contains the source electrode. The drain electrode is connected to the back surface of the semiconductor layer. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] International Publication No. 2014 / 030589A1 [Overview of the project] [Problems that the invention aims to solve]

[0006] Short-circuit withstand capability and feedback capacitance are known electrical characteristics of semiconductor devices having a MISFET structure including a gate, source, and drain. Short-circuit withstand capability is the time the device can withstand a short-circuit current. Short-circuit current is the current that flows between the source and drain when switching from the ON state to the OFF state. Feedback capacitance is the capacitance between the gate and drain.

[0007] Higher short-circuit withstand capability increases the reliability of a semiconductor device. Furthermore, lower feedback capacitance increases the switching speed of the semiconductor device. Therefore, by achieving excellent short-circuit withstand capability and high feedback capacitance, it is possible to provide semiconductor devices that can be used in a variety of applications.

[0008] However, in semiconductor devices where gate trenches and source trenches are formed to approximately equal depths, p-type deep well regions can only be formed in relatively shallow areas of the n-type semiconductor layer.

[0009] In such a structure, the depletion layer cannot be sufficiently extended from the boundary region between the semiconductor layer and the deep well region. Therefore, the narrowing of the current path of the short-circuit current by the depletion layer is insufficient, and the short-circuit withstand capability cannot be adequately improved. In addition, because the width of the depletion layer is small, the feedback capacitance cannot be adequately reduced.

[0010] One embodiment provides a semiconductor device that can improve short-circuit withstand capability and reduce feedback capacitance. [Means for solving the problem]

[0011] One embodiment provides a semiconductor device comprising: a semiconductor layer of a first conductivity type having a main surface; a first trench structure formed on the main surface; a second trench structure formed on the main surface to be deeper than the first trench structure, with a depth ratio of 1.5 to 4.0 to the depth of the first trench structure; and a well region of a second conductivity type formed along the second trench structure in the surface layer of the main surface.

[0012] One embodiment provides a semiconductor device comprising: a semiconductor layer of a first conductivity type having a first main surface on one side and a second main surface on the other side; a trench gate structure including a gate trench formed on the first main surface of the semiconductor layer and a gate electrode embedded in the gate trench via a gate insulating layer; a trench source structure including a source trench formed on the first main surface of the semiconductor layer at a distance from the gate trench and deeper than the gate trench, a source electrode embedded in the source trench, and a well region of a second conductivity type formed in the semiconductor layer along the source trench, wherein the ratio of the depth of the trench source structure to the depth of the trench gate structure is 1.5 or more and 4.0 or less; and a semiconductor device comprising: a body region of a second conductivity type formed in the region between the gate trench and the source trench on the surface of the first main surface of the semiconductor layer, a source region of a first conductivity type formed on the surface of the body region, and a drain electrode connected to the second main surface of the semiconductor layer.

[0013] One embodiment includes a first conductivity type semiconductor layer having a first main surface on one side and a second main surface on the other side; a trench gate structure including a gate trench formed on the first main surface of the semiconductor layer and a gate electrode embedded in the gate trench via a gate insulating layer; and a trench source structure including a source trench formed on the first main surface of the semiconductor layer at a distance from the gate trench and deeper than the gate trench, a source electrode embedded in the source trench, and a second conductivity type well region formed in the semiconductor layer along the source trench, wherein the trench A semiconductor device is provided, comprising: a trench source structure in which the ratio of the depth of the trench source structure to the depth of the gate structure is 1.5 or more and 4.0 or less; a body region of a second conductivity type formed in the region between the gate trench and the source trench on the surface layer of the first main surface of the semiconductor layer; a source region of a first conductivity type formed on the surface layer of the body region; and a drain electrode connected to the second main surface of the semiconductor layer, wherein the well region is continuously formed in the semiconductor layer along the side wall, bottom wall, and corner portion connecting the side wall and the bottom wall of the source trench. In these semiconductor devices, the ratio of the depth of the trench source structure to the depth of the trench gate structure is between 1.5 and 4.0. This allows the depletion layer to extend from the boundary region between the semiconductor layer and the well region toward the region on the second main surface side of the bottom wall of the gate trench.

[0014] As a result, the current path of the short-circuit current flowing between the source electrode and the drain electrode can be narrowed. In addition, the depletion layer extending from the boundary region between the semiconductor layer and the well region can inversely reduce the feedback capacitance. Therefore, a semiconductor device can be provided that has improved short-circuit withstand capability and reduced feedback capacitance.

[0015] One embodiment includes a semiconductor layer of a first conductivity type having a first main surface on one side and a second main surface on the other side; a trench gate structure having a first side wall and a first bottom wall, a gate trench formed on the first main surface of the semiconductor layer, and a gate electrode embedded in the gate trench via a gate insulating layer; a trench source structure having a second side wall and a second bottom wall, a source trench formed on the first main surface of the semiconductor layer at a distance from the gate trench, a source electrode embedded in the source trench, and a well region of a second conductivity type formed in the semiconductor layer along the source trench; and a region between the gate trench and the source trench formed on the surface layer of the first main surface of the semiconductor layer. A semiconductor device is provided, comprising a body region of a second conductivity type, a source region of a first conductivity type formed on the surface of the body region, and a drain electrode connected to the second main surface of the semiconductor layer, wherein the second side wall of the source trench includes a first wall portion located on the first main surface side of the semiconductor layer with respect to the first bottom wall of the gate trench, and a second wall portion located on the second main surface side of the semiconductor layer with respect to the first bottom wall of the gate trench, and the well region includes a first region formed along the first wall portion of the second side wall of the source trench, and a second region formed along the second wall portion of the second side wall of the source trench, having a length greater than the length of the first region with respect to the thickness direction of the semiconductor layer.

[0016] According to this semiconductor device, the well region includes a first region formed along the first wall portion of the second side wall of the source trench, and a second region formed along the second wall portion of the second side wall of the source trench.

[0017] With respect to the thickness direction of the semiconductor layer, the length of the second region of the well area is greater than the length of the first region of the well area. This allows the depletion layer to extend from the boundary region between the semiconductor layer and the well area toward the region on the second main surface side of the first bottom wall of the gate trench.

[0018] As a result, the current path of the short-circuit current flowing between the source electrode and the drain electrode can be narrowed. In addition, the depletion layer extending from the boundary region between the semiconductor layer and the well region can inversely reduce the feedback capacitance. Therefore, a semiconductor device can be provided that has improved short-circuit withstand capability and reduced feedback capacitance.

[0019] The above-mentioned, or further, objectives, features, and effects of the present invention will be made clearer by the following description of embodiments with reference to the accompanying drawings. [Brief explanation of the drawing]

[0020] [Figure 1] Figure 1 is a plan view showing a semiconductor device according to a first embodiment of the present invention. [Figure 2] Figure 2 is a cross-sectional view taken along the line II-II in Figure 1. [Figure 3] Figure 3 is a cross-sectional view illustrating the operation of the semiconductor device shown in Figure 1. [Figure 4] Figure 4 is a graph showing the current-voltage characteristics of the semiconductor device shown in Figure 1. [Figure 5] Figure 5 is a graph showing the capacitance-voltage characteristics of the semiconductor device shown in Figure 1. [Figure 6] Figure 6 is a cross-sectional view showing a semiconductor device according to a second embodiment of the present invention. [Figure 7] Figure 7 is a cross-sectional view showing a semiconductor device according to a third embodiment of the present invention. [Figure 8] Figure 8 is a cross-sectional view showing a semiconductor device according to a fourth embodiment of the present invention. [Figure 9] Figure 9 is a cross-sectional view showing a semiconductor device according to a fifth embodiment of the present invention. [Figure 10] Figure 10 is a plan view showing a semiconductor device according to a sixth embodiment of the present invention. [Figure 11] Figure 11 is a plan view showing a semiconductor device according to a seventh embodiment of the present invention. [Figure 12] Figure 12 is an enlarged view of region XII shown in Figure 11, and is a diagram illustrating the structure of the first main surface of the SiC semiconductor layer. [Figure 13] Figure 13 is a cross-sectional view along the line XIII-XIII shown in Figure 12. [Figure 14] Figure 14 is a cross-sectional view along the line XIV-XIV shown in Figure 12. [Figure 15] Figure 15 is a graph showing the relationship between the resistivity and formation temperature of polyside. [Figure 16] Figure 16 is a graph illustrating sheet resistance. [Figure 17A] Figure 17A is a cross-sectional view showing an example of a method for manufacturing the semiconductor device shown in Figure 11. [Figure 17B] Figure 17B is a cross-sectional view showing a process following Figure 17A. [Figure 17C] Figure 17C is a cross-sectional view showing a process after Figure 17B. [Figure 17D] Figure 17D is a cross-sectional view showing a process after Figure 17C. [Figure 17E] Figure 17E is a cross-sectional view showing a process after Figure 17D. [Figure 17F] Figure 17F is a cross-sectional view showing a process after Figure 17E. [Figure 17G] Figure 17G is a cross-sectional view showing a process after Figure 17F. [Figure 17H] Figure 17H ​​is a cross-sectional view showing a process after Figure 17G. [Figure 17I] Figure 17I is a cross-sectional view showing a process after Figure 17H. [Figure 17J] Figure 17J is a cross-sectional view showing a process after Figure 17I. [Figure 17K] Figure 17K is a cross-sectional view showing a process after Figure 17J. [Figure 17L] Figure 17L is a cross-sectional view showing a process after Figure 17K. [Figure 18] Figure 18 is a cross-sectional view of the region corresponding to Figure 13, and shows a semiconductor device according to the eighth embodiment of the present invention. [Figure 19] Figure 19 is a cross-sectional view of the region corresponding to Figure 13, and shows a semiconductor device according to the ninth embodiment of the present invention. [Figure 20A] Figure 20A is a cross-sectional view showing an example of a method for manufacturing the semiconductor device shown in Figure 19. [Figure 20B] Figure 20B is a cross-sectional view showing a process after Figure 20A. [Figure 20C] Figure 20C is a cross-sectional view showing a process after Figure 20B. [Figure 21] Figure 21 is an enlarged view of the region corresponding to Figure 12, and shows a semiconductor device according to the 10th embodiment of the present invention. [Figure 22] Figure 22 is a cross-sectional view along the line XXII-XXII shown in Figure 21. [Figure 23] Figure 23 is a cross-sectional view of the region corresponding to Figure 13, and is a cross-sectional view illustrating the structure of a semiconductor device according to the 11th embodiment of the present invention. [Figure 24] Figure 24 is an enlarged view of the region corresponding to Figure 12, and is an enlarged view for illustrating the structure of a semiconductor device according to the 12th embodiment of the present invention. [Figure 25] Figure 25 is a cross-sectional view of the region corresponding to Figure 13, and is a cross-sectional view illustrating the structure of a semiconductor device according to the 13th embodiment of the present invention. [Figure 26] Figure 26 is a cross-sectional view of the region corresponding to Figure 13, and is a cross-sectional view illustrating the structure of a semiconductor device according to the 14th embodiment of the present invention. [Figure 27] Figure 27 is a cross-sectional view of the region corresponding to Figure 13, and is a cross-sectional view illustrating the structure of a semiconductor device according to the 15th embodiment of the present invention. [Figure 28] Figure 28 is a cross-sectional view of the region corresponding to Figure 13, and is a cross-sectional view illustrating the structure of a semiconductor device according to the 16th embodiment of the present invention. [Figure 29] Figure 29 is a cross-sectional view of the region corresponding to Figure 13, and is a cross-sectional view illustrating the structure of a semiconductor device according to the 17th embodiment of the present invention. [Figure 30] Figure 30 is a cross-sectional view of the region corresponding to Figure 13, and is a cross-sectional view illustrating the structure of a semiconductor device according to the 18th embodiment of the present invention. [Figure 31] Figure 31 is a cross-sectional view of the region corresponding to Figure 13, and is a cross-sectional view illustrating the structure of a semiconductor device according to the 19th embodiment of the present invention. [Figure 32] Figure 32 is a cross-sectional view of the region corresponding to Figure 13, and is a cross-sectional view illustrating the structure of a semiconductor device according to the 20th embodiment of the present invention. [Figure 33] Figure 33 is a cross-sectional view of the region corresponding to Figure 13, and is a cross-sectional view illustrating the structure of a semiconductor device according to the 21st embodiment of the present invention. [Figure 34] Figure 34 is a top view showing a semiconductor device according to the 22nd embodiment of the present invention. [Figure 35] Figure 35 is a bottom view of the semiconductor device shown in Figure 34, and is a bottom view showing a first embodiment of the raised portion group. [Figure 36A] Figure 36A shows an example of the second morphology of the raised area. [Figure 36B] Figure 36B shows an example of the third morphology of the raised area. [Figure 36C] Figure 36C shows an example of the fourth morphology of the raised area. [Figure 36D] Figure 36D shows an example of the fifth morphology of the raised area. [Figure 37] Figure 37 is an enlarged view of region XXXVII shown in Figure 34, with the structure above the first main surface of the SiC semiconductor layer removed. [Figure 38] Figure 38 is a cross-sectional view along the line XXXVIII-XXXVIII in Figure 37. [Figure 39] Figure 39 is a cross-sectional view along the line XXXIX-XXXIX in Figure 37. [Figure 40] Figure 40 is an enlarged view of region XL shown in Figure 39. [Figure 41A] Figure 41A is a top view showing a semiconductor wafer used in the manufacture of the semiconductor device shown in Figure 34. [Figure 41B] Figure 41B is a bottom view of the semiconductor wafer shown in Figure 41A, after the grinding and annealing processes. [Figure 42] Figure 42 is a flowchart illustrating an example of a semiconductor device shown in Figure 34. [Figure 43A] Figure 43A is a cross-sectional view illustrating the manufacturing method shown in Figure 42. [Figure 43B] Figure 43B is a cross-sectional view illustrating a process that follows Figure 43A. [Figure 43C] Figure 43C is a cross-sectional view illustrating a process that follows Figure 43B. [Figure 43D] Figure 43D is a cross-sectional view illustrating a process that follows Figure 43C. [Figure 43E] Figure 43E is a cross-sectional view illustrating a subsequent process to Figure 43D. [Figure 43F] Figure 43F is a cross-sectional view illustrating a process that follows Figure 43E. [Figure 43G] Figure 43G is a cross-sectional view illustrating a process that follows Figure 43F. [Figure 43H] Figure 43H is a cross-sectional view illustrating a process that follows Figure 43G. [Figure 43I] Figure 43I is a cross-sectional view illustrating a subsequent process to Figure 43H. [Figure 44] Figure 44 is a bottom view corresponding to Figure 35, and is a bottom view showing a semiconductor device according to the 23rd embodiment of the present invention. [Figure 45] Figure 45 is a cross-sectional view corresponding to Figure 39, and shows a semiconductor device according to the 24th embodiment of the present invention. [Figure 46] Figure 46 is an enlarged view of region XLVI shown in Figure 45. [Figure 47] Figure 47 is a cross-sectional view corresponding to Figure 39, and shows a semiconductor device according to the 25th embodiment of the present invention. [Figure 48] Figure 48 is an enlarged view of region XLVIII shown in Figure 47. [Figure 49] Figure 49 is a top view showing a semiconductor device according to the 26th embodiment of the present invention. [Figure 50]Figure 50 is a top view of the semiconductor device shown in Figure 49, with the resin layer removed. [Figure 51] Figure 51 is an enlarged view of region LI shown in Figure 50, and is a diagram illustrating the structure of the first main surface of the SiC semiconductor layer. [Figure 52] Figure 52 is a cross-sectional view along the LII-LII line shown in Figure 51, and shows a first example of a gate trench and a first example of a source trench. [Figure 53] Figure 53 is a cross-sectional view along the line LIII-LIII shown in Figure 51, and is a cross-sectional view showing a first example of the gate wiring layer. [Figure 54] Figure 54 is an enlarged view of the LIV region shown in Figure 52. [Figure 55] Figure 55 is a cross-sectional view along the LV-LV line shown in Figure 50, and shows a first example of the active sidewall, a first example of the outer main surface, a first example of the sidewall, a first example of the diode region, a first example of the outer deep well region, a first example of the field limit structure, and a first example of the anchor hole. [Figure 56] Figure 56 is an enlarged view of region LVI shown in Figure 55, and shows a first example of the active side wall and a first example of the outer main surface. [Figure 57A] Figure 57A is a cross-sectional view of the region corresponding to Figure 54, and shows a second example of a gate trench. [Figure 57B] Figure 57B is a cross-sectional view of the region corresponding to Figure 54, and shows a third example of a gate trench. [Figure 57C] Figure 57C is a cross-sectional view of the region corresponding to Figure 54, and shows a fourth example of a gate trench. [Figure 57D] Figure 57D is a cross-sectional view of the region corresponding to Figure 54, and shows a fifth example of a gate trench. [Figure 57E] Figure 57E is a cross-sectional view of the region corresponding to Figure 54, and shows a sixth example of a gate trench. [Figure 58A]Figure 58A is a cross-sectional view of the region corresponding to Figure 54, and shows a second example of a source trench. [Figure 58B] Figure 58B is a cross-sectional view of the region corresponding to Figure 54, and shows a third example of a source trench. [Figure 58C] Figure 58C is a cross-sectional view of the region corresponding to Figure 54, and shows a fourth example of a source trench. [Figure 58D] Figure 58D is a cross-sectional view of the region corresponding to Figure 54, and shows a fifth example of a source trench. [Figure 58E] Figure 58E is a cross-sectional view of the region corresponding to Figure 54, and shows a sixth example of a source trench. [Figure 58F] Figure 58F is a cross-sectional view of the region corresponding to Figure 54, and shows a seventh example of a source trench. [Figure 58G] Figure 58G is a cross-sectional view of the region corresponding to Figure 54, and shows an example of the eighth form of a source trench. [Figure 58H] Figure 58H is a cross-sectional view of the region corresponding to Figure 54, and shows a ninth example of a source trench. [Figure 58I] Figure 58I is a cross-sectional view of the region corresponding to Figure 54, and shows a 10th example of a source trench. [Figure 58J] Figure 58J is a cross-sectional view of the region corresponding to Figure 54, and shows an eleventh example of a source trench. [Figure 58K] Figure 58K is a cross-sectional view of the region corresponding to Figure 54, and shows a twelfth example of a source trench. [Figure 58L] Figure 58L is a cross-sectional view of the region corresponding to Figure 54, and shows a 13th example of a source trench. [Figure 58M] Figure 58M is a cross-sectional view of the region corresponding to Figure 54, and shows a 14th example of a source trench. [Figure 58N]Figure 58N is a cross-sectional view of the region corresponding to Figure 54, and shows a 15th example of a source trench. [Figure 58O] Figure 58O is a cross-sectional view of the region corresponding to Figure 54, and shows a 16th example of a source trench. [Figure 58P] Figure 58P is a cross-sectional view of the region corresponding to Figure 54, and shows a cross-sectional view of the 17th example of a source trench. [Figure 58Q] Figure 58Q is a cross-sectional view of the region corresponding to Figure 54, and shows an example of the 18th form of a source trench. [Figure 59A] Figure 59A is an enlarged view of the region corresponding to Figure 56, and shows an enlarged example of a second form of the active sidewall. [Figure 59B] Figure 59B is an enlarged view of the region corresponding to Figure 56, and shows an enlarged example of a third form of the active sidewall. [Figure 59C] Figure 59C is an enlarged view of the region corresponding to Figure 56, and shows a fourth example of the active side wall. [Figure 60A] Figure 60A is an enlarged view of the region corresponding to Figure 56, and shows an enlarged example of the second form of the outer main surface. [Figure 60B] Figure 60B is an enlarged view of the region corresponding to Figure 56, and shows an example of the third form of the outer main surface. [Figure 60C] Figure 60C is an enlarged view of the region corresponding to Figure 56, and shows an enlarged example of the fourth form of the outer main surface. [Figure 61A] Figure 61A is an enlarged view of the region corresponding to Figure 56, and shows an enlarged example of a second form of the sidewall. [Figure 61B] Figure 61B is an enlarged view of the region corresponding to Figure 56, and shows an example of a third form of the sidewall. [Figure 61C] Figure 61C is an enlarged view of the region corresponding to Figure 56, and shows an enlarged example of the fourth form of the sidewall. [Figure 61D]Figure 61D is an enlarged view of the region corresponding to Figure 56, and shows an example of the fifth form of the sidewall. [Figure 61E] Figure 61E is an enlarged view of the region corresponding to Figure 56, and shows a sixth example of the sidewall configuration. [Figure 61F] Figure 61F is an enlarged view of the region corresponding to Figure 56, and shows an enlarged example of the seventh form of the sidewall. [Figure 62A] Figure 62A is a cross-sectional view of the region corresponding to Figure 55, and is an enlarged view showing a second example of the outer deep well region. [Figure 62B] Figure 62B is a cross-sectional view of the region corresponding to Figure 55, and is an enlarged view showing a third example of the outer deep well region. [Figure 62C] Figure 62C is a cross-sectional view of the region corresponding to Figure 55, and is an enlarged view showing a fourth example of the outer deep well region. [Figure 63A] Figure 63A is a cross-sectional view of the region corresponding to Figure 55, and is an enlarged view showing a second example of the field limit structure. [Figure 63B] Figure 63B is a cross-sectional view of the region corresponding to Figure 55, and is an enlarged view showing a third example of the field limit structure. [Figure 63C] Figure 63C is a cross-sectional view of the region corresponding to Figure 55, and is an enlarged view showing a fourth example of the field limit structure. [Figure 63D] Figure 63D is a cross-sectional view of the region corresponding to Figure 55, and is an enlarged view showing a fifth example of the field limit structure. [Figure 64A] Figure 64A is a cross-sectional view of the region corresponding to Figure 55, and is an enlarged view showing a second example of the anchor hole. [Figure 64B] Figure 64B is a cross-sectional view of the region corresponding to Figure 55, and is an enlarged view showing a third example of the anchor hole. [Figure 64C] Figure 64C is a cross-sectional view of the region corresponding to Figure 55, and is an enlarged view showing a fourth example of the anchor hole. [Figure 64D]Figure 64D is a plan view corresponding to Figure 50, and is a plan view showing a fifth example of the anchor hole. [Figure 65A] Figure 65A is an enlarged view of the region corresponding to Figure 54, and is an enlarged view showing an example of a method for manufacturing the semiconductor device shown in Figure 49. [Figure 65B] Figure 65B is an enlarged view showing the process after Figure 65A. [Figure 65C] Figure 65C is an enlarged view showing the process after Figure 65B. [Figure 65D] Figure 65D is an enlarged view showing the process after Figure 65C. [Figure 65E] Figure 65E is an enlarged view showing the process after Figure 65D. [Figure 65F] Figure 65F is an enlarged view showing the process after Figure 65E. [Figure 65G] Figure 65G is an enlarged view showing the process after Figure 65F. [Figure 65H] Figure 65H is an enlarged view showing the process after Figure 65G. [Figure 65I] Figure 65I is an enlarged view showing the process after Figure 65H. [Figure 65J] Figure 65J is an enlarged view showing the process after Figure 65I. [Figure 65K] Figure 65K is an enlarged view showing the process after Figure 65J. [Figure 65L] Figure 65L is an enlarged view showing the process after Figure 65K. [Figure 65M] Figure 65M is an enlarged view showing the process after Figure 65L. [Figure 65N] Figure 65N is an enlarged view showing the process after Figure 65M. [Figure 65O] Figure 65O is an enlarged view showing the process after Figure 65N. [Figure 65P] Figure 65P is an enlarged view showing the process after Figure 65O. [Figure 65Q] Figure 65Q is an enlarged view showing the process after Figure 65P. [Figure 65R] Figure 65R is an enlarged view showing the process after Figure 65Q. [Figure 65S] Figure 65S is an enlarged view showing the process after Figure 65R. [Figure 65T] Figure 65T is an enlarged view showing the process after Figure 65S. [Figure 65U] Figure 65U is an enlarged view showing the process after Figure 65T. [Figure 65V] Figure 65V is an enlarged view showing the process after Figure 65U. [Figure 65W] Figure 65W is an enlarged view showing the process after Figure 65V. [Figure 65X] Figure 65X is an enlarged view showing the process after Figure 65W. [Figure 65Y] Figure 65Y is an enlarged view showing the process after Figure 65X. [Figure 65Z] Figure 65Z is an enlarged view showing the process after Figure 65Y. [Figure 66A] Figure 66A is a cross-sectional view of the region corresponding to Figure 55, and is a cross-sectional view showing an example of a semiconductor device manufacturing method shown in Figure 49. [Figure 66B] Figure 66B is a cross-sectional view showing a process following Figure 66A. [Figure 66C] Figure 66C is a cross-sectional view showing a process after Figure 66B. [Figure 66D] Figure 66D is a cross-sectional view showing a process after Figure 66C. [Figure 66E] Figure 66E is a cross-sectional view showing a process after Figure 66D. [Figure 66F] Figure 66F is a cross-sectional view showing a process after Figure 66E. [Figure 66G] Figure 66G is a cross-sectional view showing a process after Figure 66F. [Figure 66H] Figure 66H is a cross-sectional view showing a process after Figure 66G. [Figure 66I] Figure 66I is a cross-sectional view showing a process after Figure 66H. [Figure 66J] Figure 66J is a cross-sectional view showing a process after Figure 66I. [Figure 66K] Figure 66K is a cross-sectional view showing a process after Figure 66J. [Figure 66L] Figure 66L is a cross-sectional view showing a process after Figure 66K. [Figure 66M] Figure 66M is a cross-sectional view showing a process after Figure 66L. [Figure 66N] Figure 66N is a cross-sectional view showing a process after Figure 66M. [Figure 66O] Figure 66O is a cross-sectional view showing a process after Figure 66N. [Figure 66P] Figure 66P is a cross-sectional view showing a process after Figure 66O. [Figure 66Q] Figure 66Q is a cross-sectional view showing a process after Figure 66P. [Figure 66R] Figure 66R is a cross-sectional view showing a process after Figure 66Q. [Figure 66S] Figure 66S is a cross-sectional view showing a process after Figure 66R. [Figure 66T] Figure 66T is a cross-sectional view showing a process after Figure 66S. [Figure 66U] Figure 66U is a cross-sectional view showing a process after Figure 66T. [Figure 66V] Figure 66V is a cross-sectional view showing a process after Figure 66U. [Figure 66W] Figure 66W is a cross-sectional view showing a process after Figure 66V. [Figure 66X] Figure 66X is a cross-sectional view showing a process after Figure 66W. [Figure 66Y] Figure 66Y is a cross-sectional view showing a process after Figure 66X. [Figure 66Z] Figure 66Z is a cross-sectional view showing a process after Figure 66Y. [Figure 67] Figure 67 is an enlarged view of the region corresponding to Figure 51, and is an enlarged view showing a semiconductor device according to the 27th embodiment of the present invention. [Figure 68] Figure 68 is a cross-sectional view along the LXVIII-LXVIII line shown in Figure 67. [Figure 69] Figure 69 is a cross-sectional view along the LXIX-LXIX line shown in Figure 67. [Figure 70] Figure 70 is an enlarged view of the region LXX-LXX shown in Figure 68. [Figure 71] Figure 71 is a graph showing the leakage current characteristics when NiSi is used as the low-resistance electrode layer. [Figure 72] Figure 72 is a graph showing the leakage current characteristics when CoSi2 is used as the low-resistance electrode layer. [Figure 73] Figure 73 is a graph showing the leakage current characteristics when TiSi2 is used as the low-resistance electrode layer. [Figure 74A] Figure 74A is an enlarged view of the region corresponding to Figure 70, and is an enlarged view illustrating an example of a method for manufacturing the semiconductor device shown in Figure 67. [Figure 74B] Figure 74B is an enlarged view showing the process after Figure 74A. [Figure 74C] Figure 74C is an enlarged view showing the process after Figure 74B. [Figure 74D] Figure 74D is an enlarged view showing the process after Figure 74C. [Figure 74E] Figure 74E is an enlarged view showing the process after Figure 74D. [Figure 74F] Figure 74F is an enlarged view showing the process after Figure 74E. [Figure 74G] Figure 74G is an enlarged view showing the process after Figure 74F. [Figure 75] Figure 75 is an enlarged view of the region corresponding to Figure 70, and shows a semiconductor device according to the 28th embodiment of the present invention. [Figure 76A] Figure 76A is an enlarged view of the region corresponding to Figure 75, and is an enlarged view illustrating an example of a method for manufacturing the semiconductor device shown in Figure 75. [Figure 76B] Figure 76B is an enlarged view showing the process after Figure 76A. [Figure 76C] Figure 76C is an enlarged view showing the process after Figure 76B. [Figure 76D] Figure 76D is an enlarged view showing the process after Figure 76C. [Figure 76E] Figure 76E is an enlarged view showing the process after Figure 76D. [Figure 76F]Figure 76F is an enlarged view showing the process after Figure 76E. [Figure 76G] Figure 76G is an enlarged view showing the process after Figure 76F. [Figure 77] Figure 77 is an enlarged view of the region corresponding to Figure 70, and shows a semiconductor device according to the 29th embodiment of the present invention. [Figure 78A] Figure 78A is an enlarged view of the region corresponding to Figure 77, and is an enlarged view illustrating an example of a method for manufacturing the semiconductor device shown in Figure 77. [Figure 78B] Figure 78B is an enlarged view showing the process after Figure 78A. [Figure 78C] Figure 78C is an enlarged view showing the process after Figure 78B. [Figure 78D] Figure 78D is an enlarged view showing the process after Figure 78C. [Figure 78E] Figure 78E is an enlarged view showing the process after Figure 78D. [Figure 78F] Figure 78F is an enlarged view showing the process after Figure 78E. [Figure 79] Figure 79 is an enlarged view of the region corresponding to Figure 70, and shows a semiconductor device according to the 30th embodiment of the present invention. [Figure 80] Figure 80 is a cross-sectional view of the region corresponding to Figure 69, and is a cross-sectional view showing the semiconductor device shown in Figure 79. [Figure 81] Figure 81 is a cross-sectional view of the region corresponding to Figure 55, and is a cross-sectional view showing the semiconductor device shown in Figure 79. [Figure 82A] Figure 82A is an enlarged view of the region corresponding to Figure 79, and is an enlarged view illustrating an example of a method for manufacturing the semiconductor device shown in Figure 79. [Figure 82B] Figure 82B is an enlarged view showing the process after Figure 82A. [Figure 82C] Figure 82C is an enlarged view showing the process after Figure 82B. [Figure 83] Figure 83 is a bottom view showing a semiconductor device according to the 31st embodiment of the present invention, and is a bottom view showing a first embodiment of the raised portion group. [Figure 84A] Figure 84A shows an example of the second morphology of the raised area. [Figure 84B] Figure 84B shows an example of the third morphology of the raised area. [Figure 84C] Figure 84C shows an example of the fourth morphology of the raised area. [Figure 84D] Figure 84D shows an example of the fifth morphology of the raised area. [Figure 85] Figure 85 is a cross-sectional view of the region corresponding to Figure 68, and is a cross-sectional view showing the semiconductor device shown in Figure 83. [Figure 86] Figure 86 is a cross-sectional view of the region corresponding to Figure 69, and is a cross-sectional view showing the semiconductor device shown in Figure 83. [Figure 87] Figure 87 is an enlarged view of region LXXXVII shown in Figure 86. [Figure 88] Figure 88 is a cross-sectional view of the region corresponding to Figure 55, and is a cross-sectional view showing the semiconductor device shown in Figure 83. [Figure 89] Figure 89 is a bottom view corresponding to Figure 83, and is a bottom view showing a semiconductor device according to the 32nd embodiment of the present invention. [Figure 90] Figure 90 is a cross-sectional view corresponding to Figure 86, and shows a semiconductor device according to the 33rd embodiment of the present invention. [Figure 91] Figure 91 is an enlarged view of region XCI shown in Figure 90. [Figure 92] Figure 92 is a cross-sectional view corresponding to Figure 86, and shows a semiconductor device according to the 34th embodiment of the present invention. [Figure 93] Figure 93 is an enlarged view of region XCIII shown in Figure 92. [Figure 94] Figure 94 is a cross-sectional view of the region corresponding to Figure 55, and shows a semiconductor device according to the 35th embodiment of the present invention. [Figure 95] Figure 95 is a cross-sectional view of the region corresponding to Figure 55, and shows a semiconductor device according to the 36th embodiment of the present invention. [Figure 96]Figure 96 is a cross-sectional view of the region corresponding to Figure 55, and shows a semiconductor device according to the 37th embodiment of the present invention. [Figure 97] Figure 97 is a cross-sectional view of the region corresponding to Figure 55, and shows a semiconductor device according to the 38th embodiment of the present invention. [Figure 98] Figure 98 is a cross-sectional view of the region corresponding to Figure 55, and shows a semiconductor device according to the 39th embodiment of the present invention. [Figure 99] Figure 99 is a cross-sectional view of the region corresponding to Figure 55, and shows a semiconductor device according to the 40th embodiment of the present invention. [Figure 100] Figure 100 is a cross-sectional view of the region corresponding to Figure 55, and is a cross-sectional view showing a semiconductor device according to the 41st embodiment of the present invention. [Figure 101] Figure 101 is a cross-sectional view of the region corresponding to Figure 55, and shows a semiconductor device according to the 42nd embodiment of the present invention. [Figure 102] Figure 102 is an enlarged view of the region corresponding to Figure 51, and is an enlarged view showing a semiconductor device according to the 43rd embodiment of the present invention. [Figure 103] Figure 103 is a cross-sectional view along the line CIII-CIII shown in Figure 102. [Figure 104] Figure 104 is an enlarged view of the region corresponding to Figure 51, and is an enlarged view showing a semiconductor device according to the 44th embodiment of the present invention. [Figure 105] Figure 105 is an enlarged view of the region corresponding to Figure 54, and is an enlarged view showing a semiconductor device according to the 45th embodiment of the present invention. [Figure 106] Figure 106 is a perspective view showing, through the encapsulant, a semiconductor package that can incorporate any one of the semiconductor devices according to the first to forty-fifth embodiments described above. [Figure 107] Figure 107 shows a unit cell of a 4H-SiC single crystal applied to an embodiment of the present invention. [Figure 108] Figure 108 is a plan view showing the silicon plane of the unit cell of the 4H-SiC single crystal shown in Figure 107.

Embodiment for Carrying out the Invention

[0021] FIG. 1 is a plan view showing a semiconductor device 1 according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view taken along line II-II of FIG. 1.

[0022] The semiconductor device 1 is a switching device including a vertical MISFET (Metal Insulator Semiconductor Field Effect Transistor). Referring to FIGS. 1 and 2, the semiconductor device 1 has an n-type SiC semiconductor layer 2 including a SiC (silicon carbide) single crystal.

[0023] The SiC semiconductor layer 2 includes a first main surface 3 on one side and a second main surface 4 on the other side. In this embodiment, the SiC semiconductor layer 2 has a stacked structure including a SiC semiconductor substrate 5 including a SiC single crystal and an n - -type SiC epitaxial layer 6 including a SiC single crystal. The second main surface 4 of the SiC semiconductor layer 2 is formed by the SiC semiconductor substrate 5. The first main surface 3 of the SiC semiconductor layer 2 is formed by the SiC epitaxial layer 6.

[0024] A drain electrode 7 is connected to the second main surface 4 of the SiC semiconductor layer 2. The SiC semiconductor substrate 5 is formed as an n + -type drain region. The SiC epitaxial layer 6 is formed as an n - -type drain drift region.

[0025] The n-type impurity concentration of the SiC semiconductor substrate 5 may be 1.0×10 18 cm -3 or more and 1.0×10 21 cm -3 or less. The n-type impurity concentration of the SiC epitaxial layer 6 may be ...... 15 cm -3 or more and 1.0×10 17 cm -3 or less. Hereinafter, in this specification, "impurity concentration" refers to the peak value of the impurity concentration.

[0026] Referring to Figures 1 and 2, a plurality of trench gate structures 10 and a plurality of trench source structures 11 are formed on the first main surface 3 of the SiC semiconductor layer 2. The trench gate structures 10 and trench source structures 11 are formed alternately with spacing between them along an arbitrary first direction X.

[0027] The trench gate structure 10 and the trench source structure 11 are formed in a strip shape extending along a second direction Y that is perpendicular to the first direction X. Preferably, the first direction X is the [11-20] direction and the second direction Y is the [1-100] direction.

[0028] A stripe structure is formed on the first main surface 3 of the SiC semiconductor layer 2, including a plurality of trench gate structures 10 and a plurality of trench source structures 11. With respect to the first direction X, the distance between the trench gate structures 10 and the trench source structures 11 may be between 0.3 μm and 1.0 μm.

[0029] Each trench gate structure 10 includes a gate trench 12, a gate insulating layer 13, and a gate electrode layer 14. In Figure 1, the gate electrode layer 14 is shown by hatching for clarity.

[0030] The gate trench 12 is formed by excavating the first main surface 3 of the SiC semiconductor layer 2 toward the second main surface 4. The gate trench 12 includes a first side wall 15 and a first bottom wall 16.

[0031] The gate insulating layer 13 is formed in a film-like manner along the first side wall 15, the first bottom wall 16 of the gate trench 12, and the corner 17 connecting the first side wall 15 and the first bottom wall 16. The gate insulating layer 13 defines a concave space within the gate trench 12.

[0032] The gate insulating layer 13 may contain silicon oxide. In addition to silicon oxide, the gate insulating layer 13 may contain at least one of the following: impurity-free silicon, silicon nitride, aluminum oxide, aluminum nitride, or aluminum oxynitride.

[0033] The gate electrode layer 14 is embedded in the gate trench 12, with the gate insulating layer 13 in between. More specifically, the gate electrode layer 14 is embedded in a concave space partitioned by the gate insulating layer 13.

[0034] The gate electrode layer 14 may contain conductive polysilicon. In addition to conductive polysilicon, the gate electrode layer 14 may contain at least one of titanium, nickel, copper, aluminum, silver, gold, titanium nitride, or tungsten.

[0035] Each trench source structure 11 consists of a source trench 18, a barrier forming layer 19, a source electrode layer 20 and p - It includes a deep well region 21 of the type. In Figure 1, the source electrode layer 20 is shown by hatching for clarity. The deep well region 21 is also called the pressure-resistant region.

[0036] The source trench 18 is formed by excavating the first main surface 3 of the SiC semiconductor layer 2 toward the second main surface 4. The source trench 18 includes a second side wall 22 and a second bottom wall 23.

[0037] The second side wall 22 of the source trench 18 includes a first wall portion 24 and a second wall portion 25. The first wall portion 24 of the source trench 18 is located on the first main surface 3 side of the SiC semiconductor layer 2 relative to the first bottom wall 16 of the gate trench 12. In other words, the first wall portion 24 is the portion that overlaps the gate trench 12 in a lateral direction parallel to the first main surface 3 of the SiC semiconductor layer 2.

[0038] The second wall portion 25 of the source trench 18 is located on the second main surface 4 side of the SiC semiconductor layer 2 relative to the second bottom wall 23 of the gate trench 12. In other words, the second wall portion 25 is the portion of the source trench 18 located on the second main surface 4 side of the SiC semiconductor layer 2 relative to the second bottom wall 23 of the gate trench 12.

[0039] With respect to the thickness direction of the SiC semiconductor layer 2, the length of the second wall portion 25 of the source trench 18 is greater than the length of the first wall portion 24 of the source trench 18. The second bottom wall 23 of the source trench 18 is located in the region between the first bottom wall 16 of the gate trench 12 and the second main surface 4 of the SiC semiconductor layer 2 with respect to the thickness direction of the SiC semiconductor layer 2.

[0040] In this embodiment, the second bottom wall 23 of the source trench 18 is located in the SiC epitaxial layer 6. The second bottom wall 23 of the source trench 18 may also be located in the SiC semiconductor substrate 5.

[0041] The barrier-forming layer 19 is formed in a film-like manner along the second side wall 22 and the second bottom wall 23 of the source trench 18, as well as along the corner 26 connecting the second side wall 22 and the second bottom wall 23. The barrier-forming layer 19 demarcates a concave space within the source trench 18.

[0042] The barrier-forming layer 19 is made of a different material from the conductive material of the source electrode layer 20. The barrier-forming layer 19 has a higher potential barrier than the potential barrier between the source electrode layer 20 and the deep well region 21.

[0043] A conductive barrier forming layer may be used as the barrier forming layer 19. The conductive barrier forming layer may contain at least one of conductive polysilicon, tungsten, platinum, nickel, cobalt, or molybdenum.

[0044] An insulating barrier forming layer may be used as the barrier forming layer 19. The insulating barrier forming layer may contain at least one of the following: impurity-free silicon, silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, or aluminum oxynitride. Figure 2 shows an example in which an insulating barrier forming layer is formed as the barrier forming layer 19.

[0045] The barrier-forming layer 19 is more specifically silicon oxide. It is preferable that the barrier-forming layer 19 and the gate insulating layer 13 are formed from the same material. In this case, it is preferable that the thickness of the barrier-forming layer 19 and the thickness of the gate insulating layer 13 are the same. When the barrier-forming layer 19 and the gate insulating layer 13 are formed from silicon oxide, the barrier-forming layer 19 and the gate insulating layer 13 can be formed simultaneously by a thermal oxidation treatment method.

[0046] The source electrode layer 20 is embedded in the concave space of the source trench 18, with the barrier forming layer 19 in between. The source electrode layer 20 may contain conductive polysilicon. The source electrode layer 20 may be n-type polysilicon with n-type impurities added, or p-type polysilicon with p-type impurities added.

[0047] The source electrode layer 20 may contain conductive polysilicon as well as at least one of titanium, nickel, copper, aluminum, silver, gold, titanium nitride, or tungsten.

[0048] The source electrode layer 20 may be formed from the same conductive material as the gate electrode layer 14. In this case, the gate electrode layer 14 and the source electrode layer 20 can be formed simultaneously. Of course, the source electrode layer 20 may be formed from a different conductive material than the gate electrode layer 14.

[0049] The deep well region 21 is formed in the SiC semiconductor layer 2 in a region along the source trench 18. The p-type impurity concentration in the deep well region 21 is 1.0 × 10⁻⁶. 17 cm -3 The above 1.0 × 10 19 cm-3 The following is also acceptable.

[0050] The deep well region 21 is formed in the SiC semiconductor layer 2 in a region along the second side wall 22 of the source trench 18. The deep well region 21 is formed in the SiC semiconductor layer 2 in a region along the second bottom wall 23 of the source trench 18.

[0051] In this embodiment, the deep well region 21 is continuously formed in the SiC semiconductor layer 2 along the second sidewall 22, corner 26, and second bottom wall 23 of the source trench 18. The deep well region 21 includes a first region 27 and a second region 28 along the second sidewall 22 of the source trench 18.

[0052] The first region 27 of the deep well region 21 is formed along the first wall portion 24 of the second sidewall 22 of the source trench 18. The second region 28 of the deep well region 21 is formed along the second wall portion 25 of the second sidewall 22 of the source trench 18. With respect to the thickness direction of the SiC semiconductor layer 2, the length of the second region 28 of the deep well region 21 is greater than the length of the first region 27 of the deep well region 21.

[0053] The thickness of the portion of the deep well region 21 that runs along the second bottom wall 23 of the source trench 18 may be greater than or equal to the thickness of the portion of the deep well region 21 that runs along the second side wall 22 of the source trench 18.

[0054] In the deep well region 21, the portion along the second bottom wall 23 of the source trench 18 may be located within the SiC semiconductor substrate 5, crossing the boundary region between the SiC semiconductor substrate 5 and the SiC epitaxial layer 6.

[0055] In the SiC semiconductor layer 2, p-type impurities are implanted along the direction normal to the first main surface 3 of the SiC semiconductor layer 2 in the portion along the second bottom wall 23 of the source trench 18. On the other hand, in the SiC semiconductor layer 2, p-type impurities are implanted in the portion along the second side wall 22 of the source trench 18 in a state inclined with respect to the first main surface 3 of the SiC semiconductor layer 2.

[0056] Therefore, in the SiC semiconductor layer 2, p-type impurities are injected at a deeper position along the second bottom wall 23 of the source trench 18 than along the second side wall 22 of the source trench 18. As a result, a difference in thickness occurs in the deep well region 21 between the portion along the second bottom wall 23 of the source trench 18 and the portion along the second side wall 22 of the source trench 18.

[0057] The surface layer of the first main surface 3 of the SiC semiconductor layer 2 contains p - A body region 30 of the type is formed. The body region 30 is formed in the region between the gate trench 12 and the source trench 18. In a plan view, the body region 30 is formed in a strip shape extending along the second direction Y.

[0058] Body region 30 is exposed from the first side wall 15 of gate trench 12 and the second side wall 22 of source trench 18. Body region 30 is connected to the first region 27 of deep well region 21.

[0059] The p-type impurity concentration in body region 30 is 1.0 × 10⁻⁶. 16 cm -3 The above 1.0 × 10 19 cm -3 The following are also possible: The p-type impurity concentration in the body region 30 may be approximately equal to the p-type impurity concentration in the deep well region 21. The p-type impurity concentration in the body region 30 may be higher than the p-type impurity concentration in the deep well region 21.

[0060] The surface layer of the body region 30 is n +A molded source region 31 is formed. The source region 31 is formed in the surface layer of the body region 30, in a region along the first side wall 15 of the gate trench 12. The source region 31 is exposed from the first side wall 15 of the gate trench 12.

[0061] The source region 31 may be formed in a strip shape extending along the second direction Y in a plan view. Although not shown, the source region 31 may include a portion exposed from the second side wall 22 of the source trench 18.

[0062] The width WS of the source region 31 may be 0.2 μm or more and 0.6 μm or less (for example, about 0.4 μm). In this embodiment, the width WS is the width along the first direction X in the source region 31. The n-type impurity concentration in the source region 31 is 1.0 × 10⁻⁶ 18 cm -3 The above 1.0 × 10 21 cm -3 The following is also acceptable.

[0063] The surface layer of the body region 30 is p + A type of contact region 32 is formed. The contact region 32 is formed in the surface layer of the body region 30 in a region along the second side wall 22 of the source trench 18. The contact region 32 is exposed from the second side wall 22 of the source trench 18.

[0064] The contact region 32 may be connected to the source region 31. The contact region 32 may be formed in a strip shape extending along the second direction Y in a plan view. The contact region 32 may include a portion exposed from the first side wall 15 of the adjacent gate trench 12.

[0065] The width WC of the contact region 32 may be 0.1 μm or more and 0.4 μm or less (for example, about 0.2 μm). In this embodiment, the width WC is the width along the first direction X in the contact region 32. The p-type impurity concentration in the contact region 32 is 1.0 × 10⁻⁶ 18 cm -3 The above 1.0 × 10 21cm -3 It may be as follows.

[0066] An insulating layer 40 is formed on the first main surface 3 of the SiC semiconductor layer 2. The insulating layer 40 collectively covers a plurality of trench gate structures 10. A contact hole 41 is formed in the insulating layer 40. The contact hole 41 selectively exposes the trench source structure 11, the source region 31, and the contact region 32.

[0067] A main surface source electrode 42 is formed on the insulating layer 40. The main surface source electrode 42 enters the contact hole 41 from above the insulating layer 40. The main surface source electrode 42 is electrically connected to the source electrode layer 20, the source region 31, and the contact region 32 within the contact hole 41.

[0068] The main surface source electrode 42 may be formed of the same conductive material as the source electrode layer 20. The main surface source electrode 42 may be formed of a conductive material different from the source electrode layer 20.

[0069] In this form, the source electrode layer 20 includes n-type polysilicon or p-type polysilicon, and the main surface source electrode 42 includes a metal material containing aluminum or aluminum as a main component. The main surface source electrode 42 may include at least one of conductive polysilicon, titanium, nickel, copper, aluminum, silver, gold, titanium nitride, or tungsten.

[0070] The main surface source electrode 42 may be composed of an electrode layer integrally formed with the source electrode layer 20. In this case, the source electrode layer 20 and the main surface source electrode �2 may be formed through a common process.

[0071] Hereinafter, the dimensions of the trench gate structure 10 and the dimensions of the trench source structure 11 will be specifically described.

[0072] The trench gate structure 10 has an aspect ratio D1 / W1. The aspect ratio D1 / W1 of the trench gate structure 10 is defined by the ratio of the depth D1 of the trench gate structure 10 to the width W1 of the trench gate structure 10.

[0073] The width W1 is, in this form, the width along the first direction X in the trench gate structure 10. The aspect ratio D1 / W1 of the trench gate structure 10 is also the aspect ratio of the gate trench 12.

[0074] The aspect ratio D1 / W1 of the trench gate structure 10 may be 0.25 or more and 15.0 or less. The width W1 of the trench gate structure 10 may be 0.2 μm or more and 2.0 μm or less (for example, about 0.4 μm). The depth D1 of the trench gate structure 10 may be 0.5 μm or more and 3.0 μm or less (for example, about 1.0 μm).

[0075] The trench source structure 11 has an aspect ratio D2 / W2. The aspect ratio D2 / W2 of the trench source structure 11 is the ratio of the depth D2 of the trench source structure 11 to the width W2 of the trench source structure 11.

[0076] The width W2 of the trench source structure 11 is the sum of the width WST of the source trench 18, the first width Wα of the deep well region 21, and the second width Wβ of the deep well region 21 (W2 = WST + Wα + Wβ).

[0077] The width WST is, in this form, the width along the first direction X in the source trench 18. The first width Wα is, in this form, the width along the first direction X of the portion along the second side wall 22 on one side of the source trench 18 in the deep well region 21. The second width Wβ is, in this form, the width along the first direction X of the portion along the second side wall 22 on the other side of the source trench 18 in the deep well region 21.

[0078] The aspect ratio D2 / W2 of the trench source structure 11 is greater than the aspect ratio D1 / W1 of the trench gate structure 10. The aspect ratio D2 / W2 of the trench source structure 11 may be between 0.5 and 18.0.

[0079] The ratio D2 / D1 of the depth of the trench source structure 11 to the depth D1 of the trench gate structure 10 may be between 1.5 and 4.0. Increasing the depth D2 of the trench source structure 11 can also enhance the pressure-resistant holding effect of the SJ (Super Junction) structure.

[0080] The width W2 of the trench source structure 11 may be 0.6 μm or more and 2.4 μm or less (for example, about 0.8 μm). The depth D2 of the trench source structure 11 may be 1.5 μm or more and 11 μm or less (for example, about 2.5 μm). The width W2 of the trench source structure 11 may be equal to the width W1 of the trench gate structure 10. The width W2 of the trench source structure 11 may be different from the width W1 of the trench gate structure 10.

[0081] In the trench source structure 11, the source trench 18 has an aspect ratio DST / WST. The aspect ratio DST / WST of the source trench 18 is the ratio of the depth DST of the source trench 18 to the width WST of the source trench 18.

[0082] The aspect ratio DST / WST of the source trench 18 is greater than the aspect ratio D1 / W1 of the trench gate structure 10. The aspect ratio DST / WST of the source trench 18 may be between 0.5 and 18.0.

[0083] The width WST of the source trench 18 may be between 0.2 μm and 2.0 μm (for example, about 0.4 μm). The width WST of the source trench 18 may also be equal to the width W1 of the gate trench 12 (WST = W1).

[0084] If the width WST of the source trench 18 or the width W1 of the gate trench 12 differs along the depth direction, the widths WST and W1 are defined as the widths of the openings. The depth DST of the source trench 18 may be between 1.0 μm and 10 μm (for example, about 2.0 μm).

[0085] The ratio of the depth DST of the source trench 18 to the depth D1 of the trench gate structure 10 (gate trench 12) is preferably 2 or greater. The ratio DST / D1 of the depth DST of the source trench 18 to the depth D1 of the trench gate structure 10 may exceed 4.0. In this case, attention must be paid to the durability of the resist mask used when forming the source trench 18 by etching.

[0086] For example, if the depth D1 of the trench gate structure 10 is approximately 3.0 μm and the ratio DST / D1 exceeds 4, it is expected that etching will cause the resist mask to approach or exceed its durability limit. When the resist mask exceeds its durability limit, unwanted etching of the SiC semiconductor layer 2 occurs.

[0087] Therefore, the ratio DST / D1 of the depth of the source trench 18 to the depth D1 of the trench gate structure 10 is preferably greater than 1.0 and less than or equal to 4.0. If the ratio DST / D1 is within this range, the source trench 18 can be formed appropriately.

[0088] Figure 3 is a cross-sectional view illustrating the operation of the semiconductor device 1 shown in Figure 1. In Figure 3, the same reference numerals are used for structures similar to those in Figure 2.

[0089] In semiconductor device 1, a pn junction 45 is formed in the boundary region between the SiC semiconductor layer 2 and the deep well region 21. When semiconductor device 1 switches from the ON state to the OFF state, a depletion layer 46 extends from the pn junction 45 toward the SiC semiconductor layer 2. In Figure 3, the depletion layer 46 is shown by a dashed line.

[0090] The deep well region 21 includes a first region 27 and a second region 28. The first region 27 is formed along a first wall portion 24 of a second side wall 22 of the source trench 18. The second region 28 is formed along a second wall portion 25 of the second side wall 22 of the source trench 18.

[0091] The depletion layer 46 from the pn junction 45 extends in the SiC semiconductor layer 2 in a region closer to the first main surface 3 than the first bottom wall 16 of the gate trench 12. The depletion layer 46 from the pn junction 45 extends in the SiC semiconductor layer 2 in a region closer to the second main surface 4 than the first bottom wall 16 of the gate trench 12.

[0092] When the semiconductor device 1 switches from the on state to the off state, the current path of the short - circuit current flowing from the drain electrode 7 toward the source electrode layer 20 is constricted by the depletion layer 46. Thereby, the time until the semiconductor device 1 reaches breakdown can be delayed.

[0093] In particular, according to the semiconductor device 1, the aspect ratio D2 / W2 of the trench source structure 11 is larger than the aspect ratio D1 / W1 of the trench gate structure 10. The aspect ratio D2 / W2 of the trench source structure 11 is 0.5 or more and 18.0 or less.

[0094] Moreover, the ratio D2 / D1 of the depth D2 of the trench source structure 11 to the depth D1 of the trench gate structure 10 is 1.5 or more and 4.0 or less. In the thickness direction of the SiC semiconductor layer 2, the length of the second region 28 of the deep well region 21 is larger than the length of the first region 27 of the deep well region 21.

[0095] Therefore, in the SiC semiconductor layer 2, the ratio of the area occupied by the depletion layer 46 extending in the region on the second main surface 4 side can be surely increased more than the ratio of the area occupied by the depletion layer 46 extending in the region on the first main surface 3 side. Thereby, the current path of the short - circuit current can be surely constricted in the region on the drain electrode 7 side.

[0096] The depletion layer 46 from the pn junction 45 may overlap the first bottom wall 16 of the gate trench 12. The depletion layer 46 on the second region 28 side of the deep well region 21 may overlap the first bottom wall 16 of the gate trench 12.

[0097] In this structure, the current path of the short-circuit current can be reliably narrowed in the region on the drain electrode 7 side. Of course, the depletion layer 46 on the first region 27 side of the deep well region 21 may overlap the first bottom wall 16 of the gate trench 12.

[0098] Furthermore, according to semiconductor device 1, the area occupied by the depletion layer 46 in the SiC semiconductor layer 2 can be increased, and thus the feedback capacitance Crss can be reduced inversely. The feedback capacitance Crss is the capacitance between the gate electrode layer 14 and the drain electrode 7.

[0099] As described above, semiconductor device 1 can improve short-circuit withstand capability and reduce feedback capacitance Crss.

[0100] Furthermore, according to the semiconductor device 1, a barrier-forming layer 19 is formed within the source trench 18. The barrier-forming layer 19 has a potential barrier that is higher than the potential barrier between the deep well region 21 and the source electrode layer 20.

[0101] Therefore, even if the depletion layer 46 extending from the pn junction 45 between the SiC semiconductor layer 2 and the deep well region 21 comes into contact with the inner wall surface of the source trench 18, punch-through can be suppressed. This suppresses leakage current caused by punch-through.

[0102] In the absence of the barrier-forming layer 19, punch-through tends to be more pronounced at the corners 26 of the source trench 18. This is because the depletion layer 46 extends from the second side wall 22 of the source trench 18 further along the second bottom wall 23 of the source trench 18.

[0103] Therefore, in the semiconductor device 1, the inner wall surface of the source trench 18, including the corner portion 26, is covered with a barrier-forming layer 19. This effectively suppresses the occurrence of punch-through in the source trench 18.

[0104] According to semiconductor device 1, from the viewpoint of design related to short-circuit withstand capability and feedback capacitance Crss, a depletion layer 46 is formed over a relatively wide area in the SiC semiconductor layer 2, but the barrier forming layer 19 can appropriately suppress the leakage current caused by the depletion layer 46.

[0105] Figure 4 is a graph showing the drain current-drain voltage characteristics of semiconductor device 1 shown in Figure 1. In Figure 4, the vertical axis represents the drain current ID [A / cm²]. 2 The horizontal axis represents the drain voltage VD [V]. The drain current ID is the current (short-circuit current) flowing between the drain electrode 7 and the source electrode layer 20.

[0106] Figure 4 shows curves L1 and L2. Both curves L1 and L2 were obtained by simulation. Curves L1 and L2 show the change in drain current ID when a drain voltage VD within a predetermined range is applied to the drain electrode 7. The drain voltage VD is varied within the range of 0V to 1000V.

[0107] Curve L1 shows the drain current-drain voltage characteristics of the semiconductor device in the reference example. Curve L2 shows the drain current-drain voltage characteristics of semiconductor device 1. The semiconductor device in the reference example has the same structure as semiconductor device 1, except that the depth D2 of the source trench 18 is equal to the depth D1 of the gate trench 12.

[0108] Referring to curve L1, in the semiconductor device shown in the example, when the drain voltage VD exceeds 200V, the drain current ID is 15000A / cm². 2 It exceeds this. On the other hand, referring to curve L2, in semiconductor device 1, the drain voltage VD is in the range of 0V to 1000V and the drain current ID is 15000A / cm 2It is less than.

[0109] In semiconductor device 1, when the drain voltage VD is in the range of 400V to 1000V, the drain current ID is 10000A / cm 2 More than 15000A / cm 2 It falls within the range of less than.

[0110] When the drain voltage VD is 600V, the drain current ID of semiconductor device 1 is approximately 45% lower than the drain current ID of the semiconductor device in the reference example.

[0111] From these simulation results, it was confirmed that the short-circuit withstand capability can be significantly improved by forming a deep well region 21 along the source trench 18, which is deeper than the gate trench 12.

[0112] Figure 5 is a graph showing the feedback capacitance-drain voltage characteristics of semiconductor device 1 shown in Figure 1. In Figure 5, the vertical axis represents the feedback capacitance Crss [F / cm]. 2 The horizontal axis represents the drain voltage VD [V].

[0113] Figure 5 shows curves L3 and L4. Both curves L3 and L4 were obtained by simulation. Curves L3 and L4 show the change in feedback capacitance Crss when a drain voltage VD within a predetermined range is applied to the drain electrode 7. The drain voltage VD is varied within the range of 0V to 1000V.

[0114] Curve L3 shows the feedback capacitance-drain voltage characteristics of the semiconductor device in the reference example. Curve L4 shows the feedback capacitance-drain voltage characteristics of semiconductor device 1. The semiconductor device in the reference example has the same structure as semiconductor device 1, except that the depth D2 of the source trench 18 is equal to the depth D1 of the gate trench 12.

[0115] Referring to curve L3, in the semiconductor device described in the reference example, the feedback capacitance Crss decreases gradually in the drain voltage VD range from 1V to 10V. In the semiconductor device described in the reference example, the rate of decrease in feedback capacitance Crss is approximately 25% in the drain voltage VD range from 1V to 10V.

[0116] On the other hand, in semiconductor device 1, the feedback capacitance Crss decreases sharply in the drain voltage VD range from 1V to 10V. When the drain voltage VD is 10V, the feedback capacitance Crss of semiconductor device 1 is reduced by approximately 95% compared to the feedback capacitance Crss of the semiconductor device in the reference example. In semiconductor device 1, the rate of reduction of feedback capacitance Crss is between 95% and 99% in the drain voltage VD range from 1V to 10V.

[0117] From these simulation results, it was confirmed that the feedback capacitance Crss can be significantly reduced by forming a deep well region 21 along the source trench 18, which is deeper than the gate trench 12. In other words, it was confirmed that the switching speed can be significantly improved by reducing the feedback capacitance Crss.

[0118] Figure 6 is a cross-sectional view showing a semiconductor device 51 according to a second embodiment of the present invention. In the following description, structures corresponding to the structures described for semiconductor device 1 are given the same reference numerals and their descriptions are omitted.

[0119] Referring to Figure 6, the source region 31 is exposed from the first side wall 15 of the gate trench 12 and the second side wall 22 of the source trench 18. The contact region 32 is formed within the deep well region 21 in the region along the second bottom wall 23 of the source trench 18. The contact region 32 is exposed from the second bottom wall 23 of the source trench 18.

[0120] The contact region 32 may cover the entire second bottom wall 23 of the source trench. The p-type impurity concentration in the contact region 32 is greater than the p-type impurity concentration in the deep well region 21.

[0121] Figure 6 shows an example in which the barrier forming layer 19 consists of a conductive barrier forming layer. The barrier forming layer 19 is formed along the inner wall surface of the source trench 18, selectively exposing the contact region 32 from the second bottom wall 23 of the source trench 18.

[0122] The barrier-forming layer 19 more specifically includes a first portion 52 and a second portion 53. The first portion 52 of the barrier-forming layer 19 covers the second side wall 22 of the source trench 18. The second portion 53 of the barrier-forming layer 19 partially covers the second bottom wall 23 of the source trench 18.

[0123] The second portion 53 of the barrier-forming layer 19 is continuous with the first portion 52 of the barrier-forming layer 19. The second portion 53 of the barrier-forming layer 19 extends from the corner 26 of the source trench 18 along the second bottom wall 23.

[0124] The second portion 53 of the barrier-forming layer 19 exposes the central part of the second bottom wall 23 of the source trench 18. The second portion 53 of the barrier-forming layer 19 may be formed in an endless (annular) shape in plan view.

[0125] As described above, semiconductor device 51 can achieve the same effects as those described for semiconductor device 1. Furthermore, with semiconductor device 51, even if the depletion layer 46 extends from the corner 26 of the source trench 18 along the second bottom wall 23, the barrier forming layer 19 can increase the distance for the depletion layer 46 to reach the source electrode layer 20. This makes it possible to suppress the occurrence of punch-through near the corner 26 of the source trench 18.

[0126] Figure 7 is a cross-sectional view showing a semiconductor device 61 according to a third embodiment of the present invention. In the following description, structures corresponding to the structures described for the semiconductor device 51 are given the same reference numerals and their descriptions are omitted.

[0127] The deep well region 21 has an exposed portion 62 that selectively exposes the second bottom wall 23 of the source trench 18. More specifically, the second region 28 of the deep well region 21 is formed along the corner portion 26 of the source trench 18 so as to expose the central portion of the second bottom wall 23 of the source trench 18. The second region 28 of the deep well region 21 may be formed in an endless (ring-shaped) manner in plan view.

[0128] In this configuration, the contact region 32 is not formed. The contact region 32 may be formed in the surface layer of the body region 30 in a region along the second side wall 22 of the source trench 18.

[0129] The source electrode layer 20 forms a heterojunction with the SiC semiconductor layer 2 in the exposed portion 62 of the deep well region 21. This forms a heterojunction diode 63 in which the source electrode layer 20 acts as the anode and the SiC semiconductor layer 2 acts as the cathode.

[0130] The source electrode layer 20 may contain conductive polysilicon. Of course, as long as a heterojunction diode 63 is formed, the source electrode layer 20 may contain conductive materials other than conductive polysilicon.

[0131] A body diode 64 is formed at the pn junction between the SiC semiconductor layer 2 and the body region 30. The junction barrier of the heterojunction diode 63 is smaller than the diffusion potential of the body diode 64. The junction barrier of the heterojunction diode 63 may be between 1.0 eV and 1.5 eV. The diffusion potential of the body diode 64 may be between 2.8 eV and 3.2 eV.

[0132] As described above, the semiconductor device 61 can achieve the same effects as those described for the semiconductor device 51. Furthermore, in the semiconductor device 61, when a reverse bias voltage is applied, current can be preferentially supplied to the heterojunction diode 63. This suppresses the expansion of SiC crystal defects in the SiC semiconductor layer 2. As a result, it is possible to suppress the increase in on-resistance while improving short-circuit withstand capability and reducing the feedback capacitance Crss.

[0133] Figure 8 is a cross-sectional view showing a semiconductor device 71 according to a fourth embodiment of the present invention. In the following description, structures corresponding to the structures described for the semiconductor device 51 are given the same reference numerals and their descriptions are omitted.

[0134] The barrier-forming layer 19 has a laminated structure including a plurality of barrier-forming layers formed along the inner wall of the source trench 18. In this embodiment, the barrier-forming layer 19 has a laminated structure including an insulating barrier-forming layer 72 and a conductive barrier-forming layer 73, which are laminated in this order from the inner wall of the source trench 18.

[0135] The insulating barrier forming layer 72 is formed in a film-like manner along the inner wall surface of the source trench 18. The insulating barrier forming layer 72 selectively exposes the contact region 32 from the second bottom wall 23 of the source trench 18.

[0136] The insulating barrier forming layer 72 more specifically includes a first portion 74 and a second portion 75. The first portion 74 covers the second side wall 22 of the source trench 18. The second portion 75 selectively covers the second bottom wall 23 of the source trench 18.

[0137] The second section 75 is connected to the first section 74. The second section 75 extends from the corner 26 of the source trench 18 along the second bottom wall 23, exposing the central part of the second bottom wall 23 of the source trench 18.

[0138] The insulating barrier forming layer 72 may contain at least one of the following: impurity-free silicon, silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, or aluminum oxynitride.

[0139] The conductive barrier forming layer 73 is formed as a film along the insulating barrier forming layer 72 so as to selectively expose the contact region 32 from the second bottom wall 23 of the source trench 18. The conductive barrier forming layer 73 contains a conductive material different from the conductive material of the source electrode layer 20.

[0140] The conductive barrier forming layer 73 may be formed of the same conductive material as the conductive material of the gate electrode layer 14. The conductive barrier forming layer 73 may contain at least one of conductive polysilicon, tungsten, platinum, nickel, cobalt, or molybdenum.

[0141] As described above, the semiconductor device 71 can achieve the same effects as those described for the semiconductor device 51. Furthermore, in the semiconductor device 71, the barrier forming layer 19 has a laminated structure including an insulating barrier forming layer 72 and a conductive barrier forming layer 73. As a result, the occurrence of punch-through can be suppressed by the two layers of the insulating barrier forming layer 72 and the conductive barrier forming layer 73.

[0142] If the conductive material of the conductive barrier forming layer 73 is the same as the conductive material of the gate electrode layer 14, then the gate electrode layer 14 and the conductive barrier forming layer 73 can be formed by the same process. Therefore, an increase in the number of steps can be suppressed.

[0143] Figure 9 is a cross-sectional view showing a semiconductor device 81 according to a fifth embodiment of the present invention. In the following description, structures corresponding to the structures described for semiconductor device 1 are given the same reference numerals and their descriptions are omitted.

[0144] The barrier forming layer 19 includes a first portion 82 and a second portion 83. The first portion 82 of the barrier forming layer 19 covers the second side wall 22 of the source trench 18. The second portion 83 of the barrier forming layer 19 covers the second bottom wall 23 of the source trench 18.

[0145] The first portion 82 of the barrier forming layer 19 selectively has sidewall contact holes 84 that expose the SiC semiconductor layer 2 from the second sidewall 22 of the source trench 18. The first portion 82 covers the first wall portion 24 of the source trench 18 and exposes the second wall portion 25.

[0146] The first portion 82 may be formed to traverse the boundary region between the SiC semiconductor layer 2 and the body region 30. The end of the first portion 82 on the second main surface 4 side may be formed in a region deeper than the bottom of the body region 30.

[0147] In the first portion 82, the end on the second main surface 4 side may be formed in a region shallower than the bottom of the body region 30. In the first portion 82, the end on the second main surface 4 side may be formed in a region between the bottom of the body region 30 and the bottom of the contact region 32. In these cases, the source electrode layer 20 is connected to at least the body region 30 within the source trench 18.

[0148] In the first portion 82, the end on the second main surface 4 side may be formed in the region between the first main surface 3 of the SiC semiconductor layer 2 and the bottom of the contact region 32. The barrier forming layer 19 may not have the first portion 82 and may have only the second portion 83. In these cases, the source electrode layer 20 is connected to the body region 30 and the contact region 32 within the source trench 18.

[0149] The second portion 83 of the barrier forming layer 19 is formed at a distance from the first portion 82 of the barrier forming layer 19. The second portion 83 is separated from the first portion 82. The second portion 83 may cover the corner 26 of the source trench 18.

[0150] The second portion 83 may expose the corner 26 of the source trench 18. The second portion 83 may cover the corner 26 of the source trench 18 and also cover a portion of the second side wall 22 of the source trench 18.

[0151] The source electrode layer 20 forms a Schottky junction with the SiC semiconductor layer 2 within the source trench 18. This forms a Schottky barrier diode 85 with the source electrode layer 20 as the anode and the SiC semiconductor layer 2 as the cathode.

[0152] The source electrode layer 20 may be formed of the same conductive material as the main surface source electrode 42. The source electrode layer 20 and the main surface source electrode 42 may be formed of aluminum or a metallic material that mainly contains aluminum.

[0153] The source electrode layer 20 and the main surface source electrode 42 may contain at least one of conductive polysilicon, titanium, nickel, copper, aluminum, silver, gold, titanium nitride, or tungsten. In this case, the gate electrode layer 14 is preferably formed of polysilicon (n-type polysilicon or p-type polysilicon).

[0154] The p-type deep well region 21 is formed in the SiC semiconductor layer 2 in a region along the second bottom wall 23 of the source trench 18. The deep well region 21 may also be formed continuously in the SiC semiconductor layer 2 in a region along the second side wall 22 and the corner 26 of the source trench 18, so as to expose the source electrode layer 20 from the second side wall 22 of the source trench 18.

[0155] In other words, the deep well region 21 covers the second bottom wall 23 of the source trench 18. The deep well region 21 also covers the corner 26 connecting the second side wall 22 and the second bottom wall 23 of the source trench 18. The deep well region 21 may expose almost the entire second side wall 22 of the source trench 18 in the SiC semiconductor layer 2.

[0156] The deep well region 21 is drawn out laterally from the second bottom wall 23 of the source trench 18, parallel to the first main surface 3 of the SiC semiconductor layer 2. As a result, the deep well region 21 faces the body region 30 with respect to the direction normal to the first main surface 3 of the SiC semiconductor layer 2, with a portion of the SiC semiconductor layer 2 in between.

[0157] More specifically, the source electrode layer 20 forms a Schottky junction with the SiC semiconductor layer 2 at a depth position between the body region 30 and the deep well region 21, with respect to the normal direction of the first main surface 3 of the SiC semiconductor layer 2.

[0158] More specifically, the source electrode layer 20 forms a Schottky junction with the SiC semiconductor layer 2 in the region sandwiched between the body region 30 and the deep well region 21 in the SiC semiconductor layer 2, with respect to the normal direction of the first main surface 3 of the SiC semiconductor layer 2.

[0159] The width W2 of the trench source structure 11 may coincide with the width WST of the source trench 18. In other words, the first width Wα and the second width Wβ of the deep well region 21 may both be zero.

[0160] As described above, semiconductor device 81 can achieve the same effects as those described for semiconductor device 1. Furthermore, in semiconductor device 81, when a reverse bias voltage is applied, current can be preferentially supplied to the Schottky barrier diode 85. This suppresses the expansion of SiC crystal defects in the SiC semiconductor layer 2. As a result, it is possible to improve short-circuit withstand capability and reduce feedback capacitance Crss while suppressing an increase in on-resistance.

[0161] In this embodiment, an example was described in which the source electrode layer 20 forms a Schottky junction with the SiC semiconductor layer 2 within the sidewall contact hole 84 of the barrier forming layer 19. However, an embodiment in which the barrier forming layer 19 (first portion 82 and second portion 83) is not formed may also be adopted.

[0162] Figure 10 is a plan view of a semiconductor device 91 according to the sixth embodiment of the present invention. In the following description, structures corresponding to the structures described for semiconductor device 1 are given the same reference numerals and their descriptions are omitted.

[0163] Referring to Figure 10, in this embodiment, the trench gate structure 10 is formed in a grid pattern in plan view. The trench source structure 11 may be formed within the region surrounded by the trench gate structure 10.

[0164] The source region 31 may be formed along the periphery of the trench gate structure 10. The contact region 32 may be formed along the periphery of the trench source structure 11.

[0165] As described above, the semiconductor device 91 can produce the same effects as those described for the semiconductor device 1. Furthermore, the semiconductor device 91 can also increase the current density flowing through the SiC semiconductor layer 2.

[0166] The structure of the semiconductor device 91 can also be applied to each of the embodiments described above. In other words, the structure in which the trench gate structure 10 is formed in a grid pattern in a plan view, and the trench source structure 11 is formed within the region surrounded by the trench gate structure 10, can also be applied to each of the embodiments described above.

[0167] Although the first to sixth embodiments of the present invention have been described, the first to sixth embodiments of the present invention can also be implemented in other forms.

[0168] In the first to sixth embodiments described above, the barrier forming layer 19 may selectively expose the SiC semiconductor layer 2 from the second sidewall 22 of the source trench 18. For example, the barrier forming layer 19 may expose at least one of the contact region 32, the source region 31, and the body region 30 within the source trench 18.

[0169] In the first to sixth embodiments described above, a structure in which the barrier-forming layer 19 is omitted may be adopted.

[0170] In the first to sixth embodiments described above, the gate trench 12 may be formed in a tapered shape in cross-sectional view, where the area of ​​the first bottom wall 16 is smaller than the opening area.

[0171] In the first to sixth embodiments described above, the first bottom wall 16 of the gate trench 12 may be formed parallel to the first main surface 3 of the SiC semiconductor layer 2. The first bottom wall 16 of the gate trench 12 may be formed in a convex curved shape extending from the first side wall 15 toward the second main surface 4 of the SiC semiconductor layer 2.

[0172] In the first to sixth embodiments described above, the source trench 18 may be formed in a tapered shape in cross-sectional view, where the area of ​​the second bottom wall 23 is smaller than the opening area.

[0173] In the first to sixth embodiments described above, the second bottom wall 23 of the source trench 18 may be formed parallel to the first main surface 3 of the SiC semiconductor layer 2. The second bottom wall 23 of the source trench 18 may be formed in a convex curved shape that extends outward from the second side wall 22.

[0174] In the first to sixth embodiments described above, a Si (silicon) semiconductor layer (2) may be used instead of the SiC single crystal SiC semiconductor layer (2). In other words, the Si semiconductor layer (2) may have a stacked structure including a Si semiconductor substrate (5) and a Si epitaxial layer (6).

[0175] In the first to sixth embodiments described above, a structure in which the conductivity type of each semiconductor portion is reversed may be employed. That is, the p-type portion may be formed as n-type, and the n-type portion may be formed as p-type.

[0176] In the first to sixth embodiments described above, n + Instead of the type SiC semiconductor substrate 5, p +A SiC semiconductor substrate of type (5) may be used. This structure allows for the provision of an IGBT (Insulated Gate Bipolar Transistor) instead of a MISFET.

[0177] In this case, the "source" of the MISFET is replaced with the "emitter" of the IGBT. Also, the "drain" of the MISFET is replaced with the "collector" of the IGBT. Even when an IGBT is used instead of a MISFET, the same effects as those described in each of the embodiments above can be achieved.

[0178] Figure 11 is a plan view showing a semiconductor device 101 according to the seventh embodiment of the present invention.

[0179] Referring to Figure 11, the semiconductor device 101 has a SiC semiconductor layer 102 containing a SiC (silicon carbide) single crystal. The SiC semiconductor layer 102 may also contain a 4H-SiC single crystal.

[0180] A 4H-SiC single crystal has an off-angle tilted at an angle of no more than 10° from the (0001) plane with respect to the [11-20] direction. The off-angle may be between 0° and 4°. The off-angle may be greater than 0° and less than 4°. Typically, the off-angle is set to 2° or 4°, more specifically in the range of 2°±0.2° or 4°±0.4°.

[0181] In this embodiment, the SiC semiconductor layer 102 is formed in the shape of a rectangular parallelepiped chip. The SiC semiconductor layer 102 has a first main surface 103 on one side, a second main surface 104 on the other side, and sides 105A, 105B, 105C, and 105D that connect the first main surface 103 and the second main surface 104.

[0182] The first main surface 103 and the second main surface 104 are formed in a rectangular shape when viewed from the direction of their normals (hereinafter simply referred to as "plan view"). Side surface 105A is opposite side surface 105C. Side surface 105B is opposite side surface 105D.

[0183] Sides 105A to 105D extend planarly along the normal directions of the first main surface 103 and the second main surface 104, respectively. The lengths of sides 105A to 105D may be between 1 mm and 10 mm (for example, between 2 mm and 5 mm).

[0184] The SiC semiconductor layer 102 has an active region 106 and an outer region 107. The active region 106 is the region where a vertical MISFET (Metal Insulator Semiconductor Field Effect Transistor) is formed. The outer region 107 is the region outside the active region 106.

[0185] In a plan view, the active region 106 is located in the central part of the SiC semiconductor layer 102, spaced apart from the sides 105A to 105D of the SiC semiconductor layer 102 and extending inward. In a plan view, the active region 106 is set to a rectangular shape with four sides parallel to the four sides 105A to 105D of the SiC semiconductor layer 102.

[0186] The outer region 107 is defined as the region between the side surfaces 105A to 105D of the SiC semiconductor layer 102 and the periphery of the active region 106. In a plan view, the outer region 107 is defined as an endless (quadrilateral ring) shape surrounding the active region 106.

[0187] A gate pad 108, gate finger 109, and source pad 110 are formed on the first main surface 103 of the SiC semiconductor layer 102 as first main surface electrodes. In Figure 11, the gate pad 108, gate finger 109, and source pad 110 are indicated by hatching for clarity. The gate pad 108, gate finger 109, and source pad 110 may contain aluminum or copper.

[0188] The gate pad 108 is formed along the side surface 105A of the SiC semiconductor layer 102 in a plan view. The gate pad 108 is formed along the central region of the side surface 105A of the SiC semiconductor layer 102 in a plan view. The gate pad 108 may also be formed along the corner connecting any two of the four side surfaces 105A to 105D of the SiC semiconductor layer 102 in a plan view.

[0189] The gate pad 108 is formed in a rectangular shape in plan view. The gate pad 108 is drawn out from the outer region 107 into the active region 106 so as to cross the boundary region between the outer region 107 and the active region 106 in plan view.

[0190] The gate finger 109 is formed in the outer region 107. The gate finger 109 is drawn out from the gate pad 108 and extends in a strip shape across the outer region 107. In this embodiment, the gate finger 109 is formed along three sides 105A, 105B, and 105D of the SiC semiconductor layer 102 so as to partition the active region 106 from three directions.

[0191] The source pad 110 is formed in the active region 106, spaced apart from the gate pad 108 and gate finger 109. The source pad 110 is formed in a concave shape in plan view so as to cover the concave region demarcated by the gate pad 108 and gate finger 109.

[0192] A gate voltage is applied to the gate pad 108 and gate finger 109. The gate voltage may be between 10V and 50V (for example, around 30V). A source voltage is applied to the source pad 110. The source voltage may be a reference voltage (for example, GND voltage).

[0193] Figure 12 is an enlarged view of region XII shown in Figure 11, illustrating the structure of the first main surface 103 of the SiC semiconductor layer 102. Figure 13 is a cross-sectional view along the line XIII-XIII shown in Figure 12. Figure 14 is a cross-sectional view along the line XIV-XIV shown in Figure 12.

[0194] Referring to Figures 12 to 14, the SiC semiconductor layer 102 in this configuration is n + It has a stacked structure including an n-type SiC semiconductor substrate 111 and an n-type SiC epitaxial layer 112. The second main surface 104 of the SiC semiconductor layer 102 is formed by the SiC semiconductor substrate 111.

[0195] The first main surface 103 of the SiC semiconductor layer 102 is formed by the SiC epitaxial layer 112. The second main surface 104 of the SiC semiconductor layer 102 may be a ground surface. The second main surface 104 of the SiC semiconductor layer 102 may have grinding marks.

[0196] The thickness of the SiC semiconductor substrate 111 may be 1 μm or more and less than 1000 μm. The thickness of the SiC semiconductor substrate 111 may be 5 μm or more. The thickness of the SiC semiconductor substrate 111 may be 25 μm or more. The thickness of the SiC semiconductor substrate 111 may be 50 μm or more. The thickness of the SiC semiconductor substrate 111 may be 100 μm or more.

[0197] The thickness of the SiC semiconductor substrate 111 may be 700 μm or less. The thickness of the SiC semiconductor substrate 111 may be 500 μm or less. The thickness of the SiC semiconductor substrate 111 may be 400 μm or more. The thickness of the SiC semiconductor substrate 111 may be 300 μm or less.

[0198] The thickness of the SiC semiconductor substrate 111 may be 250 μm or less. The thickness of the SiC semiconductor substrate 111 may be 200 μm or less. The thickness of the SiC semiconductor substrate 111 may be 150 μm or less. The thickness of the SiC semiconductor substrate 111 may be 100 μm or less.

[0199] The thickness of the SiC semiconductor substrate 111 is preferably 150 μm or less. By reducing the thickness of the SiC semiconductor substrate 111, the resistance can be reduced by shortening the current path.

[0200] The thickness of the SiC epitaxial layer 112 may be between 1 μm and 100 μm. The thickness of the SiC epitaxial layer 112 may be 5 μm or more. The thickness of the SiC epitaxial layer 112 may be 10 μm or more.

[0201] The thickness of the SiC epitaxial layer 112 may be 50 μm or less. The thickness of the SiC epitaxial layer 112 may be 40 μm or less. The thickness of the SiC epitaxial layer 112 may be 30 μm or less.

[0202] The thickness of the SiC epitaxial layer 112 may be 20 μm or less. Preferably, the thickness of the SiC epitaxial layer 112 is 15 μm or less. Preferably, the thickness of the SiC epitaxial layer 112 is 10 μm or less.

[0203] The n-type impurity concentration in the SiC epitaxial layer 112 is less than or equal to the n-type impurity concentration in the SiC semiconductor substrate 111. More specifically, the n-type impurity concentration in the SiC epitaxial layer 112 is less than the n-type impurity concentration in the SiC semiconductor substrate 111.

[0204] The n-type impurity concentration of the SiC semiconductor substrate 111 is 1.0 × 10⁻⁶. 18 cm -3 The above 1.0 × 10 21 cm -3 The following may also apply: The n-type impurity concentration in the SiC epitaxial layer 112 is 1.0 × 10⁻⁶. 15 cm -3 The above 1.0 × 10 18 cm -3 The following may also be the case: In this embodiment, the SiC epitaxial layer 112 has multiple regions having different n-type impurity concentrations along the direction normal to the first main surface 103 of the SiC semiconductor layer 102.

[0205] More specifically, the SiC epitaxial layer 112 includes a high-concentration region 112a with a relatively high n-type impurity concentration, and a low-concentration region 112b with a lower n-type impurity concentration compared to the high-concentration region 112a. The high-concentration region 112a is formed in the region on the first main surface 103 side. The low-concentration region 112b is formed in the region on the SiC semiconductor substrate 111 side relative to the high-concentration region 112a.

[0206] The n-type impurity concentration in the high-concentration region 112a is 1 × 10⁻⁶ 16 cm -3 The above 1 x 10 18 cm -3 The following may also apply: The n-type impurity concentration in the low-concentration region 112b is 1 × 10⁻⁶. 15 cm -3 The above 1 x 10 16 cm -3 The following is also possible: The thickness of the high-concentration region 112a is less than or equal to the thickness of the low-concentration region 112b. More specifically, the thickness of the high-concentration region 112a is less than the thickness of the low-concentration region 112b.

[0207] A drain pad 113, serving as a second main surface electrode, is connected to the second main surface 104 of the SiC semiconductor layer 102. The maximum voltage that can be applied between the source pad 110 and the drain pad 113 when the device is off may be between 1000V and 10000V.

[0208] The SiC semiconductor substrate 111 is formed as the drain region 114 of the MISFET. The SiC epitaxial layer 112 is formed as the drift region 115 of the MISFET.

[0209] In the active region 106, a p-type body region 116 is formed on the surface of the first main surface 103 of the SiC semiconductor layer 102. The p-type impurity concentration in the body region 116 is 1 × 10⁻⁶ 17 cm -3 The above 1 x 10 20 cm -3 The following may also apply. This body region 116 defines the active region 106.

[0210] In the active region 106, a plurality of gate trenches 121 are formed on the surface of the first main surface 103 of the SiC semiconductor layer 102. The plurality of gate trenches 121 are formed at intervals along an arbitrary first direction X. The plurality of gate trenches 121 are formed in a strip shape extending along a second direction Y that intersects the first direction X.

[0211] The first direction X is more specifically the direction along the sides 105B and 105D of the SiC semiconductor layer 102. The second direction Y is the direction perpendicular to the first direction X. The second direction Y is also the direction along the sides 105A and 105C of the SiC semiconductor layer 102.

[0212] Multiple gate trenches 121 are formed in a stripe pattern in a plan view. In this configuration, each gate trench 121 extends in a strip shape from one peripheral edge (side surface 105B) to the other peripheral edge (side surface 105D) on the first main surface 103 of the SiC semiconductor layer 102 in a plan view.

[0213] Each gate trench 121 crosses the intermediate portion between one peripheral edge and the other peripheral edge of the first main surface 103 in a plan view. One end of each gate trench 121 is located on one peripheral edge of the first main surface 103 of the SiC semiconductor layer 102. The other end of each gate trench 121 is located on the other peripheral edge of the first main surface 103 of the SiC semiconductor layer 102.

[0214] The first direction X may be set in the [11-20] direction ([-1-120] direction). In this case, each gate trench 121 may extend along the [11-20] direction. The first direction X may be set in the [-1100] direction ([1-100] direction) perpendicular to the [11-20] direction. In this case, each gate trench 121 may extend along the [-1100] direction ([1-100] direction).

[0215] Each gate trench 121 has a length on the order of millimeters (1 mm or more). The length of the gate trench 121 is the length from the end on the connection side of the gate trench 121 and the gate finger 109 to the opposite end in the cross-section shown in Figure 14.

[0216] The length of each gate trench 121 may be 0.5 mm or more. In this embodiment, the length of each gate trench 121 is 1 mm or more and 10 mm or less (for example, 2 mm or more and 5 mm or less). The total length of one or more gate trenches 121 per unit area is 0.5 μm / μm 2 More than 0.75μm / μm 2 The following is also acceptable.

[0217] Each gate trench 121 integrally includes an active trench portion 121a and a contact trench portion 121b. The active trench portion 121a is the portion formed in the active region 106 of the gate trench 121. The contact trench portion 121b is the portion drawn out from the active trench portion 121a to the outer region 107 of the gate trench 121.

[0218] Each gate trench 121 penetrates the body region 116 and reaches the SiC epitaxial layer 112. The bottom wall of each gate trench 121 is located within the SiC epitaxial layer 112. More specifically, the bottom wall of each gate trench 121 is located in the high-concentration region 112a of the SiC epitaxial layer 112.

[0219] With respect to the normal direction of the first main surface 103 of the SiC semiconductor layer 102, the depth of the gate trench 121 may be 0.5 μm or more and 3 μm or less (for example, about 1 μm). Preferably, the depth of the gate trench 121 is 0.5 μm or more and 1.0 μm or less.

[0220] The first directional width of the gate trench 121 may be 0.1 μm or more and 2 μm or less (for example, about 0.5 μm). Preferably, the first directional width of the gate trench 121 is 0.1 μm or more and 0.5 μm or less.

[0221] Referring to Figures 13 and 14, the opening edge portion 124 of each gate trench 121 includes a curved portion 125 that curves inward from the gate trench 121. The opening edge portion 124 of the gate trench 121 is a corner connecting the first main surface 103 of the SiC semiconductor layer 102 and the side wall of the gate trench 121.

[0222] The electric field on the opening edge 124 of the gate trench 121 is dispersed along the curved portion 125. This reduces the concentration of the electric field on the opening edge 124 of the gate trench 121.

[0223] In the surface layer of the body region 116, in the region along the side wall of the gate trench 121, n + A source region 126 of type n is formed. The n-type impurity concentration in the source region 126 is 1.0 × 10⁻⁶. 18 cm -3 The above 1.0 × 10 21 cm -3 The following is also acceptable.

[0224] Multiple source regions 126 are formed along one side wall and the other side wall of the gate trench 121 with respect to the first direction X. Each of the multiple source regions 126 is formed in a strip shape extending along the second direction Y. The multiple source regions 126 are formed in a stripe shape in a plan view.

[0225] A gate insulating layer 131 and a gate electrode layer 132 are formed within each gate trench 121. In Figure 12, the gate insulating layer 131 and the gate electrode layer 132 are shown by hatching for clarity.

[0226] The gate insulating layer 131 may contain silicon oxide. The gate insulating layer 131 may also contain other insulating films such as silicon nitride. The gate insulating layer 131 is formed in a film-like manner along the inner wall surface of the gate trench 121 such that a concave space is partitioned within the gate trench 121.

[0227] The gate insulating layer 131 includes a first region 131a, a second region 131b, and a third region 131c. The first region 131a is formed along the side wall of the gate trench 121. The second region 131b is formed along the bottom wall of the gate trench 121. The third region 131c is formed along the first main surface 103 of the SiC semiconductor layer 102.

[0228] The thickness T1 of the first region 131a is smaller than the thickness T2 of the second region 131b and the thickness T3 of the third region 131c. The ratio T2 / T1 of the thickness T1 of the first region 131a to the thickness T2 of the second region 131b may be between 2 and 5. The ratio T3 / T1 of the thickness T1 of the first region 131a to the thickness T3 of the third region 131c may be between 2 and 5.

[0229] The thickness T1 of the first region 131a may be between 0.01 μm and 0.2 μm. The thickness T2 of the second region 131b may be between 0.05 μm and 0.5 μm. The thickness T3 of the third region 131c may be between 0.05 μm and 0.5 μm.

[0230] By forming the first region 131a of the gate insulating layer 131 thinly, the increase in carriers induced in the region near the side wall of the gate trench 121 in the body region 116 can be suppressed. This suppresses the increase in channel resistance. By forming the second region 131b of the gate insulating layer 131 thickly, the electric field concentration against the bottom wall of the gate trench 121 can be mitigated.

[0231] By forming a thicker third region 131c of the gate insulating layer 131, the breakdown voltage of the gate insulating layer 131 near the opening edge portion 124 of the gate trench 121 can be improved. Furthermore, by forming a thicker third region 131c, the disappearance of the third region 131c by the etching method can be suppressed.

[0232] This prevents the first region 131a from being removed by etching due to the disappearance of the third region 131c. As a result, the gate electrode layer 132 can be properly positioned opposite the SiC semiconductor layer 102 with the gate insulating layer 131 in between.

[0233] The gate electrode layer 132 is embedded in the gate trench 121, sandwiched between the gate insulating layer 131. More specifically, the gate electrode layer 132 is embedded in the gate trench 121 so as to fill the concave space partitioned by the gate insulating layer 131. The gate electrode layer 132 is controlled by the gate voltage.

[0234] Referring to Figures 13 and 14, the gate electrode layer 132 is formed as a wall extending along the normal direction of the first main surface 103 of the SiC semiconductor layer 102 in a cross-sectional view perpendicular to the direction in which the gate trench 121 extends.

[0235] The gate electrode layer 132 has an upper end located on the opening side of the gate trench 121. The upper end of the gate electrode layer 132 is formed in a curved shape that is recessed toward the bottom wall of the gate trench 121.

[0236] The cross-sectional area of ​​the gate electrode layer 132 (the cross-sectional area perpendicular to the direction in which the gate trench 121 extends) is 0.05 μm². 2 Above 0.5 μm 2 The following is also possible: The cross-sectional area of ​​the gate electrode layer 132 is defined as the product of the depth of the gate electrode layer 132 and the width of the gate electrode layer 132.

[0237] The depth of the gate electrode layer 132 is the distance from the upper end to the lower end of the gate electrode layer 132. The width of the gate electrode layer 132 is the width of the trench at an intermediate position between the upper and lower ends of the gate electrode layer 132. If the upper end is a curved surface (in this form, a curved shape that is concave downwards), the position of the upper end of the gate electrode layer 132 is the intermediate position in the depth direction on the upper surface of the gate electrode layer 132.

[0238] The gate electrode layer 132 contains p-type polysilicon doped with p-type impurities. The p-type impurities may include at least one of boron (B), aluminum (Al), indium (In), or gallium (Ga).

[0239] The p-type impurity concentration in the gate electrode layer 132 is greater than or equal to the p-type impurity concentration in the body region 116. More specifically, the p-type impurity concentration in the gate electrode layer 132 is greater than the p-type impurity concentration in the body region 116.

[0240] The p-type impurity concentration in the gate electrode layer 132 is 1 × 10⁻⁶ 18 cm -3 The above 1 x 10 22 cm -3 The following is also possible: The sheet resistance of the gate electrode layer 132 may be 10Ω / □ or more and 500Ω / □ or less (approximately 200Ω / □ in this configuration).

[0241] Referring to Figure 14, a gate wiring layer 133 is formed in the outer region 107. The gate wiring layer 133 is electrically connected to the gate pad 108 and the gate finger 109.

[0242] The gate wiring layer 133 is formed on the first main surface 103 of the SiC semiconductor layer 102. More specifically, the gate wiring layer 133 is formed on the third region 131c of the gate insulating layer 131.

[0243] In this embodiment, the gate wiring layer 133 is formed along the gate finger 109. The gate wiring layer 133 is formed along the three sides 105A, 105B, and 105D of the SiC semiconductor layer 102 so as to partition the active region 106 from three directions.

[0244] The gate wiring layer 133 is connected to the gate electrode layer 132, which is exposed from the contact trench portion 121b of each gate trench 121. In this embodiment, the gate wiring layer 133 is formed by a lead-out portion that extends from the gate electrode layer 132 onto the first main surface 103 of the SiC semiconductor layer 102. The upper end of the gate wiring layer 133 is connected to the upper end of the gate electrode layer 132.

[0245] Referring to Figure 13, a low-resistance electrode layer 134 is formed on the gate electrode layer 132. The low-resistance electrode layer 134 covers the upper end of the gate electrode layer 132 within the gate trench 121.

[0246] The low-resistance electrode layer 134 includes a conductive material having a sheet resistance less than that of the gate electrode layer 132. The sheet resistance of the low-resistance electrode layer 134 may be between 0.01 Ω / □ and 10 Ω / □.

[0247] The current supplied into the gate trench 121 flows through the low-resistance electrode layer 134, which has a relatively low sheet resistance, and is transmitted to the entire gate electrode layer 132. This allows the entire gate electrode layer 132 (the entire active region 106) to quickly transition from the off state to the on state, thereby suppressing the delay in the switching response.

[0248] In particular, in the case of a gate trench 121 having a length on the order of millimeters, current transmission takes time, but the low-resistance electrode layer 134 can appropriately suppress the delay in the switching response. In other words, the low-resistance electrode layer 134 is formed as a current-diffusing electrode layer that diffuses current within the gate trench 121.

[0249] Furthermore, as the cell structure becomes more miniaturized, the width, depth, and cross-sectional area of ​​the gate electrode layer 132 decrease, raising concerns about delays in the switching response due to increased electrical resistance within the gate trench 121.

[0250] However, the low-resistance electrode layer 134 allows the entire gate electrode layer 132 to quickly transition from the off state to the on state, thus effectively suppressing the delay in the switching response caused by miniaturization.

[0251] The low-resistance electrode layer 134 is formed in a film-like manner. The low-resistance electrode layer 134 has a connecting portion 134a that is in contact with the upper end of the gate electrode layer 132 and a non-connecting portion 134b on the opposite side. The connecting portion 134a and the non-connecting portion 134b of the low-resistance electrode layer 134 may be formed in a curved shape following the upper end of the gate electrode layer 132. The connecting portion 134a and the non-connecting portion 134b of the low-resistance electrode layer 134 can take various forms.

[0252] The entire connection portion 134a of the low-resistance electrode layer 134 may be located above the first main surface 103 of the SiC semiconductor layer 102. The entire connection portion 134a of the low-resistance electrode layer 134 may be located below the first main surface 103 of the SiC semiconductor layer 102.

[0253] The connection portion 134a of the low-resistance electrode layer 134 may include a portion located above the first main surface 103 of the SiC semiconductor layer 102. The connection portion 134a of the low-resistance electrode layer 134 may include a portion located below the first main surface 103 of the SiC semiconductor layer 102.

[0254] For example, the central part of the connection portion 134a of the low-resistance electrode layer 134 may be located below the first main surface 103 of the SiC semiconductor layer 102, and the peripheral part of the connection portion 134a of the low-resistance electrode layer 134 may be located above the first main surface 103 of the SiC semiconductor layer 102.

[0255] The entire unconnected portion 134b of the low-resistance electrode layer 134 may be located above the first main surface 103 of the SiC semiconductor layer 102. The entire unconnected portion 134b of the low-resistance electrode layer 134 may be located below the first main surface 103 of the SiC semiconductor layer 102.

[0256] The unconnected portion 134b of the low-resistance electrode layer 134 may include a portion located above the first main surface 103 of the SiC semiconductor layer 102. The unconnected portion 134b of the low-resistance electrode layer 134 may include a portion located below the first main surface 103 of the SiC semiconductor layer 102.

[0257] For example, the central part of the unconnected portion 134b of the low-resistance electrode layer 134 may be located below the first main surface 103 of the SiC semiconductor layer 102, and the peripheral part of the unconnected portion 134b of the low-resistance electrode layer 134 may be located above the first main surface 103 of the SiC semiconductor layer 102.

[0258] The low-resistance electrode layer 134 has an edge portion 134c that is in contact with the gate insulating layer 131. The edge portion 134c of the low-resistance electrode layer 134 is in contact with the corner portion of the gate insulating layer 131 that connects the first region 131a and the second region 131b.

[0259] The edge 134c of the low-resistance electrode layer 134 is formed in the region on the first main surface 103 side of the SiC semiconductor layer 102 relative to the bottom of the source region 126. In other words, the edge 134c of the low-resistance electrode layer 134 is formed in the region on the first main surface 103 side of the SiC semiconductor layer 102, rather than in the boundary region between the body region 116 and the source region 126.

[0260] Therefore, the edge 134c of the low-resistance electrode layer 134 faces the source region 126 across the gate insulating layer 131. The edge 134c of the low-resistance electrode layer 134 does not face the body region 116 across the gate insulating layer 131.

[0261] This can suppress the formation of a current path in the region between the low-resistance electrode layer 134 and the body region 116 in the gate insulating layer 131. The current path can be formed by an undesired diffusion of the electrode material of the low-resistance electrode layer 134 with respect to the gate insulating layer 131.

[0262] In particular, the design of connecting the edge 134c of the low-resistance electrode layer 134 to the third region 131c (the corner of the gate insulating layer 131) of the relatively thick gate insulating layer 131 is effective in reducing the risk of forming a current path.

[0263] In the normal direction of the first main surface 103 of the SiC semiconductor layer 102, the thickness TR of the low-resistance electrode layer 134 is less than or equal to the thickness TG of the gate electrode layer 132 (TR ≦ TG). Preferably, the thickness TR of the low-resistance electrode layer 134 is less than the thickness TG of the gate electrode layer 132 (TR < TG). More specifically, preferably, the thickness TR of the low-resistance electrode layer 134 is less than or equal to half of the thickness TG of the gate electrode layer 132 (TR ≦ TG / 2).

[0264] The ratio TR / TG of the thickness TR of the low-resistance electrode layer 134 to the thickness TG of the gate electrode layer 132 is 0.01 or more and 1 or less. The thickness TG of the gate electrode layer 132 may be 0.5 μm or more and 3 μm or less. The thickness TR of the low-resistance electrode layer 134 may be 0.01 μm or more and 3 μm or less.

[0265] Referring to FIG. 14, in this form, the low-resistance electrode layer 134 also covers the upper end portion of the gate wiring layer 133. The portion of the low-resistance electrode layer 134 covering the upper end portion of the gate wiring layer 133 is integrally formed with the portion of the low-resistance electrode layer 134 covering the upper end portion of the gate electrode layer 132. Thereby, the low-resistance electrode layer 134 covers the entire area of the gate electrode layer 132 and the entire area of the gate wiring layer 133.

[0266] Therefore, the current supplied from the gate pad 108 and gate finger 109 to the gate wiring layer 133 flows through the low-resistance electrode layer 134, which has a relatively low sheet resistance, and is transmitted throughout the gate electrode layer 132 and the gate wiring layer 133.

[0267] This allows the entire gate electrode layer 132 (the entire active region 106) to be quickly transitioned from the off state to the on state via the gate wiring layer 133, thereby suppressing the delay in the switching response.

[0268] In particular, in the case of a gate trench 121 having a length on the order of millimeters, the low-resistance electrode layer 134 covering the upper end of the gate wiring layer 133 can effectively suppress the delay in the switching response.

[0269] The low-resistance electrode layer 134 includes a polyside layer. The polyside layer is formed by silicideizing the portion of the gate electrode layer 132 that forms the surface layer with a metallic material. More specifically, the polyside layer consists of a p-type polyside layer containing p-type impurities added to the gate electrode layer 132 (p-type polysilicon).

[0270] In this configuration, the polyside layer has a resistivity of 10 μΩ·cm to 110 μΩ·cm. More specifically, the polyside layer includes at least one of TiSi, TiSi2, NiSi, CoSi, CoSi2, MoSi2, or WSi2.

[0271] When a low-resistance electrode layer 134 is formed on p-type polysilicon, the sheet resistance within the gate trench 121 is less than or equal to the sheet resistance of the gate electrode layer 132 (p-type polysilicon) alone. Preferably, the sheet resistance within the gate trench 121 is less than or equal to the sheet resistance of n-type polysilicon with added n-type impurities.

[0272] The sheet resistance within the gate trench 121 is approximated by the sheet resistance of the low-resistance electrode layer 134. That is, the sheet resistance within the gate trench 121 may be between 0.01 Ω / □ and 10 Ω / □. Preferably, the sheet resistance within the gate trench 121 is less than 10 Ω / □.

[0273] Figure 15 shows the results of investigating the resistivity of the polyside layer. Figure 15 is a graph showing the relationship between the resistivity of polyside and the formation temperature. In Figure 15, the vertical axis represents resistivity [μΩ·cm], and the horizontal axis represents the formation temperature of polyside [°C].

[0274] Referring to Figure 15, the resistivity decreases in the order of MoSi2, WSi2, NiSi, CoSi2, and TiSi2. Therefore, the priority of materials used as polyside layers increases in the order of MoSi2, WSi2, NiSi, CoSi2, and TiSi2.

[0275] In particular, NiSi, CoSi2, and TiSi2 among these species are suitable as polyside layers for forming the low-resistivity electrode layer 134 because their resistivity values ​​and temperature dependence are relatively small.

[0276] Furthermore, the inventors' verification revealed that when TiSi2 was used as the material for the low-resistance electrode layer 134, an increase in gate-source leakage current was observed when a low electric field was applied. In contrast, when CoSi2 was used, no increase in gate-source leakage current was observed when a low electric field was applied. Considering that NiSi has issues with heat resistance compared to CoSi2, CoSi2 is the most preferred material for the polyside layer forming the low-resistance electrode layer 134.

[0277] Referring to Figures 12 and 13, in the active region 106, a plurality of source trenches 141 are formed on the first main surface 103 of the SiC semiconductor layer 102. Each source trench 141 is formed in the region between two adjacent gate trenches 121.

[0278] Each of the multiple source trenches 141 is formed in a strip-like shape extending along the second direction Y. In a plan view, the multiple source trenches 141 are formed in a stripe-like shape. With respect to the first direction X, the pitch between the centers of adjacent source trenches 141 may be 1.5 μm or more and 3 μm or less.

[0279] Each source trench 141 penetrates the body region 116 and reaches the SiC epitaxial layer 112. The bottom wall of each source trench 141 is located within the SiC epitaxial layer 112. More specifically, the bottom wall of each source trench 141 is located in the high-concentration region 112a of the SiC epitaxial layer 112.

[0280] The depth of the source trench 141 may be approximately equal to the depth of the gate trench 121. The depth of the source trench 141 may be greater than or equal to the depth of the gate trench 121. With respect to the direction normal to the first main surface 103 of the SiC semiconductor layer 102, the depth of the source trench 141 may be between 0.5 μm and 10 μm (for example, about 1 μm).

[0281] The first directional width of the source trench 141 may be approximately equal to the first directional width of the gate trench 121. The first directional width of the source trench 141 may be greater than or equal to the first directional width of the gate trench 121. The first directional width of the source trench 141 may be between 0.1 μm and 2 μm (for example, about 0.5 μm).

[0282] Each source trench 141's opening edge 142 includes a curved portion 143 that curves inward from the source trench 141. The opening edge 142 of the source trench 141 is a corner connecting the first main surface 103 of the SiC semiconductor layer 102 and the side wall of the source trench 141.

[0283] The electric field on the opening edge 142 of the source trench 141 is dispersed along the curved portion 143. This reduces the concentration of the electric field on the opening edge 142 of the source trench 141.

[0284] In the SiC semiconductor layer 102, in the region along the side wall of the source trench 141, p + A type contact region 144 is formed. The p-type impurity concentration in the contact region 144 is 1.0 × 10⁻⁶. 18 cm -3 The above 1.0 × 10 21 cm -3 The following is also possible: Multiple contact areas 144 are formed on one side and the other side of a single source trench 141.

[0285] Multiple contact regions 144 are formed at intervals along the second direction Y. Multiple contact regions 144 are formed at intervals along the first direction X from the gate trench 121.

[0286] In the SiC semiconductor layer 102, a p-type deep well region 145 is formed in the region along the inner wall of the source trench 141. The deep well region 145 is also called the breakdown voltage holding region. The deep well region 145 is formed in a band shape that extends along the source trench 141. The deep well region 145 extends along the inner wall of the source trench 141.

[0287] Referring to Figures 12 and 14, the deep well region 145 extends more specifically along the side wall of the source trench 141 and covers the bottom wall of the source trench 141 through the edge. The deep well region 145 is connected to the body region 116 at the side wall of the source trench 141.

[0288] The deep well region 145 has a bottom located on the second main surface 104 side of the SiC semiconductor layer 102 relative to the bottom wall of the gate trench 121. The deep well region 145 is formed in the high-concentration region 112a of the SiC epitaxial layer 112.

[0289] The p-type impurity concentration in the deep well region 145 may be approximately equal to the p-type impurity concentration in the body region 116. The p-type impurity concentration in the deep well region 145 may exceed the p-type impurity concentration in the body region 116. The p-type impurity concentration in the deep well region 145 may be less than the p-type impurity concentration in the body region 116.

[0290] The p-type impurity concentration in the deep well region 145 may be less than or equal to the p-type impurity concentration in the contact region 144. The p-type impurity concentration in the deep well region 145 may be less than the p-type impurity concentration in the contact region 144. The p-type impurity concentration in the deep well region 21 is 1.0 × 10⁻⁶. 17 cm -3 The above 1.0 × 10 19 cm -3 The following is also acceptable.

[0291] Referring to Figures 12 and 14, a p-type peripheral deep well region 148 is formed in the outer region 107. The peripheral deep well region 148 is electrically connected to the deep well region 145.

[0292] The peripheral deep well region 148 is at the same potential as the deep well region 145. In this configuration, the peripheral deep well region 148 is formed integrally with the deep well region 145.

[0293] More specifically, the peripheral deep well region 148 extends in a band-like manner along the periphery of the active region 106 in the outer region 107. More specifically, the peripheral deep well region 148 is formed in an endless manner (in this form, a quadrangular ring) surrounding the active region 106.

[0294] The peripheral deep well region 148 is formed in the outer region 107 along the surface of the first main surface 103 of the SiC semiconductor layer 102 and along the inner wall of the contact trench portion 121b of the gate trench 121. The peripheral deep well region 148 extends along the side wall of the contact trench portion 121b and covers the bottom wall of the contact trench portion 121b through the edge.

[0295] The peripheral deep well region 148 overlaps with the gate wiring layer 133 in a plan view. In other words, the peripheral deep well region 148 faces the gate wiring layer 133 across the gate insulating layer 131 (third region 131c).

[0296] The peripheral deep well region 148 has a bottom located on the second main surface 104 side of the SiC semiconductor layer 102 relative to the bottom wall of the contact trench portion 121b of the gate trench 121. The peripheral deep well region 148 is formed in the high-concentration region 112a of the SiC epitaxial layer 112.

[0297] The peripheral deep well region 148 includes a pull-out portion 148a that extends from the outer region 107 to the periphery of the active region 106 in a plan view. In a plan view, the pull-out portion 148a of the peripheral deep well region 148 covers the end of the source trench 141 located on the outer region 107 side.

[0298] The extension portion 148a of the peripheral deep well region 148 covers the inner wall of the active trench portion 121a at the periphery of the active region 106. The extension portion 148a of the peripheral deep well region 148 extends along the side wall of the active trench portion 121a and covers the bottom wall of the active trench portion 121a through the edge. This extension portion 148a of the peripheral deep well region 148 is connected to the deep well region 145 in the active region 106.

[0299] The extraction portion 148a of the peripheral deep well region 148 has a bottom that is located on the second main surface 104 side of the SiC semiconductor layer 102 relative to the bottom wall of the active trench portion 121a of the gate trench 121. The extraction portion 148a of the peripheral deep well region 148 is formed in the high-concentration region 112a of the SiC epitaxial layer 112.

[0300] The p-type impurity concentration in the peripheral deep well region 148 may be approximately equal to the p-type impurity concentration in the body region 116. The p-type impurity concentration in the peripheral deep well region 148 may exceed the p-type impurity concentration in the body region 116. The p-type impurity concentration in the peripheral deep well region 148 may be less than the p-type impurity concentration in the body region 116.

[0301] The p-type impurity concentration in the peripheral deep well region 148 may be approximately equal to the p-type impurity concentration in the deep well region 145. The p-type impurity concentration in the peripheral deep well region 148 may exceed the p-type impurity concentration in the deep well region 145. The p-type impurity concentration in the peripheral deep well region 148 may be less than the p-type impurity concentration in the deep well region 145.

[0302] The p-type impurity concentration in the peripheral deep well region 148 may be less than or equal to the p-type impurity concentration in the contact region 144. The p-type impurity concentration in the peripheral deep well region 148 may be less than the p-type impurity concentration in the contact region 144. The p-type impurity concentration in the peripheral deep well region 148 is 1.0 × 10⁻⁶. 17 cm -3 The above 1.0 × 10 19 cm -3 The following is also acceptable.

[0303] A source insulating layer 146 and a source electrode layer 147 are formed within each source trench 141. In Figure 12, the source insulating layer 146 and the source electrode layer 147 are indicated by hatching for clarity.

[0304] The source insulating layer 146 may contain silicon oxide. The source insulating layer 146 is formed in a film-like manner along the inner wall surface of the source trench 141 such that a concave space is partitioned within the source trench 141.

[0305] The source insulating layer 146 includes a first region 146a and a second region 146b. The first region 146a is formed along the side wall of the source trench 141. The second region 146b is formed along the bottom wall of the source trench 141. The thickness T11 of the first region 146a is less than the thickness T12 of the second region 146b.

[0306] The ratio T12 / T11 of the thickness T11 of the first region 146a to the thickness T12 of the second region 146b may be between 2 and 5. The thickness T11 of the first region 146a may be between 0.01 μm and 0.2 μm. The thickness T12 of the second region 146b may be between 0.05 μm and 0.5 μm.

[0307] The thickness T11 of the first region 146a may be approximately equal to the thickness T1 of the first region 131a of the gate insulating layer 131. The thickness T12 of the second region 146b may be approximately equal to the thickness T2 of the second region 131b of the gate insulating layer 131.

[0308] The source insulating layer 146 exposes the opening edge portion 142 of the source trench 141. More specifically, the source insulating layer 146 exposes the source region 126 and the contact region 144 from the opening edge portion 142 of the source trench 141.

[0309] More specifically, the first region 146a of the source insulating layer 146 has an upper end located on the opening side of the source trench 141. The upper end of the first region 146a is formed below the first main surface 103 of the SiC semiconductor layer 102.

[0310] The upper end of the first region 146a exposes the side wall of the source trench 141 on the opening side of the source trench 141. In this way, the first region 146a exposes the source region 126 and the contact region 144 from the opening edge portion 142 of the source trench 141.

[0311] The source electrode layer 147 is embedded in the source trench 141, sandwiched between the source insulating layer 146. More specifically, the source electrode layer 147 is embedded in the source trench 141 so as to fill the concave space partitioned by the source insulating layer 146. The source electrode layer 147 is controlled by the source voltage.

[0312] The source electrode layer 147 has an upper end located on the opening side of the source trench 141. The upper end of the source electrode layer 147 is formed below the first main surface 103 of the SiC semiconductor layer 102. The upper end of the source electrode layer 147 may also be formed flush with the upper end of the source insulating layer 146.

[0313] The upper end of the source electrode layer 147 may protrude above the upper end of the source insulating layer 146. The upper end of the source electrode layer 147 may be located below the upper end of the source insulating layer 146. The thickness of the source electrode layer 147 may be 0.5 μm or more and 10 μm or less (for example, about 1 μm).

[0314] The source electrode layer 147 preferably contains polysilicon having properties similar to SiC in terms of material properties. This reduces the stress generated within the SiC semiconductor layer 102. The source electrode layer 147 preferably contains p-type polysilicon with p-type impurities added. In this case, the source electrode layer 147 can be formed simultaneously with the gate electrode layer 132.

[0315] The p-type impurity concentration of the source electrode layer 147 is not less than the p-type impurity concentration of the body region 116. More specifically, the p-type impurity concentration of the source electrode layer 147 is greater than the p-type impurity concentration of the body region 116. The p-type impurity of the source electrode layer 147 may contain at least one of boron (B), aluminum (Al), indium (In), or gallium (Ga).

[0316] The p-type impurity concentration of the source electrode layer 147 is 1×10 18 cm -3 or more and 1×10 22 cm -3 or less. The sheet resistance of the source electrode layer 147 may be 10 Ω / sq or more and 500 Ω / sq or less (about 200 Ω / sq in this form).

[0317] The p-type impurity concentration of the source electrode layer 147 may be approximately equal to the p-type impurity concentration of the gate electrode layer 132. The sheet resistance of the source electrode layer 147 may be approximately equal to the sheet resistance of the gate electrode layer 132.

[0318] Instead of p-type polysilicon, the source electrode layer 147 may contain n-type polysilicon. Instead of p-type polysilicon, the source electrode layer 147 may contain at least one of tungsten, aluminum, copper, an aluminum alloy, or a copper alloy.

[0319] As described above, the semiconductor device 101 has a trench gate structure 151 and a trench source structure 152. The trench gate structure 151 includes a gate trench 121, a gate insulating layer 131, a gate electrode layer 132, and a low-resistance electrode layer 134. The trench source structure 152 includes a source trench 141, a source insulating layer 146, and a source electrode layer 147.

[0320] Referring to FIGS. 13 and 14, an interlayer insulating layer 153 is formed on the first main surface 103 of the SiC semiconductor layer 102. The interlayer insulating layer 153 covers the trench gate structure 151 in the active region 106 and the gate wiring layer 133 in the outer region 107.

[0321] The interlayer insulating layer 153 may contain silicon oxide or silicon nitride. Gate contact holes 154 and source contact holes 155 are formed in the interlayer insulating layer 153.

[0322] The gate contact hole 154 exposes the gate wiring layer 133 (low-resistance electrode layer 134) in the outer region 107. The source contact hole 155 exposes the source region 126, contact region 144, and trench source structure 152 in the active region 106. A gate pad 108, gate finger 109, and source pad 110 are formed on the interlayer insulating layer 153.

[0323] The gate finger 109 enters the gate contact hole 154 from above the interlayer insulating layer 153. Within the gate contact hole 154, the gate finger 109 is electrically connected to the low-resistance electrode layer 134. As a result, electrical signals from the gate pad 108 are transmitted to the gate electrode layer 132 via the low-resistance electrode layer 134, which has a relatively low resistance value.

[0324] The source pad 110 extends from above the interlayer insulating layer 153 into the source contact hole 155. Within the source contact hole 155, the source pad 110 is electrically connected to the source region 126, the contact region 144, and the source electrode layer 147. The source electrode layer 147 may be formed using a portion of the source pad 110.

[0325] Figure 16 is a graph illustrating sheet resistance. In Figure 16, the vertical axis represents sheet resistance [Ω / □], and the horizontal axis represents the item. Figure 16 shows the first bar graph L1, the second bar graph L2, and the third bar graph L3.

[0326] The first bar graph L1 represents the sheet resistance of n-type polysilicon. The second bar graph L2 represents the sheet resistance of p-type polysilicon. The third bar graph L3 represents the sheet resistance when a low-resistance electrode layer 134 is formed on p-type polysilicon. The low-resistance electrode layer 134 here contains TiSi2 (p-type titanium silicide).

[0327] Referring to the first bar graph L1, the sheet resistance of n-type polysilicon was 10Ω / □. Referring to the second bar graph L2, the sheet resistance of p-type polysilicon was 200Ω / □. Referring to the third bar graph L3, the sheet resistance when a low-resistance electrode layer 134 was formed on p-type polysilicon was 2Ω / □.

[0328] p-type polysilicon has a different work function than n-type polysilicon, and simply embedding p-type polysilicon in the gate trench 121 can increase the gate threshold voltage Vth by about 1V.

[0329] However, p-type polysilicon has a sheet resistance that is tens of times (20 times in this case) higher than that of n-type polysilicon. Therefore, when p-type polysilicon is used as the material for the gate electrode layer 132, energy loss increases significantly as the parasitic resistance in the gate trench 121 (hereinafter simply referred to as "gate resistance") increases.

[0330] In contrast, in a structure having a low-resistance electrode layer 134 on p-type polysilicon, the sheet resistance can be reduced to less than 1 / 100th compared to a structure without the low-resistance electrode layer 134. In a structure with the low-resistance electrode layer 134, the sheet resistance can be reduced to less than 1 / 5th compared to a gate electrode layer 132 containing n-type polysilicon.

[0331] As described above, semiconductor device 101 has a trench gate structure 151 in which a gate electrode layer 132 is embedded in a gate trench 121 with a gate insulating layer 131 in between. In this trench gate structure 151, the gate electrode layer 132 is covered by a low-resistance electrode layer 134 in the limited space of the gate trench 121.

[0332] The gate electrode layer 132 contains p-type polysilicon. This allows for an increase in the gate threshold voltage Vth. The low-resistance electrode layer 134 contains a conductive material having a sheet resistance less than that of p-type polysilicon.

[0333] This allows for a reduction in gate resistance. As a result, the current can be efficiently diffused along the trench gate structure 151, thereby shortening the switching delay.

[0334] In particular, the structure in which the gate electrode layer 132 is covered with a low-resistance electrode layer 134 eliminates the need to increase the p-type impurity concentration in the body region 116. Therefore, the gate threshold voltage Vth can be increased while preventing an increase in channel resistance.

[0335] Furthermore, in the semiconductor device 101, the gate wiring layer 133 in the outer region 107 is covered with a low-resistance electrode layer 134. This also helps to reduce the gate resistance in the gate wiring layer 133.

[0336] In particular, in a structure in which the gate electrode layer 132 and the gate wiring layer 133 are covered by a low-resistance electrode layer 134, the current can be efficiently diffused along the trench gate structure 151. Therefore, the switching delay can be appropriately reduced.

[0337] Figures 17A to 17L are cross-sectional views showing an example of a manufacturing method for the semiconductor device 101 shown in Figure 11. Figures 17A to 17L are cross-sectional views of the portion corresponding to Figure 12.

[0338] Referring to Figure 17A, first, n + A SiC semiconductor substrate 111 of a specific type is prepared. Next, a SiC epitaxial layer 112 is formed on the main surface of the SiC semiconductor substrate 111. The SiC epitaxial layer 112 is formed by growing SiC on the main surface of the SiC semiconductor substrate 111 using an epitaxial growth method.

[0339] In this configuration, a SiC epitaxial layer 112 having a high-concentration region 112a and a low-concentration region 112b is formed. This results in the formation of a SiC semiconductor layer 102 including a SiC semiconductor substrate 111 and the SiC epitaxial layer 112.

[0340] Next, a p-type body region 116 is formed on the surface of the first main surface 103 of the SiC semiconductor layer 102. The body region 116 is formed by introducing p-type impurities into the first main surface 103 of the SiC semiconductor layer 102.

[0341] The body region 116 may be formed on the surface of the first main surface 103 of the SiC semiconductor layer 102 by an ion implantation method via an ion implantation mask (not shown). The active region 106 is defined by this body region 116.

[0342] Next, referring to Figure 17B, n + A source region 126 of type n is formed. The source region 126 is formed by introducing n-type impurities into the surface layer of the body region 116. The source region 126 may also be formed on the surface layer of the body region 116 by an ion implantation method via an ion implantation mask 161.

[0343] Next, referring to Figure 17C, p + A type contact region 144 is formed. The contact region 144 is formed by introducing p-type impurities into the surface layer of the body region 116. The contact region 144 may also be formed on the surface layer of the body region 116 by an ion implantation method via an ion implantation mask 162.

[0344] Next, referring to Figure 17D, a mask 163 having a predetermined pattern is formed on the first main surface 103 of the SiC semiconductor layer 102. The mask 163 has a plurality of openings 164 that expose the regions where gate trenches 121 and source trenches 141 are to be formed.

[0345] Next, unwanted portions of the SiC semiconductor layer 102 are removed. These unwanted portions may be removed by an etching method (e.g., wet etching) through the mask 163. This forms the gate trench 121 and the source trench 141. The mask 163 is then removed.

[0346] Next, the deep well region 145 is formed in the SiC semiconductor layer 102 in a region along the inner wall of the source trench 141. The deep well region 145 may be formed in the SiC semiconductor layer 102 by an ion implantation method using an ion implantation mask (not shown).

[0347] Furthermore, in the outer region 107, the peripheral deep well region 148 is formed in the region along the surface of the first main surface 103 of the SiC semiconductor layer 102 and the inner wall of the contact trench portion 121b of the gate trench 121. In this process, the peripheral deep well region 148 is formed, including the pull-out portion 148a that is pulled out from the outer region 107 to the peripheral edge of the active region 106.

[0348] The peripheral deep well region 148 may be formed in the SiC semiconductor layer 102 by an ion implantation method using an ion implantation mask (not shown). Part or all of the peripheral deep well region 148 may be formed simultaneously with the deep well region 145 by utilizing the deep well region formation process. Part of the peripheral deep well region 148 may be formed simultaneously with the body region 116 by utilizing the body region formation process.

[0349] Next, referring to Figure 17E, the SiC semiconductor layer 102 is subjected to an annealing treatment. The annealing treatment may be high-temperature hydrogen annealing. The annealing temperature may be 1400°C or higher.

[0350] As a result, a curved portion 125 is formed at the opening edge portion 124 of the gate trench 121. Additionally, a curved portion 143 is formed at the opening edge portion 142 of the source trench 141.

[0351] Next, referring to Figure 17F, a base insulating layer 165, which will serve as the base for the gate insulating layer 131 and the source insulating layer 146, is formed to cover the first main surface 103 of the SiC semiconductor layer 102. The base insulating layer 165 may be formed by the CVD (chemical vapor deposition) method. The base insulating layer 165 may contain silicon oxide.

[0352] In this process, the portion of the base insulating layer 165 that covers the sidewall of the gate trench 121 and the portion that covers the sidewall of the source trench 141 is formed to be thinner than the other portions.

[0353] A base insulating layer 165 of this form is formed by adjusting predetermined conditions such as gas flow rate, gas type, gas ratio, and gas supply time in a CVD (Chemical Vapor Deposition) method. The base insulating layer 165 may also be formed by an oxidation treatment method instead of the CVD method. The oxidation treatment method may be a thermal oxidation treatment method or a wet oxidation treatment method.

[0354] Next, referring to Figure 17G, a base conductor layer 166, which serves as the base for the gate electrode layer 132, the gate wiring layer 133, and the source electrode layer 147, is formed on the first main surface 103 of the SiC semiconductor layer 102.

[0355] The base conductive layer 166 contains p-type polysilicon with p-type impurities added. The base conductive layer 166 may be formed by a CVD method. The CVD method may be LP-CVD (Low Pressure CVD).

[0356] Next, referring to Figure 17H, unwanted portions of the base conductive layer 166 are removed. The unwanted portions of the base conductive layer 166 are removed by an etching method (e.g., wet etching) through a mask (not shown) having a predetermined pattern.

[0357] This mask (not shown) covers the area where the gate wiring layer 133 is to be formed. Unnecessary portions of the base conductor layer 166 are removed until at least the portion covering the first main surface 103 of the SiC semiconductor layer 102 in the base insulating layer 165 is exposed. This forms the gate electrode layer 132, the gate wiring layer 133, and the source electrode layer 147.

[0358] If the source electrode layer 147 is made of a different electrode material than the gate electrode layer 132, the source electrode layer 147 can be formed by separately performing the same process as shown in Figures 17G to 17H for the electrode material of the source electrode layer 147. If the source electrode layer 147 is formed by a part of the source pad 110, the source electrode layer 147 is formed when the source pad 110 is formed.

[0359] Next, referring to Figure 17I, a metallic material layer 167 is formed on the gate electrode layer 132. In this embodiment, the metallic material layer 167 is formed on the first main surface 103 of the SiC semiconductor layer 102 so as to cover both the gate electrode layer 132 and the source electrode layer 147 together.

[0360] The metal material layer 167 contains a metal material that can be polycified with p-type polysilicon. The metal material layer 167 may contain at least one of Mo, W, Ni, Co, or Ti.

[0361] Next, a p-type polyside layer is formed on the surface of the gate electrode layer 132 and the gate wiring layer 133. In this configuration, a p-type polyside layer is also formed on the surface of the source electrode layer 147.

[0362] The p-type polyside layer is formed by polysidizing the surface layers of the gate electrode layer 132, the gate wiring layer 133, and the source electrode layer 147 through heat treatment of the metal material layer 167. The heat treatment of the metal material layer 167 may be performed by the RTA (Rapid Thermal Annealing) method.

[0363] As a result, a p-type polyside containing at least one of TiSi, TiSi2, NiSi, CoSi, CoSi2, MoSi2, or WSi2 is formed, depending on the metal material of the metal material layer 167. This p-type polyside layer forms the low-resistance electrode layer 134.

[0364] Next, referring to Figure 17J, the unreacted portion of the metal material layer 167 that did not bond with the p-type polysilicon is removed. The unreacted portion of the metal material layer 167 may be removed by etching (for example, wet etching).

[0365] If the low-resistance electrode layer 134 (p-type polyside) contains at least one of TiSi or CoSi, the low-resistance electrode layer 134 may be heat-treated as needed after the unreacted portion of the metal material layer 167 is removed.

[0366] The heat treatment of the low-resistance electrode layer 134 may be performed by the RTA method. This modifies TiSi to TiSi2 and CoSi to CoSi2, thereby achieving lower resistance.

[0367] Next, referring to Figure 17K, an interlayer insulating layer 153 is formed on the first main surface 103 of the SiC semiconductor layer 102. The interlayer insulating layer 153 is formed on the first main surface 103 of the SiC semiconductor layer 102 so as to cover the trench gate structure 151 and the gate wiring layer 133. The interlayer insulating layer 153 contains silicon oxide or silicon nitride. The interlayer insulating layer 153 may be formed by the CVD method.

[0368] Next, a mask 168 having a predetermined pattern is formed on the interlayer insulating layer 153. The mask 168 has a plurality of openings 169 that expose the areas where the gate contact holes 154 and source contact holes 155 are to be formed.

[0369] Next, any unwanted portions of the interlayer insulating layer 153 are removed. These unwanted portions may be removed by an etching method (e.g., dry etching) through the mask 168. This forms the gate contact holes 154 and the source contact holes 155.

[0370] Next, referring to Figure 17L, a gate pad 108, a gate finger 109, and a source pad 110 are formed on the interlayer insulating layer 153. The gate pad 108, gate finger 109, and source pad 110 are formed using a mask (not shown) having a predetermined pattern. A drain pad 113 is also formed on the second main surface 104 of the SiC semiconductor layer 102. The semiconductor device 101 is manufactured through the process including the above.

[0371] Figure 18 is a cross-sectional view of the region corresponding to Figure 13, and shows a semiconductor device 171 according to the eighth embodiment of the present invention. In the following, structures corresponding to the structures described for semiconductor device 101 are given the same reference numerals and their descriptions are omitted.

[0372] Referring to Figure 18, in the semiconductor device 171, the gate insulating layer 131 includes a bulge 172 that bulges inward into the gate trench 121 at the opening edge portion 124 of the gate trench 121. The bulge 172 is formed at the corner connecting the first region 131a and the third region 131c of the gate insulating layer 131.

[0373] The bulging portion 172 curves outward toward the inside of the gate trench 121. The bulging portion 172 narrows the opening of the gate trench 121 at the opening edge portion 124 of the gate trench 121.

[0374] The upper end of the gate electrode layer 132 has a constricted portion that is recessed along the bulge 172 of the gate insulating layer 131. The low-resistance electrode layer 134 covers the constricted portion (upper end) of the gate electrode layer 132. In this configuration, the edge 134c of the low-resistance electrode layer 134 is in contact with the bulge 172 of the gate insulating layer 131.

[0375] The bulge 172 of the gate insulating layer 131 is formed in the process shown in Figure 17F above by setting predetermined conditions (gas flow rate, gas type, gas ratio, gas supply time, etc.) for the CVD method, taking into consideration the shape of the bulge 172 of the gate insulating layer 131.

[0376] As described above, with the semiconductor device 171, the edge 134c of the low-resistance electrode layer 134 is in contact with the bulge 172 of the gate insulating layer 131. This effectively suppresses the formation of a current path in the region between the low-resistance electrode layer 134 and the SiC semiconductor layer 102.

[0377] Furthermore, according to the semiconductor device 171, in addition to the curved portion 125 of the opening edge portion 124 of the gate trench 121, a bulge portion 172 is formed on the opening edge portion 124 of the gate trench 121. This makes it possible to further improve the dielectric strength of the gate insulating layer 131 at the opening edge portion 124 of the gate trench 121.

[0378] Figure 19 is a cross-sectional view of the region corresponding to Figure 13, and shows a semiconductor device 181 according to the ninth embodiment of the present invention. In the following, structures corresponding to the structures described for the semiconductor device 101 are given the same reference numerals and their descriptions are omitted.

[0379] Referring to Figure 19, in the semiconductor device 181, the opening edge portion 124 of the gate trench 121 has an inclined portion 182 that slopes downward from the first main surface 103 of the SiC semiconductor layer 102 toward the side wall of the gate trench 121.

[0380] The inclined portion 182 of the gate trench 121 allows the electric field to be dispersed along the inclined portion 182, thereby mitigating the concentration of the electric field at the opening edge portion 124 of the gate trench 121.

[0381] The gate insulating layer 131 includes a bulge 183 that bulges inward into the gate trench 121 at the inclined portion 182 of the gate trench 121. The bulge 183 is formed at the corner connecting the first region 131a and the third region 131c of the gate insulating layer 131.

[0382] The bulging portion 183 curves outward toward the gate trench 121. The bulging portion 183 narrows the opening of the gate trench 121 at the opening edge portion 124 of the gate trench 121.

[0383] The upper end of the gate electrode layer 132 has a constricted portion that is recessed along the bulge 183 of the gate insulating layer 131. The low-resistance electrode layer 134 covers the constricted portion (upper end) of the gate electrode layer 132. In this configuration, the edge 134c of the low-resistance electrode layer 134 is in contact with the bulge 183 of the gate insulating layer 131.

[0384] The opening edge portion 142 of the source trench 141 has an inclined portion 184 that slopes downward from the first main surface 103 of the SiC semiconductor layer 102 toward the side wall of the source trench 141. The inclined portion 184 of the source trench 141 allows the electric field to be dispersed along the inclined portion 184, thereby mitigating the concentration of the electric field at the opening edge portion 142 of the source trench 141.

[0385] Figures 20A to 20C are cross-sectional views showing an example of a manufacturing method for the semiconductor device 181 shown in Figure 19.

[0386] First, referring to Figure 20A, a SiC semiconductor layer 102 is prepared in which gate trenches 121 and source trenches 141 are formed on the first main surface 103 through the processes shown in Figures 17A to 17D.

[0387] Next, referring to Figure 20B, the first main surface 103 of the SiC semiconductor layer 102 is subjected to thermal oxidation treatment to form a sacrificial oxide film 185. In this process, oxidation begins uniformly from both the first main surface 103 of the SiC semiconductor layer 102 and the side walls of the gate trench 121.

[0388] The oxide film progressing from the first main surface 103 of the SiC semiconductor layer 102 and the oxide film progressing from the side wall of the gate trench 121 are integrated at the opening edge portion 124 of the gate trench 121.

[0389] The integration of these oxide films accelerates oxidation at the opening edge portion 124 of the gate trench 121. Then, a sloping portion 182 is formed below the integrated oxide film at the opening edge portion 124 of the gate trench 121.

[0390] The oxide film progressing from the first main surface 103 of the SiC semiconductor layer 102 and the oxide film progressing from the side wall of the source trench 141 are integrated at the opening edge portion 142 of the source trench 141.

[0391] The integration of these oxide films accelerates oxidation at the opening edge portion 142 of the source trench 141. A sloping portion 184 is then formed below the integrated oxide film at the opening edge portion 142 of the source trench 141.

[0392] Next, referring to Figure 20C, the sacrificial oxide film 185 is removed. The sacrificial oxide film 185 may also be removed by an etching method (e.g., wet etching). Then, the steps shown in Figures 17F to 17L are performed in order.

[0393] In the process shown in Figure 17F, the bulge 183 of the gate insulating layer 131 is formed by setting predetermined conditions for the CVD method (gas flow rate, gas type, gas ratio, gas supply time, etc.) while also considering the shape of the bulge 183 of the gate insulating layer 131. The semiconductor device 181 is manufactured through the process including the above.

[0394] As described above, with the semiconductor device 181, the edge 134c of the low-resistance electrode layer 134 is in contact with the bulge 183 of the gate insulating layer 131. This effectively suppresses the formation of a current path in the region between the low-resistance electrode layer 134 and the SiC semiconductor layer 102.

[0395] Furthermore, according to the semiconductor device 181, in addition to the inclined portion 182 of the opening edge portion 124 of the gate trench 121, a bulge portion 183 is formed on the opening edge portion 124 of the gate trench 121. This makes it possible to further improve the dielectric strength of the gate insulating layer 131 at the opening edge portion 124 of the gate trench 121.

[0396] In this embodiment, an example of a configuration in which a gate insulating layer 131 having a bulge 183 is formed in the semiconductor device 181 has been described. However, a gate insulating layer 131 without a bulge 183 may also be formed in the semiconductor device 181.

[0397] Figure 21 is an enlarged view of the region corresponding to Figure 12, and shows a semiconductor device 191 according to the 10th embodiment of the present invention. Figure 22 is a cross-sectional view along the line XXII-XXII shown in Figure 21. Hereinafter, structures corresponding to the structures described for the semiconductor device 101 are given the same reference numerals and their descriptions are omitted.

[0398] Referring to Figures 21 and 22, in the semiconductor device 191, an outer gate trench 192 is formed on the first main surface 103 of the SiC semiconductor layer 102 in the outer region 107. The outer gate trench 192 extends in a strip shape across the outer region 107.

[0399] The outer gate trench 192 is formed in the region directly beneath the gate finger 109 on the first main surface 103 of the SiC semiconductor layer 102. The outer gate trench 192 extends along the gate finger 109.

[0400] More specifically, the outer gate trench 192 is formed along three sides 105A, 105B, and 105D of the SiC semiconductor layer 102 so as to partition the active region 106 from three directions. The outer gate trench 192 may be formed in an endless shape (e.g., a quadrilateral ring) surrounding the active region 106.

[0401] The outer gate trench 192 communicates with the contact trench portion 121b of each gate trench 121. As a result, the outer gate trench 192 and the gate trench 121 are formed by a single trench.

[0402] A gate wiring layer 133 is embedded in the outer gate trench 192. The gate wiring layer 133 is connected to the gate electrode layer 132 at the communication point between the outer gate trench 192 and the contact trench portion 121b.

[0403] In this configuration, the low-resistance electrode layer 134 covers the upper end of the gate wiring layer 133 within the outer gate trench 192. Therefore, both the low-resistance electrode layer 134 covering the gate electrode layer 132 and the low-resistance electrode layer 134 covering the gate wiring layer 133 are located within a single trench.

[0404] In this configuration, the peripheral deep well region 148 covers the inner wall of the outer gate trench 192 in the outer region 107. The peripheral deep well region 148 extends along the side wall of the outer gate trench 192 and covers the bottom wall of the outer gate trench 192 through the edge.

[0405] In other words, the peripheral deep well region 148 faces the gate wiring layer 133 across the gate insulating layer 131 in the portion that runs along the inner wall of the outer gate trench 192. Also, the peripheral deep well region 148 faces the gate electrode layer 132 across the gate insulating layer 131 in the portion that runs along the inner wall of the gate trench 121.

[0406] As described above, the semiconductor device 191 can achieve the same effects as those described for the semiconductor device 101. Furthermore, with the semiconductor device 191, it is not necessary to draw the gate wiring layer 133 onto the first main surface 103 of the SiC semiconductor layer 102.

[0407] This prevents the gate wiring layer 133 from facing the SiC semiconductor layer 102 across the gate insulating layer 131 at the opening edge portions of the gate trench 121 and the outer gate trench 192. As a result, the concentration of electric fields at the opening edge portions of the gate trench 121 can be suppressed.

[0408] Figure 23 is a cross-sectional view of the region corresponding to Figure 13, and is a cross-sectional view for explaining the structure of the semiconductor device 201 according to the 11th embodiment of the present invention. In the following, structures corresponding to the structure described for the semiconductor device 101 are given the same reference numerals and their descriptions are omitted.

[0409] Referring to Figure 23, in the semiconductor device 201, each source trench 141 is formed deeper than the gate trench 121. Therefore, the bottom wall of each source trench 141 is located on the second main surface 104 side of the SiC semiconductor layer 102 relative to the bottom of the gate trench 121. More specifically, the bottom wall of each source trench 141 is located in the high-density region 112a of the SiC epitaxial layer 112.

[0410] The ratio of the depth of the source trench 141 to the depth of the gate trench 121 may be 1.5 or greater. Preferably, the ratio of the depth of the source trench 141 to the depth of the gate trench 121 is 2 or greater.

[0411] The depth of the gate trench 121 may be between 0.5 μm and 3 μm (for example, about 1 μm). The depth of the source trench 141 may be between 0.75 μm and 10 μm (for example, about 2 μm).

[0412] The deep well region 145 extends along the inner wall of the source trench 141, similar to the semiconductor device 101, and has a bottom located on the second main surface 104 side of the SiC semiconductor layer 102 relative to the bottom wall of the gate trench 121. The deep well region 145 is formed in the high-concentration region 112a of the SiC epitaxial layer 112.

[0413] As described above, the semiconductor device 201 can achieve the same effects as those described for the semiconductor device 101.

[0414] Figure 24 is a plan view of the region corresponding to Figure 12, and is a plan view for illustrating the structure of the semiconductor device 211 according to the 12th embodiment of the present invention. In the following, structures corresponding to the structure described for the semiconductor device 101 are given the same reference numerals and their descriptions are omitted.

[0415] Referring to Figure 24, in this embodiment, the gate trench 121 is formed in a grid shape that integrally includes a plurality of gate trenches 121 extending along a first direction X and a plurality of gate trenches 121 extending along a second direction Y in a plan view.

[0416] The first main surface 103 of the SiC semiconductor layer 102 is divided into multiple cell regions 212 in a matrix by gate trenches 121. Each cell region 212 is formed in a rectangular shape in plan view. Source trenches 141 are formed in each of the multiple cell regions 212. The source trenches 141 may also be formed in a rectangular shape in plan view.

[0417] The cross-sectional view along line XIII-XIII in Figure 24 is approximately the same as the cross-sectional view shown in Figure 13. The cross-sectional view along line XIV-XIV in Figure 24 is approximately the same as the cross-sectional view shown in Figure 14.

[0418] As described above, the semiconductor device 211 can achieve the same effects as those described for the semiconductor device 101. The gate trench 121, which has a lattice-shaped structure instead of a stripe-shaped structure, can also be applied to other forms.

[0419] FIG. 25 is a cross-sectional view of a region corresponding to FIG. 13 and is a plan view for explaining the structure of the semiconductor device 221 according to the 13th embodiment of the present invention. Hereinafter, for structures corresponding to the structures described for the semiconductor device 101, the same reference numerals are given and the description thereof is omitted.

[0420] Referring to FIG. 25, in the semiconductor device 221, the SiC semiconductor layer 102 includes a p + -type SiC semiconductor substrate 222 instead of the n + -type SiC semiconductor substrate 111. The p + -type SiC semiconductor substrate 222 is formed as a collector region of an IGBT (Insulated Gate Bipolar Transistor).

[0421] The description of the semiconductor device 101 is applied by reading the "source" of the MISFET as the "emitter" of the IGBT and reading the "drain" of the MISFET as the "collector" of the IGBT for the description of the semiconductor device 221.

[0422] That is, the source pad 110 and the source region 126 are respectively read as the emitter pad (110) and the emitter region (126). Also, the drain pad 113 and the drain region 114 are respectively read as the collector electrode layer (113) and the collector region (114).

[0423] As described above, the semiconductor device 221 can also achieve the same effects as those described for the semiconductor device 101.

[0424] FIG. 26 is a cross-sectional view of a region corresponding to FIG. 13 and is a cross-sectional view for explaining the structure of the semiconductor device 231 according to the 14th embodiment of the present invention. Hereinafter, for structures corresponding to the structures described for the semiconductor device 101, the same reference numerals are given and the description thereof is omitted.

[0425] Referring to Figure 26, the contact region 144 is formed within the deep well region 145, along the bottom wall of the source trench 141. The contact region 144 is exposed from the bottom wall of the source trench 141.

[0426] The source insulating layer 146 is formed along the inner wall surface of the source trench 141 so as to selectively expose the contact area 144 from the bottom wall of the source trench 141.

[0427] The source insulating layer 146 more specifically includes a first portion 232 and a second portion 233. The first portion 232 covers the side wall of the source trench 141. The second portion 233 partially covers the bottom wall of the source trench 141.

[0428] The second part 233 is connected to the first part 232. The second part 233 extends from the corner of the source trench 141 along the bottom wall, exposing the central part of the bottom wall of the source trench 141. The second part 233 may be formed in an endless (ring-shaped) manner in plan view.

[0429] As described above, the semiconductor device 231 can achieve the same effects as those described for the semiconductor device 101. Furthermore, with the semiconductor device 231, a pn junction is formed in the boundary region between the SiC semiconductor layer 102 and the deep well region 145.

[0430] Even if a depletion layer extends from this pn junction along the bottom wall from the corner of the source trench 141, the source insulating layer 146 can increase the distance the depletion layer travels before reaching the source electrode layer 147. This suppresses the occurrence of punch-through near the corner of the source trench 141.

[0431] Figure 27 is a cross-sectional view of the region corresponding to Figure 13, and is a cross-sectional view for explaining the structure of the semiconductor device 241 according to the 15th embodiment of the present invention. In the following, structures corresponding to the structure described for the semiconductor device 101 are given the same reference numerals and their descriptions are omitted.

[0432] Referring to Figure 27, the deep well region 145 has an exposed portion 242 that selectively exposes the bottom wall of the source trench 141. The exposed portion 242 exposes the central part of the bottom wall of the source trench 141.

[0433] In this embodiment, the source insulating layer 146 includes a first portion 243 and a second portion 244. The first portion 243 covers the side wall of the source trench 141. The second portion 244 partially covers the bottom wall of the source trench 141.

[0434] The second part 244 is connected to the first part 243. The second part 244 extends from the corner of the source trench 141 along the bottom wall, exposing the central part of the bottom wall of the source trench 141. The second part 244 may be formed in an endless (ring-shaped) manner in plan view.

[0435] The source electrode layer 147 forms a heterojunction with the SiC semiconductor layer 102 in the exposed portion 242 of the deep well region 145. This forms a heterojunction diode 245 in which the source electrode layer 147 acts as the anode and the SiC semiconductor layer 102 acts as the cathode. The source electrode layer 147 may contain conductive materials other than polysilicon, as long as the heterojunction diode 245 is formed.

[0436] A body diode 246 is formed at the pn junction between the SiC semiconductor layer 102 and the body region 116. The junction barrier of the heterojunction diode 245 is smaller than the diffusion potential of the body diode 246.

[0437] The junction barrier of the heterojunction diode 245 may be between 1.0 eV and 1.5 eV. The diffusion potential of the body diode 246 may be between 2.8 eV and 3.2 eV.

[0438] As described above, the semiconductor device 241 can achieve the same effects as those described for the semiconductor device 101. Furthermore, in the semiconductor device 241, when a reverse bias voltage is applied, current can be preferentially supplied to the heterojunction diode 245.

[0439] This suppresses the expansion of SiC crystal defects in the SiC semiconductor layer 102. As a result, it is possible to improve short-circuit withstand capability and reduce the feedback capacitance Crss while suppressing an increase in on-resistance.

[0440] Figure 28 is a cross-sectional view of the region corresponding to Figure 13, and is a cross-sectional view for explaining the structure of the semiconductor device 251 according to the 16th embodiment of the present invention. In the following, structures corresponding to the structure described for the semiconductor device 101 are given the same reference numerals and their descriptions are omitted.

[0441] Referring to Figure 28, the contact region 144 is formed within the deep well region 145, along the bottom wall of the source trench 141. The contact region 144 is exposed from the bottom wall of the source trench 141.

[0442] The source insulating layer 146 has a laminated structure including a plurality of barrier-forming layers formed along the inner wall of the source trench 141. In this embodiment, the source insulating layer 146 has a laminated structure including an insulating barrier-forming layer 252 and a conductive barrier-forming layer 253, which are laminated in this order from the inner wall of the source trench 141.

[0443] The insulating barrier forming layer 252 may contain at least one of the following: impurity-free silicon, silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, or aluminum oxynitride.

[0444] The insulating barrier forming layer 252 is formed in a film-like manner along the inner wall surface of the source trench 141 so as to selectively expose the contact region 144 from the bottom wall of the source trench 141.

[0445] The insulating barrier forming layer 252 more specifically includes a first portion 254 and a second portion 255. The first portion 254 covers the side walls of the source trench 141. The second portion 255 selectively covers the bottom walls of the source trench 141.

[0446] The second section 255 is connected to the first section 254. The second section 255 extends from the corner of the source trench 141 along the bottom wall, exposing the central part of the bottom wall of the source trench 141.

[0447] The conductive barrier forming layer 253 may contain at least one of conductive polysilicon, tungsten, platinum, nickel, cobalt, or molybdenum. The conductive barrier forming layer 253 contains a conductive material different from the conductive material of the source electrode layer 147.

[0448] The conductive barrier forming layer 253 is formed in a film-like manner along the insulating barrier forming layer 252 so as to selectively expose the contact region 144 from the bottom wall of the source trench 141.

[0449] The source insulating layer 146 may include an insulating barrier forming layer made of a different insulating material than the insulating barrier forming layer 252, instead of the conductive barrier forming layer 253. The source insulating layer 146 may also include an insulating barrier forming layer made of the same insulating material as the insulating barrier forming layer 252, instead of the conductive barrier forming layer 253.

[0450] As described above, the semiconductor device 251 can achieve the same effects as those described for the semiconductor device 101. Furthermore, in the semiconductor device 251, the source insulating layer 146 has a laminated structure including an insulating barrier forming layer 252 and a conductive barrier forming layer 253. As a result, the occurrence of punch-through can be suppressed by the two layers of the insulating barrier forming layer 252 and the conductive barrier forming layer 253.

[0451] Figure 29 is a cross-sectional view of the region corresponding to Figure 13, and is a cross-sectional view for explaining the structure of the semiconductor device 261 according to the 17th embodiment of the present invention. In the following, structures corresponding to the structure described for the semiconductor device 101 are given the same reference numerals and their descriptions are omitted.

[0452] Referring to Figure 29, the contact region 144 is formed within the deep well region 145, along the bottom wall of the source trench 141. The contact region 144 is exposed from the bottom wall of the source trench 141.

[0453] The source insulating layer 146 includes a first portion 262 and a second portion 263. The first portion 262 covers the side wall of the source trench 141. The second portion 263 covers the bottom wall of the source trench 141.

[0454] The first portion 262 selectively has sidewall contact holes 264 that expose the SiC semiconductor layer 102 from the sidewall of the source trench 141. The first portion 262 may be formed to traverse the boundary region between the SiC semiconductor layer 102 and the body region 116.

[0455] The lower end of the first portion 262 (the end on the bottom wall side of the source trench 141) may be located on the bottom wall side of the source trench 141 relative to the bottom of the body region 116. In this case, the source electrode layer 147 is electrically connected to the drift region 115 within the source trench 141.

[0456] The lower end of the first portion 262 may be located on the first main surface 103 side relative to the bottom of the body region 116. The lower end of the first portion 262 may be formed in the region between the bottom of the body region 116 and the bottom of the source region 126. In these cases, the source electrode layer 147 is connected to at least the body region 116 within the source trench 141.

[0457] The lower end of the first portion 262 may be formed in the region between the first main surface 103 of the SiC semiconductor layer 102 and the bottom of the source region 126. The source insulating layer 146 may not have the first portion 262 and may have only the second portion 263. In these cases, the source electrode layer 147 is connected to the body region 116 and the contact region 144 within the source trench 141.

[0458] The second portion 263 of the source insulating layer 146 is formed at a distance from the first portion 262 of the source insulating layer 146. In other words, the second portion 263 is separated from the first portion 262. The second portion 263 may cover the corners of the source trench 141.

[0459] The second portion 263 may expose the corner of the source trench 141. The second portion 263 may cover the corner of the source trench 141 and also cover a portion of the side wall of the source trench 141.

[0460] The source electrode layer 147 forms a Schottky junction with the SiC semiconductor layer 102 (drift region 115) within the source trench 141. This forms a Schottky barrier diode 265 with the source electrode layer 147 as the anode and the SiC semiconductor layer 102 as the cathode.

[0461] The p-type deep well region 145 is formed in the SiC semiconductor layer 102 in a region along the bottom wall of the source trench 141. In this configuration, the deep well region 145 is formed in the high-concentration region 112a of the SiC epitaxial layer 112. The entire area of ​​the deep well region 145 is formed in the high-concentration region 112a.

[0462] The deep well region 145 may be formed continuously in the SiC semiconductor layer 102 along the sidewalls and corners of the source trench 141, so as to expose the source electrode layer 147 from the sidewalls of the source trench 141.

[0463] The deep well region 145 covers the bottom wall of the source trench 141. The deep well region 145 covers the corners connecting the side walls and bottom wall of the source trench 141. The deep well region 145 may expose almost the entire side wall of the source trench 141 in the SiC semiconductor layer 102.

[0464] The deep well region 145 is drawn out from the bottom wall of the source trench 141 in a lateral direction parallel to the first main surface 103 of the SiC semiconductor layer 102. As a result, the deep well region 145 faces the body region 116 with respect to the direction normal to the first main surface 103 of the SiC semiconductor layer 102, with a portion of the SiC semiconductor layer 102 (drift region 115) in between.

[0465] More specifically, the source electrode layer 147 forms a Schottky junction with the SiC semiconductor layer 102 (drift region 115) at a depth position between the body region 116 and the deep well region 145, with respect to the normal direction of the first main surface 103 of the SiC semiconductor layer 102.

[0466] More specifically, the source electrode layer 147 forms a Schottky junction with the SiC semiconductor layer 102 (drift region 115) in the region sandwiched between the body region 116 and the deep well region 145 in the SiC semiconductor layer 102, with respect to the normal direction of the first main surface 103 of the SiC semiconductor layer 102.

[0467] The source electrode layer 147 may have a stacked structure including multiple electrode layers. The source electrode layer 147 may include a first electrode layer and a second electrode layer stacked in this order from the SiC semiconductor layer 102 side.

[0468] The first electrode layer may be a barrier electrode layer containing a Ti (titanium) film and / or a TiN (titanium nitride) film. The first electrode layer may have a laminated structure in which the Ti (titanium) film and the TiN (titanium nitride) film are stacked in this order from the SiC semiconductor layer 102 side. The first electrode layer may have a single-layer structure consisting of a Ti (titanium) film or a TiN (titanium nitride) film. The second electrode layer may contain aluminum or tungsten.

[0469] As described above, the semiconductor device 261 can achieve the same effects as those described for the semiconductor device 101. Furthermore, in the semiconductor device 261, when a reverse bias voltage is applied, current can be preferentially supplied to the Schottky barrier diode 265.

[0470] This suppresses the expansion of SiC crystal defects in the SiC semiconductor layer 102. As a result, it is possible to improve short-circuit withstand capability and reduce the feedback capacitance Crss while suppressing an increase in on-resistance.

[0471] In this embodiment, an example has been described in which the source electrode layer 147 forms a Schottky junction with the SiC semiconductor layer 102 within the sidewall contact hole 264 of the source insulating layer 146. However, an embodiment in which the source insulating layer 146 (first portion 262 and second portion 263) is not formed may also be adopted.

[0472] Figure 30 is a cross-sectional view of the region corresponding to Figure 13, and is a cross-sectional view for explaining the structure of the semiconductor device 271 according to the 18th embodiment of the present invention. In the following, structures corresponding to the structure described for the semiconductor device 201 are given the same reference numerals and their descriptions are omitted.

[0473] Referring to Figure 30, the contact region 144 is formed within the deep well region 145 in a region along the bottom wall of the source trench 141. The contact region 144 is exposed from the bottom wall of the source trench 141. The source insulating layer 146 is formed along the inner wall surface of the source trench 141 so as to selectively expose the contact region 144 from the bottom wall of the source trench 141.

[0474] The source insulating layer 146 more specifically includes a first portion 272 and a second portion 273. The first portion 272 covers the side walls of the source trench 141. The second portion 273 partially covers the bottom walls of the source trench 141.

[0475] The second part 273 is connected to the first part 272. The second part 273 extends from the corner of the source trench 141 along the bottom wall, exposing the central part of the bottom wall of the source trench 141. The second part 273 may be formed in an endless (ring-shaped) manner in plan view.

[0476] As described above, semiconductor device 271 can achieve the same effects as those described for semiconductor device 201. Furthermore, with semiconductor device 271, a pn junction is formed in the boundary region between the SiC semiconductor layer 102 and the deep well region 145.

[0477] Even if a depletion layer extends from this pn junction along the bottom wall from the corner of the source trench 141, the source insulating layer 146 can increase the distance the depletion layer travels before reaching the source electrode layer 147. This suppresses the occurrence of punch-through near the corner of the source trench 141.

[0478] Figure 31 is a cross-sectional view of the region corresponding to Figure 13, and is a cross-sectional view for explaining the structure of the semiconductor device 281 according to the 19th embodiment of the present invention. In the following, structures corresponding to the structure described for the semiconductor device 201 are given the same reference numerals and their descriptions are omitted.

[0479] Referring to Figure 31, the deep well region 145 has an exposed portion 282 that selectively exposes the bottom wall of the source trench 141. The exposed portion 282 exposes the central part of the bottom wall of the source trench 141.

[0480] In this embodiment, the source insulating layer 146 includes a first portion 283 and a second portion 284. The first portion 283 covers the side walls of the source trench 141. The second portion 284 partially covers the bottom walls of the source trench 141.

[0481] The second part 284 is connected to the first part 283. The second part 284 extends from the corner of the source trench 141 along the bottom wall, exposing the central part of the bottom wall of the source trench 141. The second part 284 may be formed in an endless (ring-shaped) manner in plan view.

[0482] The source electrode layer 147 forms a heterojunction with the SiC semiconductor layer 102 in the exposed portion 282 of the deep well region 145. This forms a heterojunction diode 285 in which the source electrode layer 147 acts as the anode and the SiC semiconductor layer 102 acts as the cathode. The source electrode layer 147 may contain conductive materials other than polysilicon, as long as the heterojunction diode 285 is formed.

[0483] A body diode 286 is formed at the pn junction between the SiC semiconductor layer 102 and the body region 116. The junction barrier of the heterojunction diode 285 is smaller than the diffusion potential of the body diode 286.

[0484] The junction barrier of the heterojunction diode 285 may be between 1.0 eV and 1.5 eV. The diffusion potential of the body diode 286 may be between 2.8 eV and 3.2 eV.

[0485] As described above, semiconductor device 281 can achieve the same effects as semiconductor device 201. Furthermore, with semiconductor device 281, when a reverse bias voltage is applied, current can be preferentially supplied to the heterojunction diode 285.

[0486] This suppresses the expansion of SiC crystal defects in the SiC semiconductor layer 102. As a result, it is possible to improve short-circuit withstand capability and reduce the feedback capacitance Crss while suppressing an increase in on-resistance.

[0487] Figure 32 is a cross-sectional view of the region corresponding to Figure 13, and is a cross-sectional view for explaining the structure of the semiconductor device 291 according to the 20th embodiment of the present invention. In the following, structures corresponding to the structure described for the semiconductor device 201 are given the same reference numerals and their descriptions are omitted.

[0488] Referring to Figure 32, the contact region 144 is formed within the deep well region 145, along the bottom wall of the source trench 141. The contact region 144 is exposed from the bottom wall of the source trench 141.

[0489] The source insulating layer 146 has a laminated structure including a plurality of barrier-forming layers formed along the inner wall of the source trench 141. In this embodiment, the source insulating layer 146 has a laminated structure including an insulating barrier-forming layer 292 and a conductive barrier-forming layer 293, which are laminated in this order from the inner wall of the source trench 141.

[0490] The insulating barrier forming layer 292 may contain at least one of the following: impurity-free silicon, silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, or aluminum oxynitride.

[0491] The insulating barrier forming layer 292 is formed in a film-like manner along the inner wall surface of the source trench 141 so as to selectively expose the contact region 144 from the bottom wall of the source trench 141.

[0492] The insulating barrier forming layer 292 more specifically includes a first portion 294 and a second portion 295. The first portion 294 covers the side walls of the source trench 141. The second portion 295 selectively covers the bottom walls of the source trench 141.

[0493] The second section 295 is connected to the first section 294. The second section 295 extends from the corner of the source trench 141 along the bottom wall, exposing the central part of the bottom wall of the source trench 141.

[0494] The conductive barrier forming layer 293 may contain at least one of conductive polysilicon, tungsten, platinum, nickel, cobalt, or molybdenum. The conductive barrier forming layer 293 contains a conductive material different from the conductive material of the source electrode layer 147.

[0495] The conductive barrier forming layer 293 is formed in a film-like manner along the insulating barrier forming layer 292 so as to selectively expose the contact region 144 from the bottom wall of the source trench 141.

[0496] As described above, semiconductor device 291 can achieve the same effects as those described for semiconductor device 201. Furthermore, in semiconductor device 291, the source insulating layer 146 has a laminated structure including an insulating barrier forming layer 292 and a conductive barrier forming layer 293. As a result, the occurrence of punch-through can be suppressed by the two layers of insulating barrier forming layer 292 and conductive barrier forming layer 293.

[0497] Figure 33 is a cross-sectional view of the region corresponding to Figure 13, and is a cross-sectional view for explaining the structure of the semiconductor device 301 according to the 21st embodiment of the present invention. In the following, structures corresponding to the structure described for the semiconductor device 201 are denoted by the same reference numerals and their descriptions are omitted.

[0498] Referring to Figure 33, the contact region 144 is formed within the deep well region 145, along the bottom wall of the source trench 141. The contact region 144 is exposed from the bottom wall of the source trench 141.

[0499] The source insulating layer 146 includes a first portion 302 and a second portion 303. The first portion 302 covers the side wall of the source trench 141. The second portion 303 covers the bottom wall of the source trench 141.

[0500] The first portion 302 selectively has sidewall contact holes 304 that expose the SiC semiconductor layer 102 from the sidewall of the source trench 141. The first portion 302 may be formed to traverse the boundary region between the SiC semiconductor layer 102 and the body region 116.

[0501] The lower end of the first portion 302 (the end on the source trench 141 side) may be located on the bottom wall side of the source trench 141 relative to the bottom of the body region 116. In this case, the source electrode layer 147 is electrically connected to the drift region 115 within the source trench 141.

[0502] The lower end of the first portion 302 may be located on the first main surface 103 side relative to the bottom of the body region 116. The lower end of the first portion 302 may be formed in the region between the bottom of the body region 116 and the bottom of the source region 126. In these cases, the source electrode layer 147 is connected to at least the body region 116 within the source trench 141.

[0503] The lower end of the first portion 302 may be formed in the region between the first main surface 103 of the SiC semiconductor layer 102 and the bottom of the source region 126. The source insulating layer 146 may not have the first portion 302 and may have only the second portion 303. In these cases, the source electrode layer 147 is connected to the body region 116 and the contact region 144 within the source trench 141.

[0504] The second portion 303 of the source insulating layer 146 is formed at a distance from the first portion 302 of the source insulating layer 146. In other words, the second portion 303 is separated from the first portion 302. The second portion 303 may cover the corners of the source trench 141.

[0505] The second portion 303 may expose the corner of the source trench 141. The second portion 303 may cover the corner of the source trench 141 and also cover a portion of the side wall of the source trench 141.

[0506] The source electrode layer 147 forms a Schottky junction with the SiC semiconductor layer 102 (drift region 115) within the source trench 141. This forms a Schottky barrier diode 305 with the source electrode layer 147 as the anode and the SiC semiconductor layer 102 as the cathode.

[0507] The p-type deep well region 145 is formed in the SiC semiconductor layer 102 in a region along the bottom wall of the source trench 141. In this configuration, the deep well region 145 is formed in the high-concentration region 112a of the SiC epitaxial layer 112. The entire area of ​​the deep well region 145 is formed in the high-concentration region 112a.

[0508] The deep well region 145 may be formed continuously in the SiC semiconductor layer 102 along the sidewalls and corners of the source trench 141, so as to expose the source electrode layer 147 from the sidewalls of the source trench 141.

[0509] The deep well region 145 covers the bottom wall of the source trench 141. The deep well region 145 covers the corners connecting the side walls and bottom wall of the source trench 141. The deep well region 145 may expose almost the entire side wall of the source trench 141 in the SiC semiconductor layer 102.

[0510] The deep well region 145 is drawn out from the bottom wall of the source trench 141 in a lateral direction parallel to the first main surface 103 of the SiC semiconductor layer 102. As a result, the deep well region 145 faces the body region 116 with respect to the direction normal to the first main surface 103 of the SiC semiconductor layer 102, with a portion of the SiC semiconductor layer 102 (drift region 115) in between.

[0511] The deep well region 145 is drawn out from the bottom wall of the source trench 141 in a lateral direction parallel to the first main surface 103 of the SiC semiconductor layer 102. As a result, the deep well region 145 faces the body region 116 with respect to the direction normal to the first main surface 103 of the SiC semiconductor layer 102, with a portion of the SiC semiconductor layer 102 (drift region 115) in between.

[0512] More specifically, the source electrode layer 147 forms a Schottky junction with the SiC semiconductor layer 102 (drift region 115) at a depth position between the body region 116 and the deep well region 145, with respect to the normal direction of the first main surface 103 of the SiC semiconductor layer 102.

[0513] More specifically, the source electrode layer 147 forms a Schottky junction with the SiC semiconductor layer 102 (drift region 115) in the region sandwiched between the body region 116 and the deep well region 145 in the SiC semiconductor layer 102, with respect to the normal direction of the first main surface 103 of the SiC semiconductor layer 102.

[0514] The source electrode layer 147 may have a stacked structure including multiple electrode layers. The source electrode layer 147 may include a first electrode layer and a second electrode layer stacked in this order from the SiC semiconductor layer 102 side.

[0515] The first electrode layer may be a barrier electrode layer containing a Ti (titanium) film and / or a TiN (titanium nitride) film. The first electrode layer may have a laminated structure in which the Ti (titanium) film and the TiN (titanium nitride) film are stacked in this order from the SiC semiconductor layer 102 side. The first electrode layer may have a single-layer structure consisting of a Ti (titanium) film or a TiN (titanium nitride) film. The second electrode layer may contain aluminum or tungsten.

[0516] As described above, semiconductor device 301 can achieve the same effects as those described for semiconductor device 201. Furthermore, with semiconductor device 301, when a reverse bias voltage is applied, current can be preferentially supplied to the Schottky barrier diode 305.

[0517] This suppresses the expansion of SiC crystal defects in the SiC semiconductor layer 102. As a result, it is possible to improve short-circuit withstand capability and reduce the feedback capacitance Crss while suppressing an increase in on-resistance.

[0518] In this embodiment, an example has been described in which the source electrode layer 147 forms a Schottky junction with the SiC semiconductor layer 102 within the sidewall contact hole 264 of the source insulating layer 146. However, an embodiment in which the source insulating layer 146 (first portion 302 and second portion 303) is not formed may also be adopted.

[0519] Although the seventh to twentieth embodiments of the present invention have been described, the seventh to twentieth embodiments of the present invention can be implemented in other forms as well.

[0520] In the seventh to twenty-first embodiments described above, an example was given in which a SiC epitaxial layer 112 having a high-concentration region 112a and a low-concentration region 112b is formed by an epitaxial growth method. However, the SiC epitaxial layer 112 can also be formed by the following process.

[0521] First, a SiC epitaxial layer 112 with a relatively low n-type impurity concentration is formed by epitaxial growth. Next, n-type impurities are introduced into the surface layer of the SiC epitaxial layer 112 by ion implantation. This forms a SiC epitaxial layer 112 having a high-concentration region 112a and a low-concentration region 112b.

[0522] In the seventh to twenty-first embodiments described above, an example was described in which the SiC semiconductor layer 102 has a stacked structure including a SiC semiconductor substrate 111 and a SiC epitaxial layer 112. However, the SiC semiconductor layer 102 may have a single-layer structure consisting of the SiC semiconductor substrate 111. The SiC semiconductor layer 102 may have a single-layer structure consisting of the SiC epitaxial layer 112.

[0523] In the seventh to twenty-first embodiments described above, a structure in which the conductivity type of each semiconductor portion is reversed may be adopted. That is, the p-type portion may be made n-type, and the n-type portion may be made p-type.

[0524] In the seventh to twenty-first embodiments described above, examples were given in which a gate electrode layer 132 and a gate wiring layer 133 containing p-type polysilicon doped with p-type impurities were formed. However, if the increase in gate threshold voltage Vth is not a concern, the gate electrode layer 132 and the gate wiring layer 133 may contain n-type polysilicon doped with n-type impurities instead of p-type polysilicon.

[0525] The low-resistance electrode layer 134 may be formed by silicideizing the surface layer portion of the gate electrode layer 132 (n-type polysilicon) with a metallic material. In other words, the low-resistance electrode layer 134 may contain n-type polysilicon. With such a structure, the gate resistance can be reduced.

[0526] In the seventh to 21st embodiments described above, the structure of the semiconductor device 221 may be adopted. That is, in the seventh to 21st embodiments described above, n + Instead of the type SiC semiconductor substrate 111, p +A SiC semiconductor substrate 222 of type 222 may be used. In this case, the descriptions of the seventh to thirteenth embodiments above shall be read as follows: "source" shall be read as "emitter" and "drain" shall be read as "collector".

[0527] Figure 34 is a top view showing a semiconductor device 311 according to the 22nd embodiment of the present invention. Figure 35 is a bottom view of the semiconductor device 311 shown in Figure 34. Hereinafter, structures corresponding to the structures described for the semiconductor device 101 will be denoted by the same reference numerals.

[0528] Referring to Figure 34, the semiconductor device 311 has a SiC semiconductor layer 102 containing a SiC (silicon carbide) single crystal. The SiC semiconductor layer 102 may also contain a 4H-SiC single crystal.

[0529] A 4H-SiC single crystal has an off-angle that is tilted at an angle of 10° or less with respect to the [11-20] direction from the

[0001] plane. The off-angle may be between 0° and 4°. The off-angle may be greater than 0° and less than 4°. Typically, the off-angle is set to 2° or 4°, more specifically in the range of 2°±0.2° or 4°±0.4°.

[0530] In this embodiment, the SiC semiconductor layer 102 is formed in the shape of a rectangular parallelepiped chip. The SiC semiconductor layer 102 has a first main surface 103 on one side, a second main surface 104 on the other side, and sides 105A, 105B, 105C, and 105D connecting the first main surface 103 and the second main surface 104. The first main surface 103 and the second main surface 104 are formed in a quadrilateral shape (rectangular in this embodiment) when viewed from the direction of their normals in a plan view (hereinafter simply referred to as "plan view").

[0531] Side 105A faces side 105C. Side 105B faces side 105D. The four sides 105A to 105D each extend planarly along the direction normal to the first main surface 103 and the second main surface 104. The lengths of sides 105A to 105D may each be between 1 mm and 10 mm (for example, between 2 mm and 5 mm).

[0532] The SiC semiconductor layer 102 has an active region 106 and an outer region 107. The active region 106 is the region where the vertical MISFET is formed. The outer region 107 is the region outside the active region 106.

[0533] The active region 106 is located in the center of the SiC semiconductor layer 102, with a gap in the inward region from the sides 105A to 105D of the SiC semiconductor layer 102 in a plan view. The active region 106 is set in a quadrilateral shape (rectangular in this form) with four sides parallel to the four sides 105A to 105D of the SiC semiconductor layer 102 in a plan view.

[0534] The outer region 107 is defined as the region between the side surfaces 105A to 105D of the SiC semiconductor layer 102 and the periphery of the active region 106. In a plan view, the outer region 107 is defined as an endless (quadrilateral ring) shape surrounding the active region 106.

[0535] A gate pad 108, a gate finger 109, and a source pad 110 are formed on the first main surface 103 of the SiC semiconductor layer 102. The gate pad 108, gate finger 109, and source pad 110 may contain aluminum and / or copper.

[0536] The gate pad 108 is formed along the side surface 105A of the SiC semiconductor layer 102 in a plan view. The gate pad 108 is formed along the central region of the side surface 105A of the SiC semiconductor layer 102 in a plan view. The gate pad 108 may also be formed along the corner connecting any two of the four side surfaces 105A to 105D of the SiC semiconductor layer 102 in a plan view.

[0537] The gate pad 108 is formed in a rectangular shape in plan view. The gate pad 108 is drawn out from the outer region 107 into the active region 106 so as to cross the boundary region between the outer region 107 and the active region 106 in plan view.

[0538] The gate finger 109 includes an outer gate finger 109A and an inner gate finger 109B. The outer gate finger 109A extends from the gate pad 108 to the outer region 107. The outer gate finger 109A extends in a strip-like manner across the outer region 107.

[0539] In this embodiment, the outer gate finger 109A is formed along three sides 105A, 105B, and 105D of the SiC semiconductor layer 102 so as to partition the active region 106 from three directions.

[0540] The inner gate finger 109B is extended from the gate pad 108 into the active area 106. The inner gate finger 109B extends in a strip-like manner through the active area 106. The inner gate finger 109B extends from side 105A to side 105C.

[0541] The source pad 110 is formed in the active region 106, spaced apart from the gate pad 108 and gate finger 109. The source pad 110 is formed in a C-shape (inverted C-shape in Figure 34) in plan view so as to cover the C-shaped region (inverted C-shape in Figure 34) demarcated by the gate pad 108 and gate finger 109.

[0542] A gate voltage is applied to the gate pad 108 and gate finger 109. The gate voltage may be between 10V and 50V (for example, around 30V). A source voltage is applied to the source pad 110. The source voltage may be a reference voltage (for example, GND voltage).

[0543] A resin layer 312 is formed on the first main surface 103 of the SiC semiconductor layer 102 (more specifically, on the interlayer insulating layer 153). In Figure 34, the resin layer 312 is shown by hatching for clarity. The resin layer 312 covers the gate pad 108, gate finger 109, and source pad 110.

[0544] The resin layer 312 may contain a negative-type or positive-type photosensitive resin. In this embodiment, the resin layer 312 contains polybenzoxazole as an example of a positive-type photosensitive resin. The resin layer 312 may also contain polyimide as an example of a negative-type photosensitive resin.

[0545] The peripheral edge of the resin layer 312 is formed with a gap inward from the side surfaces 105A to 105D of the SiC semiconductor layer 102. As a result, the peripheral edge of the resin layer 312 exposes the first main surface 103 of the SiC semiconductor layer 102. More specifically, the peripheral edge of the resin layer 312 exposes the interlayer insulating layer 153.

[0546] The resin layer 312 has a gate pad opening 313 and a source pad opening 314. The gate pad opening 313 exposes the gate pad 108. The source pad opening 314 exposes the source pad 110.

[0547] Referring to Figure 35 and its enlarged view, a group of raised portions 316, including a plurality of raised portions 315, is formed on the second main surface 104 of the SiC semiconductor layer 102. The plurality of raised portions 315 are portions that are raised on the second main surface 104 of the SiC semiconductor layer 102 along the direction normal to the second main surface 104 of the SiC semiconductor layer 102.

[0548] Multiple raised portions 315 are formed spaced apart from each other along an arbitrary first direction X and a second direction Y intersecting the first direction X. The first direction X is one of the planar directions of the first main surface 103 of the SiC semiconductor layer 102.

[0549] In this embodiment, the first direction X is set parallel to the sides 105B and 105D of the SiC semiconductor layer 102. More specifically, the second direction Y is perpendicular to the first direction X. That is, in this embodiment, the second direction Y is set parallel to the sides 105A and 105C of the SiC semiconductor layer 102.

[0550] The raised portion group 316 has a first portion 317 in which some of the raised portions 315 overlap with the first direction X in a first view from the first direction X.

[0551] Furthermore, the raised portion group 316 has several raised portions 315 that are spaced apart from the first portion 317, and also has a second portion 318 that overlaps with the first direction X when viewed in the first direction.

[0552] The multiple raised portions 315 are formed continuously along the first direction X. More specifically, the multiple raised portions 315 have a dotted pattern, which is spaced apart along the first direction X and the second direction Y.

[0553] The multiple raised portions 315 are formed continuously along the first direction X while maintaining this dotted pattern. In this embodiment, the multiple raised portions 315 are formed in a plan view from the periphery of one side surface 105A to the periphery of the other side surface 105C of the SiC semiconductor layer 102.

[0554] The distances between the multiple raised portions 315 formed at intervals in the first direction X in the raised portion group 316 may be different from each other. The distances between the multiple raised portions 315 formed at intervals in the second direction Y in the raised portion group 316 may also be different from each other.

[0555] The multiple raised portions 315 may each be formed with non-uniform shapes, sizes, and thicknesses. The thickness of the raised portion 315 is the distance from the base to the top (tip) of the raised portion 315 with respect to the direction normal to the second main surface 104 of the SiC semiconductor layer 102.

[0556] Each of the multiple raised portions 315 may have a size greater than 0 μm and less than or equal to 10 μm. Each raised portion 315 may have a thickness of 500 nm or less (for example, 1 nm to 250 nm).

[0557] The raised portion group 316 is formed on the second main surface 104 of the SiC semiconductor layer 102 in an area narrower than the width of the side surfaces 105A to 105D (side surfaces 105A and 105C in this configuration) of the SiC semiconductor layer 102.

[0558] The raised portion group 316 is formed in a range of 1 / 1000 to 1 / 5 of the width of the side surfaces 105A to 105D (in this embodiment, side surfaces 105A and 105C) of the SiC semiconductor layer 102.

[0559] The raised portion group 316 may be formed in a range of 1 / 200th to 1 / 10th of the width of the side surfaces 105A to 105D (in this embodiment, side surfaces 105A and 105C) of the SiC semiconductor layer 102.

[0560] The raised portion group 316 may be formed in a range of 10 μm to 200 μm with respect to the second direction Y. The raised portion group 316 may be formed in a range of 50 μm to 150 μm with respect to the second direction Y. The raised portion group 316 may be formed in a range of 80 μm to 120 μm with respect to the second direction Y.

[0561] The raised portion group 316 has a layout in which multiple raised portions 315 overlap in the first direction X when viewed from the first direction X. As a result, the raised portion group 316 forms a raised portion group region 319 that extends in a band shape along the first direction X, formed by a collection pattern of multiple raised portions 315 that are continuously scattered along the first direction X.

[0562] In other words, the raised portion group region 319 includes a plurality of raised portions 315 (raised portion group 316) formed in a band-shaped region extending along the first direction X on the second main surface 104 of the SiC semiconductor layer 102.

[0563] Multiple raised areas 316 (raised area regions 319) having this configuration are formed on the second main surface 104 of the SiC semiconductor layer 102, spaced apart along the second direction Y.

[0564] In other words, the scattered pattern of multiple raised portions 315 is formed intermittently in a second-direction view as seen from a second-direction Y. The distance between multiple groups of raised portions 316 may be between 1% and 25% of the area in which the groups of raised portions 316 are formed.

[0565] With respect to the second direction Y, the distance between adjacent groups of raised parts 316 may be 100 μm or less. The distance between groups of raised parts 316 may be 5 μm or more and 50 μm or less. The distance between groups of raised parts 316 may be 20 μm or less.

[0566] The first direction X may be set in the [11-20] direction, and the second direction Y may be set in the [1-100] direction. In other words, the raised portion group 316 may form a band-shaped raised portion group region 319 extending substantially parallel or parallel to the [11-20] direction, and multiple such regions may be formed at intervals along the [1-100] direction.

[0567] The first direction X may be set in the [1-100] direction, and the second direction Y may be set in the [11-20] direction. In other words, the raised portion group 316 may form a band-shaped raised portion group region 319 extending substantially parallel or parallel to the [1-100] direction, and multiple such regions may be formed at intervals along the [11-20] direction.

[0568] In the second main surface 104 of the SiC semiconductor layer 102, a space 320 is defined between groups of adjacent raised portions 316 in the second direction Y, which does not have a dotted pattern consisting of multiple raised portions 315.

[0569] Space 320 is divided into strips extending parallel to the first direction X by adjacent groups of raised portions 316 (raised portion region 319). As a result, a stripe pattern is formed on the second main surface 104 of the SiC semiconductor layer 102 in which the raised portions 316 and space 320 are alternately formed along the second direction Y.

[0570] Multiple grooves 321 are formed on the second main surface 104 of the SiC semiconductor layer 102. In Figure 35 and its enlarged view, the grooves 321 are indicated by lines. The grooves 321 are formed in the raised portion group 316 and the space 320.

[0571] The multiple grooves 321 include grinding marks resulting from grinding the second wafer main surface 333 of the SiC semiconductor wafer 331, which will be described later. Therefore, the direction in which the grooves 321 extend differs depending on the position from which the SiC semiconductor layer 102 is cut from the SiC semiconductor wafer 331.

[0572] The grooves 321 may extend substantially parallel to or parallel to each group of raised sections 316. The grooves 321 may include portions that intersect with the group of raised sections 316. The grooves 321 may extend along directions that intersect or are perpendicular to each group of raised sections 316. The grooves 321 may extend in a straight line or in an arc shape.

[0573] Some of the multiple raised portions 315 included in each group of raised portions 316 are formed at intervals along the groove 321. In other words, each group of raised portions 316 includes a third portion 322 in which some of the multiple raised portions 315 are formed at intervals along the groove 321 when viewed from above.

[0574] Each group of raised portions 316 is formed, for example, by an annealing process. Multiple raised portions 315 may be laser processing marks formed by a laser annealing process.

[0575] Multiple raised portions 315 along the groove 321 (the third portion 322 of the group of raised portions 316) may be formed by an annealing treatment method on the second main surface 104 of the SiC semiconductor layer 102 (the second wafer main surface 333 of the SiC semiconductor wafer 331) that is demarcated by the groove 321.

[0576] Each raised portion group 316 can take on various forms by adjusting the annealing conditions (in this case, laser annealing conditions), as shown in Figures 36A to 36D.

[0577] Figure 36A shows an example of the second form of each of the 316 raised areas.

[0578] As shown in Figure 36A, the group of raised portions 316 may include convex, curved raised portions 315 that extend along a first direction X in a plan view and protrude along a second direction Y (towards the side surface 105B in Figure 36A). The raised portions 315 may be formed by a plurality of overlapping raised portions 315.

[0579] The distance between the two furthest points in the raised portion 315 may be between 1 μm and 200 μm (approximately 50 μm in this embodiment). With respect to the first direction X, the distance between multiple adjacent raised portions 315 is set to a value of 10% or more of the size of the raised portion 315. Multiple raised portions 315 are formed by shifting the laser irradiation positions of adjacent portions in the first direction X.

[0580] Figure 36B shows an example of the third form of the raised section group 316.

[0581] As shown in Figure 36B, the group of raised portions 316 may include a concave curved raised portion 315 that extends along the second direction Y in a plan view and is recessed along the first direction X. The raised portion 315 may be formed by a plurality of overlapping raised portions 315.

[0582] The distance between the two furthest points in each raised portion 315 may be between 1 μm and 200 μm (approximately 50 μm in this embodiment). Multiple raised portions 315 are formed by overlapping the adjacent laser irradiation positions by 50% to 70%.

[0583] Figure 36C shows an example of the fourth morphology of the raised portion group 316.

[0584] As shown in Figure 36C, the group of raised portions 316 may include linear raised portions 315 that extend along the second direction Y in a plan view and are recessed along the first direction X. The raised portions 315 may have projections that protrude along the first direction X. The raised portions 315 may be formed by a plurality of overlapping raised portions 315.

[0585] The distance between the two furthest points in the raised portion 315 may be between 1 μm and 200 μm (approximately 50 μm in this embodiment). Multiple raised portions 315 are formed by overlapping the adjacent laser irradiation positions by 70% to 90%.

[0586] Figure 36D shows an example of the fifth morphology of the raised section 316.

[0587] As shown in Figure 36D, the group of raised parts 316 may have a layout in which rows of raised parts, each containing a plurality of raised parts 315 arranged at intervals along the second direction Y, are formed at intervals along the first direction X.

[0588] The distance between the two furthest points in the raised portion 315 may be between 1 μm and 200 μm (approximately 5 μm in this embodiment). Multiple raised portions 315 are formed by overlapping the laser irradiation positions of adjacent portions by 90% or more and less than 100%.

[0589] Figure 37 is an enlarged view of region XXXVII shown in Figure 34, with the structure above the first main surface 103 of the SiC semiconductor layer 102 removed. Figure 38 is a cross-sectional view along the line XXXVIII-XXXVIII in Figure 37. Figure 39 is a cross-sectional view along the line XXXIX-XXXIX in Figure 37. Figure 40 is an enlarged view of region XL shown in Figure 39.

[0590] Referring to Figures 37 to 39, the semiconductor device 311 has the same planar and cross-sectional structure as the semiconductor device 101, except that a group of raised portions 316 is formed on the second main surface 104 of the SiC semiconductor layer 102.

[0591] Referring to Figure 40, the group of raised portions 316 (multiple raised portions 315) and the groove 321 are formed in the SiC semiconductor substrate 111. A modified layer 323 is formed on the surface of the second main surface 104 of the SiC semiconductor layer 102 (SiC semiconductor substrate 111), in which a portion of the SiC has been modified to other properties. The modified layer 323 is formed by an annealing treatment method on the second main surface 104 of the SiC semiconductor layer 102.

[0592] The modified layer 323 contains Si atoms and C atoms. More specifically, the modified layer 323 has a lower carbon density in the SiC semiconductor layer 102 (SiC semiconductor substrate 111) than in the region outside the modified layer 323.

[0593] Furthermore, the modified layer 323 has a silicon density higher than the carbon density. In other words, the modified layer 323 includes a Si modified layer in which the SiC of the SiC semiconductor layer 102 (SiC semiconductor substrate 111) has been modified to Si. The Si modified layer may also be a Si amorphous layer.

[0594] The modified layer 323 may contain lattice defects resulting from the modification of SiC. In other words, the modified layer 323 may contain lattice defect regions having defect levels introduced as a result of the modification of SiC.

[0595] In this configuration, the modified layer 323 is formed in the region along the raised portion group 316 on the surface of the second main surface 104 of the SiC semiconductor layer 102. As a result, multiple raised portions 315 in each raised portion group 316 are formed by the modified layer 323.

[0596] In this configuration, the modified layer 323 further extends from the raised portion group 316 toward the space 320. In other words, the annealing treatment of the second main surface 104 of the SiC semiconductor layer 102 also extends toward the space 320.

[0597] In the modified layer 323, the thickness of the portion along the raised portion group 316 is greater than or equal to the thickness of the portion along the space 320 due to the presence of the raised portion 315. More specifically, the thickness of the portion along the raised portion group 316 in the modified layer 323 is greater than the thickness of the portion along the space 320 in the modified layer 323.

[0598] The thickness of the modified layer 323 may be between 1 nm and 1000 nm. The thickness Ta of the region of the modified layer 323 that forms the raised portion 315 may be between 50 nm and 1000 nm. The thickness Tb of the region of the modified layer 323 outside the raised portion 315 may be between 1 nm and 300 nm.

[0599] The thickness Ta may be between 50 nm and 100 nm. The thickness Ta may be between 100 nm and 150 nm. The thickness Ta may be between 150 nm and 200 nm. The thickness Ta may be between 200 nm and 250 nm.

[0600] The thickness Ta may be between 250 nm and 300 nm. The thickness Ta may be between 300 nm and 350 nm. The thickness Ta may be between 350 nm and 400 nm. The thickness Ta may be between 400 nm and 450 nm. The thickness Ta may be between 450 nm and 500 nm.

[0601] The thickness Ta may be 500 nm or more and 600 nm or less. The thickness Ta may be 600 nm or more and 700 nm or less. The thickness Ta may be 700 nm or more and 800 nm or less. The thickness Ta may be 800 nm or more and 900 nm or less. The thickness Ta may be 900 nm or more and 1000 nm or less.

[0602] The thickness Tb may be between 1 nm and 10 nm. The thickness Tb may be between 10 nm and 50 nm. The thickness Tb may be between 50 nm and 100 nm.

[0603] The thickness Tb may be between 100 nm and 150 nm. The thickness Tb may be between 150 nm and 200 nm. The thickness Tb may be between 200 nm and 250 nm. The thickness Tb may be between 250 nm and 300 nm.

[0604] The thickness Tb may be 1 / 2, 1 / 3, 1 / 4, 1 / 5, 1 / 6, 1 / 7, 1 / 8, 1 / 9, 1 / 10, 1 / 11, 1 / 12, 1 / 13, 1 / 14, 1 / 15, 1 / 16, 1 / 17, 1 / 18, 1 / 19, or 1 / 20 of the thickness Ta.

[0605] When the raised portion group 316 is not present on the second main surface 104 of the SiC semiconductor layer 102, the resistance value of the second main surface 104 is greater than the resistance value of the second main surface 104 when the raised portion group 316 is present on the second main surface 104 of the SiC semiconductor layer 102.

[0606] In other words, the multiple raised portions 316 have an electrical resistance value that is less than or equal to the resistance value of a single SiC crystal. More specifically, the multiple raised portions 316 have an electrical resistance value that is less than the resistance value of a single SiC crystal.

[0607] Furthermore, the multiple groups of raised sections 316 have a resistance value less than or equal to the resistance value of the space 320. More specifically, the multiple groups of raised sections 316 have a resistance value less than the resistance value of the space 320.

[0608] The resistance of the raised portion group 316 is reduced by the modified layer 323. In other words, the resistance of the raised portion group 316 is less than that of the SiC single crystal due to the modified layer 323, which alters the properties of SiC. Furthermore, the resistance of the space 320 is also reduced by the modified layer 323.

[0609] In this configuration, the drain pad 113 is directly connected to the second main surface 104 of the SiC semiconductor layer 102. The drain pad 113 covers the group of raised portions 316 on the second main surface 104 of the SiC semiconductor layer 102. The drain pad 113 covers multiple groups of raised portions 316 collectively.

[0610] The drain pad 113 is formed in a film-like manner, following the outer surface of the group of raised parts 316 (the outer surfaces of the multiple raised parts 315) and the inner surface of the groove 321. As a result, the portion of the outer surface of the drain pad 113 that covers the group of raised parts 316 (the multiple raised parts 315) has a raised part 113a that is raised in a direction away from the second main surface 104. In addition, the portion of the outer surface of the drain pad 113 that covers the groove 321 has a recess 113b that is recessed toward the second main surface 104.

[0611] The drain pad 113 forms ohmic contact with the second main surface 104 of the SiC semiconductor layer 102. More specifically, the drain pad 113 forms ohmic contact with the raised portion group 316.

[0612] More specifically, the drain pad 113 forms ohmic contact with the group of raised portions 316. In this embodiment, the drain pad 113 also forms ohmic contact with the space 320.

[0613] The drain pad 113 has a laminated structure including a plurality of electrode layers stacked on the second main surface 104 of the SiC semiconductor layer 102. In this embodiment, the drain pad 113 has a four-layer structure including a Ti layer 324, a Ni layer 325, an Au layer 326, and an Ag layer 327, stacked in this order from the second main surface 104 of the SiC semiconductor layer 102.

[0614] The Ti layer 324, Ni layer 325, Au layer 326, and Ag layer 327 are formed in a film-like manner, following the outer surface of the raised portion group 316 (the outer surface of the multiple raised portions 315) and the inner surface of the groove 321, respectively. The raised portion 113a and recess 113b of the drain pad 113 are formed on the outer surface of the Ag layer 327.

[0615] The Ti layer 324 is directly connected to the second main surface 104 of the SiC semiconductor layer 102. The Ti layer 324 covers multiple groups of raised portions 316 collectively and forms ohmic contact with the second main surface 104 of the SiC semiconductor layer 102. In this configuration, the Ti layer 324 also forms ohmic contact with the space 320.

[0616] The Ni layer 325 covers almost or entirely the Ti layer 324. The Au layer 326 covers almost or entirely the Ni layer 325. The Ag layer 327 covers almost or entirely the Au layer 326.

[0617] The thickness of the Ti layer 324 may be between 0.01 μm and 5 μm (for example, about 0.07 μm). The thickness of the Ni layer 325 may be between 0.1 μm and 40 μm (for example, about 1.2 μm).

[0618] The thickness of the Au layer 326 may be between 0.1 μm and 40 μm (for example, about 0.07 μm). The thickness of the Ag layer 327 may be between 0.1 μm and 40 μm (for example, about 0.3 μm). Of course, the drain pad 113 may have a single-layer structure consisting of a Ti layer 324, a Ni layer 325, an Au layer 326, or an Ag layer 327.

[0619] The drain pad 113 forms ohmic contact with the second main surface 104 of the SiC semiconductor layer 102 without the need for a silicide layer whose main component is silicide. The drain pad 113 also forms ohmic contact with each group of raised portions 316 without the need for a silicide layer whose main component is silicide.

[0620] The drain pad 113 forms ohmic contact with the second main surface 104 of the SiC semiconductor layer 102 without the need for a carbon layer, which is primarily composed of carbon. The drain pad 113 also forms ohmic contact with each group of raised portions 316 without the need for a carbon layer, which is primarily composed of carbon.

[0621] The drain pad 113 does not include any region in which a material mainly composed of silicide is formed in layers. Furthermore, the drain pad 113 does not include any region in which a material mainly composed of carbon is formed in layers.

[0622] Figure 41A is a top view showing a SiC semiconductor wafer 331 used in the manufacture of the semiconductor device 311 shown in Figure 34. Figure 41B is a bottom view of the SiC semiconductor wafer 331 shown in Figure 41A, showing the state after grinding and annealing processes on the second wafer main surface 333 of the SiC semiconductor wafer 331.

[0623] Referring to Figures 41A and 41B, the SiC semiconductor wafer 331 is made of a disc-shaped plate-like SiC single crystal. The SiC semiconductor wafer 331 serves as the base for the SiC semiconductor substrate 111.

[0624] The SiC semiconductor wafer 331 has a first wafer main surface 332 on one side, a second wafer main surface 333 on the other side, and a wafer side surface 334 connecting the first wafer main surface 332 and the second wafer main surface 333.

[0625] The SiC semiconductor wafer 331 may contain a 4H-SiC single crystal. The first wafer main surface 332 of the SiC semiconductor wafer 331 has an off-angle that is tilted at an angle of 10° or less with respect to the [11-20] direction from the (0001) plane.

[0626] The off-angle may be between 0° and 4°. The off-angle may be greater than 0° and less than 4°. Typically, the off-angle is set to 2° or 4°, more specifically, within the range of 2°±0.2° or 4°±0.4°.

[0627] One or more (one in this embodiment) orientation flats 335 indicating the crystal orientation are formed on the wafer side surface 334 of the SiC semiconductor wafer 331. The orientation flats 335 are notches formed on the periphery of the SiC semiconductor wafer 331. In this embodiment, the orientation flats 335 extend linearly along the [11-20] direction.

[0628] The first wafer main surface 332 is the device formation surface on which the MISFET is formed. Multiple device formation regions 336 corresponding to the semiconductor device 311 are set on the first wafer main surface 332.

[0629] In this embodiment, the multiple device formation regions 336 are arranged in a matrix along the [11-20] direction ([-1-120] direction) and the [-1100] direction ([1-100] direction).

[0630] The dicing lines 337 are grid-like regions that demarcate multiple device formation regions 336. The semiconductor device 311 is cut out by cutting the SiC semiconductor wafer 331 along the periphery (dicing lines 337) of the multiple device formation regions 336.

[0631] Referring to Figure 41B, after the grinding process and annealing treatment of the second main surface 333 of the SiC semiconductor wafer 331, a plurality of raised areas 316 and a plurality of grinding marks 338 are formed on the second main surface 333 of the SiC semiconductor wafer 331.

[0632] The multiple groups of raised portions 316 are formed in a stripe pattern that is substantially parallel or parallel to the orientation flat 335. The multiple groups of raised portions 316 may also be formed in a stripe pattern that intersects or is perpendicular to the orientation flat 335.

[0633] Each of the multiple grinding marks 338 extends in an arc shape from the center to the periphery of the SiC semiconductor wafer 331. The multiple grinding marks 338 generally include grinding marks 338 that intersect in the [11-20] direction and the [1-100] direction.

[0634] Furthermore, the multiple grinding marks 338 include grinding marks 338 that extend substantially parallel to or parallel to the [11-20] direction or the [1-100] direction in portions where the tangent of the arc is along the [11-20] direction or the [1-100] direction. The groove 321 formed on the second main surface 104 of the SiC semiconductor layer 102 may be formed by a portion of the grinding marks 338.

[0635] Figure 42 is a flowchart illustrating an example of a manufacturing method for the semiconductor device 311 shown in Figure 34. Figures 43A to 43I are cross-sectional views illustrating a manufacturing method for the semiconductor device 311 shown in Figure 34.

[0636] In the method for manufacturing the semiconductor device 311, the processing step for the second wafer main surface 333 is performed prior to the drain pad 113 formation step (see Figure 17L) related to the method for manufacturing the semiconductor device 101. The processing step for the second wafer main surface 333 may be performed after the formation steps for the gate pad 108, gate finger 109, and source pad 110.

[0637] Referring to Figure 43A, first, the processes shown in Figures 17A to 17L are carried out to prepare a SiC semiconductor wafer 331 on which MISFETs are fabricated on the first wafer main surface 332. The second wafer main surface 333 of the SiC semiconductor wafer 331 is in an unprocessed state.

[0638] Next, referring to Figure 43B, the second wafer main surface 333 of the SiC semiconductor wafer 331 is ground (step S1 in Figure 42). In this step, the second wafer main surface 333 of the SiC semiconductor wafer 331 is ground using abrasive grains having a grit size of 500 or higher.

[0639] The abrasive grain size is preferably between 1000 and 5000. This creates multiple grinding marks 338 on the second main surface 333 of the SiC semiconductor wafer 331 (see also Figure 41B). This also flattens the second main surface 333 of the SiC semiconductor wafer 331 and simultaneously thins the SiC semiconductor wafer 331.

[0640] Next, referring to Figure 43C, a metal layer 341 is formed on the second wafer main surface 333 of the SiC semiconductor wafer 331 (step S2 in Figure 42). In this embodiment, the metal layer 341 consists of a Ni layer. The Ni layer may be formed by sputtering. The thickness of the Ni layer may be between 100 Å and 1000 Å.

[0641] Next, referring to Figure 43D, an annealing process is performed on the second wafer main surface 333 of the SiC semiconductor wafer 331 (step S3 in Figure 42). In this step, a laser annealing process is performed as an example of an annealing method.

[0642] In laser annealing, pulsed laser light with a laser diameter φ of 50 μm to 200 μm (for example, around 100 μm) is used. The pulsed laser light is UV laser light with wavelengths in the ultraviolet region. The energy of the pulsed laser light is 1.0 J / cm². 2 More than 4.0J / cm 2 The following (for example, 3.0 J / cm²) 2 (To a certain extent) is also acceptable.

[0643] A pulsed laser beam is injected into the second wafer main surface 333 of the SiC semiconductor wafer 331 via the metal layer 341. In this embodiment, the pulsed laser beam is injected into the second wafer main surface 333 of the SiC semiconductor wafer 331 while moving along the orientation flat 335.

[0644] In the region of the second wafer main surface 333 of the SiC semiconductor wafer 331 into which pulsed laser light is injected, one or more raised portions 315 are formed on the second wafer main surface 333 of the SiC semiconductor wafer 331.

[0645] Furthermore, in the region of the second main surface 333 of the SiC semiconductor wafer 331 where pulsed laser light is injected, a modified layer 323 is formed in which the SiC of the SiC semiconductor wafer 331 is modified to other properties. More specifically, the SiC of the SiC semiconductor wafer 331 is modified to Si by heating, which causes C atoms to be removed from the SiC and / or sublimation.

[0646] This forms a modified layer 323 containing a Si modified layer. The modified layer 323 may also contain a silicon amorphous layer. The modified layer 323 may also contain C atoms. One or more raised portions 315 formed on the second wafer main surface 333 may be formed by this modified layer 323.

[0647] Then, pulsed laser light is continuously injected in the direction along the orientation flat 335, and a plurality of raised portions 315 are formed along the orientation flat 335. As a result, a group of raised portions 316, including the plurality of raised portions 315 and aligned in the [11-20] direction, is formed on the second wafer main surface 333 of the SiC semiconductor wafer 331.

[0648] When one group of raised areas 316 is formed, the irradiation position of the pulsed laser light is moved in the [1-100] direction. Then, the pulsed laser light is again irradiated onto the second wafer main surface 333 of the SiC semiconductor wafer 331, with the irradiation position moved along the orientation flat 335.

[0649] As a result, another group of raised portions 316 extending substantially parallel to or parallel to one group of raised portions 316 is formed on the second wafer main surface 333 of the SiC semiconductor wafer 331.

[0650] In the laser annealing process, this process is repeated until multiple groups of raised areas 316 are formed over almost or entirely the second main surface 333 of the SiC semiconductor wafer 331 (see also Figure 41B).

[0651] In this configuration, the metal layer 341, after undergoing laser annealing, has a laminated structure including a carbon layer 342, a NiSi (nickel silicide) layer 343, and a Ni layer 344, which are stacked in this order from the second wafer main surface 333 side of the SiC semiconductor wafer 331.

[0652] In other words, the laser annealing method includes a step of reacting the metal layer 341 with the SiC semiconductor wafer 331 to form a silicide. More specifically, the laser annealing method includes a step of forming a NiSi layer 343.

[0653] In the laser annealing process, in addition to the NiSi layer 343, a carbon layer 342 containing C atoms is formed as a byproduct within the metal layer 341. The carbon layer 342 is formed by the precipitation of C atoms that made up SiC.

[0654] In the metal layer 341, the carbon layer 342 and the NiSi layer 343 can act as delamination initiation points. In other words, the metal layer 341 can be used as the drain pad 113 as is, but the metal layer 341 has problems with poor connection and increased resistance due to poor connection. Therefore, it is preferable to form a different metal layer as the drain pad 113 from the metal layer 341.

[0655] The temperature applied to the metal layer 341 during the formation of the NiSi layer 343 is above the melting point of the gate pad 108, gate finger 109, and source pad 110 (for example, above 1000°C).

[0656] According to the laser annealing method, the temperature of the second wafer main surface 333 of the SiC semiconductor wafer 331 can be locally increased, thus eliminating the need to heat the gate pad 108, gate finger 109, and source pad 110. Therefore, melting of the gate pad 108, gate finger 109, and source pad 110 can be appropriately suppressed.

[0657] Next, referring to Figure 43E, the metal layer 341 is removed. The metal layer 341 removal process is carried out until the second wafer main surface 333 of the SiC semiconductor wafer 331 is exposed.

[0658] In this process, first, the NiSi layer 343 and Ni layer 344 within the metal layer 341 are removed (step S4 in Figure 42). The NiSi layer 343 and Ni layer 344 may also be removed by wet etching.

[0659] Next, referring to Figure 43F, the carbon layer 342 within the metal layer 341 is removed (step S5 in Figure 42). The carbon layer 342 may also be removed by dry etching.

[0660] Next, referring to Figure 43G, the residues of the NiSi layer 343 and Ni layer 344 adhering to the second wafer main surface 333 of the SiC semiconductor wafer 331 are removed (step S6 in Figure 42). The NiSi layer 343 and Ni layer 344 may also be removed by wet etching.

[0661] Next, referring to Figure 43H, the residue of the carbon layer 342 attached to the second wafer main surface 333 of the SiC semiconductor wafer 331 is removed (step S7 in Figure 42). The carbon layer 342 may also be removed by dry etching.

[0662] Next, the native oxide film is removed from the second wafer main surface 333 of the SiC semiconductor wafer 331 (step S8 in Figure 42). The native oxide film may also be removed by wet etching.

[0663] Thus, in this configuration, the steps of removing the Ni-containing layer (NiSi layer 343 and Ni layer 344) and the carbon-containing layer (carbon layer 342) are repeated twice.

[0664] This allows for the proper removal of the metal layer 341. Furthermore, after the removal of the metal layer 341, the second wafer main surface 333 of the SiC semiconductor wafer 331, whose resistance has been reduced by laser annealing, is properly exposed.

[0665] Next, referring to Figure 43I, the drain pad 113 is formed on the second wafer main surface 333 of the SiC semiconductor wafer 331 (step S9 in Figure 42).

[0666] This process includes forming a Ti layer 324, a Ni layer 325, an Au layer 326, and an Ag layer 327 in that order on the second wafer main surface 333 of the SiC semiconductor wafer 331. The Ti layer 324, Ni layer 325, Au layer 326, and Ag layer 327 may all be formed by sputtering.

[0667] Of the drain pad 113, the Ti layer 324 is directly connected to the second wafer main surface 333 of the SiC semiconductor wafer 331. The Ti layer 324 covers multiple groups of raised portions 316 collectively, forming ohmic contact between the Ti layer and the multiple groups of raised portions 316 and between the Ti layer and the multiple spaces 320.

[0668] Next, the SiC semiconductor wafer 331 is cut along the periphery (dicing line 337) of multiple device formation regions 336. This cuts out multiple semiconductor devices 311 from the SiC semiconductor wafer 331. The semiconductor device 311 is manufactured through the process including the above.

[0669] As described above, the semiconductor device 311 can achieve the same effects as those described for the semiconductor device 101. Furthermore, the semiconductor device 311 can increase the connection area of ​​the drain pad 113 to the second main surface 104 of the SiC semiconductor layer 102 by the raised portion group 316. This improves the electrical characteristics.

[0670] More specifically, the drain pad 113 forms ohmic contact with the raised portion group 316. This allows for good ohmic characteristics between the SiC semiconductor layer 102 and the drain pad 113, thereby improving electrical characteristics.

[0671] Furthermore, according to the semiconductor device 311, the drain pad 113 is directly connected to the second main surface 104 of the SiC semiconductor layer 102. More specifically, the drain pad 113 forms ohmic contact with the raised portion group 316 without the presence of a carbon layer.

[0672] Carbon layers and silicide layers are prone to delamination. Therefore, the structure in which the drain pad 113 is directly connected to the second main surface 104 of the SiC semiconductor layer 102 can appropriately suppress connection failures and the increase in resistance values ​​caused by such connection failures.

[0673] Figure 44 is a bottom view corresponding to Figure 35, and is a bottom view showing a semiconductor device 351 according to the 23rd embodiment of the present invention. In the following, structures corresponding to the structures described for semiconductor device 311 are given the same reference numerals and their descriptions are omitted.

[0674] Referring to Figure 44, the semiconductor device 351 has a plurality of raised portion groups 316, including a first raised portion group 316A and a second raised portion group 316B.

[0675] The first group of raised portions 316A includes a plurality of first raised portions 315A formed on the second main surface 104 of the SiC semiconductor layer 102. The plurality of first raised portions 315A are portions that are raised along the direction normal to the second main surface 104 of the SiC semiconductor layer 102.

[0676] Multiple first raised portions 315A are formed spaced apart from each other along a first direction X and a second direction Y intersecting the first direction X. Some of the multiple first raised portions 315A have a first portion 317A that overlaps with the first direction X in a first view from the first direction X.

[0677] Furthermore, the first raised portion 315A is formed such that some of the first raised portions 315A are spaced apart from the first portion 317A, and it has a second portion 318A that overlaps with the first direction X when viewed in the first direction.

[0678] Multiple first raised portions 315A are formed continuously along a first direction X. More specifically, the multiple first raised portions 315A have a dotted pattern that is spaced apart along the first direction X and the second direction Y.

[0679] The multiple first raised portions 315A are formed continuously along the first direction X while maintaining this dotted pattern. In this configuration, the dotted pattern of the multiple first raised portions 315A is formed in a plan view from the periphery of one side surface 105A to the periphery of the other side surface 105C of the SiC semiconductor layer 102.

[0680] The first group of raised sections 316A has a layout in which multiple raised sections 315 overlap in the first direction X when viewed from the first direction X. As a result, the first group of raised sections 316A forms a first raised section region 319A that extends in a band shape along the first direction X, formed by a collection pattern of multiple raised sections 315 that are continuously scattered along the first direction X.

[0681] In other words, the first raised portion group region 319A includes a plurality of first raised portions 315A (first raised portion group 316A) formed in a band-shaped region extending along the first direction X on the second main surface 104 of the SiC semiconductor layer 102.

[0682] The second group of raised portions 316B includes a plurality of second raised portions 315B formed on the second main surface 104 of the SiC semiconductor layer 102. The plurality of second raised portions 315B are portions that are raised along the direction normal to the second main surface 104 of the SiC semiconductor layer 102.

[0683] Multiple second raised portions 315B are formed spaced apart from each other along a first direction X and a second direction Y that intersects the first direction X. The group of second raised portions 316B has a first portion 317B in which some of the multiple second raised portions 315B overlap with the second direction Y in a second-direction view as seen from the second direction Y.

[0684] Furthermore, the second raised portion group 316B is formed such that some of the second raised portions 315B are spaced apart from the first portion 317B, and it also has a second portion 318B that overlaps with the second direction Y in a second view.

[0685] Multiple second raised portions 315B are formed continuously along the second direction Y. More specifically, the multiple second raised portions 315B have a dotted pattern that is spaced apart along the first direction X and the second direction Y.

[0686] The multiple second raised portions 315B are formed continuously along the second direction Y while maintaining this dotted pattern. In this configuration, the dotted pattern of the multiple second raised portions 315B is formed in a plan view from the periphery of one side surface 105B to the periphery of the other side surface 105D of the SiC semiconductor layer 102.

[0687] The second raised portion group 316B has a layout in which multiple second raised portions 315B overlap in the second direction Y when viewed from the second direction Y. As a result, the second raised portion group 316B forms a second raised portion region 319B that extends in a band shape along the second direction Y, formed by a collection pattern of multiple second raised portions 315B that are continuously scattered along the second direction Y.

[0688] In other words, the second raised portion group region 319B includes a plurality of second raised portions 315B (second raised portion group 316B) formed in a band-shaped region extending along the second direction Y on the second main surface 104 of the SiC semiconductor layer 102.

[0689] The second raised portion group 316B (second raised portion group region 319B) crosses the first raised portion group 316A (first raised portion group region 319A). As a result, an intersection region 352 is formed on the second main surface 104 of the SiC semiconductor layer 102 where the first raised portion group 316A (first raised portion group region 319A) and the second raised portion group 316B (second raised portion group region 319B) intersect each other.

[0690] In this configuration, multiple first raised portions 316A are formed at intervals along the second direction Y on the second main surface 104 of the SiC semiconductor layer 102. In other words, the dotted pattern of multiple first raised portions 315A is formed intermittently with respect to the second direction Y.

[0691] Furthermore, in this configuration, multiple second raised portions 316B are formed at intervals along the first direction X on the second main surface 104 of the SiC semiconductor layer 102. In other words, the dotted pattern of multiple second raised portions 315B is formed intermittently with respect to the first direction X.

[0692] Therefore, in this configuration, the intersecting region 352 is formed in a matrix-like arrangement with spacing between them along the first direction X and the second direction Y. Furthermore, the space 320 is partitioned by the first raised portion group 316A and the second raised portion group 316B. The space 320 is formed in a matrix-like arrangement with spacing between them along the first direction X and the second direction Y.

[0693] In the intersection region 352, the multiple first raised portions 315A and the multiple second raised portions 315B may overlap each other. The thickness of the multiple first raised portions 315A and the multiple second raised portions 315B formed in the intersection region 352 may be greater than the thickness of the first raised portions 315A and the second raised portions 315B formed in the region outside the intersection region 352.

[0694] Furthermore, the number of first raised portions 315A and second raised portions 315B formed in the intersection region 352 may be greater than the number of first raised portions 315A and second raised portions 315B formed in the region outside the intersection region 352.

[0695] The first direction X may be set in the [11-20] direction, and the second direction Y may be set in the [1-100] direction. In other words, the first raised section group 316A (first raised section group region 319A) may be formed substantially parallel or parallel to the [11-20] direction, and the second raised section group 316B (second raised section group region 319B) may be formed substantially parallel or parallel to the [1-100] direction.

[0696] The first direction X may be set in the [1-100] direction, and the second direction Y may be set in the [11-20] direction. In other words, the first raised section group 316A (first raised section group region 319A) may be formed substantially parallel or parallel to the [1-100] direction, and the second raised section group 316B (second raised section group region 319B) may be formed substantially parallel or parallel to the [11-20] direction.

[0697] The first raised portion 315A and the first group of raised portions 316A correspond to the raised portion 315 and the group of raised portions 316 according to the 22nd embodiment. The description of the raised portion 315 and the group of raised portions 316 according to the 22nd embodiment shall be applied mutatis mutandis to the description of the first raised portion 315A and the first group of raised portions 316A, and other specific descriptions of the first raised portion 315A and the first group of raised portions 316A shall be omitted.

[0698] The second raised portion 315B and the second raised portion group 316B correspond to the raised portion 315 and the raised portion group 316 according to the 22nd embodiment. The description of the raised portion 315 and the raised portion group 316 according to the 22nd embodiment shall be applied mutatis mutandis to the other description of the second raised portion 315B and the second raised portion group 316B, and other specific descriptions of the second raised portion 315B and the second raised portion group 316B shall be omitted.

[0699] In this embodiment, the drain pad 113 covers the first group of raised portions 316A and the second group of raised portions 316B on the second main surface 104 of the SiC semiconductor layer 102. In this embodiment, the drain pad 113 covers multiple first group of raised portions 316A and multiple second group of raised portions 316B collectively.

[0700] The drain pad 113 is formed in a film-like manner, following the outer surface of the first raised portion group 316A (outer surface of the first raised portion 315A), the outer surface of the second raised portion group 316B (outer surface of the second raised portion 315B), and the inner surface of the groove 321.

[0701] As a result, although not shown in the diagram, a raised portion 113a is formed on the outer surface of the drain pad 113 in the portion that covers the first raised portion group 316A (first raised portion 315A) and the second raised portion group 316B (second raised portion 315B). In addition, a recess 113b is formed on the outer surface of the drain pad 113 in the portion that covers the groove 321.

[0702] The drain pad 113 forms ohmic contact with the second main surface 104 of the SiC semiconductor layer 102. More specifically, the drain pad 113 forms ohmic contact with the first raised portion group 316A and the second raised portion group 316B.

[0703] More specifically, the drain pad 113 forms ohmic contact with a plurality of first raised portion groups 316A and a plurality of second raised portion groups 316B. In this embodiment, the drain pad 113 also forms ohmic contact with the space 320.

[0704] The portion of the drain pad 113 that covers the first group of raised parts 316A and the second group of raised parts 316B engages with the uneven portion demarcated by the multiple first group of raised parts 316A, the multiple second group of raised parts 316B, and the multiple grooves 321.

[0705] In other words, the contact area of ​​the drain pad 113 with respect to the second main surface 104 of the SiC semiconductor layer 102 is increased by the multiple first raised portion groups 316A, multiple second raised portion groups 316B, and multiple grooves 321. This increases the adhesion force of the drain pad 113 to the second main surface 104 of the SiC semiconductor layer 102.

[0706] A semiconductor device 351 with such a structure is manufactured by performing the following steps in the laser annealing process (step S3 in Figure 42) described above.

[0707] First, a plurality of first raised areas 316A are formed along a direction substantially parallel or parallel to the orientation flat 335 by a laser annealing process. Next, a plurality of second raised areas 316B are formed along a direction intersecting (orthogonal to) the orientation flat 335 by a laser annealing process.

[0708] In this process, multiple first groups of raised portions 316A are formed in a direction intersecting (orthogonal to) the orientation flat 335, and multiple second groups of raised portions 316B may be formed substantially parallel to or parallel to the orientation flat 335. Subsequently, the semiconductor device 351 is manufactured through steps S4 to S9 shown in Figure 42.

[0709] The first raised section group 316A and the second raised section group 316B may be formed in any order. Therefore, multiple first raised section groups 316A may be formed after multiple second raised section groups 316B have been formed. Furthermore, multiple first raised section groups 316A and multiple second raised section groups 316B may be formed alternately.

[0710] As described above, the semiconductor device 351 can achieve the same effects as those described for the semiconductor device 311.

[0711] Figure 45 is a cross-sectional view corresponding to Figure 39, showing a semiconductor device 361 according to the 24th embodiment of the present invention. Figure 46 is an enlarged view of region XLVI shown in Figure 45. Hereafter, structures corresponding to the structures described for semiconductor device 311 are given the same reference numerals and their descriptions are omitted.

[0712] In the semiconductor device 361, the drain pad 113 has a three-layer structure including a Ni layer 325, an Au layer 326, and an Ag layer 327, which are stacked in this order from the second main surface 104 of the SiC semiconductor layer 102. In other words, the drain pad 113 is formed by omitting the formation step of the Ti layer 324 in step S9 of Figure 42.

[0713] The Ni layer 325 is directly connected to the second main surface 104 of the SiC semiconductor layer 102. The Ni layer 325 covers multiple groups of raised areas 316 collectively.

[0714] The Ni layer 325 forms ohmic contact with the raised portion group 316 and with the space 320. The Au layer 326 covers almost or entirely the Ni layer 325. The Ag layer 327 covers almost or entirely the Au layer 326.

[0715] As described above, the semiconductor device 361 can also produce the same effects as those described for the semiconductor device 311. In the semiconductor device 361, the drain pad 113 may have a single-layer structure made of a Ni layer 325.

[0716] Figure 47 is a cross-sectional view corresponding to Figure 39, showing a semiconductor device 371 according to the 25th embodiment of the present invention. Figure 48 is an enlarged view of region XLVIII shown in Figure 47. Hereafter, structures corresponding to the structures described for semiconductor device 311 are given the same reference numerals and their descriptions are omitted.

[0717] In the semiconductor device 371, the drain pad 113 includes a metal layer 341, an Au layer 326, and an Ag layer 327. In this embodiment, the metal layer 341 has a laminated structure including a carbon layer 342, a NiSi layer 343, and a Ni layer 344, which are stacked in this order from the second main surface 104 side of the SiC semiconductor layer 102.

[0718] The metal layer 341 is connected to the second main surface 104 of the SiC semiconductor layer 102. The metal layer 341 covers multiple groups of raised portions 316 collectively.

[0719] The metal layer 341 forms ohmic contact with the raised portion group 316 and with the space 320. The Au layer 326 covers almost or entirely the entire area of ​​the metal layer 341. The Ag layer 327 covers almost or entirely the entire area of ​​the Au layer 326.

[0720] The semiconductor device 371 is formed by omitting the step of removing the metal layer 341 (see steps S4 to S8 shown in Figure 42) as shown in Figure 42. In the semiconductor device 371, in step S9 of Figure 42, the Au layer 326 and the Ag layer 327 are formed on the metal layer 341.

[0721] As described above, according to semiconductor device 371, the drain pad 113 includes a carbon layer 342 and a NiSi layer 343. Although semiconductor device 371 cannot increase the connection strength of the drain pad 113 to the same extent as semiconductor device 311, it can achieve almost the same effects as those described for semiconductor device 311. In semiconductor device 371, the drain pad 113 may consist only of a metal layer 341.

[0722] Although the 22nd to 25th embodiments of the present invention have been described above, the 22nd to 25th embodiments of the present invention can be implemented in other forms as well.

[0723] In the aforementioned 22nd to 25th embodiments, examples were described in which the SiC semiconductor layer 102 has a stacked structure including a SiC semiconductor substrate 111 and a SiC epitaxial layer 112.

[0724] However, the SiC semiconductor layer 102 may have a single-layer structure made of the SiC semiconductor substrate 111. The SiC semiconductor layer 102 may have a single-layer structure made of the SiC epitaxial layer 112.

[0725] In the aforementioned 22nd to 25th embodiments, an example was described in which a SiC epitaxial layer 112 having a high-concentration region 112a and a low-concentration region 112b is formed by an epitaxial growth method. However, the SiC epitaxial layer 112 can also be formed by the following process.

[0726] First, a SiC epitaxial layer 112 with a relatively low n-type impurity concentration is formed by epitaxial growth. Next, n-type impurities are introduced into the surface layer of the SiC epitaxial layer 112 by ion implantation. This forms a SiC epitaxial layer 112 having a high-concentration region 112a and a low-concentration region 112b.

[0727] In the aforementioned 22nd to 25th embodiments, examples were described in which a gate electrode layer 132 and a gate wiring layer 133 containing p-type polysilicon doped with p-type impurities were formed. However, if the increase in gate threshold voltage Vth is not a concern, the gate electrode layer 132 and gate wiring layer 133 may contain n-type polysilicon doped with n-type impurities instead of p-type polysilicon.

[0728] In other words, the low-resistance electrode layer 134 may contain n-type polysilicon. The low-resistance electrode layer 134 may be formed by silicideizing the portion that forms the surface layer of the gate electrode layer 132 (n-type polysilicon) with a metallic material. In this case, the gate resistance can be reduced.

[0729] In the aforementioned 22nd to 25th embodiments, a structure in which the conductivity type of each semiconductor portion is reversed may be adopted. That is, the p-type portion may be made n-type, and the n-type portion may be made p-type.

[0730] In the aforementioned 22nd to 25th embodiments, n + Instead of the type SiC semiconductor substrate 111, p + A SiC semiconductor substrate (111) of type 111 may be used. In this case, the descriptions of the 22nd to 25th embodiments above should be read as "emitter" instead of "source" and "collector" instead of "drain".

[0731] Figure 49 is a top view showing a semiconductor device 401 according to the 26th embodiment of the present invention. Figure 50 is a top view showing the semiconductor device 401 shown in Figure 49, with the resin layer 416 removed.

[0732] Referring to Figures 49 and 50, the semiconductor device 401 has a SiC semiconductor layer 402 containing a SiC (silicon carbide) single crystal. The SiC semiconductor layer 402 may also contain a 4H-SiC single crystal.

[0733] A 4H-SiC single crystal has an off-angle that is tilted at an angle of 10° or less with respect to the [11-20] direction from the

[0001] plane. The off-angle may be between 0° and 4°. The off-angle may be greater than 0° and less than 4°. Typically, the off-angle is set to 2° or 4°, more specifically in the range of 2°±0.2° or 4°±0.4°.

[0734] In this embodiment, the SiC semiconductor layer 402 is formed in the shape of a rectangular parallelepiped chip. The SiC semiconductor layer 402 has a first main surface 403 on one side, a second main surface 404 on the other side, and sides 405A, 405B, 405C, and 405D connecting the first main surface 403 and the second main surface 404. The first main surface 403 and the second main surface 404 are formed in a quadrilateral shape (rectangular in this embodiment) when viewed from the direction of their normals in a plan view (hereinafter simply referred to as "plan view").

[0735] Side 405A faces side 405C. Side 405B faces side 405D. Sides 405A to 405D extend planarly along the normal directions of the first main surface 403 and the second main surface 404, respectively. The lengths of sides 405A to 405D may be between 1 mm and 10 mm (for example, between 2 mm and 5 mm).

[0736] The SiC semiconductor layer 402 has an active region 406 and an outer region 407. The active region 406 is the region where the vertical MISFET is formed. The outer region 407 is the region outside the active region 406.

[0737] The active region 406 is located in the center of the SiC semiconductor layer 402, with a gap in the inward region from the sides 405A to 405D of the SiC semiconductor layer 402 in a plan view. The active region 406 is set in a quadrilateral shape (rectangular in this form) with four sides parallel to the sides 405A to 405D of the SiC semiconductor layer 402 in a plan view.

[0738] The outer region 407 is defined as the region between the side surfaces 405A to 405D of the SiC semiconductor layer 402 and the periphery of the active region 406. In a plan view, the outer region 407 is defined as an endless (quadrilateral ring) shape surrounding the active region 406.

[0739] A main surface gate electrode 408 and a main surface source electrode 409 are formed on the first main surface 403 of the SiC semiconductor layer 402.

[0740] The main surface gate electrode 408 includes a gate pad 410 and a gate finger 411. In this embodiment, the gate pad 410 and the gate finger 411 are located in the active region 406.

[0741] The gate pad 410 is formed along the side surface 405A of the SiC semiconductor layer 402 in a plan view. The gate pad 410 is formed along the central region of the side surface 405A of the SiC semiconductor layer 402 in a plan view.

[0742] The gate pad 410 may be formed along the corner connecting any two of the sides 405A to 405D of the SiC semiconductor layer 402 in a plan view. The gate pad 410 is formed in a square shape in a plan view.

[0743] The gate finger 411 includes an outer gate finger 411A and an inner gate finger 411B.

[0744] The outer gate finger 411A extends from the gate pad 410 and is band-shaped along the periphery of the active region 406. In this embodiment, the outer gate finger 411A is formed along the three sides 405A, 405B, and 405D of the SiC semiconductor layer 402 so as to partition the inner region of the active region 406 from three directions.

[0745] The outer gate finger 411A has a pair of open ends 412A and 412B. The pair of open ends 412A and 412B of the outer gate finger 411A are formed in the region facing the gate pad 410, with the inner region of the active region 406 in between. In this embodiment, the pair of open ends 412A and 412B of the outer gate finger 411A are formed along the side surface 405C of the SiC semiconductor layer 402.

[0746] The inner gate finger 411B is drawn out from the gate pad 410 into the inner region of the active region 406. The inner gate finger 411B extends in a band shape into the inner region of the active region 406. The inner gate finger 411B extends from side 405A to side 405C.

[0747] In this embodiment, the main surface source electrode 409 includes a source pad 413, source routing wiring 414, and a source connection portion 415.

[0748] The source pad 413 is formed in the active region 406, spaced apart from the gate pad 410 and gate finger 411. The source pad 413 is formed in a C-shape (inverted C-shape in Figures 49 and 50) in plan view so as to cover the C-shaped region (inverted C-shape in Figures 49 and 50) demarcated by the gate pad 410 and gate finger 411.

[0749] The source routing 414 is formed in the outer region 407. The source routing 414 extends in a strip shape along the active region 406. In this configuration, the source routing 414 is formed in an endless (square ring) shape surrounding the active region 406 in a plan view. The source routing 414 is electrically connected to the SiC semiconductor layer 402 in the outer region 407.

[0750] The source connection section 415 connects the source pad 413 and the source routing wiring 414. The source connection section 415 is located in the region between the pair of open ends 412A and 412B of the outer gate finger 411A. The source connection section 415 extends from the source pad 413 across the boundary region between the active region 406 and the outer region 407 and connects to the source routing wiring 414.

[0751] The MISFET formed in the active region 406 contains, by its structure, an npn-type parasitic bipolar transistor. When an avalanche current generated in the outer region 407 flows into the active region 406, the parasitic bipolar transistor turns on. In this case, the control of the MISFET may become unstable, for example, due to latch-up.

[0752] Therefore, the semiconductor device 401 utilizes the structure of the main surface source electrode 409 to form an avalanche current absorption structure that absorbs avalanche current generated in the region outside the active region 406.

[0753] More specifically, the source routing 414 absorbs the avalanche current generated in the outer region 407. As a result, the avalanche current reaches the source pad 413 via the source connection 415. If an external connection wire (e.g., bonding wire) is connected to the source pad 413, the avalanche current is drawn out by this wire.

[0754] This prevents the parasitic bipolar transistor from being turned on by unwanted currents generated in the outer region 407. Therefore, latch-up can be suppressed, and the control stability of the MISFET can be improved.

[0755] A gate voltage is applied to the gate pad 410 and gate finger 411. The gate voltage may be between 10V and 50V (for example, around 30V). A source voltage is applied to the source pad 413. The source voltage may be a reference voltage (for example, GND voltage).

[0756] A resin layer 416 is formed on the first main surface 403 of the SiC semiconductor layer 402 (more specifically, on the interlayer insulating layer 491, which will be described later). In Figure 49, the resin layer 416 is shown by hatching for clarity. The resin layer 416 covers the gate pad 410, gate finger 411, and source pad 413.

[0757] The resin layer 416 may contain a negative-type or positive-type photosensitive resin. In this embodiment, the resin layer 416 contains polybenzoxazole as an example of a positive-type photosensitive resin. The resin layer 416 may also contain polyimide as an example of a negative-type photosensitive resin.

[0758] The resin layer 416 has a gate pad opening 417 and a source pad opening 418 formed therein. The gate pad opening 417 exposes the gate pad 410. The source pad opening 418 exposes the source pad 413.

[0759] The peripheral edge 419 of the resin layer 416 is formed with a gap in the inward region from the side surfaces 405A to 405D of the SiC semiconductor layer 402. As a result, the resin layer 416 exposes the peripheral edge of the SiC semiconductor layer 402 (more specifically, the interlayer insulating layer 491, which will be described later).

[0760] The peripheral edge 419 of the resin layer 416 is the portion that formed the dicing street when cutting the semiconductor device 401 from a single SiC semiconductor wafer. By exposing the peripheral edge of the SiC semiconductor layer 402 from the resin layer 416, it becomes unnecessary to physically cut the resin layer 416.

[0761] Therefore, the semiconductor device 401 can be smoothly cut from a single SiC semiconductor wafer. The sides 405A to 405D of the SiC semiconductor layer 402 may be cut surfaces (ground surfaces). The sides 405A to 405D of the SiC semiconductor layer 402 may have grinding marks.

[0762] Figure 51 is an enlarged view of region LI shown in Figure 50, illustrating the structure of the first main surface 403 of the SiC semiconductor layer 402. Figure 52 is a cross-sectional view along the LII-LII line shown in Figure 51, showing a first embodiment of the gate trench 431 and a first embodiment of the source trench 441. Figure 53 is a cross-sectional view along the LIII-LIII line shown in Figure 51, showing a first embodiment of the gate wiring layer 436. Figure 54 is an enlarged view of region LIV shown in Figure 52.

[0763] Figure 55 is a cross-sectional view along the LV-LV line shown in Figure 50, showing a first embodiment of the active sidewall 464, a first embodiment of the outer main surface 462, a first embodiment of the sidewall 482, a first embodiment of the diode region 471, a first embodiment of the outer deep well region 472, a first embodiment of the field limit structure 473, and a first embodiment of the anchor hole 495. Figure 56 is an enlarged view of region LVI shown in Figure 55, showing a first embodiment of the active sidewall 464 and a first embodiment of the outer main surface 462.

[0764] Referring to Figures 51 to 55, the SiC semiconductor layer 402 in this configuration is n + It has a stacked structure including an n-type SiC semiconductor substrate 421 and an n-type SiC epitaxial layer 422. The second main surface 404 of the SiC semiconductor layer 402 is formed by the SiC semiconductor substrate 421.

[0765] The first main surface 403 of the SiC semiconductor layer 402 is formed by the SiC epitaxial layer 422. The second main surface 404 of the SiC semiconductor layer 402 may be a ground surface. The second main surface 404 of the SiC semiconductor layer 402 may have grinding marks.

[0766] The thickness of the SiC semiconductor substrate 421 may be 1 μm or more and less than 1000 μm. The thickness of the SiC semiconductor substrate 421 may be 5 μm or more. The thickness of the SiC semiconductor substrate 421 may be 25 μm or more. The thickness of the SiC semiconductor substrate 421 may be 50 μm or more. The thickness of the SiC semiconductor substrate 421 may be 100 μm or more.

[0767] The thickness of the SiC semiconductor substrate 421 may be 700 μm or less. The thickness of the SiC semiconductor substrate 421 may be 500 μm or less. The thickness of the SiC semiconductor substrate 421 may be 400 μm or more. The thickness of the SiC semiconductor substrate 421 may be 300 μm or less.

[0768] The thickness of the SiC semiconductor substrate 421 may be 250 μm or less. The thickness of the SiC semiconductor substrate 421 may be 200 μm or less. The thickness of the SiC semiconductor substrate 421 may be 150 μm or less. The thickness of the SiC semiconductor substrate 421 may be 100 μm or less.

[0769] The thickness of the SiC semiconductor substrate 421 is preferably 150 μm or less. By reducing the thickness of the SiC semiconductor substrate 421, the resistance can be reduced by shortening the current path.

[0770] The thickness of the SiC epitaxial layer 422 may be 1 μm or more and 100 μm or less. The thickness of the SiC epitaxial layer 422 may be 5 μm or more. The thickness of the SiC epitaxial layer 422 may be 10 μm or more.

[0771] The thickness of the SiC epitaxial layer 422 may be 50 μm or less. The thickness of the SiC epitaxial layer 422 may be 40 μm or less. The thickness of the SiC epitaxial layer 422 may be 30 μm or less.

[0772] The thickness of the SiC epitaxial layer 422 may be 20 μm or less. Preferably, the thickness of the SiC epitaxial layer 422 is 15 μm or less. Preferably, the thickness of the SiC epitaxial layer 422 is 10 μm or less.

[0773] The n-type impurity concentration in the SiC epitaxial layer 422 is less than or equal to the n-type impurity concentration in the SiC semiconductor substrate 421. The n-type impurity concentration in the SiC epitaxial layer 6 is 1.0 × 10⁻⁶. 15 cm -3 The above 1.0 × 10 18 cm -3 The following is also acceptable.

[0774] In this embodiment, the SiC epitaxial layer 422 has multiple regions having different n-type impurity concentrations along the direction normal to the first main surface 403 of the SiC semiconductor layer 402. More specifically, the SiC epitaxial layer 422 includes a high-concentration region 422a with a relatively high n-type impurity concentration, and a low-concentration region 422b with a lower n-type impurity concentration than the high-concentration region 422a.

[0775] The high-concentration region 422a is formed in the region on the first main surface 403 side. The low-concentration region 422b is formed in the region on the second main surface 404 side of the SiC semiconductor layer 402 relative to the high-concentration region 422a.

[0776] The n-type impurity concentration in the high-concentration region 422a is 1 × 10⁻⁶ 16 cm -3 The above 1 x 10 18 cm -3 The following may also apply: The n-type impurity concentration in the low-concentration region 422b is 1 × 10⁻⁶. 15 cm -3 The above 1 x 10 16 cm -3 The following is also acceptable.

[0777] The thickness of the high-concentration region 422a is less than or equal to the thickness of the low-concentration region 422b. More specifically, the thickness of the high-concentration region 422a is less than the thickness of the low-concentration region 422b. In other words, the thickness of the high-concentration region 422a is less than half the total thickness of the SiC epitaxial layer 422.

[0778] A drain pad 423, serving as a second main surface electrode, is connected to the second main surface 404 of the SiC semiconductor layer 402. The maximum voltage that can be applied between the source pad 413 and the drain pad 423 when the device is off may be between 1000V and 10000V.

[0779] The drain pad 423 may include at least one of a Ti layer, a Ni layer, an Au layer, or an Ag layer. The drain pad 423 may have a four-layer structure including a Ti layer, a Ni layer, an Au layer, and an Ag layer stacked in this order from the second main surface 404 of the SiC semiconductor layer 402.

[0780] The SiC semiconductor substrate 421 is formed as the drain region 424 of the MISFET. The SiC epitaxial layer 422 is formed as the drift region 425 of the MISFET.

[0781] In the active region 406, a p-type body region 426 is formed on the surface of the first main surface 403 of the SiC semiconductor layer 402. The body region 426 defines the active region 406.

[0782] In other words, in this configuration, the body region 426 is formed over the entire area of ​​the region that forms the active region 406 on the first main surface 403 of the SiC semiconductor layer 402. The p-type impurity concentration of the body region 426 is 1 × 10⁻⁶ 17 cm -3 The above 1 x 10 20 cm -3 The following is also acceptable.

[0783] In the active region 406, a plurality of gate trenches 431 are formed on the surface of the first main surface 403 of the SiC semiconductor layer 402. The plurality of gate trenches 431 are formed at intervals along an arbitrary first direction X. The plurality of gate trenches 431 are formed in a strip shape extending along a second direction Y that intersects the first direction X.

[0784] The first direction X is more specifically the direction along the sides 405B and 405D of the SiC semiconductor layer 402. The second direction Y is the direction perpendicular to the first direction X. The second direction Y is also the direction along the sides 405A and 405C of the SiC semiconductor layer 402.

[0785] Multiple gate trenches 431 are formed in a striped pattern in a plan view. In this configuration, each gate trench 431 extends in a strip-like manner from one peripheral edge (side surface 405B) to the other peripheral edge (side surface 405D) in the active region 406.

[0786] Each gate trench 431 crosses the intermediate portion between one periphery and the other periphery in the active region 406. One end of each gate trench 431 is located at one periphery in the active region 406. The other end of each gate trench 431 is located at the other periphery in the active region 406.

[0787] The first direction X may be set in the [11-20] direction ([-1-120] direction). In this case, each gate trench 431 may extend along the [11-20] direction. The first direction X may be set in the [-1100] direction ([1-100] direction) perpendicular to the [11-20] direction. In this case, each gate trench 431 may extend along the [-1100] direction ([1-100] direction).

[0788] Each gate trench 431 has a length on the order of millimeters. That is, the length of the gate trench 431 is the length from the end on the connection side of the gate trench 431 and the gate finger 411 to the opposite end in the cross-section shown in Figure 53.

[0789] The length of each gate trench 431 may be 0.5 mm or more. In this embodiment, the length of each gate trench 431 is 1 mm or more and 10 mm or less (for example, 2 mm or more and 5 mm or less). The total length of one or more gate trenches 431 per unit area is 0.5 μm / μm 2 More than 0.75μm / μm 2 The following is also acceptable.

[0790] Each gate trench 431 integrally includes an active trench portion 431a and a contact trench portion 431b. The active trench portion 431a is the portion that aligns with the channel region of the MISFET in the active region 406.

[0791] The contact trench portion 431b is primarily intended to make contact with the gate finger 411 in the gate trench 431. The contact trench portion 431b extends from the active trench portion 431a to the periphery of the active region 406. The contact trench portion 431b is formed in the region directly below the gate finger 411. The amount of extension of the contact trench portion 431b is arbitrary.

[0792] Each gate trench 431 penetrates the body region 426 and reaches the SiC epitaxial layer 422. The bottom wall of each gate trench 431 is located within the SiC epitaxial layer 422.

[0793] The bottom wall of each gate trench 431 is located more specifically in the high-concentration region 422a of the SiC epitaxial layer 422. The bottom wall of the gate trench 431 may be formed parallel to the first main surface 403 of the SiC semiconductor layer 402.

[0794] The sidewalls of the gate trench 431 may extend along the direction normal to the first main surface 403 of the SiC semiconductor layer 402. In other words, the sidewalls of the gate trench 431 may be formed substantially perpendicular to the first main surface 403 of the SiC semiconductor layer 402.

[0795] With respect to the normal direction of the first main surface 403 of the SiC semiconductor layer 402, the depth of the gate trench 431 may be 0.5 μm or more and 3 μm or less (for example, about 1 μm). Preferably, the depth of the gate trench 431 is 0.5 μm or more and 1.0 μm or less.

[0796] The first directional width of the gate trench 431 may be 0.1 μm or more and 2 μm or less (for example, about 0.5 μm). Preferably, the first directional width of the gate trench 431 is 0.1 μm or more and 0.5 μm or less.

[0797] Referring to Figure 54, each gate trench 431 opening edge 432 includes an inclined portion 433 that slopes downward from the first main surface 403 of the SiC semiconductor layer 402 toward the inside of the gate trench 431. The opening edge 432 of the gate trench 431 is a corner connecting the first main surface 403 of the SiC semiconductor layer 402 and the side wall of the gate trench 431.

[0798] In this configuration, the inclined portion 433 is formed in a concave curve that curves inward toward the SiC semiconductor layer 402. The inclined portion 433 may also be formed in a convex curve that curves inward toward the gate trench 431.

[0799] The electric field on the opening edge 432 of the gate trench 431 is dispersed along the inclined portion 433. This reduces the concentration of the electric field on the opening edge 432 of the gate trench 431.

[0800] A gate insulating layer 434 and a gate electrode layer 435 are formed within each gate trench 431. In Figure 51, the gate insulating layer 434 and the gate electrode layer 435 are shown by hatching for clarity.

[0801] The gate insulating layer 434 contains silicon oxide. The gate insulating layer 434 may also contain other insulating films such as silicon nitride. The gate insulating layer 434 is formed in a film-like manner along the inner wall surface of the gate trench 431 such that a concave space is partitioned within the gate trench 431.

[0802] The gate insulating layer 434 includes a first region 434a, a second region 434b, and a third region 434c. The first region 434a is formed along the side wall of the gate trench 431. The second region 434b is formed along the bottom wall of the gate trench 431. The third region 434c is formed along the first main surface 403 of the SiC semiconductor layer 402.

[0803] The thickness T1 of the first region 434a is smaller than the thickness T2 of the second region 434b and the thickness T3 of the third region 434c. The ratio T2 / T1 of the thickness T1 of the first region 434a to the thickness T2 of the second region 434b may be between 2 and 5. The ratio T3 / T1 of the thickness T1 of the first region 434a to the thickness T3 of the third region 434c may be between 2 and 5.

[0804] The thickness T1 of the first region 434a may be between 0.01 μm and 0.2 μm. The thickness T2 of the second region 434b may be between 0.05 μm and 0.5 μm. The thickness T3 of the third region 434c may be between 0.05 μm and 0.5 μm.

[0805] By forming a thin first region 434a of the gate insulating layer 434, the increase in carriers induced in the region near the side wall of the gate trench 431 in the body region 426 can be suppressed. This suppresses the increase in channel resistance. By forming a thick second region 434b of the gate insulating layer 434, the electric field concentration against the bottom wall of the gate trench 431 can be mitigated.

[0806] By forming a thicker third region 434c of the gate insulating layer 434, the breakdown voltage of the gate insulating layer 434 near the opening edge portion 432 of the gate trench 431 can be improved. Furthermore, by forming a thicker third region 434c, the disappearance of the third region 434c by the etching method can be suppressed.

[0807] This prevents the first region 434a from being removed by etching due to the disappearance of the third region 434c. As a result, the gate electrode layer 435 can be properly positioned opposite the SiC semiconductor layer 402 (body region 426) with the gate insulating layer 434 in between.

[0808] The gate insulating layer 434 further includes a bulge 434d that bulges inward into the gate trench 431 at the opening edge 432 of the gate trench 431. The bulge 434d is formed at the corner connecting the first region 434a and the third region 434c of the gate insulating layer 434.

[0809] The bulging portion 434d curves inward from the gate trench 431. The bulging portion 434d narrows the opening of the gate trench 431 at the opening edge portion 432 of the gate trench 431.

[0810] The bulging portion 434d improves the dielectric strength of the gate insulating layer 434 at the opening edge portion 432. Of course, a gate insulating layer 434 without the bulging portion 434d may be formed. A gate insulating layer 434 with a uniform thickness may also be formed.

[0811] The gate electrode layer 435 is embedded in the gate trench 431, sandwiched between the gate insulating layer 434. More specifically, the gate electrode layer 435 is embedded in the gate trench 431 so as to fill the concave space partitioned by the gate insulating layer 434. The gate electrode layer 435 is controlled by the gate voltage.

[0812] The gate electrode layer 435 is formed as a wall extending along the normal direction of the first main surface 403 of the SiC semiconductor layer 402 in a cross-sectional view perpendicular to the direction in which the gate trench 431 extends. The gate electrode layer 435 has an upper end located on the opening side of the gate trench 431.

[0813] The upper end of the gate electrode layer 435 is formed in a curved shape that is recessed toward the bottom wall of the gate trench 431. The upper end of the gate electrode layer 435 has a constricted portion that is aligned with the bulge 434d of the gate insulating layer 434.

[0814] The cross-sectional area of ​​the gate electrode layer 435 (the cross-sectional area perpendicular to the direction in which the gate trench 431 extends) is 0.05 μm². 2 Above 0.5 μm 2 The following is also possible: The cross-sectional area of ​​the gate electrode layer 435 is defined as the product of the depth of the gate electrode layer 435 and the width of the gate electrode layer 435.

[0815] The depth of the gate electrode layer 435 is the distance from the upper end to the lower end of the gate electrode layer 435. The width of the gate electrode layer 435 is the width of the trench at an intermediate position between the upper and lower ends of the gate electrode layer 435. If the upper end is curved (in this form, a curved shape that is concave downwards), the position of the upper end of the gate electrode layer 435 is the intermediate position in the depth direction on the upper surface of the gate electrode layer 435.

[0816] The gate electrode layer 435 may contain conductive polysilicon. The gate electrode layer 435 may contain n-type polysilicon or p-type polysilicon as examples of conductive polysilicon. Instead of conductive polysilicon, the gate electrode layer 435 may contain at least one of tungsten, aluminum, copper, aluminum alloy, or copper alloy.

[0817] Referring to Figures 51 and 53, a gate wiring layer 436 is formed in the active region 406. The gate wiring layer 436 is electrically connected to the gate pad 410 and the gate finger 411. In Figure 53, the gate wiring layer 436 is shown by hatching for clarity.

[0818] The gate wiring layer 436 is formed on the first main surface 403 of the SiC semiconductor layer 402. More specifically, the gate wiring layer 436 is formed on the third region 434c of the gate insulating layer 434.

[0819] In this embodiment, the gate wiring layer 436 is formed along the gate finger 411. More specifically, the gate wiring layer 436 is formed along the three sides 405A, 405B, and 405D of the SiC semiconductor layer 402 so as to partition the inner region of the active region 406 from three directions.

[0820] The gate wiring layer 436 is connected to the gate electrode layer 435, which is exposed from the contact trench portion 431b of each gate trench 431. In this embodiment, the gate wiring layer 436 is formed by a lead-out portion that is drawn out from the gate electrode layer 435 onto the first main surface 403 of the SiC semiconductor layer 402. The upper end of the gate wiring layer 436 is connected to the upper end of the gate electrode layer 435.

[0821] Referring to Figures 51, 52, and 54, in the active region 406, a plurality of source trenches (trenches) 441 are formed on the first main surface 403 of the SiC semiconductor layer 402. Each source trench 441 is formed in the region between two adjacent gate trenches 431.

[0822] Each of the multiple source trenches 441 is formed in a strip-like shape extending along the second direction Y. In a plan view, the multiple source trenches 441 are formed in a stripe-like shape. With respect to the first direction X, the pitch between the centers of adjacent source trenches 441 may be 1.5 μm or more and 3 μm or less.

[0823] Each source trench 441 penetrates the body region 426 and reaches the SiC epitaxial layer 422. The bottom wall of each source trench 441 is located within the SiC epitaxial layer 422. More specifically, the bottom wall of each source trench 441 is located in the high-concentration region 422a.

[0824] In this configuration, the depth of the source trench 441 is greater than or equal to the depth of the gate trench 431. More specifically, the depth of the source trench 441 is greater than the depth of the gate trench 431. The bottom wall of the source trench 441 is located on the second main surface 404 side of the SiC semiconductor layer 402 relative to the bottom wall of the gate trench 431.

[0825] The bottom wall of the source trench 441 is located in the region between the bottom wall of the gate trench 431 and the low-concentration region 422b. The bottom wall of the source trench 441 may be formed parallel to the first main surface 403 of the SiC semiconductor layer 402.

[0826] The sidewalls of the source trench 441 may extend along the direction normal to the first main surface 403 of the SiC semiconductor layer 402. In other words, the sidewalls of the source trench 441 may be formed substantially perpendicular to the first main surface 403 of the SiC semiconductor layer 402.

[0827] With respect to the normal direction of the first main surface 403 of the SiC semiconductor layer 402, the depth of the source trench 441 may be 0.5 μm or more and 10 μm or less (for example, about 2 μm). The ratio of the depth of the source trench 441 to the depth of the gate trench 431 may be 1.5 or more. Preferably, the ratio of the depth of the source trench 44...

Claims

1. A SiC semiconductor layer having a main surface on which gate trenches are formed, A gate insulating layer formed along the inner wall of the gate trench, A gate electrode layer made of polysilicon, embedded in the gate trench with the gate insulating layer in between, A semiconductor device comprising a low-resistance electrode layer covering the gate electrode layer, the low-resistance electrode layer comprising a conductive material having a sheet resistance less than the sheet resistance of the gate electrode layer.

2. The semiconductor device according to claim 1, wherein the low-resistance electrode layer covers the gate electrode layer within the gate trench.

3. The semiconductor device according to claim 1 or 2, wherein the length of the gate trench is 1 mm or more and 10 mm or less.

4. In a plan view, the total length of the gate trench per unit area is 0.5 μm / μm ２ 0.75μm / μm or more ２ The semiconductor device according to any one of claims 1 to 3, which is as follows:

5. The gate trenches include a plurality of gate trenches formed at intervals in one direction, and the total length of one or more gate trenches per unit area in a plan view is 0.5 μm / μm ２ 0.75μm / μm or more ２ The semiconductor device according to any one of claims 1 to 4, which is as follows:

6. In a cross-sectional view when the gate trench is cut in a direction perpendicular to the direction in which it extends, the cross-sectional area of ​​the gate electrode layer is 0.05 μm². ２ The above 0.5 μm ２ The semiconductor device according to any one of claims 1 to 5, which is as follows:

7. The semiconductor device according to any one of claims 1 to 6, wherein the thickness of the low-resistance electrode layer is less than or equal to the thickness of the gate electrode layer.

8. The semiconductor device according to any one of claims 1 to 7, wherein the thickness of the low-resistance electrode layer is less than the thickness of the gate electrode layer.

9. The semiconductor device according to any one of claims 1 to 8, wherein the ratio of the thickness of the low-resistance electrode layer to the thickness of the gate electrode layer is 0.01 or more and 1 or less.

10. The semiconductor device according to any one of claims 1 to 9, wherein the thickness of the gate electrode layer is 0.5 μm or more and 3 μm or less.

11. The semiconductor device according to any one of claims 1 to 10, wherein the thickness of the low-resistance electrode layer is 0.01 μm or more and 3 μm or less.

12. The semiconductor device according to any one of claims 1 to 11, wherein the gate electrode layer is made of n-type polysilicon with n-type impurities added, or p-type polysilicon with p-type impurities added.

13. The semiconductor device according to any one of claims 1 to 12, wherein the gate electrode layer is made of p-type polysilicon to which p-type impurities have been added.

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