System and device for a U-shaped vertical electrode and method for manufacturing the same

Abstract

This invention provides a system and device for a U-shaped vertical electrode and a method for manufacturing the same. [Solution] The device of the present invention comprises a first electrode including a first electrode segment, a second electrode segment, and a third electrode segment; a second electrode extending parallel to the first electrode; a first dielectric material disposed between the first electrode and the second electrode; a second dielectric material disposed between the first electrode segment and the third electrode segment; and a third electrode in contact with the first electrode and extending in a direction perpendicular to the first electrode, wherein the first electrode segment is coupled to the second electrode segment, the second electrode segment is coupled to the third electrode segment, and the first electrode segment extends parallel to the third electrode segment.

Description

Technical Field

[0001] The present invention relates to microelectronics and integrated circuit (IC) structures, and more particularly to semiconductor structures including electrodes having a three-dimensional shape.

Background Art

[0002] Semiconductor devices are fabricated using complex three-dimensional structures composed of smaller components. Such components include, for example, circuit components such as transistors and capacitors, which are replicated in large numbers and addressed using a matrix of intersecting lines. However, forming an address matrix is complex, and it is difficult to ensure the formation of conductive lines and / or sufficient insulation between each line. Further, the background concepts described herein are for the sole purpose of providing information and are not intended to limit the present invention, and it should be noted that the described background or field is not intended to limit the disclosure herein to a particular application or concept.

Summary of the Invention

Problems to be Solved by the Invention

[0003] The present invention has been made in view of the above prior art, and an object of the present invention is to provide a system and device for a U-shaped vertical electrode and a method for manufacturing the same.

Means for Solving the Problems

[0004] A device according to one aspect of the present invention made to achieve the above objectives comprises a first electrode including a first electrode segment, a second electrode segment, and a third electrode segment; a second electrode extending parallel to the first electrode; a first dielectric material disposed between the first electrode and the second electrode; a second dielectric material disposed between the first electrode segment and the third electrode segment; and a third electrode in contact with the first electrode and extending in a direction perpendicular to the first electrode, wherein the first electrode segment is coupled to the second electrode segment, the second electrode segment is coupled to the third electrode segment, and the first electrode segment extends parallel to the third electrode segment.

[0005] The first dielectric material comprises one or more of carbides, nitrides, and oxides, and the second dielectric material may comprise one or more of carbides, nitrides, and oxides. The first dielectric material may be different from the second dielectric material. The first electrode may include a vertical bit line electrode, and the third electrode may include a cell electrode. The first dielectric material extends in a direction parallel to the first electrode, and the second dielectric material may extend in a direction parallel to the first electrode. The second electrode further includes a fourth electrode segment, a fifth electrode segment, and a sixth electrode segment, wherein the fourth electrode segment is coupled to the fifth electrode segment, the fifth electrode segment is coupled to the sixth electrode segment, the fourth electrode segment extends in a direction parallel to the sixth electrode segment, and the second electrode segment may extend in a direction parallel to the fifth electrode segment. The second electrode segment may extend in a direction perpendicular to the first electrode segment.

[0006] A system according to one aspect of the present invention, made to achieve the above objective, comprises a first electrode including a first electrode segment, a second electrode segment, a third electrode segment, and a fourth electrode segment; a second electrode extending in a direction parallel to the first electrode; an interelectrode dielectric disposed between the first electrode and the second electrode; an intraelectrode dielectric disposed between the first electrode segment and the second electrode segment; and a third electrode extending in a direction perpendicular to the first electrode and the second electrode and coupled to the first electrode, wherein the first electrode segment is in contact with the second electrode segment, the second electrode segment is in contact with the third electrode segment, the third electrode segment extends in a direction parallel to the first electrode segment, the third electrode segment is in contact with the fourth electrode segment, and the fourth electrode segment extends in a direction parallel to the second electrode segment.

[0007] The dielectric material between the electrodes may include one or more of carbides, nitrides, or oxides. The dielectric material between the electrodes may extend in a direction parallel to the first electrode. The first electrode segment may come into contact with the fourth electrode segment. The material of the dielectric between the electrodes may be different from the material of the dielectric within the electrodes. The first electrode segment, the second electrode segment, the third electrode segment, and the fourth electrode segment can form a structure that surrounds the dielectric material within the electrode.

[0008] A method for manufacturing a device according to one aspect of the present invention, made to achieve the above objective, comprises the steps of: forming a trench; forming a mold by forming a conductor in the trench; forming a second dielectric in the mold; removing at least a portion of the conductor to form one or more dielectric openings; and forming a first dielectric in the one or more dielectric openings.

[0009] The step of forming the conductor may be based on at least one of chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The material of the first dielectric may be different from the material of the second dielectric. The method may further include forming the first dielectric in one or more dielectric openings, and then depositing a top conductor on the conductor and the second dielectric. The step of forming the second dielectric can be carried out by at least one selected from the group consisting of atomic layer deposition and chemical vapor deposition. The second dielectric may include a nitride, and the first dielectric may include an oxide. The method may further include the step of trimming the second dielectric and at least one of the conductors by a wet etching process to expand the one or more dielectric openings before forming the first dielectric in the one or more dielectric openings. [Effects of the Invention]

[0010] According to the present invention, the U-shaped electrode structure constitutes a large space, allowing for flexibility in the formation of connecting electrodes and simplifying the process of forming vertical electrodes. Furthermore, the second dielectric material reduces the surface area of ​​each electrode, thereby reducing the capacitance between each electrode. [Brief explanation of the drawing]

[0011] [Figure 1A] This is a cross-sectional view of a first example semiconductor structure according to one embodiment of the present invention. [Figure 1B] This is a plan view of a first example semiconductor structure according to one embodiment of the present invention. [Figure 1C] This is a perspective view of a first example semiconductor structure according to one embodiment of the present invention. [Figure 2A] This is a plan view of each step in the manufacturing method of a semiconductor structure according to one embodiment of the present invention. [Figure 2B] This is a plan view of each step in the manufacturing method of a semiconductor structure according to one embodiment of the present invention. [Figure 2C] This is a plan view of each step in the manufacturing method of a semiconductor structure according to one embodiment of the present invention. [Figure 2D] A plan view of each step of a method for manufacturing a semiconductor structure of the first example according to an embodiment of the present invention. [Figure 2E] A plan view of each step of a method for manufacturing a semiconductor structure of the first example according to an embodiment of the present invention. [Figure 2F] A plan view of each step of a method for manufacturing a semiconductor structure of the first example according to an embodiment of the present invention. [Figure 2G] A plan view of each step of a method for manufacturing a semiconductor structure of the first example according to an embodiment of the present invention. [Figure 2H] A plan view of each step of a method for manufacturing a semiconductor structure of the first example according to an embodiment of the present invention. [Figure 2I] A plan view of each step of a method for manufacturing a semiconductor structure of the first example according to an embodiment of the present invention. [Figure 2J] A plan view of each step of a method for manufacturing a semiconductor structure of the first example according to an embodiment of the present invention. [Figure 2K] A plan view of each step of a method for manufacturing a semiconductor structure of the first example according to an embodiment of the present invention. [Figure 3A] A cross-sectional view of each step of a method for manufacturing a semiconductor structure of the first example according to an embodiment of the present invention. [Figure 3B] A cross-sectional view of each step of a method for manufacturing a semiconductor structure of the first example according to an embodiment of the present invention. [Figure 3C] A cross-sectional view of each step of a method for manufacturing a semiconductor structure of the first example according to an embodiment of the present invention. [Figure 3D] A cross-sectional view of each step of a method for manufacturing a semiconductor structure of the first example according to an embodiment of the present invention. [Figure 3E] A cross-sectional view of each step of a method for manufacturing a semiconductor structure of the first example according to an embodiment of the present invention. [Figure 3F] A cross-sectional view of each step of a method for manufacturing a semiconductor structure of the first example according to an embodiment of the present invention. [Figure 3G] A cross-sectional view of each step of a method for manufacturing a semiconductor structure of the first example according to an embodiment of the present invention. [Figure 3H]These are cross-sectional views of each step in the manufacturing method of a first example of a semiconductor structure according to one embodiment of the present invention. [Figure 3I] These are cross-sectional views of each step in the manufacturing method of a first example of a semiconductor structure according to one embodiment of the present invention. [Figure 4A] This is a perspective view of each step in the manufacturing method of a first example semiconductor structure according to one embodiment of the present invention. [Figure 4B] This is a perspective view of each step in the manufacturing method of a first example semiconductor structure according to one embodiment of the present invention. [Figure 4C] This is a perspective view of each step in the manufacturing method of a first example semiconductor structure according to one embodiment of the present invention. [Figure 4D] This is a perspective view of each step in the manufacturing method of a first example semiconductor structure according to one embodiment of the present invention. [Figure 4E] This is a perspective view of each step in the manufacturing method of a first example semiconductor structure according to one embodiment of the present invention. [Figure 4F] This is a perspective view of each step in the manufacturing method of a first example semiconductor structure according to one embodiment of the present invention. [Figure 4G] This is a perspective view of each step in the manufacturing method of a first example semiconductor structure according to one embodiment of the present invention. [Figure 4H] This is a perspective view of each step in the manufacturing method of a first example semiconductor structure according to one embodiment of the present invention. [Figure 4I] This is a perspective view of each step in the manufacturing method of a first example semiconductor structure according to one embodiment of the present invention. [Figure 4J] This is a perspective view of each step in the manufacturing method of a first example semiconductor structure according to one embodiment of the present invention. [Figure 5] This is a flowchart of a method for manufacturing a semiconductor structure, the first example, according to one embodiment of the present invention. [Figure 6A] This is a cross-sectional view of a second example of a semiconductor structure according to one embodiment of the present invention. [Figure 6B] This is a plan view of a second example of a semiconductor structure according to one embodiment of the present invention. [Figure 6C] This is a perspective view of a second example semiconductor structure according to one embodiment of the present invention. [Figure 7A]These are cross-sectional views of each step in a second example of a semiconductor structure manufacturing method according to one embodiment of the present invention. [Figure 7B] These are cross-sectional views of each step in a second example of a semiconductor structure manufacturing method according to one embodiment of the present invention. [Figure 7C] These are cross-sectional views of each step in a second example of a semiconductor structure manufacturing method according to one embodiment of the present invention. [Figure 7D] These are cross-sectional views of each step in a second example of a semiconductor structure manufacturing method according to one embodiment of the present invention. [Figure 8] This is a flowchart of a method for manufacturing a second example of a semiconductor structure according to one embodiment of the present invention. [Modes for carrying out the invention]

[0012] Hereinafter, specific examples of embodiments for carrying out the present invention will be described in detail with reference to the drawings.

[0013] In the following detailed description, many specific examples are given to provide a complete understanding of the invention. However, those skilled in the art will understand that the disclosed embodiments can be carried out without these specific details. In other examples, well-known methods, procedures, components, and circuits are not described in detail so as not to obscure the invention disclosed herein.

[0014] Throughout this specification, the phrase "one embodiment" or "an embodiment" means that any particular feature, structure, or characteristic described in relation to that embodiment may be included in at least one embodiment disclosed herein. Therefore, while the expressions "in one embodiment," "in an embodiment," or "according to one embodiment" (or other expressions of similar importance) appear in various places throughout this specification, they do not necessarily all refer to the same embodiment. Furthermore, particular features, structures, or characteristics can be combined in any suitable way in one or more embodiments. In this regard, the term "exemplary" as used herein means "serving as an example, illustration, or descriptive element." Embodiments described as "exemplary" herein are not necessarily construed as being preferable or advantageous to other embodiments. Furthermore, particular features, structures, or characteristics can be combined in any suitable way in one or more embodiments. Also, depending on the context of the discussion herein, singular terms may include their corresponding plural forms, and plural terms may include their corresponding singular forms. Similarly, hyphenated words such as "two-dimensional" and "pre-determined" can be used interchangeably with their hyphenated forms, "two-dimensional" and "predetermined," and words with a capital letter at the beginning, such as "counter clockwise" and "three-dimensional," can be used interchangeably with their lowercase forms, "counter clockwise" and "three-dimensional," respectively. Such occasional interchangeable usages are not considered contradictory.

[0015] Furthermore, depending on the context of the discussion in this specification, singular terms may include their corresponding plural forms, and plural terms may include their corresponding singular forms. It should also be noted that the various figures (including component diagrams) shown and discussed in this specification are for illustrative purposes only and are not drawn to scale. For example, the dimensions of some elements may be exaggerated relative to others for clarity. Additionally, where appropriate, reference numerals are repeated between figures to indicate corresponding and / or similar elements.

[0016] The terms used herein are for illustrative purposes only and are not intended to limit the scope of the claims. In this specification, the singular forms “a,” “an,” and “the” are intended to include the plural form unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and / or “comprising,” as used herein, identify the presence of a described feature, integer, step, operation, element, and / or component, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0017] When an element or layer is referred to as being on another element or layer, or as being "connected to" or "coupled to" another element or layer, it will be understood that the element or layer may be directly on, connected to, or coupled to the other element or layer, or that there may be an intervening element or layer. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there is no intervening element or layer. The same symbol refers to the same element throughout. As used herein, the term "and / or" includes any combination of one or more of the related enumerated items.

[0018] As used herein, terms such as “first,” “second,” etc., are used as labels for preceding nouns and do not imply any kind of order (e.g., spatial, temporal, logical, etc.) unless explicitly defined as in the following examples. Furthermore, the same reference numerals may be used across two or more figures to refer to parts, components, blocks, circuits, units, or modules having the same or similar function. However, such usage is solely for the sake of simplification of explanation and ease of discussion, and does not imply that the structural or architectural details of such components or units are the same across all embodiments, or that such commonly referred parts / modules are the only way to carry out some of the exemplary embodiments disclosed herein.

[0019] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as those generally understood by those skilled in the art in which the present invention pertains. Furthermore, terms as defined in commonly used dictionaries should be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and it will be understood that they should not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0020] In this specification, the term "substrate" refers to various materials and structures, including silicon wafers, silicon on an insulator such as glass (SOI) wafers, wafers made of other semiconductor materials such as germanium, and other semiconductor materials on an insulator. In some embodiments, the substrate includes an organic material. In some embodiments, the substrate, either alone or in combination, is referred to as a wafer, die, or chip.

[0021] In this specification, "memory" refers to various forms of semiconductor memory, including both volatile memory, which loses data when the power is cut off, and non-volatile memory, which retains data even after the power is cut off. Examples of volatile memory include static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate DRAM (DDR DRAM), and other forms of random access memory. Examples of non-volatile memory include flash memory devices, read-only memory (ROM), programmable read-only memory (PROM), electronically programmable read-only memory (EPROM), electronically erasable and programmable read-only memory (EEPROM), phase-change random access memory (PROM), ferroelectric random access memory (FeRAM), and resistive random access memory (ReRAM).

[0022] As used herein, three-dimensional memory or 3D memory refers to any form of memory, including both volatile and non-volatile memories, that includes individual elements arranged in three dimensions. For example, multiple memory cell planes are stacked on top of each other. As used herein, vertical stack dynamic random access memory (VSDRAM) refers to a three-dimensional structure of DRAM in which each layer of DRAM elements is stacked on top of each other. In some embodiments, the 3D memory is arranged such that the addressing matrix is ​​orthogonal to the memory cells. That is, in some embodiments, the bit lines, word lines, and capacitors each extend in different directions, orthogonal to each other. In some embodiments, the vertical direction, i.e., the direction perpendicular to the plane of the substrate, is parallel to the bit lines. In some embodiments, the word lines or capacitors extend in the vertical direction. As used herein, the terms bit lines, word lines, read lines, address lines, grids, arrays, and matrices are used interchangeably to describe various electrodes arranged to supply signals at the point where two lines intersect within a larger device.

[0023] In this specification, conductors or conductive materials refer to a variety of conductive materials, which are used alone or in combination with other materials. In one embodiment, the conductor includes semiconductor materials, such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), and other suitable materials. In some embodiments, the conductor includes metals such as copper (Cu), tungsten (W), and titanium (Ti), either alone or in combination. In some embodiments, the conductor includes combinations of materials including oxides and nitrides. This enumeration of such elements is not intended to be exhaustive, and in other embodiments, any other known type of conductive material may be used.

[0024] As used herein, dielectrics or dielectric materials refer to nonconductive materials and include various semiconductor materials and their carbides, nitrides, oxides, such as silicon nitride (Si3N4) and silicon dioxide (SiO2). Such dielectric materials have relatively low relative permittivity (εr), for example less than 10 (εr<10), less than 20 (εr<20), less than 30 (εr<30), less than 40 (εr<40), less than 50 (εr<50), or less than 100 (εr<100), and are therefore poorly conductive. In some embodiments, the dielectric material includes a fluid material. In some embodiments, the dielectric material takes the form of an air gap.

[0025] This specification discloses various embodiments of systems and devices related to U-shaped vertical electrodes in 3D memory devices and methods for manufacturing the same. The 3D memory device has vertically oriented bit lines that form a U shape, and these vertical bit lines are formed of a conductor and arranged separated from each other by an interlayer insulator. The interlayer insulator includes a first dielectric that provides insulation between each bit line electrode and a second dielectric that provides insulation between each end of the individual electrodes. Therefore, the U-shaped electrode structure constitutes a large space, allowing flexibility in the formation of connecting electrodes and simplifying the process of forming the vertical electrodes. Furthermore, the second dielectric material reduces the surface area of ​​each electrode, thereby reducing the capacitance between each electrode. In some embodiments, the first dielectric is a liner dielectric and the second dielectric is a bulk dielectric. In some embodiments, the interlayer insulator is formed mainly of the first dielectric. In other embodiments, however, it may be formed mainly of the second dielectric.

[0026] The interlayer insulator and U-shaped vertical bit lines are first formed by creating trenches within the 3D memory device, the trenches being perpendicular to the orientation of the word lines and capacitors. Within the trenches, one or more dielectric materials, including a second dielectric material, are deposited to form a substrate insulating layer that provides electrical insulation between the electrodes and the substrate. Next, a sacrificial dielectric layer is deposited on top of the substrate insulating layer to fill the trenches. A series of vertically extending openings are formed by etching the sacrificial dielectric layer within the trenches, thereby forming a mold. Within the mold, conductors are deposited conformally so as to cover the exposed surfaces, resulting in a rectangular opening in the center. After the conductors are deposited, the first dielectric is used to fill the rectangular openings of the conductors and form an in-electrode insulating layer to separate the vertical portions of the conductors. Subsequently, the mold, including the remainder of the sacrificial dielectric, is removed by etching, creating gaps between each conductor. Next, within the gaps, one or more U-shaped vertical electrodes are formed by trimming the first dielectric, the second dielectric, and at least a portion of the conductors. Subsequently, additional dielectric material is deposited between each U-shaped vertical electrode, forming an inter-electrode insulating layer.

[0027] Figures 1A to 1C show a first example semiconductor structure according to one embodiment of the present invention. Figure 1A shows cross-sectional views in the X and Z directions of an exemplary embodiment of the first device structure 100. Figure 1B shows plan views of the first device structure 100 in the X and Y directions, and Figure 1C shows a perspective view of the first device structure 100.

[0028] The first device structure 100 forms part of a 3D memory device, as well as part of any other suitable three-dimensional semiconductor device.

[0029] In the example shown in Figure 1A, the 3D memory device takes the form of a vertically stacked device, with individual device layers 120 stacked on top of each other. In one embodiment, each device layer 120 takes the form of a memory device such as a DRAM, and as a result, the 3D memory device of the first device structure 100 takes the form of a vertically stacked DRAM. However, in other embodiments, the form of the individual device layers 120 can vary and may include one or more layers of SRAM, SDRAM, or any other suitable memory device, either alone or in combination. In the exemplary embodiments of Figures 1A to 1C, the individual device layers 120 are substantially similar to each other, but in other embodiments, at least two of the individual device layers 120 may differ from each other with respect to the number of devices, the types of devices, and the layout of the devices.

[0030] In the first device structure 100, individual elements such as capacitors, memory cells, or other suitable elements are addressed using one or more vertical electrodes 110 and one or more horizontal electrodes 116, through which signals are supplied to one or more cell electrodes 130. In the exemplary embodiments shown in Figures 1A to 1C, one or more vertical electrodes 110 extend in the Z direction, one or more horizontal electrodes 116 extend in the Y direction, and one or more cell electrodes 130 extend substantially in the X direction. In some embodiments, one or more vertical electrodes 110 are used as bit lines and one or more horizontal electrodes 116 are used as word lines. In other embodiments, one or more vertical electrodes 110 may be used as word lines and one or more horizontal electrodes 116 may be used as bit lines.

[0031] One or more vertical electrodes 110 take the form of U-shaped electrodes, which include two opposing portions extending in the Z direction, namely a first vertical electrode segment 111 and a second vertical electrode segment 113. At least one of the first vertical electrode segment 111 and the second vertical electrode segment 113 is coupled to one or more cell electrodes 130 extending in the X direction. The first vertical electrode segment 111 and the second vertical electrode segment 113 are connected by a bottom electrode segment 109 extending in the X direction between them. A substrate insulating layer 107 is formed between the substrate 101 and the bottom electrode segment 109. The substrate insulating layer 107 is made of a dielectric material and provides electrical insulation between the substrate 101 and one or more vertical electrodes 110.

[0032] As shown in Figures 1A to 1C, an inter-electrode insulating layer 103 is formed between each of the one or more vertical electrodes 110. In one embodiment, the inter-electrode insulating layer 103 comprises one or more dielectric materials, including a first dielectric material 106 that forms an insulating layer between each of the one or more vertical electrodes 110, and a second dielectric material 108 that forms an insulating layer between a first vertical electrode segment 111 and a second vertical electrode segment 113 that constitute a single electrode among the one or more vertical electrodes 110. In one embodiment, the dielectric materials used to form the first dielectric material 106 and the second dielectric material 108 include semiconductor materials, as well as their nitrides, carbides, and oxides. In one embodiment, the first dielectric material 106 and the second dielectric material 108 are composed of silicon oxide, silicon nitride, or gallium nitride, gallium oxide, or other similar materials. In one embodiment, the first dielectric material 106 and the second dielectric material 108 are composed of the same dielectric material. On the other hand, in other embodiments, the first dielectric material 106 and the second dielectric material 108 are composed of different materials, and these materials have different etching response rates. In one embodiment, an additional dielectric material, such as a third dielectric material or a fourth dielectric material, may be formed within the interelectrode insulating layer 103. Thus, one or more vertical electrodes 110 are separated from each other by the first dielectric material 106 and separated as a pair of interdigitated electrodes (IDEs). In one embodiment, the first dielectric material 106 is selected to prevent short circuits between one or more vertical electrodes 110. In one embodiment, the first dielectric material 106 is selected to have a low relative permittivity (εr) to reduce the effect of parasitic capacitance between one or more vertical electrodes 110.

[0033] Since one or more vertical electrodes 110 have a second dielectric material 108 between the first vertical electrode segment 111 and the second vertical electrode segment 113, the cross-sectional area of ​​each of the one or more vertical electrodes 110 in the Z and X directions is smaller compared to the case where the one or more vertical electrodes are integrated electrodes extending across the entire space of one or more cell electrodes 130. Since capacitance depends on surface area, the capacitance between each of the one or more vertical electrodes 110 is also reduced compared to an integrated electrode. Furthermore, the reduction of conductive material and the addition of dielectric material improve thermal and electrical insulation between each of the one or more vertical electrodes 110, as well as between the one or more vertical electrodes 110 and the substrate 101.

[0034] One or more cell electrodes 130 are separated into one or more left-side cell electrodes 104 and one or more right-side cell electrodes 114 by one or more vertical electrodes 110. The one or more left-side cell electrodes 104 and one or more right-side cell electrodes 114 are made of materials suitable for use in semiconductor devices, such as semiconductor materials such as silicon and germanium, as well as metals or other suitable conductors, either alone or in combination. In one embodiment, the one or more left-side cell electrodes 104 and one or more right-side cell electrodes 114 are made of substantially the same material. In other embodiments, the one or more left-side cell electrodes 104 and one or more right-side cell electrodes 114 may be made of different materials. In one embodiment, one or more cell electrodes 130 form part of one or more transistors 102. The one or more transistors 102 receive source-side current from one or more vertical electrodes 110, and gate current is supplied by one or more horizontal electrodes 116. Drain-side electrodes are coupled to one or more transistors 102 to provide drain current in the drain region 122. The presence of a gate current on one or more horizontal electrodes 116 induces an electric field effect within one or more cell electrodes 130, causing a current to flow between the source and drain sides. One or more transistors 102, in combination with capacitors in the drain region 122, form individual memory cells.

[0035] In one embodiment, one or more insulating layers are provided between each of one or more cell electrodes 130. In one embodiment, one or more left-side insulating layers 105 are arranged between each of one or more left-side cell electrodes 104. Similarly, in one embodiment, one or more right-side insulating layers 115 are arranged between each of one or more right-side cell electrodes 114. In one embodiment, insulating layers such as one or more left-side insulating layers 105 or one or more right-side insulating layers 115 are composed of dielectric materials, and also include semiconductor materials, as well as nitrides, carbides, and oxides thereof. In one embodiment, one or more left-side insulating layers 105 or one or more right-side insulating layers 115 are composed of silicon oxide, silicon nitride, or other similar materials such as gallium nitride, gallium oxide, and combinations thereof. In one embodiment, one or more left-side insulating layers 105 or one or more right-side insulating layers 115 are composed of the same dielectric material. On the other hand, in other embodiments, one or more left-side insulating layers 105 or one or more right-side insulating layers 115 may be composed of different materials. In one embodiment, at least one of one or more left-side insulating layers 105 or one or more right-side insulating layers 115 is formed of a material substantially identical to one or more of the first dielectric material 106 and the second dielectric material 108. In other embodiments, however, the material of one or more left-side insulating layers 105 or one or more right-side insulating layers 115 may be different from the first dielectric material 106 and the second dielectric material 108.

[0036] Figures 2A to 2K, 3A to 3I, and 4A to 4J are diagrams illustrating the steps of a first example of a method for manufacturing a semiconductor structure according to one embodiment of the present invention, with Figures 2A to 2K showing exemplary embodiments of the process for forming a device structure such as the first device structure 100 or any other device structure shown herein in plan view. Figures 3A to 3I and 4A to 4J show corresponding cross-sectional and perspective views of the process. Figure 5 is a flowchart of a first example of a method for manufacturing a semiconductor structure according to one embodiment of the present invention, showing exemplary embodiments of the process 500 for forming a device structure corresponding to the exemplary embodiments of Figures 2A to 2K, 3A to 3I, and 4A to 4J.

[0037] Figures 2A, 3A, and 4A show step S505 in the process of Figure 5, where the initial stack is prepared before the trenches are formed. Individual device layers 120 are formed in the initial stage with one or more left-side cell electrodes 104 and one or more right-side cell electrodes 114 formed as part of one or more transistors 102. One or more left-side cell electrodes 104 and one or more right-side cell electrodes 114 are formed of a semiconductor material such as silicon or germanium and are formed using an appropriate process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), and / or atomic layer deposition (ALD). In one embodiment, one or more left-side cell electrodes 104 and one or more right-side cell electrodes 114 are formed using an epitaxial process. One or more left-side insulating layers 105 are formed between each of the one or more left-side cell electrodes 104, and one or more right-side insulating layers 115 are formed between each of the one or more right-side cell electrodes 114. One or more left-side insulating layers 105 and one or more right-side insulating layers 115 are composed of dielectric material and are formed using appropriate processes such as CVD, PVD, and / or ALD. In one embodiment, one or more left-side insulating layers 105 and one or more right-side insulating layers 115 are formed by a selective removal process such as etching to remove a portion of the semiconductor material used to form the cell electrodes, followed by a deposition process. One or more horizontal electrodes 116 are similarly formed by a selective removal process such as etching, and then a conductive material is formed by appropriate processes such as CVD, PVD, and / or ALD. Furthermore, dielectric material is deposited between one or more left-side cell electrodes 104 and one or more right-side cell electrodes 114 to form a central column 202. The central column 202 is formed using a first dielectric material similar to that used in the one or more left-side insulating layers 105 and one or more right-side insulating layers 115. In one embodiment, the central column 202 is formed as part of the formation of the one or more left-side insulating layers 105 and one or more right-side insulating layers 115, while in other embodiments, the central column 202 may be formed separately.

[0038] Figures 2B, 3B, and 4B show step S510 in the process of Figure 5, where a mask 204 is formed on top of the device. The mask 204 can be any suitable material, such as dielectric materials like nitrides, carbides, oxides, and photoresists. The material of the mask 204 is selected so that selective removal processes, such as etching processes, do not affect the material of the mask 204. Meanwhile, the central pillar 202 is selectively removed.

[0039] Figures 2C, 3C, and 4C-4D show step S515 in the process of Figure 5, where the mask 204 is patterned to generate a mask pattern 206. In one embodiment, the mask pattern 206 is formed by using etching processes such as a wet etching process using chemicals and a dry etching process using reactive plasma, as well as any other suitable removal method. In an embodiment as shown in Figure 4C, the mask pattern 206 is formed by a masking step such as a photoresist mask formed using a lithography process to selectively cover a portion of the first device structure 100, and by using any other suitable patterning method to pattern the mask 204.

[0040] Figures 2D, 3D, 3E, and 4E show step S520 in the process of Figure 5, where a trench 210 is formed within the first device structure 100. The trench 210 separates one or more cell electrodes 130 into one or more left-side cell electrodes 104 and one or more right-side cell electrodes 114. The trench 210 is formed using any suitable semiconductor process, including etching, which includes both chemical wet etching processes and reactive plasma dry etching processes, as well as various techniques such as lithography, mechanical drilling or cutting, lasers, combinations of these methods, and other suitable methods known in the art. The width of the trench 210 between the one or more left-side cell electrodes 104 and the one or more right-side cell electrodes 114 is approximately 150 nm, but in other embodiments, the width may vary as appropriate from 1 nm to 10 μm. In the embodiment shown in Figure 2D, the trench 210 is illustrated to extend between one or more left-side cell electrodes 104 and one or more right-side cell electrodes 114, and includes a lateral recess into the space between each of the one or more left-side cell electrodes 104, between each of the one or more right-side cell electrodes 114, or both. However, in one embodiment, the trench 210 may form a flat surface without extending laterally beyond one or more left-side cell electrodes 104 or one or more right-side cell electrodes 114.

[0041] In one embodiment, as shown in Figure 3D, the trench 210 extends to the surface of the substrate 101. The substrate insulating layer 107 is formed by depositing a suitable dielectric material, such as a nitride, oxide, or carbide, within the trench 210, as shown in Figure 3E. In an embodiment as shown in Figure 4E, the trench 210 is formed such that a portion of the central column 202 is left open to form the substrate insulating layer 107.

[0042] After the trench 210 and the substrate insulating layer 107 are formed, the remaining portion of the mask 204 is removed. For example, in one embodiment, a planarization process such as chemical mechanical polishing (CMP) is used to remove the remaining portion of the mask 204. Other processes, such as etching, can be used alone or in combination with the planarization process.

[0043] Figures 2E, 3F, and 4F show step S530 in the process of Figure 5, where the sacrificial dielectric 212 is deposited in the trench 210 and on the substrate insulating layer 107. The sacrificial dielectric 212 is deposited using CVD, ALD, or other suitable process to fill the remainder of the trench 210. In one embodiment, the sacrificial dielectric 212 is selected for ease of removal and is composed of a carbon-based dielectric material such as carbide.

[0044] Figures 2F, 3G, and 4G show step S540 in the process of Figure 5, where an opening 214 is formed within the sacrificial dielectric 212. The opening 214 is formed using etching processes, including, for example, a wet etching process using chemicals and a dry etching process using reactive plasma, as well as other suitable removal methods. In one embodiment, the etching process is used in combination with a masking step, such as a photoresist mask formed by a lithography process to selectively cover a portion of the first device structure 100. It may also be used in combination with other suitable methods for patterning the sacrificial dielectric 212. In one embodiment, if the sacrificial dielectric 212 is formed of a carbon material, dry etching is suitable for its removal. The relative size of the opening 214 in the XY direction is large, and the opening extends between two of one or more cell electrodes 130 and further extends along the trench 210 beyond one or more left-side insulating layers 105 and one or more right-side insulating layers 115. Therefore, the relatively large size of the opening 214 in the XY direction provides a larger critical dimension for additional steps compared to the case where it is defined by the spacing between each of the cell electrodes 130. It also allows for a smaller aspect ratio in the inter-electrode insulating layer 103 compared to the case where it is defined by the spacing between each of the cell electrodes 130.

[0045] Figures 2G, 3H, and 4H show step S550 in the process of Figure 5, where a conductive material 220 is deposited in the opening 214, and the conductive material 220 is used to form one or more vertical electrodes 110. The conductive material 220 includes doped semiconductor materials, metals such as tungsten, functionalized carbon nanomaterials, and any other suitable conductive material. In one embodiment, the conductive material of one or more vertical electrodes 110 is formed by a semiconductor process such as CVD, ALD, PVD, electroplating, or any other suitable method for forming the conductive material. In one embodiment, the opening 214 in the sacrificial dielectric 212 serves as a template for forming the conductive material 220. In one embodiment, the conductive material 220 is formed using a conformal process, resulting in the conductive material 220 being formed on the exposed surface of the opening 214 containing the sacrificial dielectric 212, and on the surface of the trench 210 containing one or more cell electrodes 130, one or more left-side insulating layers 105, and one or more right-side insulating layers 115. Thus, the conductive material 220 is coupled to one or more cell electrodes 130 and has a U-shaped cross-section. The remainder of the opening 214 is referred to as the electrode internal opening 216.

[0046] Figures 2H, 3I, and 4I show step S560 in the process of Figure 5, where the second dielectric material 108 is deposited in the electrode opening 216. In one embodiment, the electrode opening 216 in the conductive material 220 serves as a template for forming the second dielectric material 108. The second dielectric material 108 is formed using a conformal process such as ALD, as well as any other suitable process. The second dielectric material 108 forms a film on the exposed surface of the electrode opening 216. In one embodiment, the second dielectric material 108 includes semiconductor materials, as well as their nitrides, carbides, and oxides such as silicon, silicon carbide, silicon nitride, and silicon dioxide, as well as any other suitable materials such as air gaps, ceramic materials, and polymer materials having high dielectric constants. In one embodiment, the conformal deposition of the second dielectric material 108 leaves a portion of the electrode opening 216 still open for additional deposition. In other embodiments, however, the electrode opening 216 can be completely filled with the second dielectric material 108.

[0047] Figure 2I shows step S570 in the process of Figure 5, where the remainder of the sacrificial dielectric 212 is removed. The remainder of the sacrificial dielectric 212 is removed by any suitable process, including an etching process including a wet etching process using chemicals and a dry etching process using reactive plasma, as well as any other suitable removal method. The opening formed by the removal of the remainder of the sacrificial dielectric 212 is referred to as the inter-electrode opening 222.

[0048] Figure 2J shows step S580 in the process of Figure 5, where the conductive material 220 and the second dielectric material 108 are trimmed to a predetermined size, and the inter-electrode opening 222 is expanded to fit the size of one or more cell electrodes 130, thereby forming a dielectric opening 224. The conductive material 220 and the second dielectric material 108 are trimmed by any suitable process, including an etching process including a wet etching process using chemicals and a dry etching process using reactive plasma, as well as any other suitable removal method. In one embodiment, the materials constituting the conductive material 220 and the materials constituting the second dielectric material 108 are different, and an etchant effective for the second dielectric material 108 is ineffective for the conductive material 220, so the boundary between the conductive material 220 and the second dielectric material 108 functions as an etching stop. In one embodiment, the boundary between the conductive material 220 and the second dielectric material 108 is a self-aligning etching stop. In other embodiments, one or more masking and patterning steps may be included to define the mask used for etching.

[0049] Figures 2K and 4J show step S590 in the process of Figure 5, where the interelectrode opening 222 is expanded to form a dielectric opening 224, after which the first dielectric material 106 is deposited in the dielectric opening 224. The first dielectric material 106 includes semiconductor materials, as well as nitrides, oxides, and carbides, including silicon nitride, silicon oxide, and any other suitable dielectric. In one embodiment, the first dielectric material 106 is formed by a semiconductor process such as CVD, ALD, PVD, or any other suitable method. In one embodiment, excess material is removed using a planarization process such as CMP.

[0050] Figures 6A to 6C show a second example of a semiconductor structure according to one embodiment of the present invention. Figure 6A shows an exemplary embodiment of the second device structure 600 in a cross-sectional view along the X and Z directions. Figure 6B shows a plan view of the second device structure 600 in the X and Y directions, and Figure 6C shows a perspective view of the second device structure 600.

[0051] The second device structure 600, shown in Figures 6A to 6C, differs from the first device structure by including a top electrode segment 602 in addition to the first vertical electrode segment 111, the second vertical electrode segment 113, and the bottom electrode segment 109. The top electrode segment 602 is formed parallel to the direction of the substrate 101 and parallel to the bottom electrode segment 109. The top electrode segment 602 is formed to provide a conductive plug, providing a larger contact area for one or more vertical electrodes 110 to couple with additional electrodes.

[0052] Figures 7A to 7D are diagrams showing each step of a second example of a semiconductor structure manufacturing method according to one embodiment of the present invention, and Figures 7A to 7D show exemplary embodiments of the process for forming a device structure such as the second device structure 600. Figure 8 is a flowchart of a second example of a semiconductor structure manufacturing method according to one embodiment of the present invention, and shows an exemplary embodiment of the process 800 for forming a device structure corresponding to the exemplary embodiments in Figures 7A to 7D.

[0053] Figure 7A shows step S810 in the process of Figure 8, where the first device structure 100 is formed. The process for forming the first device structure 100 is the same as described above with respect to process 500, and is the same as described in detail in Figures 2A to 2K, 3A to 3I, and 4A to 4J.

[0054] Figure 7B shows step S820 in the process of Figure 8, where the top 702 of the second dielectric material 108 is removed. The removal of the top 702 of the second dielectric material 108 is carried out by an etching process including wet etching and dry etching, as well as any other suitable method in the art. By removing the top 702 of the second dielectric material 108, a sufficient amount of the second dielectric material 108 is removed so that one or more vertical electrodes 110 are exposed.

[0055] Figure 7C shows step S830 in the process of Figure 8, where an additional conductor 704 is deposited as a layer on the device, including the exposed portion of the second dielectric material 108. The additional conductor 704 is made of the same material as the material used for one or more vertical electrodes 110. The additional conductor 704 is deposited using any suitable technique, such as PVD, CVD, ALD, or electroplating. The additional conductor 704 is formed using a different technique than the conductors used to form one or more vertical electrodes 110, because the step coverage for replacing the top 702 of the second dielectric material 108 is lower than the step coverage for the trench 210.

[0056] Figure 7D shows step S840 in the process of Figure 8, where the additional conductor 704 is patterned to form the top electrode segment 602. The patterning is any suitable process, such as wet etching or dry etching, and incorporates one or more additional masking processes. For example, a photolithography process is used to define a mask covering the top electrode segment 602, and the remaining surface of the additional conductor 704 is removed using a process such as etching.

[0057] This specification includes details of many specific embodiments, but these details of embodiments should not be construed as limitations on the claims, but rather as descriptions of features specific to a particular embodiment. Certain features described herein in the context of a separate embodiment may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented separately in multiple embodiments or in any appropriate subordinate combination. Furthermore, features are described above as acting in a certain combination, and may even be initially claimed as such, but one or more features from the claimed combination may be removed from that combination, and the claimed combination may relate to a subcombination or variation of a subcombination.

[0058] Similarly, while operations are depicted in a specific order in the diagrams, this should not be understood as requiring that such operations be performed in a specific illustrated or sequential order, or that all illustrated operations be performed, in order to achieve a favorable result. In some situations, multitasking or parallel processing may be advantageous. Furthermore, the separation of various system components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated in a single software product or packaged in multiple software products.

[0059] Thus, specific embodiments of the present invention have been described herein. Other embodiments are within the scope of the claims. In some cases, favorable results can still be obtained by performing the operations described in the claims in a different order. Furthermore, the steps depicted in the figures do not necessarily need to be in the specific illustrated order or sequential order to obtain favorable results. In certain implementations, multitasking and parallel processing may be advantageous.

[0060] Although embodiments of the present invention have been described in detail above with reference to the drawings, the present invention is not limited to the embodiments described above, and can be modified and implemented in various ways without departing from the technical spirit of the present invention. [Explanation of Symbols]

[0061] 100, 600 First and second device structures 101 circuit board 102 transistors 103 Inter-electrode insulating layer 104 Left cell electrode (first electrode segment) 114 Right-side cell electrode (third electrode segment) 105, 115 Left side, right side insulating layer 106 First Dielectric Material (Inter-electrode Dielectric) 108 Second Dielectric Material (Electrode Dielectric) 107 Substrate insulating layer 109 Bottom electrode segment 110 Vertical electrode (third electrode) (conductor) 111 First Vertical Electrode Segment 113 Second Vertical Electrode Segment 116 horizontal electrode 120 device layers 122 Drain region 130 cell electrodes 202 Central pillar 204 masks 206 Mask Patterns 210 Trench 212 Sacrificial Dielectrics 214 Opening (mold) 216 Electrode opening (mold) 220 Conductive materials (conductors) 222 Interelectrode opening 224 Dielectric aperture 602 Top electrode segment 702 Top of the second dielectric material 704 Additional conductor (top conductor)

Claims

1. A first electrode including a first electrode segment, a second electrode segment, and a third electrode segment, A second electrode extending parallel to the first electrode, A first dielectric material disposed between the first electrode and the second electrode, A second dielectric material disposed between the first electrode segment and the third electrode segment, The device comprises a third electrode that contacts the first electrode and extends in a direction perpendicular to the first electrode, The first electrode segment is coupled to the second electrode segment, The preceding second electrode segment is coupled to the preceding third electrode segment. The device is characterized in that the first electrode segment extends parallel to the third electrode segment.

2. The first dielectric material comprises one or more of carbides, nitrides, or oxides. The device according to claim 1, characterized in that the second dielectric material includes one or more of carbides, nitrides, or oxides.

3. The device according to claim 1, characterized in that the first dielectric material is different from the second dielectric material.

4. The first electrode includes a vertical bit line electrode, The device according to claim 1, characterized in that the third electrode includes a cell electrode.

5. The first dielectric material extends in a direction parallel to the first electrode, The device according to claim 1, characterized in that the second dielectric material extends in a direction parallel to the first electrode.

6. The second electrode further includes a fourth electrode segment, a fifth electrode segment, and a sixth electrode segment. The fourth electrode segment is coupled to the fifth electrode segment. The fifth electrode segment is coupled to the sixth electrode segment. The fourth electrode segment extends in a direction parallel to the sixth electrode segment, The device according to claim 1, characterized in that the second electrode segment extends in a direction parallel to the fifth electrode segment.

7. The device according to claim 1, characterized in that the second electrode segment extends in a direction perpendicular to the first electrode segment.

8. A first electrode including a first electrode segment, a second electrode segment, a third electrode segment, and a fourth electrode segment, A second electrode extending in a direction parallel to the first electrode, An interelectrode dielectric is disposed between the first electrode and the second electrode, A dielectric material within the electrode, disposed between the first electrode segment and the second electrode segment, The device comprises a third electrode extending in a direction perpendicular to the first electrode and the second electrode and coupled to the first electrode, The first electrode segment is in contact with the second electrode segment, The second electrode segment is in contact with the third electrode segment, The third electrode segment extends in a direction parallel to the first electrode segment, The third electrode segment is in contact with the fourth electrode segment, The system is characterized in that the fourth electrode segment extends in a direction parallel to the second electrode segment.

9. The system according to claim 8, characterized in that the dielectric material between electrodes includes one or more of carbides, nitrides, or oxides.

10. The system according to claim 8, characterized in that the dielectric between electrodes extends in a direction parallel to the first electrode.

11. The system according to claim 8, characterized in that the first electrode segment is in contact with the fourth electrode segment.

12. The system according to claim 8, characterized in that the material of the dielectric between electrodes is different from the material of the dielectric within the electrodes.

13. The system according to claim 8, characterized in that the first electrode segment, the second electrode segment, the third electrode segment, and the fourth electrode segment form a structure that surrounds the dielectric material inside the electrode.

14. A method for manufacturing a device, The step of forming a trench, The steps include forming a conductor in the trench to form a mold, The steps include forming a second dielectric material within the mold, The steps include removing at least a portion of the conductor to form one or more dielectric openings, A method characterized by comprising the step of forming a first dielectric in one or more dielectric openings.

15. The method according to 14, characterized in that the step of forming the conductor is based on at least one of chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

16. The method according to 14, characterized in that the material of the first dielectric is different from the material of the second dielectric.

17. The method according to 14, further comprising depositing a top conductor on the conductor and the second dielectric after forming the first dielectric in one or more dielectric openings.

18. The method according to 14, characterized in that the step of forming the second dielectric is carried out by at least one selected from the group consisting of atomic layer deposition and chemical vapor deposition.

19. The second dielectric material includes a nitride, The method according to 14, characterized in that the first dielectric comprises an oxide.

20. The method according to 14, further comprising the step of trimming the second dielectric and at least one of the conductors by a wet etching process to expand the one or more dielectric openings before forming the first dielectric in the one or more dielectric openings.

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