Memory device

Abstract

The present invention provides a memory device capable of preventing excessive current from flowing through the memory cells. [Solution] The memory device according to the embodiment comprises a first wiring 10, a second wiring 20, and a memory cell 30 provided between the first wiring and the second wiring, wherein the memory cell includes a main memory section 30m including a variable resistance memory element 40 and a two-terminal switching element 50, a first electrode 61 provided between the first wiring and the main memory section, and a second electrode 62 provided between the second wiring and the main memory section, wherein at least one of the first electrode and the second electrode includes a structure in which a first main electrode layer, a second main electrode layer, and a sub-electrode layer provided between the first main electrode layer and the second main electrode layer are stacked, and the resistivity of the material of the sub-electrode layer is higher than the resistivity of the material of the first main electrode layer and the resistivity of the material of the second main electrode layer.

Description

Technical Field

[0001] Embodiments of the present invention relate to a memory device.

Background Art

[0002] There has been proposed a memory device in which a plurality of memory cells each including a variable resistance memory element and a selector (switching element) are integrated on a semiconductor substrate.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] To provide a memory device capable of preventing an excessive current from flowing through a memory cell.

Means for Solving the Problems

[0005] A memory device according to an embodiment comprises a first wiring extending in a first direction, a second wiring extending in a second direction intersecting the first direction, and a memory cell provided between the first wiring and the second wiring, wherein the memory cell includes a main memory section containing variable resistance memory elements and two-terminal switching elements stacked in a third direction intersecting the first and second directions, a first electrode provided between the first wiring and the main memory section and connected to the first wiring and the main memory section, and a second electrode provided between the second wiring and the main memory section and connected to the second wiring and the main memory section, wherein at least one of the first electrode and the second electrode includes a structure in which a first main electrode layer, a second main electrode layer, and a sub-electrode layer provided between the first main electrode layer and the second main electrode layer are stacked in the third direction, and the resistivity of the material of the sub-electrode layer is higher than the resistivity of the material of the first main electrode layer and the resistivity of the material of the second main electrode layer. [Brief explanation of the drawing]

[0006] [Figure 1] This is a schematic perspective view showing the configuration of the storage device according to the embodiment. [Figure 2] This is a schematic cross-sectional view showing the configuration of a storage device according to the embodiment. [Figure 3] This is a schematic cross-sectional view showing an example of the configuration of a magnetoresistive element in a memory device according to the embodiment. [Figure 4] This is a schematic cross-sectional view showing another example of the configuration of the magnetoresistive element in the memory device according to the embodiment. [Figure 5] This figure schematically shows the current-voltage characteristics of the selector of the storage device according to the embodiment. [Figure 6] This is a schematic cross-sectional view showing the configuration of at least one of the lower electrode and upper electrode of the storage device according to the embodiment. [Figure 7] This is a schematic cross-sectional view showing a modified example of the configuration of at least one of the lower electrode and upper electrode of the storage device according to the embodiment. [Figure 8]This is a schematic cross-sectional view showing the configuration of a modified example of the storage device according to the embodiment. [Modes for carrying out the invention]

[0007] The embodiments will be described below with reference to the drawings.

[0008] Figure 1 is a schematic perspective view showing the configuration of a storage device according to this embodiment.

[0009] The memory device according to this embodiment is provided on a lower region (not shown) including a semiconductor substrate (not shown), and includes a plurality of lower wirings (one of the first wirings and the second wirings) 10, each extending in the X direction, a plurality of upper wirings (the other of the first wirings and the second wirings) 20, each extending in the Y direction, and a plurality of memory cells 30 provided between the plurality of lower wirings 10 and the plurality of upper wirings 20.

[0010] One of the lower wiring 10 and the upper wiring 20 corresponds to a word line, and the other of the lower wiring 10 and the upper wiring 20 corresponds to a bit line.

[0011] Figure 2 is a schematic cross-sectional view showing the configuration of the storage device according to this embodiment.

[0012] As shown in Figure 2, the memory cell 30 includes a main memory section 30m, a lower electrode (one of the first electrode and the second electrode) 61, and an upper electrode (the other of the first electrode and the second electrode) 62, with the main memory section 30m, the lower electrode 61, and the upper electrode 62 stacked in the Z direction.

[0013] The main memory unit 30m functions as the substantial memory unit of the memory cell 30, and includes a magnetoresistive element (also referred to as a magnetoresistive element body, hereinafter described using the term magnetoresistive element), which is a non-volatile variable resistance memory element, 40, a selector 50 which is a two-terminal switching element, and an intermediate electrode (third electrode) 63 provided between the magnetoresistive element 40 and the selector 50. The magnetoresistive element 40, the selector 50, and the intermediate electrode 63 are laminated in the Z direction, and the magnetoresistive element 40 and the selector 50 are connected in series via the intermediate electrode 63.

[0014] The lower electrode 61 is provided between the lower wiring 10 and the main memory unit 30m and is connected to the lower wiring 10 and the main memory unit 30m. The upper electrode 62 is provided between the upper wiring 20 and the main memory unit 30m and is connected to the upper wiring 20 and the main memory unit 30m.

[0015] The X direction, the Y direction, and the Z direction are directions that intersect each other. More specifically, the X direction, the Y direction, and the Z direction are orthogonal to each other.

[0016] FIG. 3 is a cross-sectional view schematically showing an example of the configuration of the magnetoresistive element 40.

[0017] The magnetoresistive element 40 is a MTJ (Magnetic Tunnel Junction) element and includes a memory layer (first magnetic layer) 41, a reference layer (second magnetic layer) 42, a tunnel barrier layer (non-magnetic layer) 43, a shift canceling layer (third magnetic layer) 44, and an intermediate layer 45, and these layers 41 to 45 have a structure laminated in the Z direction.

[0018] The memory layer 41 is a ferromagnetic layer having a variable magnetization direction, and is formed of, for example, a CoFeB layer containing cobalt (Co), iron (Fe), and boron (B). The variable magnetization direction means that the magnetization direction changes with respect to a predetermined write current.

[0019] The reference layer 42 is a ferromagnetic layer having a fixed magnetization direction, and is formed of, for example, a CoFeB layer containing cobalt (Co), iron (Fe), and boron (B). The fixed magnetization direction means that the magnetization direction does not change with respect to a predetermined write current.

[0020] The tunnel barrier layer 43 is an insulating layer provided between the memory layer 41 and the reference layer 42, and is formed of, for example, a MgO layer containing magnesium (Mg) and oxygen (O).

[0021] The shift canceling layer 44 is a ferromagnetic layer having a fixed magnetization direction antiparallel to the magnetization direction of the reference layer 42, and has a function of canceling the magnetic field applied from the reference layer 42 to the memory layer 41. The shift canceling layer 44 is formed of, for example, a superlattice layer in which cobalt (Co) and platinum (Pt) are alternately laminated.

[0022] The intermediate layer 45 is provided between the reference layer 42 and the shift canceling layer 44, and is formed of, for example, a ruthenium (Ru) layer.

[0023] When the magnetization direction of the memory layer 41 is parallel to the magnetization direction of the reference layer 42, the magnetoresistive effect element 40 is in a low-resistance state having a relatively low resistance. When the magnetization direction of the memory layer 41 is antiparallel to the magnetization direction of the reference layer 42, the magnetoresistive effect element 40 is in a high-resistance state having a relatively high resistance. Therefore, the magnetoresistive effect element 40 can store binary data according to its resistance state.

[0024] FIG. 4 is a cross-sectional view schematically showing another example of the configuration of the magnetoresistive effect element 40.

[0025] The magnetoresistive element 40 shown in Figure 3 was a bottom-free type magnetoresistive element with the memory layer 41 located below the reference layer 42, while the magnetoresistive element 40 shown in Figure 4 is a top-free type magnetoresistive element with the memory layer 41 located above the reference layer 42. The stacking order of layers 41-45 is reversed between the magnetoresistive element 40 shown in Figure 3 and the magnetoresistive element 40 shown in Figure 4.

[0026] Instead of the magnetoresistive element 40 shown in Figure 3, a magnetoresistive element 40 as shown in Figure 4 may be used.

[0027] Returning to the explanation of Figure 2, the selector 50 includes a selector material layer (switching material layer) formed of a material as described later, and has a switching function. In the example shown in Figure 2, the selector 50 substantially corresponds to the selector material layer, the lower electrode 61 functions as the lower electrode of the selector, and the intermediate electrode 63 functions as the upper electrode of the selector.

[0028] Figure 5 is a schematic diagram showing the current-voltage characteristics of the selector 50.

[0029] The selector 50 has the characteristic of transitioning from the off state to the on state when the voltage applied between the two terminals is equal to or greater than the threshold voltage Vth, and transitioning from the on state to the off state when the voltage applied between the two terminals is equal to or less than the hold voltage Vhold. In the example in Figure 2, the voltage applied between the two terminals corresponds to the voltage applied between the lower electrode 61 and the intermediate electrode 63.

[0030] When a voltage is applied between the lower wiring 10 and the upper wiring 20, and the voltage applied to the selector 50 becomes greater than or equal to the threshold voltage Vth, the selector 50 switches from the off state to the on state, making it possible to write to or read from the magnetoresistive element 40 connected in series with the selector 50.

[0031] The selector material layer of selector 50 contains materials containing silicon (Si) and oxygen (O), materials containing silicon (Si) and nitrogen (N), materials containing hafnium (Hf) and oxygen (O), materials containing tantalum (Ta) and oxygen (O), materials containing titanium (Ti) and oxygen (O), materials containing tungsten (W) and oxygen (O), materials containing zirconium (Zr) and oxygen (O), materials containing aluminum (Al) and oxygen (O), and materials containing nickel (Ni) and oxygen (O). It is preferable that the material is formed from a material selected from materials containing niobium (Nb) and oxygen (O), materials containing arsenic (As) and sulfur (S), materials containing zinc (Zn) and tellurium (Te), materials containing germanium (Ge) and selenium (Se), materials containing germanium (Ge) and arsenic (As), materials containing germanium (Ge) and tellurium (Te), materials containing carbon (C) and tellurium (Te), and materials containing arsenic (As) and tellurium (Te).

[0032] More specifically, the selector material layer of selector 50 is preferably selected from SiO layer, SiN layer, SiON layer, AsSiO layer, AsSiOTi layer, AsSiOTiN layer, AsSiOTiNC layer, HfO layer, AsHfO layer, TaO layer, TiO layer, WO layer, ZrO layer, AlO layer, NiO layer, NbO layer, AsS layer, ZnTe layer, AsZnTe layer, SiZnTe layer, AsSiZnTe layer, GeSe layer, GeAsSeTe layer, GeAs layer, GeTe layer, CTe layer, SiAsTe layer, SiGeAsTe layer, GeAsTe layer, AsTe layer, and SiGeAsSe layer.

[0033] Furthermore, the selector material layer may contain, in addition to the materials described above, at least one element selected from carbon (C), nitrogen (N), indium (In), and boron (B).

[0034] At least one of the lower electrode 61 and the upper electrode 62 includes a structure in which a first main electrode layer, a second main electrode layer, and a sub-electrode layer provided between the first and second main electrode layers are stacked in the Z direction. That is, only one of the lower electrode 61 and the upper electrode 62 may have such a stacked structure, or both the lower electrode 61 and the upper electrode 62 may have such a stacked structure. The resistivity of the material of the sub-electrode layer is higher than the resistivity of the material of the first main electrode layer and the resistivity of the material of the second main electrode layer.

[0035] Figure 6 is a schematic cross-sectional view showing the configuration of at least one of the lower electrode 61 and the upper electrode 62.

[0036] In the example shown in Figure 6, at least one of the lower electrode 61 and the upper electrode 62 includes two main electrode layers (first and second main electrode layers) 60a and one auxiliary electrode layer 60b provided between the two main electrode layers 60a. That is, the auxiliary electrode layer 60b is sandwiched between the two main electrode layers 60a.

[0037] The main electrode layer 60a preferably contains at least one element selected from carbon (C), titanium (Ti), tantalum (Ta), and tungsten (W). In addition to these elements, the main electrode layer 60a may further contain at least one element selected from nitrogen (N) and silicon (Si).

[0038] More specifically, the main electrode layer 60a is preferably selected from a C layer, a CN layer, a Ti layer, a Ta layer, a TiN layer, a TaN layer, a TiCN layer, a TiAlN layer, a W layer, a WN layer, a WSi layer, and a WSiN layer.

[0039] Although the two main electrode layers 60a are usually made of the same material, they do not necessarily have to be made of the same material.

[0040] As already mentioned, the material of the auxiliary electrode layer 60b has a higher resistivity than the material of the main electrode layer 60a. Preferably, the auxiliary electrode layer 60b contains at least one of a metallic element and a semiconductor element, and at least one of oxygen (O) and nitrogen (N).

[0041] The metallic and semiconductor elements contained in the auxiliary electrode layer 60b are preferably selected from tungsten (W), silicon (Si), aluminum (Al), titanium (Ti), indium (In), tantalum (Ta), hafnium (Hf), zinc (Zn), ruthenium (Ru), tin (Sn), magnesium (Mg), zirconium (Zr), and chromium (Cr).

[0042] More specifically, the auxiliary electrode layer 60b is preferably selected from a WSiN layer, a WSiO layer, a SiN layer, an SiO layer, an AlO layer, a TiN layer, an InO layer, a WN layer, a TaN layer, an HfO layer, a ZnO layer, a RuO layer, a SnO layer, a MgO layer, a ZrN layer, a CrN layer, an AlN layer, and an HfN layer.

[0043] Furthermore, the auxiliary electrode layer 60b may further contain at least one element selected from nickel (Ni), molybdenum (Mo), vanadium (V), carbon (C), boron (B), phosphorus (P), and sulfur (S).

[0044] As described above, in this embodiment, at least one of the lower electrode 61 and the upper electrode 62 includes a structure in which two main electrode layers 60a and a sub-electrode layer 60b provided between the two main electrode layers 60a are stacked, and the resistivity of the material of the sub-electrode layer 60b is higher than the resistivity of the material of the main electrode layer 60a. With this configuration, in this embodiment, it is possible to prevent excessive current from flowing through the memory cell 30, as will be described below.

[0045] As already mentioned, when the voltage applied to the selector 50 exceeds the threshold voltage Vth, the selector 50 transitions from the off state to the on state, making it possible to write to or read from the magnetoresistive element 40 connected in series with the selector 50. However, when the selector 50 transitions from the off state to the on state, the resistance of the selector 50 decreases rapidly, causing the overall resistance of the memory cell 30 to also decrease rapidly. As a result, there is a risk that excessive current, such as spike current, may flow through the memory cell 30. When excessive current flows through the memory cell 30 in this way, the characteristics and reliability of the memory cell 30 may deteriorate.

[0046] In this embodiment, at least one of the lower electrode 61 and the upper electrode 62 includes a sub-electrode layer 60b made of a material with a higher resistivity than the material of the main electrode layer 60a. Therefore, even if the resistance of the selector 50 decreases sharply when the selector 50 transitions from the off state to the on state, the high-resistivity sub-electrode layer 60b can suppress a sharp decrease in the overall resistance of the memory cell 30. Consequently, in this embodiment, it is possible to suppress the flow of excessive current to the memory cell 30 when the selector 50 transitions from the off state to the on state, thereby preventing deterioration of the characteristics and reliability of the memory cell 30.

[0047] Figure 7 is a schematic cross-sectional view showing a modified example of the configuration of at least one of the lower electrode 61 and the upper electrode 62.

[0048] As shown in Figure 7, at least one of the lower electrode 61 and the upper electrode 62 may include three or more main electrode layers 60a and two or more auxiliary electrode layers 60b. Each of the auxiliary electrode layers 60b is provided between adjacent main electrode layers (first and second main electrode layers) 60a.

[0049] While three or more main electrode layers 60a are usually formed from the same material, it is not necessary for all three or more main electrode layers 60a to be made from the same material. Similarly, while two or more auxiliary electrode layers 60b are usually formed from the same material, it is not necessary for all two or more auxiliary electrode layers 60b to be made from the same material.

[0050] The same effects as described above can be obtained even when using the electrode configuration shown in Figure 7.

[0051] Furthermore, at least one of the lower electrode 61 and the upper electrode 62 may have the electrode configuration shown in Figures 6 and 7, and the intermediate electrode 63 may also have the electrode configuration shown in Figures 6 and 7.

[0052] Figure 8 is a schematic cross-sectional view showing the configuration of a modified example of the storage device according to this embodiment.

[0053] In the embodiment described above, as shown in Figure 2, the magnetoresistive element 40 is provided on the upper side of the selector 50, the magnetoresistive element 40 is connected to the upper electrode 62, and the selector 50 is connected to the lower electrode 61. In this modified example, as shown in Figure 8, the magnetoresistive element 40 is provided on the lower side of the selector 50, the magnetoresistive element 40 is connected to the lower electrode 61, and the selector 50 is connected to the upper electrode 62.

[0054] In this modified example, the basic configuration is the same as that of the embodiment described above, and it is possible to obtain the same effects as described above.

[0055] In the above-described embodiment, a magnetoresistive element was used as the variable resistance memory element, but other resistance-changing memory elements may also be used as the variable resistance memory element.

[0056] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0057] 10...Lower wiring 20...Upper wiring 30...Memory cells 30m...Main memory section 40…Magnetoresistive element 41...Memory layer 42...Reference layer 43...Tunnel barrier layer 44... Shift-canceling layer 45... Intermediate layer 50...Selector 60a...Main electrode layer 60b...Sub-electrode layer 61...Lower electrode 62...Upper electrode 63...Intermediate electrode

Claims

1. A first wiring extending in the first direction, A second wiring extending in a second direction intersecting the first direction, A memory cell provided between the first wiring and the second wiring, A storage device comprising, The aforementioned memory cell is A main memory section including variable resistance memory elements and two-terminal switching elements stacked in a third direction intersecting the first and second directions, A first electrode is provided between the first wiring and the main memory unit, and is connected to the first wiring and the main memory unit. A second electrode is provided between the second wiring and the main memory unit, and is connected to the second wiring and the main memory unit. Includes, At least one of the first electrode and the second electrode includes a structure in which a first main electrode layer, a second main electrode layer, and a sub-electrode layer provided between the first main electrode layer and the second main electrode layer are stacked in the third direction. The resistivity of the material of the auxiliary electrode layer is higher than the resistivity of the material of the first main electrode layer and the resistivity of the material of the second main electrode layer. A storage device characterized by the following features.

2. Each of the first and second main electrode layers contains at least one element selected from carbon (C), titanium (Ti), tantalum (Ta), and tungsten (W). The storage device according to feature 1.

3. Each of the first and second main electrode layers further contains at least one element selected from nitrogen (N) and silicon (Si). The storage device according to claim 2.

4. Each of the first and second main electrode layers is selected from a C layer, a CN layer, a Ti layer, a Ta layer, a TiN layer, a TaN layer, a TiCN layer, a TiAlN layer, a W layer, a WN layer, a WSi layer, and a WSiN layer. The storage device according to feature 1.

5. The auxiliary electrode layer contains at least one of a metallic element and a semiconductor element, and at least one of oxygen (O) and nitrogen (N). The storage device according to feature 1.

6. The aforementioned metallic and semiconductor elements are selected from tungsten (W), silicon (Si), aluminum (Al), titanium (Ti), indium (In), tantalum (Ta), hafnium (Hf), zinc (Zn), ruthenium (Ru), tin (Sn), magnesium (Mg), zirconium (Zr), and chromium (Cr). The storage device according to feature 5.

7. The auxiliary electrode layer is selected from WSiN layer, WSiO layer, SiN layer, SiO layer, AlO layer, TiN layer, InO layer, WN layer, TaN layer, HfO layer, ZnO layer, RuO layer, SnO layer, MgO layer, ZrN layer, CrN layer, AlN layer, and HfN layer. The storage device according to feature 1.

8. The switching element is made of a material containing silicon (Si) and oxygen (O), a material containing silicon (Si) and nitrogen (N), a material containing hafnium (Hf) and oxygen (O), a material containing tantalum (Ta) and oxygen (O), a material containing titanium (Ti) and oxygen (O), a material containing tungsten (W) and oxygen (O), a material containing zirconium (Zr) and oxygen (O), a material containing aluminum (Al) and oxygen (O), or a material containing nickel (Ni) and oxygen (O). The material includes a switching material layer formed from a material selected from materials containing niobium (Nb) and oxygen (O), arsenic (As) and sulfur (S), zinc (Zn) and tellurium (Te), germanium (Ge) and selenium (Se), germanium (Ge) and arsenic (As), germanium (Ge) and tellurium (Te), carbon (C) and tellurium (Te), and arsenic (As) and tellurium (Te). The storage device according to feature 1.

9. The switching material layer is selected from SiO layer, SiN layer, SiON layer, AsSiO layer, AsSiOTi layer, AsSiOTiN layer, AsSiOTiNC layer, HfO layer, AsHfO layer, TaO layer, TiO layer, WO layer, ZrO layer, AlO layer, NiO layer, NboO layer, AsS layer, ZnTe layer, AsZnTe layer, SiZnTe layer, AsSiZnTe layer, GeSe layer, GeAsSeTe layer, GeAs layer, GeTe layer, CTe layer, SiAsTe layer, SiGeAsTe layer, GeAsTe layer, AsTe layer, and SiGeAsSe layer. The storage device according to feature 1.

10. One of the first and second electrodes is connected to the variable resistance memory element, and the other of the first and second electrodes is connected to the switching element. The storage device according to feature 1.

11. The main memory section further includes a third electrode provided between the variable resistance memory element and the switching element. The storage device according to feature 1.

12. The variable resistance memory element is a magnetoresistive element. The storage device according to feature 1.

13. The switching element has the characteristic of transitioning from an off state to an on state when the voltage applied between its two terminals exceeds a threshold voltage. The storage device according to feature 1.

14. When a voltage is applied between the first and second wirings, causing the switching element to turn on, it becomes possible to write to or read from the variable resistor memory element. The storage device according to feature 1.

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