Semiconductor device and method for manufacturing a semiconductor device

Abstract

To suppress short circuits caused by wire interference. [Solution] The semiconductor device of the embodiment comprises a wiring board, a first semiconductor module arranged on the main surface of the wiring board and having one or more first semiconductor chips stacked on top of it, a wire connecting one of the one or more first semiconductor chips to the wiring board, and a second semiconductor module arranged adjacent to the first semiconductor module on the main surface of the wiring board and having a plurality of second semiconductor chips stacked on top of it, wherein the second semiconductor module has an adhesive layer between the Nth (N is an integer of 1 or more) second semiconductor chip from the bottom layer and the N+1th second semiconductor chip, and at least a portion of the wire is in contact with the adhesive layer.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing a semiconductor device.

Background Art

[0002] For example, there is a semiconductor package in which a plurality of semiconductor modules in which a plurality of memory chips are stacked are mounted on a wiring board via wires. The plurality of semiconductor modules may be mounted close to each other. At this time, a wire extending from one semiconductor module may interfere with an adjacent semiconductor module and cause a short circuit.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] One embodiment aims to provide a semiconductor device and a method for manufacturing a semiconductor device that can suppress a short circuit caused by wire interference.

Means for Solving the Problems

[0005] The semiconductor device of the embodiment comprises a wiring board, a first semiconductor module disposed on the main surface of the wiring board and having one or more first semiconductor chips stacked on top of each other, a wire connecting one of the one or more first semiconductor chips to the wiring board, and a second semiconductor module disposed adjacent to the first semiconductor module on the main surface of the wiring board and having a plurality of second semiconductor chips stacked on top of each other, wherein the second semiconductor module has an adhesive layer between the Nth (N is an integer of 1 or more) second semiconductor chip from the bottom layer and the N+1th second semiconductor chip, and at least a portion of the wire is in contact with the adhesive layer. [Brief explanation of the drawing]

[0006] [Figure 1] A top view showing a schematic configuration example of a semiconductor device according to an embodiment. [Figure 2] A cross-sectional view showing the detailed configuration of a semiconductor device according to an embodiment. [Figure 3] A side view showing the detailed configuration of a semiconductor device according to an embodiment. [Figure 4] A diagram showing an example of the procedure for manufacturing a semiconductor device according to an embodiment. [Figure 5] A diagram showing an example of the procedure for manufacturing a semiconductor device according to an embodiment. [Figure 6] A diagram showing an example of the procedure for manufacturing a semiconductor device according to an embodiment. [Figure 7] A diagram showing an example of the procedure for manufacturing a semiconductor device according to an embodiment. [Figure 8] A diagram showing an example of the procedure for manufacturing a semiconductor device according to an embodiment. [Figure 9] A diagram showing an example of the procedure for manufacturing a semiconductor device according to an embodiment. [Figure 10] A diagram illustrating a semiconductor device according to a modified example 1 of the embodiment. [Figure 11] A diagram illustrating a semiconductor device according to a modified example 2 of the embodiment. [Figure 12]A top view showing a schematic configuration example of a semiconductor device according to modified embodiment 3. [Figure 13] A cross-sectional view showing the detailed configuration of a semiconductor device according to a modified example of the embodiment 3. [Modes for carrying out the invention]

[0007] Embodiments will be described in detail below with reference to the drawings. However, the present invention is not limited to the embodiments described below. Furthermore, the components in the embodiments described below include those that are easily conceivable by those skilled in the art or that are substantially the same.

[0008] [Embodiment] (Example of semiconductor device configuration) Figure 1 is a top view showing a schematic configuration example of a semiconductor device 1 according to an embodiment. However, in Figure 1, some components such as sealing members are omitted from the illustration.

[0009] In this specification, the side on which the first semiconductor module 100 and the second semiconductor module 200 are mounted is considered upward when viewed from the wiring board 10, and the wiring board 10 side is considered downward, with this vertical direction being defined as the Z direction. The X and Y directions are both directions that align with the orientation of the surface of the wiring board 10, and the X and Y directions are mutually orthogonal. The X direction is an example of a third direction. The side in which the arrow of each axis points is considered the positive direction, and the opposite side is considered the negative direction. The positive Y direction is an example of a first direction, and the negative Y direction is an example of a second direction. The positive Z direction is an example of a stacking direction.

[0010] As shown in Figure 1, the semiconductor device 1 is configured as a package in which multiple semiconductor chips are sealed. The semiconductor device 1 comprises a wiring board 10, a first semiconductor module 100, a second semiconductor module 200, and wires W1 and W2.

[0011] On the upper surface 10a, which is the main surface of the wiring board 10, a first semiconductor module 100 and a second semiconductor module 200 are arranged side by side in the X direction. The first semiconductor module 100 and the second semiconductor module 200 each have a structure in which a plurality of semiconductor chips are stacked. The semiconductor chips are small pieces obtained by singulating a Si substrate or the like, and for example, incorporate semiconductor elements not shown in the figure. The semiconductor element is a non-volatile memory such as a NAND flash memory, for example.

[0012] Also, when viewed from the Z direction, on both ends in the Y direction outside the first semiconductor module 100 and the second semiconductor module 200 of the wiring board 10, a plurality of electrodes 11 and electrodes 12 arranged side by side along the X direction are respectively arranged. More specifically, the electrode 11 is arranged at a position biased toward the negative X direction at the end on the negative Y direction side of the wiring board 10. Also, the electrode 12 is arranged at a position biased toward the positive X direction at the end on the positive Y direction side of the wiring board 10. That is, the electrode 11 is located on the negative Y direction side when viewed from the first semiconductor module 100, and the electrode 12 is located on the positive Y direction side when viewed from the second semiconductor module 200.

[0013] The upper surface 10a of the wiring board 10 is covered with a solder resist 20. The plurality of electrodes 11 and the electrodes 12 are respectively exposed from the openings 21 and the openings 22 of the solder resist 20.

[0014] The first semiconductor module 100 has a structure in which semiconductor chips 111 to 118 are stacked so as to shift in the positive Y direction. As a result, at the end on the negative Y direction side of the upper surfaces of the individual semiconductor chips 111 to 117, a portion that does not overlap with the semiconductor chips 112 to 118 directly above occurs. A plurality of electrode pads 121 to 128 arranged side by side in the X direction are respectively provided at this portion and at the end on the negative Y direction side of the upper surface of the uppermost semiconductor chip 118. The electrode pads 121 to 128 are connected to semiconductor elements not shown incorporated in each of the semiconductor chips 111 to 118. Also, a wire W1 extending toward the electrode 11 is connected to each of the electrode pads 121 to 128.

[0015] The second semiconductor module 200 has a stacked structure in which semiconductor chips 211 to 218 are shifted in the negative Y direction. As a result, at the end portions on the positive Y-direction side of the upper surfaces of the individual semiconductor chips 211 to 217, portions that do not overlap with the semiconductor chips 212 to 218 directly above are formed. A plurality of electrode pads 221 to 228 arranged in the X direction are provided at these portions and at the end portions on the positive Y-direction side of the upper surface of the uppermost semiconductor chip 218, respectively. Further, a wire W2 extending toward the electrode 12 is connected to each of the electrode pads 221 to 228.

[0016] The wires W1 and W2 are made of, for example, at least one of metal materials such as Au, Cu, Pd, Cu, and Ag. The wires W1 and W2 connect the electrode pads 121 to 128 and the electrode pads 221 to 228 provided in the first semiconductor module 100 and the second semiconductor module 200, respectively, to the electrode 11 and the electrode 12. Thereby, the wiring board 10, the first semiconductor module 100, and the second semiconductor module 200 are electrically connected.

[0017] The wiring board 10, the first semiconductor module 100, the second semiconductor module 200, and the wires W1 and W2 are covered with a sealing member not shown in the figure.

[0018] FIG. 2 is a cross-sectional view showing a detailed configuration of the semiconductor device 1 according to the embodiment. More specifically, FIG. 2(a) is a cross-sectional view taken along the line AA in FIG. 1. That is, FIG. 2(a) is a cross-sectional view of the semiconductor device 1 including the second semiconductor module 200. Further, FIG. 2(b) is a view showing a cross-section taken along the line AA in FIG. 1 with a cross-section taken along the line BB in FIG. 1 superimposed. That is, FIG. 2(b) is a view in which a cross-sectional view of the semiconductor device 1 including the first semiconductor module 100 and a cross-section of the semiconductor device 1 including the second semiconductor module 200 are superimposed. In FIG. 2(b), for the sake of clarity, the configuration included in the second semiconductor module 200 may be shown by a broken line and some hatching may be omitted.

[0019] As shown in Figures 2(a) and (b), the wiring board 10 is constructed as a multilayer substrate in which an insulating layer 16 and a conductive layer 17 are alternately laminated multiple times. The wiring board 10 also includes electrodes 11 and 12.

[0020] The insulating layer 16 is composed of carbon fibers, glass fibers, or aramid fibers, for example, that have been impregnated with a thermosetting resin such as epoxy resin before curing.

[0021] The conductive layer 17, and electrodes 11 and 12 are made of a metal such as Cu. The conductive layer 17 has a wiring pattern and is connected to electrodes 11 and 12, respectively. Electrodes (not shown) located on the lower surface of the wiring board 10 are electrically connected to an external power supply such as a host computer via a motherboard or the like.

[0022] Spacers 31 and 32 are provided on the upper surface 10a of the wiring board 10. Spacers 31 and 32 are small pieces of Si substrate or the like. Spacer 31 supports the first semiconductor module 100 on its upper surface, and spacer 32 supports the second semiconductor module 200 on its upper surface. As a result, spaces are formed between the upper surface 10a of the wiring board 10 and the lower surfaces of the first semiconductor module 100 and the second semiconductor module 200, respectively.

[0023] A controller 51 is provided in the space formed by spacers 31 and 32. The controller 51 incorporates an integrated circuit capable of controlling the operation of the first semiconductor module 100 and the second semiconductor module 200. The controller 51 is connected to the conductive layer 17 via electrodes 53. This electrically connects the controller 51 and the wiring board 10.

[0024] As shown in Figure 2(a), the second semiconductor module 200 has a configuration in which semiconductor chips 211 to 218 are stacked in order from bottom to top. As described above, the semiconductor chips 211 to 218 are stacked so as they move upward, they shift toward the negative direction of Y. Semiconductor chips 211 to 218 are examples of the second semiconductor chip.

[0025] For example, semiconductor chip 212 is positioned on the top surface of the bottom semiconductor chip 211, slightly shifted in the negative Y direction relative to semiconductor chip 211. Furthermore, semiconductor chip 213 is positioned on the top surface of semiconductor chip 212, further shifted in the negative Y direction relative to semiconductor chip 212.

[0026] However, in semiconductor chip 215, the shift direction between semiconductor chip 214 and semiconductor chip 215 is different. That is, semiconductor chip 215 is positioned on the upper surface of semiconductor chip 214, shifted in the positive Y direction as viewed from semiconductor chip 214. As a result, the Y-positive side edge of the upper surface of semiconductor chip 214 is covered by semiconductor chip 215. Furthermore, by being positioned in a shifted position in the positive Y direction, the distance between semiconductor chip 215 and each of the semiconductor chips 216-218 stacked on semiconductor chip 215 and the electrode 12 is shortened. Consequently, the length of the wire W2 connecting them is shortened. As a result, the electrical characteristics of semiconductor device 1 are improved.

[0027] In this embodiment, an example is shown where the shift direction between semiconductor chip 214 and semiconductor chip 215 is different in semiconductor chip 215, but this is not limited to this example. The shift direction may be different in any of the semiconductor chips 211 to 218.

[0028] Adhesive layers 241 to 248 are provided on the underside of each of the semiconductor chips 211 to 218. The adhesive layers 241 to 248 are also called die attach films (DAFs) and are thermosetting resins molded into a film.

[0029] For example, among the adhesive layers 241 to 248, the bottommost adhesive layer 241, located on the underside of the semiconductor chip 211, adheres the semiconductor chip 211 to the upper surface of the spacer 32. The second-to-last adhesive layer 242 adheres the semiconductor chip 212 to the upper surface of the semiconductor chip 211. In this way, the adhesive layers 242 to 248 are interposed between adjacent semiconductor chips 211 to 218, adhering them to each other.

[0030] Of the adhesive layers 241-248, the thickness of adhesive layer 245, which is provided on the underside of the semiconductor chip 215, is greater than the thicknesses of adhesive layers 241-244, 246, and 247. This is to embed the wire 324 extending from the electrode pad 224, which will be described later. Similarly, the thickness of the uppermost adhesive layer 248, which is provided on the underside of the semiconductor chip 218, is also greater than the thicknesses of adhesive layers 241-244, 246, and 247. This is to embed the wire 315 extending from the electrode pad 125, which will be described later. The thicknesses of adhesive layers 245 and 248 are, for example, 20 μm or more, while the thicknesses of the other adhesive layers are, for example, 10 μm.

[0031] Electrode pads 221 to 228 are provided at the positive Y-direction ends of the upper surfaces of each semiconductor chip 211 to 218. Wires 321 to 328 are connected to electrode pads 221 to 228, respectively. Wires 321 to 328 are examples of wire W2 (Figure 1).

[0032] Wires 321-328 connect adjacent electrode pads 221-228 to each other, and to electrode 12 with any of the electrode pads 221-228. Each of the wires 321-328 extends upward from each of the electrode pads 221-228, curves downward at a certain height, and connects to other electrode pads or electrode 12. Each of the wires 321-328 is formed by a wire bonding method.

[0033] For example, a wire 328 extending from electrode pad 228 curves above electrode pad 228 and connects to the electrode pad 227 below it. Also, for example, a wire 327 extending from electrode pad 227 curves above electrode pad 227 and connects to the electrode pad 226 below it. Also, for example, a wire 325 extending from electrode pad 225 curves above electrode pad 225 and connects to electrode 12.

[0034] For example, wire 324 connects electrode pad 224 and electrode pad 223. At least a portion of wire 324 is embedded in adhesive layer 245 provided on the underside of semiconductor chip 215. This is because, due to the different shift directions between semiconductor chip 214 and semiconductor chip 215, the end of the upper surface of semiconductor chip 214 on the positive Y side is covered by semiconductor chip 215. The diameter of wire 324 is, for example, 18 μm. Therefore, wire 324 can be embedded in adhesive layer 245 having a layer thickness of, for example, 20 μm.

[0035] As shown in Figure 2(b), the first semiconductor module 100 has a configuration in which semiconductor chips 111 to 118 are stacked in order from bottom to top. As described above, the semiconductor chips 111 to 118 are stacked so as they move upward, they shift toward the positive direction of Y. Semiconductor chips 111 to 118 are examples of the first semiconductor chips.

[0036] Furthermore, in semiconductor chip 115, the shift direction between semiconductor chip 114 and semiconductor chip 115 is different. That is, semiconductor chip 115 is positioned on the upper surface of semiconductor chip 114, shifted in the negative Y direction relative to semiconductor chip 114. As a result, the edge of the upper surface of semiconductor chip 114 on the negative Y direction side is covered by semiconductor chip 115.

[0037] Although eight semiconductor chips are stacked here, the number of stacked semiconductor chips is not limited to this. For example, the first semiconductor module 100 may have one semiconductor chip.

[0038] Adhesive layers 141 to 148 are provided on the underside of each semiconductor chip 111 to 118. The adhesive layers 141 to 148 are, for example, die attach films. The adhesive layers 141 to 148 are interposed between adjacent semiconductor chips 111 to 118, bonding them together.

[0039] Of the adhesive layers 141 to 148, the thickness of adhesive layer 145, which is provided on the underside of the semiconductor chip 115, is greater than that of the other adhesive layers. This is to embed the wire 314 extending from the electrode pad 124, which will be described later.

[0040] Electrode pads 121 to 128 are provided at the negative Y-direction ends of the upper surfaces 111a to 118a, which serve as the first surfaces of the semiconductor chips 111 to 118. Wires 311 to 318 are connected to electrode pads 121 to 128, respectively. Wires 311 to 318 are examples of wire W1 (Figure 1).

[0041] From this point forward, if there is no need to distinguish between wires 311 and 318 individually, they may be collectively referred to as wire W1, and if there is no need to distinguish between wires 321 and 328 individually, they may be collectively referred to as wire W2.

[0042] Wires 311-318 connect adjacent electrode pads 121-128 to each other, and to electrode 11 with any of the electrode pads 121-128. Each of the wires 311-318 extends upward from each of the electrode pads 121-128, curves downward at a certain height, and connects to other electrode pads or electrode 11. Each of the wires 311-318 is formed by a wire bonding method.

[0043] For example, a wire 318 extending from electrode pad 128 curves above electrode pad 128 and connects to the electrode pad 127 below it. Also, for example, a wire 317 extending from electrode pad 127 curves above electrode pad 127 and connects to the electrode pad 126 below it.

[0044] For example, the wire 315 extending from the electrode pad 125 curves above the electrode pad 125 and connects to the electrode 11. The height at which the wire 315 curves, that is, the height at the upper end 315a of the wire 315, is approximately equal to the height at the adhesive layer 248 of the second semiconductor module 200. As will be described in detail later, the upper end 315a of the wire 315 is embedded in the adhesive layer 248.

[0045] The height of the upper end 315a of wire 315 is, for example, 100 μm above the upper surface 115a of the semiconductor chip 115. Wire 315 is longer than the other wires connecting the electrode pads 121 to 128.

[0046] The first semiconductor module 100, the second semiconductor module 200, the wires 311-318, the wires 321-328, and the wiring board 10 are all covered by a sealing member 500.

[0047] Next, using Figure 3, we will describe the detailed configuration of the wires 311 to 318 connected to each of the semiconductor chips 111 to 118.

[0048] Figure 3 is a side view showing the detailed configuration of the semiconductor device 1 according to the embodiment. More specifically, Figure 3(a) is a side view of the semiconductor device 1 viewed from the negative Y direction. Figure 3(b) is a partially enlarged view of the framed area A in Figure 3(a), and Figure 3(c) is a view of the configuration included in the framed area A in Figure 3(a) viewed from the negative X direction. Note that in Figures 3(a) to (c), some components such as the sealing member 500 are not shown.

[0049] As shown in Figure 3(a), multiple wires 311 to 318 extend from each of the upper surfaces 111a to 118a of the semiconductor chips 111 to 118. For example, from the upper surface 115a of semiconductor chip 115, wires 315-1 to 315-k (where k is an integer greater than or equal to 1) extend as wire 315. Each of wires 315-1 to 315-k is connected to electrodes 11-1 to 11-k, which serve as electrode 11.

[0050] Each of the wires 315-1 to 315-k is arranged in this order from the end on the positive X side of the upper surface 115a of the semiconductor chip 115, with a predetermined or greater spacing between them. As a result, as shown in Figure 3(a), a portion of wire 315-1, which is positioned closest to the second semiconductor module 200, may extend outwards towards the second semiconductor module 200.

[0051] Incidentally, in order to miniaturize the semiconductor device 1, it is desirable to arrange the first semiconductor module 100 and the second semiconductor module 200 in close proximity on the wiring board 10. However, if the first semiconductor module 100 and the second semiconductor module 200 are arranged in close proximity, there is a risk that a portion of the wire W1 extending from the first semiconductor module 100 may interfere with the second semiconductor module 200. For example, as shown in Figure 3(a), if the second semiconductor module 200 has semiconductor chips 211 to 218, if the wire W1 extending from the first semiconductor module 100 interferes with any side of the semiconductor chips 211 to 218, a short circuit may occur between the first semiconductor module 100 and the second semiconductor module 200.

[0052] Interference of wire W1 with the second semiconductor module 200 can occur, for example, during the formation of wire W1 or during sealing by the sealing member 500. This is because wire W1 may bend during its formation or shift position during sealing. Such bending or shifting of wire W1 becomes more pronounced as the length of wire W1 increases.

[0053] Therefore, in the semiconductor device 1 of this embodiment, as shown in Figure 3(a), a portion of the wire W1 extending from the first semiconductor module 100 is embedded in the adhesive layer of the second semiconductor module 200. Specifically, for example, a portion of the wire 315-1 extending from the upper surface 115a of the semiconductor chip 115 is embedded in the adhesive layer 248 provided between the semiconductor chip 218 and the semiconductor chip 217 of the second semiconductor module 200.

[0054] More specifically, as shown in Figures 3(b) and (c), the wire 315-1 is embedded in the portion of the adhesive layer 248 that does not overlap with the semiconductor chip 217 directly beneath it. The wire 315-1 extends through the space between the side surface 248a of the adhesive layer 248 on the negative X-direction side and the portion of the bottom surface 248b of the adhesive layer 248 that does not overlap with the semiconductor chip 217.

[0055] As a result, since the wire 315-1 is supported by the adhesive layer 248, it is possible to prevent the wire 315-1 from bending or shifting. This prevents the wire 315-1 from interfering with the second semiconductor module 200, even when the first semiconductor module 100 and the second semiconductor module 200 are placed in close proximity. As a result, it is possible to prevent a short circuit between the first semiconductor module 100 and the second semiconductor module 200.

[0056] In this embodiment, an example in which the wire 315-1 is embedded in the adhesive layer 248 has been described, but the wire 315-1 does not necessarily have to be embedded in the adhesive layer 248. It is sufficient that at least a part of the wire 315-1 is in contact with the adhesive layer 248.

[0057] More specifically, for example, when viewing a cross-section including the lower surface 248b of the adhesive layer 248, a portion of the lower surface 248b may be recessed upwards, and a portion of the cross-section of the wire 315-1 may be embedded in the recessed portion. In other words, a portion of the cross-section of the wire 315-1 may be fitted into the recessed portion of the lower surface 248b. Alternatively, for example, a portion of the lower surface 248b may not be recessed at all. It is sufficient that a portion of the lower surface 248b and a portion of the cross-section of the wire 315-1 are in contact when viewing a cross-section including the lower surface 248b of the adhesive layer 248. Embedding is one example of contact.

[0058] As mentioned above, the thickness of the adhesive layer 248 is preferably 20 μm or more, and more preferably 40 μm to 60 μm. The diameter of the wire 315-1 is, for example, 18 μm. Therefore, the wire 315-1 can be embedded in the adhesive layer 248.

[0059] (Method of manufacturing semiconductor devices) Figures 4-9 show an example of the procedure for manufacturing the semiconductor device 1 according to the embodiment. More specifically, Figures 4(a) to 9(a) are top views of the wiring board 10 as seen from the positive Z direction, and correspond to Figure 1. Figures 4(b) to 9(b) are diagrams showing the cross-sections along lines AA and BB of Figure 1 superimposed, and correspond to Figure 2(b). In Figures 4(b) to 9(b), for ease of viewing, the components included in the second semiconductor module 200 are shown with dashed lines, and some hatching may be omitted.

[0060] In Figures 4(a) and 4(b), first, multiple electrodes 11 and 12 are formed on the wiring board 10. Specifically, multiple electrodes 11 are formed at the negative Y-direction end of the wiring board 10, at a position biased toward the negative X-direction, and multiple electrodes 12 are formed at the positive Y-direction end, at a position biased toward the positive X-direction. Next, the wiring board 10 is covered with solder resist 20, and openings 21 and 22 are formed in the portions overlapping with the multiple electrodes 11 and 12. As a result, electrodes 11 and 12 are exposed on the upper surface 10a of the wiring board 10.

[0061] Next, the semiconductor chip 111 is placed on the upper surface 10a of the wiring board 10. At this time, the semiconductor chip 111 is positioned so that the electrode pad 121 formed on the negative Y-direction end of the upper surface 111a of the semiconductor chip 111 faces the electrode 11.

[0062] As shown in Figure 4(b), an adhesive layer 141 is provided on the lower surface of the semiconductor chip 111. The adhesive layer 141 is bonded to the upper surface of the spacer 31.

[0063] The controller 51 is connected to the upper surface 10a of the wiring board 10 before the semiconductor chip 111 is placed.

[0064] In Figures 5(a) and (b), semiconductor chips 112 to 114 are stacked on semiconductor chip 111, up to the fourth layer from the bottom. At this time, semiconductor chips 112 to 114 are stacked sequentially while shifting toward the positive direction of Y so as not to overlap with the electrode pads 121 to 123 formed on the negative Y-direction ends of the upper surfaces 111a to 113a of semiconductor chips 111 to 113a.

[0065] As shown in Figure 5(b), each of the semiconductor chips 111 to 114 is fixed to each other by adhesive layers 142 to 144 provided on the lower surface of each of the semiconductor chips 112 to 114. In this way, the first lower module is formed. The first lower module is the portion of the first semiconductor module 100 that includes the semiconductor chips 111 to 114. The semiconductor chips 111 to 114 are the lower semiconductor chips of the semiconductor chips 111 to 118.

[0066] In Figures 6(a) and 6(b), first, the semiconductor chip 211 is placed on the upper surface 10a of the wiring board 10, at a position on the positive X direction side as viewed from the semiconductor chips 111 to 114. At this time, the semiconductor chip 211 is positioned so that the electrode pad 221 formed on the positive Y direction end of the upper surface of the semiconductor chip 211 faces the multiple electrodes 12 of the wiring board 10.

[0067] As shown in Figure 6(b), an adhesive layer 241 is provided on the lower surface of the semiconductor chip 211. The adhesive layer 241 is bonded to the upper surface of the spacer 32.

[0068] Next, semiconductor chips 212 to 214, starting from the bottom layer and counting to the fourth layer, are stacked on semiconductor chip 211. At this time, semiconductor chips 212 to 214 are stacked while shifting them toward the negative direction of Y so as not to overlap with electrode pads 221 to 223 formed on the positive Y-direction ends of the upper surfaces of semiconductor chips 211 to 213. Each of the semiconductor chips 212 to 214 is fixed to each other by adhesive layers 242 to 244 provided on the lower surface of each semiconductor chip 212 to 214. In this way, the second lower module is formed. The second lower module is the portion of the second semiconductor module 200 that includes semiconductor chips 211 to 214, starting from the bottom layer and counting to the fourth layer.

[0069] Next, wires 311-314 (W1) and 321-324 (W2) are formed using a wire bonding method. This electrically connects semiconductor chips 111-114 and 211-214 with the wiring board 10.

[0070] In Figures 7(a) and 7(b), semiconductor chips 115 to 118 are stacked on semiconductor chip 114. Specifically, as shown in Figure 7(b), first, semiconductor chip 115 is placed on the upper surface 114a of semiconductor chip 114 at a position shifted in the negative Y direction relative to semiconductor chip 114. Semiconductor chip 115 is fixed to semiconductor chip 114 by an adhesive layer 145 provided on the lower surface of semiconductor chip 115. At this time, the wire 314 extending from the electrode pad 124 is embedded in the adhesive layer 145.

[0071] Next, semiconductor chips 116 to 118 are stacked on semiconductor chip 115 while shifting them in the positive direction of Y. As shown in Figure 7(b), each of the semiconductor chips 115 to 118 is fixed to each other by adhesive layers 146 to 148 provided on the lower surface of semiconductor chips 116 to 118. In this way, the first upper module is formed on the first lower module described above. The first upper module is the portion of the first semiconductor module 100 that includes semiconductor chips 115 to 118. Semiconductor chips 115 to 118 are the upper semiconductor chips of semiconductor chips 111 to 118.

[0072] Next, as shown in Figure 7(b), wires 315-318 (W1) are formed by the wire bonding method. This electrically connects the first semiconductor module 100 and the wiring board 10. Wires 315-318 (W1) are an example of the first wires.

[0073] Furthermore, when forming the wire 315, for example, the wire 315 is extended upward from the upper surface 115a of the semiconductor chip 115, curved downward at a height h from the upper surface 115a to form the upper end portion 315a, and connected to the electrode 11. The height h is, for example, 100 μm. This ensures that when the adhesive layer 248 is formed later, the height position of the adhesive layer 248 and the height position of the upper end portion 315a of the wire 315 are approximately equal.

[0074] In Figures 8(a) and 8(b), semiconductor chips 215 to 218 are stacked on semiconductor chip 214. Specifically, first, semiconductor chip 215 is placed on the upper surface of semiconductor chip 214 at a position shifted in the positive Y direction relative to semiconductor chip 214. Semiconductor chip 215 is fixed to semiconductor chip 214 by an adhesive layer 245 provided on the lower surface of semiconductor chip 215. At this time, although not shown in the figure, wire 324 extending from semiconductor chip 214 is embedded in the adhesive layer 245.

[0075] Next, semiconductor chips 216 to 217 are stacked on semiconductor chip 215 while shifting them in the negative direction of Y. Each of the semiconductor chips 215 to 217 is fixed to the others by adhesive layers 246 to 247 provided on the underside of semiconductor chips 216 to 217.

[0076] Next, a semiconductor chip 218 is stacked on the semiconductor chip 217 while shifting it in the negative direction of Y. At this time, the upper end 315a of the wire 315 (wire 315-1 in Figure 3(a)) extending from the upper surface 115a of the semiconductor chip 115 is embedded in the adhesive layer 248 provided on the lower surface of the semiconductor chip 218. As a result, the wire 315 is supported by the adhesive layer 248. In this way, a second upper module is formed on the second lower module described above. The second upper module is the portion of the second semiconductor module 200 that includes semiconductor chips 215 to 218 from the fourth layer from the bottom upwards.

[0077] Next, as shown in Figure 9(b), wires 325-328 (wire W2) are formed by the wire bonding method. This electrically connects the second semiconductor module 200 and the wiring board 10. Note that, for convenience, wires 326 and 327 are omitted from the illustration in Figure 9(b).

[0078] Next, the wiring board 10, the first semiconductor module 100, the second semiconductor module 200, and the wires W1 and W2 are covered with the sealing member 500. This completes the manufacturing of the semiconductor device 1 according to the embodiment.

[0079] [Summary] The semiconductor device 1 of this embodiment includes a first semiconductor module 100 and a second semiconductor module 200, which are arranged adjacent to the upper surface 10a of a wiring board 10. The first semiconductor module 100 has a configuration in which semiconductor chips 111 to 118 are stacked. At least one of the semiconductor chips 111 to 118 is connected to the wiring board 10 by a wire W1. The second semiconductor module 200 has a configuration in which semiconductor chips 211 to 218 are stacked. The second semiconductor module 200 has an adhesive layer 248 between, for example, semiconductor chips 217 and 218 among the semiconductor chips 211 to 218. At least a portion of the wire W1 extending from the first semiconductor module 100 is in contact with the adhesive layer 248 of the second semiconductor module 200.

[0080] As a result, the wire W1 is supported by the adhesive layer 248, which suppresses interference between the wire W1 and the semiconductor chips 211-218. This suppresses short circuits between the first semiconductor module 100 and the second semiconductor module 200.

[0081] Furthermore, by suppressing short circuits between the first semiconductor module 100 and the second semiconductor module 200, the degree of freedom in the placement of the first semiconductor module 100 and the second semiconductor module 200 is improved. For example, the distance between the first semiconductor module 100 and the second semiconductor module 200 can be further reduced. This makes it possible to further miniaturize the semiconductor device 1.

[0082] [Example 1] A modified example of the embodiment will be described using Figure 10.

[0083] In the above-described embodiment, the wire 315-1 extending from the first semiconductor module 100 is embedded in an adhesive layer 248 provided on the lower surface of the semiconductor chip 218 of the second semiconductor module 200. However, the embedding destination of the wire 315-1 is not limited to the adhesive layer 248. In Modification 1, the embedding destination of the wire 315-1 differs from that of the above-described embodiment. In the following, components similar to those in the above-described embodiment are denoted by the same reference numerals, and their descriptions may be omitted.

[0084] Figure 10 is a diagram illustrating a semiconductor device 2 according to a modified example 1 of the embodiment. More specifically, Figure 10 is a side view of the semiconductor device 2 according to the modified example 1, viewed from the negative direction of Y, and corresponds to Figure 3(a). In Figure 10, however, some components, such as the sealing member 500, are not shown.

[0085] As shown in Figure 10, in the semiconductor device 2 of Modified Example 1, the layer thickness of semiconductor chip 216, for example, is greater than that of the other semiconductor chips 211 to 218. As a result, the height position of the adhesive layer 247 provided on the lower surface of semiconductor chip 217, which is stacked on semiconductor chip 216, is raised by the amount of the increase in the layer thickness of semiconductor chip 216. Consequently, the height position of the adhesive layer 247 and the height position of the upper end 315a of the wire 315-1 become approximately equal. This makes it possible to embed the wire 315-1 in adhesive layer 247, which is different from adhesive layer 248.

[0086] The semiconductor device 2 of the modified example 1 provides the same effects as the semiconductor device 1 of the embodiment described above.

[0087] [Differentiation 2] A modified example of the embodiment, part 2, will be described using Figure 11.

[0088] In the above-described modification 1, the embedding location of the wire 315-1 was changed by changing the layer thickness of the semiconductor chip 216. In contrast, in modification 2, the adhesive layer at the embedding location is changed to match the height position of the upper end portion 315a of the wire 315-1. In the following, components similar to those in the above-described embodiment and modification 1 are denoted by the same reference numerals, and their descriptions may be omitted.

[0089] Figure 11 is a diagram illustrating a semiconductor device 3 according to a modified example 2 of the embodiment. More specifically, Figure 11 is a side view of the semiconductor device 3 according to modified example 2, viewed from the negative direction of Y, and corresponds to Figure 10. Note that in Figure 11 as well, some components such as sealing members are omitted from the illustration.

[0090] As shown in Figure 11, in the semiconductor device 3 of Modified Example 2, the height position of the upper end 315a of the wire 315-1 is lower. Also, the thickness of the adhesive layer 247 is greater than the thickness of the adhesive layers 241-244, 246, and 248. In the above embodiment, as shown in Figure 3(a), etc., the wire 315-1 extended from the upper surface 115a of the semiconductor chip 115 in a direction that forms, for example, 80-90° with respect to the upper surface 115a. In contrast, in Modified Example 2, the position of the electrode 11-1 to which the wire 315-1 is connected has moved to the positive X side, as shown in Figure 11. Therefore, as shown in Figure 11, the wire 315-1 extends from the upper surface 115a of the semiconductor chip 115 in a direction that forms, for example, 45° with respect to the upper surface 115a. This makes it possible to lower the height position of the upper end 315a of the wire 315-1. As a result, the height position of the upper end 315a of the wire 315-1 becomes approximately equal to the height position of the adhesive layer 247. Therefore, it becomes possible to embed the wire 315-1 in adhesive layer 247, which is different from adhesive layer 248. In other words, the thickness of any of the adhesive layers 241 to 248 that is approximately equal to the height position of the upper end 315a of the wire 315-1 can be selectively increased, and the wire 315-1 can be embedded in it. For example, if the height position of the upper end 315a of the wire 315-1 is approximately equal to the height position of adhesive layer 246, the wire 315-1 may be embedded in adhesive layer 246. In that case, the thickness of adhesive layer 246 is greater than the thickness of adhesive layers 241 to 244 and 247 to 248.

[0091] Thus, even if, for example, the position of the electrode 11-1 to which the wire 315-1 is connected moves along the X direction compared to the first embodiment and modified example 1, the embedding destination of the upper end 315a of the wire 315-1 can be adjusted. That is, it is possible to increase the thickness of either the angle θ with respect to the upper surface 115a or the height position of the adhesive layer included in the second semiconductor module 200, and select it as the embedding destination.

[0092] The semiconductor device 3 of the modified example 2 provides the same effects as the semiconductor device 1 of the above-described embodiment.

[0093] In the embodiments and modifications 1 and 2 described above, examples were given in which the wire 315-1 is embedded in an arbitrary adhesive layer, but this is not limited to this. Any wire W1 extending from any of the semiconductor chips 111 to 118 may be embedded in the adhesive layer.

[0094] [Difference 3] A third modified example of the embodiment will be described using Figures 12-13.

[0095] In the semiconductor device 4 of the modified example 3, the arrangement direction of the first semiconductor module 100 and the second semiconductor module 200 differs from that of the embodiment described above. In the following description, components similar to those in the embodiment described above are denoted by the same reference numerals, and their descriptions may be omitted.

[0096] Figure 12 is a top view showing a schematic configuration example of a semiconductor device 4 according to the third modified embodiment. More specifically, Figure 12 corresponds to Figure 1. Figure 13 is a cross-sectional view showing the detailed configuration of the semiconductor device 4 according to the third modified embodiment. More specifically, Figure 13 is a cross-section along the CC line in Figure 12.

[0097] As shown in Figures 12 and 13, a first semiconductor module 100 and a second semiconductor module 200 are arranged side by side in the Y direction on the upper surface 10a of the wiring board 10. Specifically, the first semiconductor module 100 is positioned on the positive Y direction side of the upper surface 10a of the wiring board 10, and the second semiconductor module 200 is positioned on the negative Y direction side as viewed from the first semiconductor module 100. In addition, multiple electrodes 11 are positioned on the negative Y direction side as viewed from the first semiconductor module 100, and multiple electrodes 12 are positioned on the negative Y direction side as viewed from the second semiconductor module 200.

[0098] The semiconductor chips 111-118 and 211-218 are stacked such that they shift toward the positive direction of Y as they extend upwards. Electrode pads 121-128 and 221-228 (Figure 12) are provided at the negative Y-direction ends of the top surfaces 111a-118a of semiconductor chips 111-118 and the top surfaces of semiconductor chips 211-218, respectively. Wires 311-318 and 321-328 (Figure 13) are connected to the electrode pads 121-128 and 221-228, respectively. Wires 311-318 and 321-328 extend toward the negative Y direction and are connected to electrodes 11 and 12, respectively.

[0099] As shown in Figure 13, at least a portion of the wire 315 extending from the negative Y-direction end of the upper surface 115a of the semiconductor chip 115 is embedded in the adhesive layer 248 of the second semiconductor module 200. This supports the wire 315 in the adhesive layer 248.

[0100] The semiconductor device 4 of the modified example 3 provides the same effects as the embodiment described above.

[0101] [Other variations] In the embodiments and modifications described above, for example, the adhesive layers 247 and 248 were provided on the lower surfaces of the semiconductor chips 217 and 218, respectively, but this is not limited to this. For example, adhesive layers may be provided on the sides of the semiconductor chips 217 and 218, and the wire 315 may be embedded in the adhesive layer.

[0102] Furthermore, although the above-described embodiments and modifications describe an example in which one wire 315 is embedded in the adhesive layer 248, this is not limited to this. For example, multiple wires 315 may be embedded in the adhesive layer 248. Also, the adhesive layers to which the multiple wires are embedded may be different.

[0103] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0104] 1-4... Semiconductor device, 10... Wiring board, 10a... Top surface, 11,12... Electrodes, 100... First semiconductor module, 111-118, 211-218... Semiconductor chip, 112a-118a... Top surface, 141-148, 241-248... Adhesive layer, 200... Second semiconductor module, 311-318, 321-328... Wires.

Claims

1. Wiring board and A first semiconductor module is arranged on the main surface of the wiring board and has one or more first semiconductor chips stacked on it, A wire connecting one of the one or more first semiconductor chips and the wiring board, A second semiconductor module is arranged adjacent to the first semiconductor module on the main surface of the wiring board, and a plurality of second semiconductor chips are stacked on top of each other. Equipped with, The second semiconductor module is Among the plurality of second semiconductor chips, there is an adhesive layer between the Nth (where N is an integer greater than or equal to 1) second semiconductor chip from the bottom layer and the (N+1)th second semiconductor chip. At least a portion of the aforementioned wire is In contact with the aforementioned adhesive layer, Semiconductor equipment.

2. The first semiconductor module includes: Multiple first semiconductor chips are stacked on top of each other. The semiconductor device according to claim 1.

3. The aforementioned wire is Extending from the first surface of the one or more first semiconductor chips facing the stacking direction, The semiconductor device according to claim 2.

4. The aforementioned plurality of first semiconductor chips are They are stacked so as to be shifted in a first direction along the main surface, The aforementioned wire is Extending from the end of the first surface of the plurality of first semiconductor chips in a second direction opposite to the first direction, The aforementioned plurality of second semiconductor chips are They are stacked so as to shift in the second direction, The first and second semiconductor modules are, Intersecting the first and second directions and adjacent to the third direction along the main surface, The semiconductor device according to claim 3.

5. The aforementioned plurality of first semiconductor chips are They are stacked so as to be shifted in a first direction along the main surface, The aforementioned wire is Extending from the end of the first surface of the plurality of first semiconductor chips in a second direction opposite to the first direction, The aforementioned plurality of second semiconductor chips are They are stacked so as to shift in the first direction, The second semiconductor module is Adjacent to the first semiconductor module in the second direction, The semiconductor device according to claim 3.

6. The second semiconductor module is The plurality of adhesive layers, including the adhesive layer, are located between the plurality of second semiconductor chips. Of the plurality of adhesive layers, the thickness of one adhesive layer is greater than the thickness of at least one other adhesive layer. The semiconductor device according to claim 4 or 5.

7. At least a portion of the aforementioned wire is The adhesive layer is embedded in the aforementioned adhesive layer, The semiconductor device according to claim 4 or 5.

8. A first semiconductor module is formed on the main surface of a wiring board, in which one or more first semiconductor chips are stacked. A wire is formed to connect each of the one or more first semiconductor chips to the wiring board. A second semiconductor module is formed on the main surface of the wiring board at a position adjacent to the first semiconductor module, in which a plurality of second semiconductor chips are stacked. Forming the semiconductor module described above (2) is An adhesive layer is formed between the Nth (where N is an integer greater than or equal to 1) second semiconductor chip from the bottom layer and the N+1th second semiconductor chip, The adhesive layer is brought into contact with at least a portion of the wire, including, A method for manufacturing a semiconductor device.

9. Forming the first semiconductor module is This includes stacking a plurality of first semiconductor chips so as to be shifted in a first direction along the main surface, Forming the aforementioned wire is This includes connecting the wire to the end of the first surface of the plurality of first semiconductor chips facing the stacking direction, in a second direction opposite to the first direction, Forming the semiconductor module described above (2) is This includes stacking the plurality of second semiconductor chips so as to be shifted in the second direction, The method for manufacturing a semiconductor device according to claim 8.

10. The first semiconductor module is The plurality of first semiconductor chips include a first lower module containing a lower layer first semiconductor chip and a first upper module containing an upper layer first semiconductor chip, The second semiconductor module is The plurality of second semiconductor chips includes a second lower module containing the second semiconductor chips from the bottom layer up to the Lth (where L is an integer of 1 or more) which is smaller than N, and a second upper module containing the second semiconductor chips above the Lth, Forming the first semiconductor module is The first lower module is formed on the main surface, After the second lower module is formed at a position adjacent to the first lower module on the main surface, the first upper module is formed on the first lower module. Includes, Forming the aforementioned wire is To form a first wire that connects each of the first semiconductor chips included in the first upper module to the wiring board, Includes, Forming the semiconductor module described above (2) is The second lower module is formed at a position adjacent to the first lower module on the main surface, After the first wire is formed, the second upper module is formed on the second lower module, The adhesive layer is formed between the Nth second semiconductor chip and the N+1th second semiconductor chip from the bottom layer among the second semiconductor chips included in the second upper module, The adhesive layer is brought into contact with at least a portion of the first wire, including, The method for manufacturing a semiconductor device according to claim 9.

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