Pressure-contact semiconductor device

Abstract

To improve the reliability of pressure-contact semiconductor devices. [Solution] The pressure-contact semiconductor device comprises a first electrode, a second electrode, a pair of metal plates disposed between the first electrode and the second electrode, a semiconductor element located between the pair of metal plates and having a semiconductor portion and an electrode portion disposed on the upper surface of the semiconductor portion and having an upper surface having a smaller area than the lower surface of the metal plates, and a metal sintered layer disposed between one of the pair of metal plates and the electrode portion.

Description

Technical Field

[0001] Embodiments of the present invention relate to a pressure-contact type semiconductor device.

Background Art

[0002] There is known a pressure-contact type semiconductor device that realizes improvement in power density by double-sided heat dissipation and high reliability under high voltage and large current. In the pressure-contact type semiconductor device, a plurality of semiconductor elements provided inside an insulating frame are sandwiched between upper and lower electrode blocks and have a hermetically sealed structure.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The problem to be solved by the present invention is to improve the reliability of the pressure-contact type semiconductor device.

Means for Solving the Problems

[0005] The pressure-contact type semiconductor device according to the embodiment includes a first electrode, a second electrode, a pair of metal plates disposed between the first electrode and the second electrode, a semiconductor portion located between the pair of metal plates, and an electrode portion disposed on the upper surface of the semiconductor portion and having an upper surface smaller in area than the lower surface of the metal plate. The semiconductor device further includes a metal sintered layer disposed between one of the pair of metal plates and the electrode portion.

Brief Description of the Drawings

[0006] [Figure 1] It is a perspective view of the semiconductor device according to the embodiment. [Figure 2] It is a schematic cross-sectional view of a part of the semiconductor device. [Figure 3] This is a magnified view of region D in Figure 2. [Figure 4] This is an enlarged view of region D in the semiconductor device according to Modification 1. [Figure 5] This is an enlarged view of region D in the semiconductor device according to modified example 2. [Modes for carrying out the invention]

[0007] Each embodiment of the present invention will be described below with reference to the drawings.

[0008] Drawings are schematic or conceptual, and the relationships between the thickness and width of each part, as well as the ratios of the sizes of different parts, are not necessarily identical to those of reality. Even when representing the same part, the dimensions and ratios may differ between drawings.

[0009] In this specification and in each figure, elements similar to those already described are denoted by the same reference numerals, and detailed explanations are omitted as appropriate. In the description of the embodiments, in a plan view, the direction from the center of the semiconductor device 1 toward the outer circumference is also called the radial direction. For the sake of explanation, the direction from the second electrode 15 toward the first electrode 10 is referred to as "up," and the opposite direction is referred to as "down." These directions are based on the relative positional relationship between the first electrode 10 and the second electrode 15 and are independent of the direction of gravity.

[0010] <First Embodiment> Figure 1 is a perspective view of a semiconductor device according to an embodiment. Figure 2 is a schematic cross-sectional view of a part of a semiconductor device. As shown in Figures 1 and 2, the semiconductor device 1 according to this embodiment is an IEGT (Injection Enhanced Gate Transistor), or PPI (Press Pack IEGT), as a pressure-contact type semiconductor device. An IEGT is an IGBT (Insulated Gate Bipola Transistor) that has an electron injection enhancement effect. The semiconductor device 1 comprises a first electrode 10, a second electrode 15, a housing 20, a resin frame 30, a pair of metal plates 35, and a semiconductor element 40.

[0011] The first electrode 10 is provided on the upper side of the semiconductor device 1. The second electrode 15 is provided on the lower side of the semiconductor device 1. The first electrode 10 and the second electrode 15 are, for example, cylindrical in shape. The first electrode 10 and the second electrode 15 are made of a metal, for example, copper.

[0012] The housing 20 is, for example, cylindrical. The inner diameter of the housing 20 is, for example, 80 mm or more. The radial thickness of the housing 20 is, for example, 4 mm or more and 20 mm or less. The housing 20 is, for example, alumina. In addition to alumina, other materials such as silicon nitride, zirconia, aluminum nitride, etc. may be used for the housing 20.

[0013] The resin frame 30 is made of resin and is provided inside the housing 20. At least a portion of the resin frame 30 is provided between the first electrode 10 and the second electrode 15. The resin frame 30 is formed in a grid pattern in plan view and holds the semiconductor elements 40 within each rectangle of the grid. The resin frame 30 has the function of ensuring an insulating distance between the multiple semiconductor elements 40 and aligning the multiple semiconductor elements 40.

[0014] The pair of metal plates 35 are arranged between the first electrode 10 and the second electrode 15 so as to sandwich the semiconductor element 40. The pair of metal plates 35 are preferably made of a metal with high heat resistance and pressure resistance, and one example is a molybdenum plate.

[0015] The semiconductor element 40 is disposed between a pair of metal plates 35. In the present embodiment, the semiconductor element 40 is an IEGT, but it is not particularly limited as long as it is a device having electrodes on the top and bottom. For example, it may be a diode such as an FRD (Fast Recovery Diode). It may also be a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). Further, for example, an IEGT and an FRD may be mounted together. It may also be an RC-IEGT (Reverse Conductive-IEGT) in which a diode and an IEGT are integrated on one chip. Furthermore, it is not limited to silicon, and a device using silicon carbide (SiC) may also be used.

[0016] FIG. 3 is an enlarged view of region D in FIG. 2. As shown in FIG. 3, the semiconductor element 40 includes a semiconductor portion 40a and an electrode portion 40b disposed on the upper surface of the semiconductor portion 40a. Although omitted in FIG. 3, an emitter layer is disposed on the upper surface of the semiconductor portion 40a, a collector layer is disposed on the lower surface of the semiconductor portion 40a, and a gate wiring is disposed on the emitter layer side. The electrode portion 40b contains, for example, aluminum. The upper surface of the electrode portion 40b has a smaller area than the lower surface of the metal plate 35. Specifically, it is preferable that the area S1 of the lower surface of the metal plate 35 and the area S2 of the upper surface of the electrode portion 40b satisfy the ratio of 1 < S1 / S2 ≤ 1.25.

[0017] A metal sintered layer 42 is disposed between the metal plate 35 and the electrode portion 40b. The metal sintered layer 42 joins the metal plate 35 and the electrode portion 40b by pressure sintering. The metal sintered layer 42 includes, as an example, a silver sintered body.

[0018] In the semiconductor device 1 according to the present embodiment, during pressure sintering, as shown in region R1, since the area of the lower surface of the metal plate 35 is larger than the area of the upper surface of the electrode portion 40b, the periphery of the metal plate 35 does not press the electrode portion 40b through the metal sintered layer 42. On the other hand, if the area of the metal plate is smaller than the area of the electrode portion, the periphery of the metal plate may press the electrode portion through the sintered layer and damage the electrode portion. Thus, by having the above configuration, the semiconductor device 1 according to the present embodiment can avoid damage to the electrode portion 40b.

[0019] (Modification 1) Referring to FIG. 4, Modification 1 of the semiconductor device 1 will be described. FIG. 4 is an enlarged view of region D in the semiconductor device 1 according to Modification 1.

[0020] In the semiconductor device 1 according to Modification 1, as shown in region R2, the periphery of the metal plate 35 is chamfered in a plan view. Specifically, as an example, it is preferable that the periphery of the metal plate 35 is R-chamfered so as to have a rounded shape with a radius of curvature R≧0.05 mm. As another example, the periphery of the metal plate 35 may be C-chamfered with C≧0.05 mm.

[0021] In the semiconductor device 1 according to Modification 1, during pressure sintering, as shown in region R2, since the periphery of the metal plate 35 is chamfered, the periphery of the metal plate 35 does not press the electrode portion 40b through the metal sintered layer 42. On the other hand, if the periphery of the metal plate is not chamfered, the periphery of the metal plate may press the electrode portion through the metal sintered layer and damage the electrode portion. Thus, by having the above configuration, the semiconductor device 1 according to Modification 1 can avoid damage to the electrode portion 40b.

[0022] (Modification 2) Referring to FIG. 5, Modification 2 of the semiconductor device 1 will be described. FIG. 5 is an enlarged view of region D in the semiconductor device 1 according to Modification 2.

[0023] In the semiconductor device 1 according to the second modification, the upper and lower surfaces of the metal sintered layer 42 have a smaller area than the lower surface of the metal plate 35 and the upper surface of the electrode portion 40b in plan view. Specifically, it is preferable that 1 < S1 / S3 ≤ 1.25, where S1 is the area of the lower surface of the metal plate 35 and S3 is the area of the upper (or lower) surface of the metal sintered layer 42. Also, it is preferable that 1 < S2 / S3 ≤ 1.25, where S2 is the area of the upper surface of the electrode portion 40b and S3 is the area of the upper (or lower) surface of the metal sintered layer 42.

[0024] In the semiconductor device 1 according to the second modification, during pressure sintering, as shown in region R3, since the areas of the upper and lower surfaces of the metal sintered layer 42 are smaller than the areas of the lower surface of the metal plate 35 and the upper surface of the electrode portion 40b, the periphery of the metal plate 35 does not press the electrode portion 40b through the metal sintered layer 42. On the other hand, if the areas of the upper and lower surfaces of the metal sintered layer 42 are comparable to or larger than the areas of the lower surface of the metal plate 35 and the upper surface of the electrode portion 40b, the periphery of the metal plate may press the electrode portion through the metal sintered layer, damaging the electrode portion. Thus, the semiconductor device 1 according to the second modification can avoid damage to the electrode portion 40b by having the above configuration.

[0025] As described above, some embodiments of the present invention have been illustrated. However, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, changes, etc. can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and its equivalent scope. Also, the above-described embodiments can be implemented in combination with each other.

Explanation of Reference Numerals

[0026] 1: Semiconductor device, 10: First electrode, 15: Second electrode, 20: Housing, 30: Resin frame, 35: Metal plate, 40: Semiconductor element, 40a: Semiconductor portion, 40b: Electrode portion, 42: Metal sintered layer

Claims

1. First electrode and The second electrode and A pair of metal plates disposed between the first electrode and the second electrode, A semiconductor element having a semiconductor portion located between the pair of metal plates and an electrode portion positioned on the upper surface of the semiconductor portion and having an upper surface with a smaller area than the lower surface of the metal plate, A pressure-contact type semiconductor device comprising a metal sintered layer disposed between one of the pair of metal plates and the electrode portion.

2. First electrode and The second electrode and A pair of metal plates, whose edges are beveled, are positioned between the first electrode and the second electrode. A semiconductor element having a semiconductor portion and an electrode portion positioned on the upper surface of the semiconductor portion, located between the pair of metal plates, A pressure-contact type semiconductor device comprising a metal sintered layer disposed between one of the pair of metal plates and the electrode portion.

3. First electrode and The second electrode and A pair of metal plates disposed between the first electrode and the second electrode, A semiconductor element having a semiconductor portion and an electrode portion positioned on the upper surface of the semiconductor portion, located between the pair of metal plates, A pressure-contact type semiconductor device comprising: a metal sintered layer disposed between one of the pair of metal plates and the electrode portion, and having a lower surface and an upper surface smaller in area than the lower surface of the metal plate and the upper surface of the electrode portion.

4. A cylindrical housing, A pressure-contact type semiconductor device according to any one of claims 1 to 3, comprising a resin frame provided within the housing and holding a plurality of semiconductor elements.

5. The pressure-contact type semiconductor device according to claim 4, wherein the resin frame is formed in a grid pattern within the housing, and the semiconductor element is held within each rectangle of the grid.

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