Semiconductor equipment

Abstract

The present invention provides a semiconductor device that can shorten the termination region while suppressing a reduction in breakdown voltage. [Solution] The semiconductor device according to the embodiment comprises: a first semiconductor region of a first conductivity type having a central portion and a peripheral portion surrounding the central portion; a second semiconductor region of a first conductivity type located below the first semiconductor region and provided in the central portion, having a higher impurity concentration than the first semiconductor region; a third semiconductor region of a second conductivity type located above the first semiconductor region and provided in the central portion; a first electrode located on the lower surface of the second semiconductor region and provided in the central portion, electrically connected to the second semiconductor region; a second electrode located on the upper surface of the third semiconductor region and electrically connected to the third semiconductor region; an annular region of a second conductivity type located in the peripheral portion above the first semiconductor region, surrounding the third semiconductor region; and a fourth semiconductor region of a second conductivity type provided on the side surface of the first semiconductor region.

Description

[Technical Field]

[0001] Embodiments of the present invention relate to semiconductor devices. [Background technology]

[0002] Semiconductor devices such as diodes, metal oxide silicon field effect transistors (MOSFETs), and insulated gate bipolar transistors (IGBTs) are used for applications such as power conversion. These semiconductor devices are provided with a termination region to maintain voltage withstand capability. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Patent No. 4469584 [Overview of the project] [Problems that the invention aims to solve]

[0004] The problem that this invention aims to solve is to provide a semiconductor device that can shorten the termination region while suppressing a reduction in breakdown voltage. [Means for solving the problem]

[0005] The semiconductor device according to this embodiment includes: a first semiconductor region of a first conductivity type having a central portion and a terminal region surrounding the central portion; a second semiconductor region of a first conductivity type located below the first semiconductor region and provided in the central portion, having a higher impurity concentration than the first semiconductor region; a third semiconductor region of a second conductivity type located above the first semiconductor region and provided in the central portion; a first electrode located on the lower surface of the second semiconductor region and provided in the central portion, electrically connected to the second semiconductor region; a second electrode located on the upper surface of the third semiconductor region and electrically connected to the third semiconductor region; an annular region of a second conductivity type located in the terminal region at the upper part of the first semiconductor region so as to surround the third semiconductor region; and a fourth semiconductor region of a second conductivity type provided on the side surface of the first semiconductor region. [Brief explanation of the drawing]

[0006] [Figure 1] This is a plan view representing a semiconductor device according to the first embodiment. [Figure 2] This is a cross-sectional view taken along line II-II in Figure 1. [Figure 3] This is a schematic diagram illustrating the operation of a semiconductor device. [Figure 4] This is a cross-sectional view of a semiconductor device according to Modified Example 1. [Figure 5] This is a cross-sectional view of a semiconductor device according to modified example 2. [Figure 6] This graph shows the simulation results as an example of an implementation. [Figure 7] This graph shows the simulation results as an example. [Modes for carrying out the invention]

[0007] Each embodiment of the present invention will be described below with reference to the drawings.

[0008] Drawings are schematic or conceptual, and the relationships between the thickness and width of each part, as well as the ratios of the sizes of different parts, are not necessarily identical to those of reality. Even when representing the same part, the dimensions and ratios may be depicted differently in different drawings.

[0009] In this specification and in each figure, elements similar to those already described are denoted by the same reference numerals, and detailed explanations are omitted as appropriate.

[0010] In the following description and drawings, n + , n, n - and p + , p, p - The notation indicates the relative levels of each impurity concentration. That is, a "+" indicates a relatively higher impurity concentration than a notation without either a "+" or "-", and a "-" indicates a relatively lower impurity concentration than a notation without either a "+" or "-". When both p-type and n-type impurities are present in each region, these notations represent the relative levels of the net impurity concentration after the impurities have compensated for each other.

[0011] <First Embodiment> Each embodiment described below may be implemented by reversing the p-type and n-type of each semiconductor region. Figure 1 is a plan view representing a semiconductor device according to the first embodiment. In Figure 1, the insulating portion 40 is omitted. Figure 2 is a cross-sectional view taken along line II-II in Figure 1.

[0012] The semiconductor device 100 according to the first embodiment is, for example, a diode. As shown in Figures 1 and 2, the semiconductor device 100 has a semiconductor layer SL, a lower electrode 21 as a first electrode, an upper electrode 22 as a second electrode, and an insulating portion 40.

[0013] In the description of the embodiments, an XYZ orthogonal coordinate system is used. That is, the direction from the lower electrode 21 to the upper electrode 22 is defined as the Z direction. Two directions that are perpendicular to the Z direction and orthogonal to each other are defined as the X direction and the Y direction. Also, in a plan view, the direction from the center to the outer periphery of the semiconductor device 100 is also referred to as the radial direction. For the sake of description, the direction from the lower electrode 21 to the upper electrode 22 is referred to as "up", and the opposite direction is referred to as "down". These directions are independent of the direction of gravity based on the relative positional relationship between the lower electrode 21 and the upper electrode 22.

[0014] As shown in FIG. 2, the semiconductor layer SL includes a first semiconductor region 1 of the first conductivity type (e.g., n - type), a second semiconductor region 11 (e.g., an n contact layer) of the first conductivity type having an impurity concentration higher than that of the first semiconductor region 1, a third semiconductor region 12 of the second conductivity type (e.g., p type), an annular region 30 of the second conductivity type (e.g., p + type) having an impurity concentration lower than that of the third semiconductor region 12 as an example, a second annular region 31 of the second conductivity type (e.g., p - type) having an impurity concentration lower than that of the third semiconductor region as an example, and a fourth semiconductor region 32 of the second conductivity type (e.g., p - type) having an impurity concentration higher than that of the third semiconductor region 12. + The second semiconductor region 11 is provided below the first semiconductor region 1 and at the central portion excluding the terminal region in a plan view. A lower electrode 21 electrically connected to the second semiconductor region 11 is disposed on the lower surface of the second semiconductor region 11. The lower electrode 21 is provided at the central portion of the semiconductor device 100 in a plan view. Preferably, the lower electrode 21 has a shorter radial length than the second semiconductor region 11. In the example shown in FIG. 2, the lower electrode 21 has a radial length shorter by a length W than the second semiconductor region 11. By doing so, it is possible to prevent the voltage generated in the first semiconductor region 1 from being applied to the lower electrode 21.

[0015]

[0016] ​The third semiconductor region 12 is located above the first semiconductor region 1 and is provided at the central portion excluding the termination region in a plan view. An upper electrode 22 electrically connected to the third semiconductor region 12 is disposed on the upper surface of the third semiconductor region 12. The upper electrode 22 is provided at the central portion in the plan view of the semiconductor device 100.

[0017] In the termination region above the first semiconductor region 1, a plurality of annular regions 30 are arranged so as to surround the third semiconductor region 12. As shown in FIG. 1, the plurality of annular regions 30 are arranged annularly at predetermined intervals from each other in the termination region in the plan view of the semiconductor device 100. The number of the plurality of annular regions 30 is appropriately designed according to the withstand voltage required for the semiconductor device 100.

[0018] The insulating portion 40 is provided, as an example, on the upper surfaces of a part of the upper electrode 22 and the peripheral portion of the semiconductor device 100. Therefore, the insulating portion 40 seals the upper surface of the termination region of the semiconductor device 100. On the other hand, the upper surface of the central portion of the upper electrode 22 is not covered by the insulating portion 40 and is exposed to the outside.

[0019] A fourth semiconductor region 32 is continuously provided on the side surface of the first semiconductor region 1. As shown in FIG. 1, the fourth semiconductor region 32 is arranged at the outer edge in the plan view of the semiconductor device 100.

[0020] In the termination region on the lower surface of the first semiconductor region 1, a plurality of second annular regions 31 are provided so as to surround the second semiconductor region 11. The plurality of second annular regions 31 are arranged annularly at predetermined intervals from each other in the termination region in the plan view of the semiconductor device 100. The number of the plurality of second annular regions 31 is appropriately designed according to the withstand voltage required for the semiconductor device 100, and preferably, the number of the second annular regions 31 is less than the number of the annular regions 30.

[0021] The operation of the first embodiment will be described while referring to FIG. 3. FIG. 3 is a schematic diagram showing the operation of the semiconductor device.

[0022] The operation of the semiconductor device 100 will now be described. When a positive voltage is applied to the upper electrode 22 relative to the lower electrode 21, a forward voltage is applied to the pn junction surface between the first semiconductor region 1 and the second semiconductor region 11. As a result, the semiconductor device 100 turns on, and current flows from the upper electrode 22 to the lower electrode 21.

[0023] Subsequently, when a positive voltage is applied to the lower electrode 21 relative to the upper electrode 22, the current flow stops, and the semiconductor device 100 switches from the ON state to the OFF state. A reverse voltage is applied to the pn junction surface between the first semiconductor region 1 and the second semiconductor region 11. Due to the application of the reverse voltage, as shown in Figure 3(a), the leading edge D of the depletion layer spreads downward toward the terminal region from the pn junction surface between the first semiconductor region 1 and the second semiconductor region 11 in a convex shape.

[0024] The leading edge D of the depletion layer has difficulty penetrating the fourth semiconductor region 32, which has a high impurity concentration and is located on the side surface of the semiconductor device 100. On the other hand, since there is still an undepleted region in the central part of the first semiconductor region 1, it spreads downward in an upward convex shape, as shown in Figure 3(b). Furthermore, as shown in Figure 3(c), the leading edge D of the depletion layer spreads toward the second semiconductor region 11, i.e., toward the central part. In this way, because the fourth semiconductor region 32, which has a high impurity concentration, is provided on the side surface of the semiconductor device 100, the radial spreading of the depletion layer can be suppressed, and the breakdown voltage can be maintained with a shortened termination region.

[0025] An example of the materials used for each component of the semiconductor device 100 will be described.

[0026] The first semiconductor region 1, the second semiconductor region 11, the third semiconductor region 12, the cyclic region 30, the second cyclic region 31, and the fourth semiconductor region 32 contain silicon, silicon carbide, gallium nitride, or gallium arsenide as semiconductor materials. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony can be used as n-type impurities. Boron can also be used as a p-type impurity. The lower electrode 21 and the upper electrode 22 contain a metal such as aluminum or copper. The insulating portion 40 contains an insulating resin material such as polyimide.

[0027] (Variation 1) A modified example 1 of the semiconductor device 100 will be described with reference to Figure 4. Figure 4 is a cross-sectional view of the semiconductor device 100 according to Modified Example 1.

[0028] As shown in Figure 4, in Modification 1, the second annular region 31 is not provided in the terminal region on the lower surface of the first semiconductor region 1. Even in this configuration, since the fourth semiconductor region 32 is provided on the side surface of the first semiconductor region 1, the radial spreading of the depletion layer tip D can be suppressed in the same way as in the above embodiment, and the breakdown voltage can be maintained with a shortened terminal region.

[0029] (Modification 2) A modified example 2 of the semiconductor device 100 will be described with reference to Figure 5. Figure 5 is a cross-sectional view of a semiconductor device according to modified example 2.

[0030] As shown in Figure 5, in Modification 2, a fifth semiconductor region 33 of a second conductivity type with a lower impurity concentration than the third semiconductor region 12 is intermittently provided on the side surface of the first semiconductor region 1. Even in this configuration, the fifth semiconductor region 33 intermittently provided on the side surface of the first semiconductor region 1 functions as an electric field relaxation layer, making it possible to maintain breakdown voltage with a shortened termination region.

[0031] (Examples) Examples and reference examples of the semiconductor device 100 will be described with reference to Figures 6 and 7. Figure 6 is a graph showing the simulation results of semiconductor device 100 as an example. Figure 7 is a graph showing the simulation results of a semiconductor device as an example.

[0032] In Figures 6 and 7, L1 represents the length of the lower electrode 21. L2 represents the length of the second semiconductor region 11. L3 represents the length of the upper electrode 22. L4 represents the length of the area where multiple annular regions 30 are arranged. L4 + L5 represents the length of the termination region in the embodiment. L6 represents the length of the lower electrode in the reference example. L4 + L7 represents the length of the termination region in the reference example. Note that in the embodiment in Figure 6, the fourth semiconductor region 32 is provided on the side surface of the first semiconductor region 1, but in the reference example in Figure 7, the simulation was performed under the condition that the fourth semiconductor region 32 is not provided on the side surface of the first semiconductor region 1.

[0033] Comparing Figures 6 and 7, it can be seen that the length of the termination region L4+L5 in the embodiment was shortened compared to the length of the termination region L4+L7 in the comparative example. In other words, this embodiment shows that the semiconductor device 100 according to this embodiment is able to maintain breakdown voltage while shortening the termination region because a fourth semiconductor region 32 with a high impurity concentration is provided on the side surface of the first semiconductor region 1.

[0034] (Other embodiments) Although embodiments have been described above, the application of the technical concept of this disclosure is not limited to the above embodiments. For example, the fourth semiconductor region 32, which is continuously provided on the side surface of the semiconductor device 100, may have an impurity concentration similar to that of the third semiconductor region 12. Also, the plurality of second annular regions 31, which are arranged in the terminal region on the lower surface of the first semiconductor region 1, may have an impurity concentration similar to that of the third semiconductor region 12.

[0035] Furthermore, although the semiconductor device 100 is implemented as a diode in the above embodiment, the invention is not limited to this configuration. For example, the semiconductor device 100 may be an IGBT (Insulated Gate Bipolar Transistor) with a P layer as a collector layer on its lower side. Alternatively, it may be a MOS (Metal Oxide Semiconductor) with a trench-type gate electrode, a P layer, and an N layer on its upper side. Also, the type of termination is not limited to the above embodiment and may be a resurf, field plate, VLD (Variation of Lateral Doping), etc.

[0036] Although several embodiments of the present invention have been illustrated above, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. Furthermore, the embodiments described above can be implemented in combination with each other. [Explanation of Symbols]

[0037] 1: First semiconductor region, 11: Second semiconductor region, 12: Third semiconductor region, 21: Lower electrode, 22: Upper electrode, 30: Ring region, 31: Second ring region, 32: Fourth semiconductor region, 33: Fifth semiconductor region, 40: Insulating part, 100: Semiconductor device

Claims

1. A first semiconductor region of a first conductivity type having a central portion and an end region surrounding the central portion, A second semiconductor region having a first conductivity type and a higher impurity concentration than the first semiconductor region is provided in the lower part of the first semiconductor region, located in the central part. The upper part of the first semiconductor region, comprising a third semiconductor region of a second conductivity type provided in the central part, The lower surface of the second semiconductor region, the first electrode located in the central part and electrically connected to the second semiconductor region, A second electrode is positioned on the upper surface of the third semiconductor region and electrically connected to the third semiconductor region, An annular region of a second conductivity type is provided in the terminal region at the top of the first semiconductor region, so as to surround the third semiconductor region. A fourth semiconductor region of a second conductivity type is provided on the side surface of the first semiconductor region, A semiconductor device equipped with the following features.

2. The semiconductor device according to claim 1, wherein the impurity concentration in the fourth semiconductor region is higher than the impurity concentration in the third semiconductor region.

3. The semiconductor device according to claim 1, wherein the impurity concentration of the fourth semiconductor region is lower than that of the third semiconductor region, and the fourth semiconductor region is provided in multiple locations.

4. The semiconductor device according to any one of claims 1 to 3, wherein a second annular region of a second conductivity type is provided in the terminal region on the lower surface of the first semiconductor region.

5. The semiconductor device according to claim 4, wherein the number of second annular regions is less than the number of annular regions.

6. The semiconductor device according to claim 4, wherein the impurity concentration in the second cyclic region is lower than that in the third semiconductor region.

Images