Semiconductor memory

Abstract

The present invention provides a semiconductor memory device that enables good connectivity between transistors and capacitors. [Solution] The semiconductor memory device according to the embodiment includes a plurality of memory cells arranged in first and second directions, each memory cell extending in a third direction and including a MOS transistor 30 and a capacitor 40, the MOS transistor including a first insulating layer 32 extending in the third direction, a semiconductor layer 31 extending in the third direction so as to surround the side surface of the first insulating layer and formed of a two-dimensional material, and a gate electrode provided on the outside of the semiconductor layer, the capacitor including a first electrode 41, a second electrode 42, and a capacitor material layer 43 extending in the third direction, the first electrode surrounding the side surface of the second electrode, the capacitor material layer provided between the first electrode and the second electrode, and the first electrode in contact with the first end of the semiconductor layer in the third direction.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor memory device.

Background Art

[0002] A semiconductor memory device has been proposed in which a plurality of memory cells each including a transistor and a capacitor are three-dimensionally integrated on a semiconductor substrate.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] To provide a semiconductor memory device capable of obtaining a good connection between a transistor and a capacitor.

Means for Solving the Problems

[0005] The semiconductor memory device according to the embodiment includes a plurality of memory cells arranged in a first direction and a second direction intersecting the first direction, each of the plurality of memory cells extending in a third direction intersecting the first and second directions, and including a MOS transistor and a capacitor adjacent to the MOS transistor in the third direction, the MOS transistor including a first insulating layer extending in the third direction, a semiconductor layer extending in the third direction so as to surround the side surface of the first insulating layer and formed of a two-dimensional material, and a gate electrode provided on the outside of the semiconductor layer, the capacitor including a first electrode, a second electrode and a capacitor material layer extending in the third direction, the structure in which the first electrode surrounds the side surface of the second electrode and the capacitor material layer is provided between the first electrode and the second electrode, and the first electrode is in contact with the first end of the semiconductor layer in the third direction. [Brief explanation of the drawing]

[0006] [Figure 1] This is an electrical circuit diagram showing the basic configuration of a semiconductor memory device according to the first embodiment. [Figure 2] This is a schematic perspective view showing an example of the basic configuration of a semiconductor memory device according to the first embodiment. [Figure 3] This is a schematic perspective view showing another example of the basic configuration of a semiconductor memory device according to the first embodiment. [Figure 4] This is a schematic cross-sectional view showing the configuration of a semiconductor memory device according to the first embodiment. [Figure 5A] This is a schematic cross-sectional view showing the configuration of a MOS transistor in a semiconductor memory device according to the first embodiment. [Figure 5B] This is a schematic cross-sectional view showing the configuration of the capacitor in the semiconductor memory device according to the first embodiment. [Figure 6] This is a schematic cross-sectional view showing the specific structure of a capacitor in a semiconductor memory device according to the first embodiment.

[0007] [Figure 7A] This is a schematic cross-sectional view showing a part of the method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 7B] This is a schematic cross-sectional view showing a part of the method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 7C] This is a schematic cross-sectional view showing a part of the method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 7D] This is a schematic cross-sectional view showing a part of the method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 7E] This is a schematic cross-sectional view showing a part of the method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 7F] This is a schematic cross-sectional view showing a part of the method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 7G] This is a schematic cross-sectional view showing a part of the method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 8] This is a schematic cross-sectional view showing the configuration of a semiconductor memory device according to a modified example of the first embodiment. [Figure 9] This is a schematic cross-sectional view showing the configuration of a semiconductor memory device according to the second embodiment. [Figure 10A] This is a schematic cross-sectional view showing the configuration of a MOS transistor in a semiconductor memory device according to the second embodiment. [Figure 10B] This is a schematic cross-sectional view showing the configuration of the capacitor in the semiconductor memory device according to the second embodiment. [Figure 11A] This is a schematic cross-sectional view showing a part of the first manufacturing method of a semiconductor memory device according to the second embodiment. [Figure 11B] This is a schematic cross-sectional view showing a part of the first manufacturing method of a semiconductor memory device according to the second embodiment. [Figure 11C] This is a schematic cross-sectional view showing a part of the first manufacturing method of a semiconductor memory device according to the second embodiment. [Figure 11D] This is a schematic cross-sectional view showing a part of the first manufacturing method of a semiconductor memory device according to the second embodiment. [Figure 12A] It is a cross-sectional view schematically showing a part of a second manufacturing method of a semiconductor memory device according to a second embodiment. [Figure 12B] It is a cross-sectional view schematically showing a part of a second manufacturing method of a semiconductor memory device according to a second embodiment. [Figure 12C] It is a cross-sectional view schematically showing a part of a second manufacturing method of a semiconductor memory device according to a second embodiment. [Figure 12D] It is a cross-sectional view schematically showing a part of a second manufacturing method of a semiconductor memory device according to a second embodiment. [Figure 12E] It is a cross-sectional view schematically showing a part of a second manufacturing method of a semiconductor memory device according to a second embodiment. [Figure 12F] It is a cross-sectional view schematically showing a part of a second manufacturing method of a semiconductor memory device according to a second embodiment. [Figure 12G] It is a cross-sectional view schematically showing a part of a second manufacturing method of a semiconductor memory device according to a second embodiment. [Figure 12H] It is a cross-sectional view schematically showing a part of a second manufacturing method of a semiconductor memory device according to a second embodiment. [Figure 12I] It is a cross-sectional view schematically showing a part of a second manufacturing method of a semiconductor memory device according to a second embodiment. [Figure 12J] It is a cross-sectional view schematically showing a part of a second manufacturing method of a semiconductor memory device according to a second embodiment. [Figure 13] It is a cross-sectional view schematically showing the configuration of a semiconductor memory device according to a modified example of a second embodiment. [Figure 14] It is a cross-sectional view schematically showing the configuration of a semiconductor memory device according to a third embodiment. [Figure 15A] It is a cross-sectional view schematically showing a part of a manufacturing method of a semiconductor memory device according to a third embodiment. [Figure 15B] It is a cross-sectional view schematically showing a part of a manufacturing method of a semiconductor memory device according to a third embodiment. [Figure 15C] It is a cross-sectional view schematically showing a part of a manufacturing method of a semiconductor memory device according to a third embodiment. [Figure 15D] This is a schematic cross-sectional view showing a part of the method for manufacturing a semiconductor memory device according to the third embodiment. [Figure 15E] This is a schematic cross-sectional view showing a part of the method for manufacturing a semiconductor memory device according to the third embodiment. [Modes for carrying out the invention]

[0008] The embodiments will be described below with reference to the drawings.

[0009] (First Embodiment) Figure 1 is an electrical circuit diagram showing the basic configuration of a semiconductor memory device according to the first embodiment.

[0010] As shown in Figure 1, the semiconductor memory device of this embodiment is a DRAM and includes a plurality of word lines 10, a plurality of bit lines 20, and a plurality of memory cells 50. Similar to a normal DRAM, each memory cell 50 includes a MOS transistor 30 and a capacitor 40. The gate electrode of the MOS transistor 30 is connected to the word line 10, one of the source and drain terminals of the MOS transistor 30 is connected to the bit line 20, and the other source and drain terminal is connected to the capacitor 40.

[0011] Figure 2 is a schematic perspective view showing an example of the basic configuration of a semiconductor memory device according to this embodiment.

[0012] As shown in Figure 2, the semiconductor memory device of this embodiment has a three-dimensional structure and includes a plurality of word lines 10 each extending in the Y direction (first direction), a plurality of bit lines 20 each extending in the Z direction (second direction), and a plurality of memory cells 50 arranged in the Y and Z directions. Each word line 10 is connected to the plurality of memory cells 50 arranged in the Y direction, and each bit line 20 is connected to the plurality of memory cells 50 arranged in the Z direction. Each memory cell 50 extends in the X direction and includes a MOS transistor 30 and a capacitor 40 adjacent to each other in the X direction.

[0013] Figure 3 is a schematic perspective view showing another example of the basic configuration of the semiconductor memory device according to this embodiment.

[0014] The basic configuration of the semiconductor memory device shown in Figure 3 is the same as that of the semiconductor memory device shown in Figure 2. However, in Figure 3, each of the multiple word lines 10 extends in the Z direction (first direction), and each of the multiple bit lines 20 extends in the Y direction (second direction). The other basic configurations are the same as those in Figure 2.

[0015] Figure 4 is a schematic cross-sectional view perpendicular to the Y direction showing the configuration of the semiconductor memory device according to this embodiment. Note that, for illustrative purposes, the word line 10 and bit line 20 are not shown in Figure 4; however, in reality, the word line 10 and bit line 20 are provided on the left side of the structure shown in Figure 4. The same applies to the other figures described later.

[0016] Figure 5A is a schematic cross-sectional view showing the configuration of the MOS transistor 30 of the semiconductor memory device according to this embodiment, perpendicular to the X direction. Figure 5B is a schematic cross-sectional view showing the configuration of the capacitor 40 of the semiconductor memory device according to this embodiment, perpendicular to the X direction.

[0017] In Figures 2, 3, 5A, and 5B, the memory cell 50, including the MOS transistor 30 and capacitor 40, is shown as cylindrical; however, in reality, the memory cell 50 is closer to a prismatic shape. Furthermore, the shape is not limited to those shown in these drawings.

[0018] The configuration of the semiconductor memory device according to this embodiment will be described below with reference to Figures 2 (or 3), 4, 5A, and 5B.

[0019] As already mentioned, each memory cell 50 of the semiconductor memory device of this embodiment extends in the X direction and includes adjacent MOS transistors 30 and capacitors 40 in the X direction. Furthermore, multiple memory cells 50 are surrounded by insulating regions 60, and adjacent memory cells 50 are insulated from each other by the insulating regions 60.

[0020] The MOS transistor 30 includes an insulating layer 32 stretched in the X direction, a semiconductor layer 31 stretched in the X direction surrounding the sides of the insulating layer 32 and formed of a two-dimensional material, and a gate electrode provided on the outside of the semiconductor layer 31. Specifically, it is as follows.

[0021] The MOS transistor 30 includes a semiconductor layer 31 having a cylindrical structure that extends in the X direction, and a channel is formed in the semiconductor layer 31. An insulating layer 32 is provided on the inner side of the inner surface of the cylindrical semiconductor layer 31, and the inside of the semiconductor layer 31 is filled with the insulating layer 32.

[0022] The gate electrode of the MOS transistor 30 is included in the word line 10, and a portion of the word line 10 functions as the gate electrode of the MOS transistor 30. Specifically, a cylindrical semiconductor layer 31 extends in the X direction through the gate electrode. A gate insulating layer (not shown) is provided between the semiconductor layer 31 and the gate electrode.

[0023] One end of the semiconductor layer 31 in the X direction (the first end) and the region near the first end correspond to the region including one of the source terminals and drain terminals (the first terminal region), and the other end of the semiconductor layer 31 in the X direction (the second end) and the region near the second end correspond to the region including the other terminal of the source terminal and drain terminal (the second terminal region). A capacitor 40 is connected to the first terminal region of the semiconductor layer 31, and a bit line 20 is connected to the second terminal region of the semiconductor layer 31.

[0024] The semiconductor layer 31 is formed of a two-dimensional material. The two-dimensional material has a layered structure formed of one or more single atomic layers, and within each single atomic layer, the atoms constituting the single atomic layer are strongly bonded together by covalent bonds. Furthermore, when the layered structure is formed of two or more single atomic layers, the layered structure has a structure in which two or more single atomic layers are stacked, and a vdW (van del Waals) gap is provided between adjacent single atomic layers in the stacking direction. In this embodiment, the stretching direction of the semiconductor layer 31 (X direction) and the stretching direction of the layered structure of the two-dimensional material (stretching direction of the single atomic layer) are the same direction.

[0025] The two-dimensional material described above is preferably selected from materials containing tungsten (W) and sulfur (S) (specifically, WS2), materials containing tungsten (W) and selenium (Se) (specifically, WSe2), materials containing molybdenum (Mo) and sulfur (S) (specifically, MoS2), materials containing molybdenum (Mo) and selenium (Se) (specifically, MoSe2), and materials containing molybdenum (Mo) and tellurium (Te) (specifically, MoTe2).

[0026] The capacitor 40 includes a first electrode 41, a second electrode 42, a capacitor material layer 43, and an insulating layer 44, each extending in the X direction. The first electrode 41 surrounds the side surface of the second electrode 42, the capacitor material layer 43 is provided between the first electrode 41 and the second electrode 42, and the second electrode 42 is provided outside the insulating layer 44 so as to surround its outer surface. The insulating layer 44 is optional. In this case, the second electrode 42 will have a columnar structure. Specifically, it is as follows.

[0027] The capacitor 40 has a columnar structure extending in the X direction and includes a first electrode 41 made of a conductive material, a second electrode 42 made of a conductive material and provided inside the first electrode 41, a capacitor material layer (capacitor insulating layer) 43 made of an insulating material and provided between the first electrode 41 and the second electrode 42, and an insulating layer 44 provided inside the second electrode 42. The first electrode 41, the second electrode 42, the capacitor material layer 43, and the insulating layer 44 are all extended in the X direction, and the first electrode 41, the second electrode 42, and the capacitor material layer 43 substantially function as a capacitor. The first electrode 41 is connected to the MOS transistor 30, and the second electrode 42 functions as a plate electrode.

[0028] Specifically, the first electrode 41 is connected to the semiconductor layer 31 in the portion included in the first terminal region described above. More specifically, the first electrode 41 is in contact with one end (first end) of the semiconductor layer 31 in the X direction. Since the semiconductor layer 31 has a cylindrical structure that extends in the X direction, the first end of the semiconductor layer 31 has a ring shape when viewed from the X direction. Therefore, the first electrode 41 is in contact with this ring-shaped first end of the semiconductor layer 31.

[0029] In this embodiment, the X-direction end of the insulating layer 32, which is provided inside the semiconductor layer 31, is recessed in the X-direction relative to the first end of the semiconductor layer 31. Therefore, in this embodiment, the first electrode 41 is in contact with the portion of the inner surface of the semiconductor layer 31 located near the first end, and also in contact with the X-direction end of the insulating layer 32.

[0030] In this embodiment, the first electrode 41 is formed of a single conductive portion (first conductive portion). This first conductive portion is made of a material containing carbon or a metallic element. The first conductive portion may be made of a single element or of an alloy containing multiple elements.

[0031] Figure 6 is a schematic cross-sectional view showing a more specific structure of the capacitor 40. As shown in Figure 6, the inner surface of the first conductive portion constituting the first electrode 41 has an uneven shape. Therefore, the interface between the first conductive portion (first electrode 41) and the capacitor material layer 43 is uneven, and the interface between the capacitor material layer 43 and the second electrode 42 is also uneven. The uneven shape of the inner surface of the first conductive portion can be formed by a method described later.

[0032] As described above, in this embodiment, the semiconductor layer 31 of the MOS transistor 30 is formed of a two-dimensional material, and the first electrode 41 of the capacitor 40 is in contact with one end of the semiconductor layer 31 in the X direction (the first end). With this configuration, in this embodiment, as described below, the contact resistance between the semiconductor layer 31 and the first electrode 41 can be significantly reduced, and a good connection between the MOS transistor 30 and the capacitor 40 can be obtained.

[0033] In two-dimensional materials, the contact resistance in the direction perpendicular to the thickness direction of the layered structure is significantly lower than the contact resistance in the thickness direction of the layered structure. In other words, in two-dimensional materials, the contact resistance in the direction parallel to the stretching direction of the single atomic layer contained in the layered structure (the direction parallel to the plane constituting the single atomic layer) is significantly lower than the contact resistance in the direction perpendicular to the stretching direction of the single atomic layer.

[0034] In this embodiment, the stretching direction (X direction) of the semiconductor layer 31 and the stretching direction of the layered structure of the two-dimensional material are the same, and the first electrode 41 of the capacitor 40 is in contact with one end (first end) of the semiconductor layer 31 in the X direction. Therefore, it is possible to significantly reduce the contact resistance between the first electrode 41 and the semiconductor layer 31.

[0035] Furthermore, in this embodiment, the inner surface of the first conductive portion constituting the first electrode 41 has an uneven shape. Therefore, the interface between the first conductive portion and the capacitor material layer 43 is uneven, and the interface between the capacitor material layer 43 and the second electrode 42 is also uneven. As a result, the effective area of ​​the capacitor 40 can be increased, and the capacitance of the capacitor 40 can be increased.

[0036] Furthermore, if the first electrode 41 has an uneven shape, there is a risk that the contact area between the first electrode 41 and the first edge of the semiconductor layer 31 may not be sufficient. Even in such cases, the contact resistance (contact resistance per unit area) reduction effect makes it possible to sufficiently reduce the contact resistance between the first electrode 41 and the semiconductor layer 31.

[0037] Furthermore, in this embodiment, since the first electrode 41 is also in contact with a portion of the inner surface of the semiconductor layer 31 located near the first edge, the contact area between the first electrode 41 and the semiconductor layer 31 can be increased. Therefore, it is possible to further reduce the contact resistance.

[0038] Next, the method for manufacturing the semiconductor memory device according to this embodiment will be described with reference to the cross-sectional views shown in Figures 7A to 7G.

[0039] First, as shown in Figure 7A, a laminated structure is formed in which insulating layers 60 and sacrificial layers 71 are alternately stacked. For example, silicon oxide is used for the insulating layer 60 and silicon nitride is used for the sacrificial layer 71. Next, the insulating layer 60 and sacrificial layer 71 are etched to form multiple grooves (not shown) in the laminated structure that extend in the X and Z directions, respectively. Furthermore, the multiple grooves are filled with an insulating material (such as silicon oxide) similar to that of the insulating layer 60. The insulating material filled in the multiple grooves separates and insulates the memory cells aligned in the Y direction.

[0040] Next, as shown in Figure 7B, the sacrificial layer 71 is selectively etched from the insulating layer 60 to form a space 72.

[0041] Next, as shown in Figure 7C, a semiconductor layer 31 made of a two-dimensional material is formed on the inner surface of the insulating layer 60, and then an insulating layer 32 is formed inside the semiconductor layer 31. For example, silicon nitride or silicon oxynitride can be used for the insulating layer 32.

[0042] Next, as shown in Figure 7D, the semiconductor layer 31 is selectively etched from the insulating layer 60 and the insulating layer 32 to form a space 73.

[0043] Next, as shown in Figure 7E, the insulating layer 32 is selectively etched against the insulating layer 60 and the semiconductor layer 31 to form a space 74. At this time, the etching is performed so that the edge of the insulating layer 32 is recessed relative to the edge of the semiconductor layer 31 to form a recess 74r.

[0044] Next, as shown in Figure 7F, the first electrode 41 is formed along the inner surface of the space 74. As already mentioned, the first electrode 41 has an uneven surface. Specifically, the uneven surface can be formed by the method described below.

[0045] The first method involves carbonizing an organic structure. Specifically, by evaporating the solvent from a polymer solution under high humidity conditions and then carbonizing it, it is possible to form a carbon electrode with an uneven surface.

[0046] The second method involves immersing the organic structure in a conductive dispersion. Specifically, by immersing the organic structure in an ITO dispersion, the ITO dispersion can fill the gaps between numerous polymer particles, and by further annealing, it is possible to form a porous ITO electrode.

[0047] The third method involves forming a porous electrode by de-alloying. Specifically, an alloy is created from two metals with different solubility levels, and then immersed in an etching solution to dissolve only one of the metal components. This causes the remaining metal component to become isolated and unstable on the surface. As a result, the remaining metal component diffuses and aggregates on the surface, leading to self-organization and ultimately the formation of a porous metal electrode.

[0048] These methods are applied to the space 74 and the recess 74r to form the first electrode 41 having an uneven shape. Note that the method for forming the first electrode 41 having an uneven shape is not limited to the methods described above, and other methods may also be used.

[0049] After the process shown in Figure 7F, a capacitor material layer 43 is formed on the first electrode 41, as shown in Figure 7G, and then a second electrode 42 is formed on the capacitor material layer 43.

[0050] Subsequently, by forming an insulating layer 44 within the space 74, a structure like that shown in Figure 4 can be obtained.

[0051] Figure 8 is a schematic cross-sectional view perpendicular to the Y direction showing the configuration of a semiconductor memory device according to a modified example of this embodiment.

[0052] In this modified example, the X-direction end of the insulating layer 32 provided inside the semiconductor layer 31 is not recessed in the X-direction relative to the X-direction end (first end) of the semiconductor layer 31, and the X-direction end of the insulating layer 32 and the first end of the semiconductor layer 31 are located in the same plane substantially perpendicular to the X-direction. Therefore, in this modified example, the first electrode 41 is substantially in contact only with the first end of the semiconductor layer 31. The other basic configurations are the same as those of the embodiment described above.

[0053] The configuration of this modified example can be formed by etching in the process shown in Figure 7E of the above-described embodiment, such that the edge of the insulating layer 32 is located in the same plane as the edge of the semiconductor layer 31.

[0054] In this modified example, the basic configuration is the same as that of the embodiment described above, and it is possible to obtain the same effects as the basic effects of the embodiment described above.

[0055] (Second embodiment) Next, a second embodiment will be described. The basic aspects are the same as in the first embodiment, and explanations of the matters described in the first embodiment will be omitted.

[0056] Figure 9 is a schematic cross-sectional view perpendicular to the Y direction showing the configuration of the semiconductor memory device according to this embodiment. Note that, for illustrative purposes, the word line 10 and bit line 20 are not shown in Figure 9; however, in reality, the word line 10 and bit line 20 are provided to the left of the structure shown in Figure 9. The same applies to the other figures described later.

[0057] Figure 10A is a schematic cross-sectional view showing the configuration of the MOS transistor 30 of the semiconductor memory device according to this embodiment, perpendicular to the X direction. Figure 10B is a schematic cross-sectional view showing the configuration of the capacitor 40 of the semiconductor memory device according to this embodiment, perpendicular to the X direction.

[0058] The overall configuration is the same as in Figures 1, 2, and 3 of the first embodiment. However, as described in the first embodiment, in this embodiment as well, the shape of the memory cell 50, including the MOS transistor 30 and capacitor 40, is cylindrical in Figures 2, 3, 10A, and 10B, but in reality, the shape of the memory cell 50 is closer to a rectangular prism. Note that the shape is not limited to those shown in these drawings.

[0059] The configuration of the semiconductor memory device according to this embodiment will be described below with reference to Figures 2 (or 3), 9, 10A, and 10B.

[0060] In this embodiment, the first electrode 41 of the capacitor 40 includes a first conductive portion 41a and a second conductive portion 41b. Specifically, the first conductive portion 41a is provided between the second conductive portion 41b and the capacitor material layer 43.

[0061] The first conductive portion 41a is basically the same as the first conductive portion constituting the first electrode 41 described in the first embodiment. That is, the first conductive portion 41a has the same structure as the first conductive portion of the first embodiment, is made of the same material as the first conductive portion of the first embodiment, and, as in Figure 6 of the first embodiment, the inner surface of the first conductive portion 41a has an uneven shape. Therefore, as in the first embodiment, the interface between the first conductive portion 41a and the capacitor material layer 43 is uneven, and the interface between the capacitor material layer 43 and the second electrode 42 is also uneven.

[0062] The second conductive portion 41b is provided on the outside of the first conductive portion 41a, and both the inner surface (the surface on the side of the first conductive portion 41a) and the outer surface (the surface on the opposite side of the inner surface) of the second conductive portion 41b have a flat shape.

[0063] In this embodiment, as in the first embodiment, the first electrode 41 is in contact with one end of the semiconductor layer 31 in the X direction (the first end). Also in this embodiment, as in the first embodiment, the end of the insulating layer 32 provided inside the semiconductor layer 31 in the X direction is recessed in the X direction relative to the first end of the semiconductor layer 31. Therefore, in this embodiment, as in the first embodiment, the first electrode 41 is in contact with the portion of the inner surface of the semiconductor layer 31 located near the first end, and further in contact with the end of the insulating layer 32 in the X direction.

[0064] As described above, the basic configuration of this embodiment is the same as that of the first embodiment, and the same effects as those of the first embodiment can be obtained in this embodiment as well.

[0065] Furthermore, in this embodiment, as in the first embodiment, the surface of the first conductive portion 41a has an uneven shape, but in this embodiment, a second conductive portion 41b having a flat surface shape is provided on the outside of the first conductive portion 41a. As a result, the second conductive portion 41b having a flat surface shape comes into contact with the semiconductor layer 31, making it possible to obtain a sufficient contact area between the first electrode 41 and the semiconductor layer 31. Therefore, it is possible to reliably and sufficiently reduce the contact resistance between the first electrode 41 and the semiconductor layer 31.

[0066] Next, a first method for manufacturing the semiconductor memory device according to this embodiment will be described with reference to the cross-sectional views shown in Figures 11A to 11D.

[0067] First, a structure as shown in Figure 11A is formed by the same process as in Figures 7A to 7E of the first embodiment.

[0068] Next, as shown in Figure 11B, a second conductive portion 41b is formed along the inner surface of space 74.

[0069] Next, as shown in Figure 11C, a first conductive portion 41a is formed along the inner surface of the space 74. As already mentioned, the first conductive portion 41a has an uneven shape. The specific method for forming the first conductive portion 41a is the same as in the first embodiment. In this way, the first electrode 41, including the first conductive portion 41a and the second conductive portion 41b, is formed.

[0070] Next, as shown in Figure 11D, a capacitor material layer 43 is formed on the first electrode 41, and then a second electrode 42 is formed on the capacitor material layer 43.

[0071] Subsequently, by forming an insulating layer 44 within the space 74, a structure like that shown in Figure 9 can be obtained.

[0072] Next, a second method for manufacturing the semiconductor memory device according to this embodiment will be described with reference to the cross-sectional views shown in Figures 12A to 12J.

[0073] First, a structure as shown in Figure 12A is formed by a process similar to that shown in Figure 7A of the first embodiment.

[0074] Next, as shown in Figure 12B, the sacrificial layer 71 is selectively etched from the insulating layer 60 to form a space 75. Then, as shown in Figure 12C, a metallic material layer is formed as a sacrificial layer 76 within the space 75.

[0075] Next, as shown in Figure 12D, the sacrificial layer 71 is selectively etched from the insulating layer 60 and the sacrificial layer 76 to form spaces 77. Then, as shown in Figure 12E, a SAM (self-assembled monolayer) layer 78 is formed on the surface of the sacrificial layer 76.

[0076] Next, as shown in Figure 12F, a semiconductor layer 31 is formed on the inner surface of the space 77. Then, as shown in Figure 12G, a portion of the semiconductor layer 31 and the SAM layer 78 are removed to expose the surface of the sacrificial layer 76.

[0077] Next, as shown in Figure 12H, an insulating layer 32 is formed in the space 77. Then, as shown in Figure 12I, the sacrificial layer 76 is removed to expose the surface of the insulating layer 32. Next, as shown in Figure 12J, the insulating layer 32 is etched so that its edges are recessed relative to the edges of the semiconductor layer 31, forming a recess 74r.

[0078] The subsequent steps are the same as those in the first manufacturing method. That is, after performing the same steps as in Figures 11B to 11D of the first manufacturing method, an insulating layer 44 is formed in the space 74 in Figure 11D, thereby obtaining the structure shown in Figure 9, etc.

[0079] Figure 13 is a schematic cross-sectional view perpendicular to the Y direction showing the configuration of a semiconductor memory device according to a modified example of this embodiment.

[0080] In this modified example, the X-direction end of the insulating layer 32 provided inside the semiconductor layer 31 is not recessed in the X-direction relative to the X-direction end (first end) of the semiconductor layer 31, and the X-direction end of the insulating layer 32 and the first end of the semiconductor layer 31 are located in the same plane substantially perpendicular to the X-direction. Therefore, in this modified example, the first electrode 41, including the first conductive portion 41a and the second conductive portion 41b, is substantially in contact only with the first end of the semiconductor layer 31. The other basic configurations are the same as those of the embodiments described above.

[0081] The configuration of this modified example can be formed by etching in the step shown in Figure 11A of the first manufacturing method described above, so that the edge of the insulating layer 32 is located in the same plane as the edge of the semiconductor layer 31. Alternatively, it can be formed by etching in the step shown in Figure 12J of the second manufacturing method described above, so that the edge of the insulating layer 32 is located in the same plane as the edge of the semiconductor layer 31.

[0082] In this modified example, the basic configuration is the same as that of the embodiment described above, and it is possible to obtain the same effects as the basic effects of the embodiment described above.

[0083] (Third embodiment) Next, a third embodiment will be described. The basic principles are the same as in the first embodiment, and explanations of the matters described in the first embodiment will be omitted.

[0084] Figure 14 is a schematic cross-sectional view perpendicular to the Y direction showing the configuration of a semiconductor memory device according to this embodiment.

[0085] In this embodiment, the MOS transistor 30 has a structure that extends in the X and Y directions, and the bit line 20 extends in the Z direction so as to penetrate the region of multiple MOS transistors 30 stacked in the Z direction. Specifically, the semiconductor layer 31, insulating layer 32, gate electrode 33, and gate insulating layer 34 of the MOS transistor 30 are provided so as to surround the side surface of the bit line 20.

[0086] The semiconductor layer 31 included in the MOS transistor 30 has a basically cylindrical shape when viewed from the X direction. Furthermore, the semiconductor layer 31 extends in the X and Y directions so as to surround the side surface of the bit line 20 when viewed from the Z direction. Similar to the first embodiment, the semiconductor layer 31 is formed from a two-dimensional material, and the first end of the semiconductor layer 31 is in contact with the first electrode 41 of the capacitor 40. The second end of the semiconductor layer 31 is in contact with the bit line 20 so as to surround its side surface. The end of the insulating layer 32 and the second end of the semiconductor layer 31 are substantially located in the same plane along the Z direction. The end of the insulating layer 32 on the side of the bit line 20 toward the center may be recessed away from the center of the bit line 20 relative to the end of the semiconductor layer 31 on the side of the bit line 20 toward the center (the second end). The gate electrode 33 is connected to the word line 10 extending in the Y direction.

[0087] The capacitor 40 includes a first electrode 41, a second electrode 42, and a capacitor material layer 43. Similar to the first embodiment, the inner surface of the first conductive portion of the first electrode 41 has an uneven shape, the interface between the first conductive portion (first electrode 41) and the capacitor material layer 43 is uneven, and the interface between the capacitor material layer 43 and the second electrode 42 is also uneven.

[0088] Next, the method for manufacturing the semiconductor memory device according to this embodiment will be described with reference to the cross-sectional views shown in Figures 15A to 15E.

[0089] In this embodiment, as in the process shown in Figure 7A of the first embodiment, first, a laminated structure is formed in which the insulating layer 60 and the sacrificial layer 71 are alternately stacked in the Z direction. Next, the insulating layer 60 and the sacrificial layer 71 are etched to form a plurality of grooves (not shown) in the laminated structure that extend in the X and Z directions, respectively. Furthermore, the plurality of grooves are filled with an insulating material (such as silicon oxide) similar to that of the insulating layer 60. The insulating material filled in the plurality of grooves separates and insulates the memory cells aligned in the Y direction.

[0090] Next, a structure as shown in Figure 15A is formed. Specifically, first, a hole for the bit line 20 is formed. Then, a portion of the sacrificial layer 71 is removed to form a space for the MOS transistor 30. After that, a conductive film that will become the gate electrode 33 and a sacrificial layer (neither shown) are formed in order to fill the space for the MOS transistor 30 and on the inner surface of the hole for the bit line 20. The hole for the bit line 20 is not completely filled with the sacrificial layer. Next, the sacrificial layer is etched to expose the conductive film on the inner surface of the hole for the bit line 20 and its vicinity. By selectively removing this exposed conductive film, the gate electrode 33 is formed along the inner surface of the space. After that, the hole for the bit line 20 and the space for the MOS transistor 30 are filled with the sacrificial layer 81. Furthermore, a portion of the sacrificial layer 71 is removed to form a space for the word line 10, and the word line 10 is formed in the space. In this way, a structure as shown in Figure 15A is obtained.

[0091] Next, as shown in Figure 15B, a portion of the sacrificial layer 71 is removed to form a space 82 for the capacitor 40, and then the sacrificial layer 81 is removed to form a hole 83.

[0092] Next, as shown in Figure 15C, a gate insulating layer 34, a semiconductor layer 31, and an insulating layer 32 are formed in the space 82 and the hole 83. At this time, the hole 83 is not completely filled with the insulating layer 32, leaving a hole 84.

[0093] Next, as shown in Figure 15D, the semiconductor layer 31 and the insulating layer 32 are etched through the hole 84 to form the hole 85 and the recess 86. By forming the recess 86, the X-direction edge (second edge) of the semiconductor layer 31 is exposed.

[0094] Next, as shown in Figure 15E, the bit line 20 is formed by filling the hole 85 and the recess 86 with a conductive material.

[0095] The subsequent basic steps are the same as in the first embodiment. That is, the semiconductor layer 31 and insulating layer 32 in the region where the MOS transistor 30 is formed are left, and the semiconductor layer 31 and insulating layer 32 in the region where the capacitor 40 is formed are removed. This creates a space for the capacitor 40, and by forming the first electrode 41, the second electrode 42 and the capacitor material layer 43 within the space for the capacitor 40, the structure shown in Figure 14 is obtained.

[0096] As described above, the basic configuration of this embodiment is the same as that of the first embodiment, and the same effects as those of the first embodiment can be obtained in this embodiment as well. In this embodiment, the above-described embodiments and modifications can also be applied.

[0097] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0098] 10... Word line 20... Bit line 30…MOS transistor 31…Semiconductor layer 32…Insulating layer (first insulating layer) 33…Gate electrode 34…Gate insulating layer 40…Capacitor 41...First electrode 41a...First conductive part 41b...Second conductive part 42...Second electrode 43...Capacitor material layer 44...Insulating layer (second insulating layer) 50…membrane cells 60...Insulation area

Claims

1. A semiconductor memory device comprising a plurality of memory cells arranged in a first direction and a second direction intersecting the first direction, Each of the plurality of memory cells extends in a third direction intersecting the first and second directions and includes a MOS transistor and a capacitor adjacent to the MOS transistor in the third direction. The MOS transistor includes a first insulating layer stretched in the third direction, a semiconductor layer stretched in the third direction so as to surround the side surface of the first insulating layer and formed of a two-dimensional material, and a gate electrode provided on the outside of the semiconductor layer. The capacitor includes a first electrode, a second electrode, and a capacitor material layer extending in the third direction, wherein the first electrode surrounds the side surface of the second electrode, and the capacitor material layer is provided between the first electrode and the second electrode. The first electrode is in contact with the first end of the semiconductor layer in the third direction. Semiconductor memory device.

2. The semiconductor layer has a tubular structure that extends in the third direction. The semiconductor memory device according to claim 1.

3. When viewed from the third direction, the first end has a ring-shaped form. The semiconductor memory device according to claim 2.

4. The first electrode is in further contact with a portion of the inner surface of the semiconductor layer located near the first end. The semiconductor memory device according to claim 1.

5. The first electrode includes a first conductive portion, The interface between the first conductive portion and the capacitor material layer is uneven. The semiconductor memory device according to claim 1.

6. The first conductive portion is formed of a material containing carbon or a metallic element. The semiconductor memory device according to claim 5.

7. The first electrode further includes a second conductive portion, The first conductive portion is provided between the second conductive portion and the capacitor material layer. The semiconductor memory device according to claim 5.

8. The two-dimensional material is selected from materials containing tungsten (W) and sulfur (S), materials containing tungsten (W) and selenium (Se), materials containing molybdenum (Mo) and sulfur (S), materials containing molybdenum (Mo) and selenium (Se), and materials containing molybdenum (Mo) and tellurium (Te). The semiconductor memory device according to claim 1.

9. The first electrode is further in contact with the third end of the first insulating layer. The semiconductor memory device according to claim 1.

10. The end of the first insulating layer in the third direction is recessed in the third direction relative to the first end of the semiconductor layer. The semiconductor memory device according to claim 9.

11. The end of the first insulating layer in the third direction and the first end of the semiconductor layer are substantially located in the same plane. The semiconductor memory device according to claim 9.

12. The capacitor further includes a second insulating layer extending in the third direction, The second electrode is provided on the outside of the second insulating layer. The semiconductor memory device according to claim 1.

13. Further includes insulating regions that insulate adjacent memory cells from one another. The semiconductor memory device according to claim 1.

14. The invention further includes word lines connecting a plurality of memory cells arranged in the first direction, The word line includes the gate electrode. The semiconductor memory device according to claim 1.

15. The system further includes bit lines connecting a plurality of memory cells arranged in the second direction, The bit line is connected to a region including the second end in the third direction of the semiconductor layer. The semiconductor memory device according to claim 1.

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