memory devices

Abstract

To reduce the manufacturing cost of memory devices. [Solution] The memory device of the embodiment includes first and second conductive members, a plurality of memory cells, and a shield electrode. Each of the first and second conductive members is provided extending in a first direction. The first and second conductive members are aligned in a second direction. The plurality of memory cells are aligned in the first direction. Each of the plurality of memory cells includes first and second transistors aligned in a second direction. The first transistor has a gate electrode and a channel region electrically connected to the first conductive member. The second transistor has a channel region electrically connected to the second conductive member and a gate electrode electrically connected to the channel region of the first transistor. The shield electrode is electrically connected to the second conductive member between each of two adjacent memory cells in the first direction and is provided so as to overlap with the gate electrode of the second transistor in the first direction.

Description

Technical Field

[0001] The embodiments relate to a memory device.

Background Art

[0002] A DRAM (Dynamic Random Access Memory) having memory cells stacked in three dimensions is known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] To provide a low-cost three-dimensional stacked memory.

Means for Solving the Problems

[0005] The memory device of the embodiment includes a substrate, a first conductive member and a second conductive member, a plurality of memory cells, and a shield electrode. Each of the first conductive member and the second conductive member is provided to extend in a first direction intersecting the surface of the substrate. The first conductive member and the second conductive member are arranged side by side in a second direction parallel to the surface of the substrate. The plurality of memory cells are arranged side by side in the first direction. Each of the plurality of memory cells includes a first transistor and a second transistor arranged side by side in the second direction. The first transistor has a gate electrode and a channel region electrically connected to the first conductive member. The second transistor has a channel region electrically connected to the second conductive member and a gate electrode electrically connected to the channel region of the first transistor. The shield electrode is provided between two adjacent memory cells in the first direction among the plurality of memory cells, is electrically connected to the second conductive member, and is provided so as to overlap the gate electrode of the second transistor in the first direction. [Brief explanation of the drawing]

[0006] [Figure 1] A block diagram showing an example of the configuration of a memory system equipped with a memory device according to the first embodiment. [Figure 2] A perspective view showing an example of the structure of a memory device according to the first embodiment. [Figure 3] A circuit diagram showing an example of the circuit configuration of a memory cell in a memory device according to the first embodiment. [Figure 4] A cross-sectional view showing an example of the structure of a memory cell array in a memory device according to the first embodiment. [Figure 5] A cross-sectional view along the VV line in Figure 4, showing an example of the structure of a memory cell array in a memory device according to the first embodiment. [Figure 6] A cross-sectional view along the line VI-VI in Figure 4 shows an example of the structure of a memory cell array in a memory device according to the first embodiment. [Figure 7] A cross-sectional view showing an example of the structure in the manufacturing process of a memory device according to the first embodiment. [Figure 8] A cross-sectional view showing an example of the structure in the manufacturing process of a memory device according to the first embodiment. [Figure 9] A cross-sectional view showing an example of the structure in the manufacturing process of a memory device according to the first embodiment. [Figure 10] A cross-sectional view along line XX in Figure 9, showing an example of the structure in the manufacturing process of a memory device according to the first embodiment. [Figure 11] A cross-sectional view showing an example of the structure in the manufacturing process of a memory device according to the first embodiment. [Figure 12] A cross-sectional view along line XII-XII in Figure 11, showing an example of the structure in the manufacturing process of a memory device according to the first embodiment. [Figure 13] A cross-sectional view showing an example of the structure in the manufacturing process of a memory device according to the first embodiment. [Figure 14]Cross-sectional view showing an example of the structure in the manufacturing process of the memory device according to the first embodiment. [Figure 15] Cross-sectional view taken along line XV-XV of FIG. 14, showing an example of the structure in the manufacturing process of the memory device according to the first embodiment. [Figure 16] Cross-sectional view showing an example of the structure in the manufacturing process of the memory device according to the first embodiment. [Figure 17] Cross-sectional view showing an example of the structure in the manufacturing process of the memory device according to the first embodiment. [Figure 18] Cross-sectional view showing an example of the structure in the manufacturing process of the memory device according to the first embodiment. [Figure 19] Cross-sectional view showing an example of the structure in the manufacturing process of the memory device according to the first embodiment. [Figure 20] Cross-sectional view showing an example of the structure in the manufacturing process of the memory device according to the first embodiment. [Figure 21] Cross-sectional view showing an example of the structure in the manufacturing process of the memory device according to the first embodiment. [Figure 22] Cross-sectional view showing an example of the structure in the manufacturing process of the memory device according to the first embodiment. [Figure 23] Cross-sectional view showing an example of the structure in the manufacturing process of the memory device according to the first embodiment. [Figure 24] Cross-sectional view showing an example of the structure in the manufacturing process of the memory device according to the first embodiment. [Figure 25] Circuit diagram showing an example of the circuit configuration of the memory cell included in the memory device according to the comparative example. [Figure 26] Cross-sectional view showing an example of the structure of the memory cell array included in the memory device according to the comparative example. [Figure 27] Cross-sectional view showing an example of the structure of the memory cell array included in the memory device according to the second embodiment. [Figure 28] Cross-sectional view taken along line XXVIII-XXVIII of FIG. 27, showing an example of the structure of the memory cell array included in the memory device according to the second embodiment. [Figure 29]A cross-sectional view taken along line XXIX-XXIX of FIG. 27 showing an example of the structure of a memory cell array included in a memory device according to the second embodiment. [Figure 30] A cross-sectional view showing an example of the structure in the manufacturing process of a memory device according to the second embodiment. [Figure 31] A cross-sectional view taken along line XXXI-XXXI of FIG. 30 showing an example of the structure in the manufacturing process of a memory device according to the second embodiment. [Figure 32] A cross-sectional view showing an example of the structure in the manufacturing process of a memory device according to the second embodiment. [Figure 33] A cross-sectional view showing an example of the structure in the manufacturing process of a memory device according to the second embodiment. [Figure 34] A cross-sectional view taken along line XXXIV-XXXIV of FIG. 33 showing an example of the structure in the manufacturing process of a memory device according to the second embodiment. [Figure 35] A cross-sectional view showing an example of the structure in the manufacturing process of a memory device according to the second embodiment. [Figure 36] A cross-sectional view taken along line XXXVI-XXXVI of FIG. 35 showing an example of the structure in the manufacturing process of a memory device according to the second embodiment. [Figure 37] A cross-sectional view showing an example of the structure in the manufacturing process of a memory device according to the second embodiment. [Figure 38] A cross-sectional view showing an example of the structure in the manufacturing process of a memory device according to the second embodiment. [Figure 39] A cross-sectional view taken along line XXXIX-XXXIX of FIG. 38 showing an example of the structure in the manufacturing process of a memory device according to the second embodiment. [Figure 40] A cross-sectional view showing an example of the structure in the manufacturing process of a memory device according to the second embodiment. [Figure 41] A cross-sectional view taken along line XLI-XLI of FIG. 40 showing an example of the structure in the manufacturing process of a memory device according to the second embodiment. [Figure 42] A cross-sectional view showing an example of the structure of a memory cell array included in a memory device according to the third embodiment. [Figure 43] A cross-sectional view along the line XLIII-XLIII in Figure 42 shows an example of the structure of a memory cell array in a memory device according to the third embodiment. [Figure 44] A cross-sectional view showing an example of the structure of a memory cell array in a memory device according to the third embodiment, and a cross-sectional view along the line XLIV-XLIV in Figure 42. [Figure 45] A cross-sectional view showing an example of the structure in the manufacturing process of a memory device according to the third embodiment. [Figure 46] A cross-sectional view showing an example of the structure in the manufacturing process of a memory device according to the third embodiment. [Figure 47] A cross-sectional view along the line XLVII-XLVII in Figure 46 shows an example of the structure in the manufacturing process of a memory device according to the third embodiment. [Figure 48] A cross-sectional view showing an example of the structure in the manufacturing process of a memory device according to the third embodiment. [Figure 49] A cross-sectional view along the XLIX-XLIX line in Figure 48, showing an example of the structure in the manufacturing process of a memory device according to the third embodiment. [Figure 50] A cross-sectional view showing an example of the structure in the manufacturing process of a memory device according to the third embodiment. [Figure 51] A cross-sectional view showing an example of the structure in the manufacturing process of a memory device according to the third embodiment. [Figure 52] A cross-sectional view along the line LII-LII in Figure 50, showing an example of the structure in the manufacturing process of a memory device according to the third embodiment. [Figure 53] A cross-sectional view showing an example of the structure in the manufacturing process of a memory device according to the third embodiment. [Figure 54] A cross-sectional view showing an example of the structure in the manufacturing process of a memory device according to the third embodiment. [Figure 55] A cross-sectional view along the LV-LV line in Figure 54, showing an example of the structure in the manufacturing process of a memory device according to the third embodiment. [Figure 56] A cross-sectional view showing an example of the structure in the manufacturing process of a memory device according to the third embodiment. [Figure 57] A cross-sectional view along line XVII-XVII in Figure 56, showing an example of the structure in the manufacturing process of a memory device according to the third embodiment. [Figure 58] A cross-sectional view showing an example of the structure in the manufacturing process of a memory device according to the third embodiment. [Figure 59] A cross-sectional view showing an example of the structure in the manufacturing process of a memory device according to the third embodiment. [Figure 60] A cross-sectional view showing an example of the structure in the manufacturing process of a memory device according to the third embodiment. [Figure 61] A cross-sectional view showing an example of the structure in the manufacturing process of a memory device according to the third embodiment. [Figure 62] A cross-sectional view along the line LXII-LXII in Figure 61, showing an example of the structure in the manufacturing process of a memory device according to the third embodiment. [Figure 63] A cross-sectional view showing an example of the structure of a memory cell array in a memory device according to a modified example of the third embodiment. [Figure 64] A cross-sectional view showing an example of the structure of a memory cell array in a memory device according to a modified example of the third embodiment. [Figure 65] A perspective view showing an example of the structure of a memory device according to the fourth embodiment. [Figure 66] A circuit diagram showing an example of the circuit configuration of a memory cell in a memory device according to the fourth embodiment. [Figure 67] A cross-sectional view showing an example of the structure of a memory cell array in a memory device according to the fourth embodiment. [Figure 68] A cross-sectional view along the line LXVIII-LXVIII in Figure 67 shows an example of the structure of a memory cell array in a memory device according to the fourth embodiment. [Figure 69] A cross-sectional view along the LXIX-LXIX line in Figure 67 shows an example of the structure of a memory cell array in a memory device according to the fourth embodiment. [Figure 70] A cross-sectional view showing an example of the structure in the manufacturing process of a memory device according to the fourth embodiment. [Figure 71]A cross-sectional view showing an example of the structure in the manufacturing process of a memory device according to the fourth embodiment. [Figure 72] A cross-sectional view showing an example of the structure in the manufacturing process of a memory device according to the fourth embodiment. [Figure 73] A cross-sectional view showing an example of the structure in the manufacturing process of a memory device according to the fourth embodiment. [Figure 74] A cross-sectional view showing an example of the structure in the manufacturing process of a memory device according to the fourth embodiment. [Figure 75] A cross-sectional view showing an example of the structure in the manufacturing process of a memory device according to the fourth embodiment. [Figure 76] A cross-sectional view showing an example of the structure in the manufacturing process of a memory device according to the fourth embodiment. [Figure 77] A cross-sectional view showing an example of the structure in the manufacturing process of a memory device according to the fourth embodiment. [Figure 78] A cross-sectional view showing an example of the structure in the manufacturing process of a memory device according to the fourth embodiment. [Figure 79] A cross-sectional view showing an example of the structure in the manufacturing process of a memory device according to the fourth embodiment. [Modes for carrying out the invention]

[0007] Each embodiment will be described below with reference to the drawings. Each embodiment illustrates an apparatus or method for realizing the technical idea of ​​the invention. The drawings are schematic or conceptual. The dimensions and proportions in each drawing are not necessarily the same as those of actual objects. In the following description, components having substantially the same function and configuration are denoted by the same reference numerals.

[0008] In this specification, a predetermined direction parallel to the top surface of the substrate is referred to as the "X direction." A direction parallel to the top surface of the substrate and perpendicular to the X direction is referred to as the "Y direction." A direction perpendicular to the top surface of the substrate is referred to as the "Z direction." A cross-section parallel to both the X and Z directions is referred to as the "XZ cross-section." A cross-section parallel to both the X and Y directions is referred to as the "XY cross-section." In this specification, expressions such as "top" and "bottom" are based on the substrate. For example, the direction away from the substrate along the Z direction is referred to as "top," and the direction approaching the substrate along the Z direction is referred to as "bottom." Furthermore, when referring to a certain configuration as the "bottom surface" or "bottom end," it means the surface or end of that configuration that is on the substrate side. When referring to a certain configuration as the "top surface" or "top end," it means the surface or end of that configuration that is on the opposite side of the substrate. Furthermore, a surface that intersects with the X or Y direction is referred to as a "side surface."

[0009] <1> First Embodiment The memory device 100 according to the first embodiment is a type of DRAM (Dynamic Random Access Memory) equipped with memory cells stacked in three dimensions. Details of the memory device 100 according to the first embodiment will be described below.

[0010] <1-1> Composition First, the configuration of the memory device 100 according to the first embodiment will be explained using Figures 1 to 6.

[0011] <1-1-1> Configuration of memory device 100 Figure 1 is a block diagram showing an example configuration of a memory system 1 comprising a memory device 100 according to a first embodiment. As shown in Figure 1, the memory system 1 includes, for example, a memory device 100 and a memory controller 200. The memory device 100 is connected to the memory controller 200 and is configured to read and write data based on instructions from the memory controller 200. The memory device 100 receives, for example, an address ADR, a command CMD, data DT, and a control signal CNT from the memory controller 200. The memory device 100 sends the control signal CNT and data DT to the memory controller 200. The memory device 100 includes, for example, a memory cell array 110, a row control circuit 120, a column control circuit 130, a read / write circuit 140, an input / output circuit 150, and a control circuit 160.

[0012] The memory cell array 110 is a circuit used for storing data. Although not shown in the diagram, the memory cell array 110 includes, for example, a plurality of memory cells MC, a plurality of word lines, and a plurality of bit lines. Each memory cell MC can store at least one bit of data. The plurality of word lines include a plurality of write word lines WWL and a plurality of read word lines RWL. The plurality of bit lines include a plurality of write bit lines WBL and a plurality of read bit lines RBL. Each memory cell MC is connected to a pair of write word lines WWL and read word lines RWL, and a pair of write bit lines WBL and read bit lines RBL. For example, a row address is assigned to the pair of write word lines WWL and read word lines RWL. For example, a column address is assigned to the pair of write bit lines WBL and read bit lines RBL. Each memory cell MC can be identified by its row address and column address.

[0013] The row control circuit 120 controls the wiring (write word line WWL and read word line RWL) assigned in the row direction in the memory cell array 110. The row control circuit 120 selects (activates) a word line according to the address ADR. The row control circuit 120 also sets the unselected word line to an unselected state (deactivates). The row control circuit 120 then supplies a predetermined voltage to the selected word line and the unselected word line, respectively. The row control circuit 120 includes, for example, a driver circuit for generating a voltage to be applied to the word line WL and an address decoder for decoding the address ADR. The row control circuit 120 may select a pair of write word line WWL and read word line RWL based on the decoding result of the address ADR.

[0014] The column control circuit 130 controls the wiring (bit lines BL) assigned in the column direction in the memory cell array 110. The column control circuit 130 includes, for example, an address decoder that decodes the address ADR and a sense amplifier. The sense amplifier can amplify the voltage of the read bit line RBL. For example, when the read word line RWL is activated by the row control circuit 120, the voltage of the read bit line RBL changes according to the data (charge) stored in the associated memory cell MC. The sense amplifier then amplifies the change in the voltage of the read bit line RBL to a voltage that the read / write circuit 140 can read. The column control circuit 130 can also apply a voltage to the write bit line WBL corresponding to the data to be written to the memory cell MC. When the write word line WWL is activated by the row control circuit 120, data (charge) is stored in the memory cell MC associated with the write bit line WBL and the activated write word line WWL.

[0015] The read / write circuit 140 is configured to write data to the memory cell array 110 and read data from the memory cell array 110. For example, when writing data, the read / write circuit 140 sends a signal (voltage or current) corresponding to the data requested to be written to the memory cell array 110 to the memory cell array 110 via the column control circuit 130. When reading data, the read / write circuit 140 receives a signal (voltage or current) corresponding to the data read from the memory cell array 110 via the column control circuit 130. The read / write circuit 140 can then read (determine) the data stored in the memory cell MC by detecting a change in the voltage or current of the read bit line RBL. The memory device 100 may also have separate circuits for writing data and reading data.

[0016] The input / output circuit 150 is an interface circuit that manages communication between the memory device 100 and the memory controller 200. The input / output circuit 150 receives commands CMD, addresses ADR, data DT (for example, data requested to be written to the memory cell array 110), and multiple control signals CNT from the memory controller 200. The input / output circuit 150 sends the control signals CNT and data DT (for example, data read from the memory cell array 110) to the memory controller 200.

[0017] The control circuit 160 controls the row control circuit 120, column control circuit 130, read / write circuit 140, etc., based on the command CMD and control signal CNT, and executes the operations that the memory device 100 should perform. The control circuit 160 controls the row control circuit 120, column control circuit 130, read / write circuit 140, etc., at timings synchronized with the clock signal CLK. In the memory device 100, data writing and data reading are performed at timings synchronized with the clock signal CLK. The clock signal CLK may be generated internally within the memory device 100 or supplied externally. The control circuit 160 may also be referred to as a sequencer, internal controller, etc.

[0018] <1-1-2> Structure of memory device 100 The structure of the memory device 100 according to the first embodiment will be described below. In the following description, we will explain the case where the extension direction of the memory cell MC corresponds to the X direction, the extension directions of the write word line WWL and the read word line RWL each correspond to the Y direction, and the extension directions of the write bit line WBL and the read bit line RBL each correspond to the Z direction.

[0019] Figure 2 is a perspective view showing an example of the structure of a memory device 100 according to the first embodiment. As shown in Figure 2, the memory device 100 includes a semiconductor substrate SUB. A memory cell array 110 is provided above the semiconductor substrate SUB. Hereinafter, the region in which the memory cell array 110 is provided will be referred to as the "memory region (MR)". The semiconductor substrate SUB is, for example, a silicon (Si) substrate containing P-type impurities such as boron (B). An insulating layer and an electrode layer, not shown in the figure, are provided on the upper surface of the semiconductor substrate SUB. These insulating layers and electrode layers constitute a control circuit for controlling the memory device 100. For example, a sense amplifier is provided in the region directly below the memory cell array 110.

[0020] The memory cell array 110 includes a plurality of memory cells MC, a plurality of write word lines WWL, a plurality of read word lines RWL, and a plurality of ground lines GND. Furthermore, the memory cell array 110 includes a plurality of memory layers ML aligned in the Z direction. Each memory layer ML includes a pair of write word lines WWL and read word lines RWL aligned in the X direction, and a plurality of memory cells MC aligned in the Y direction. In each memory layer ML, each of the plurality of memory cells MC is positioned between the pair of write word lines WWL and read word lines RWL. Each of the plurality of memory cells MC is electrically connected to the pair of write word lines WWL and read word lines RWL.

[0021] In the memory region MR, a pair of write bit lines WBL and read bit lines RBL are aligned in the X direction. In the memory region MR, multiple write bit lines WBL are aligned in the Y direction. In the memory region MR, multiple read bit lines RBL are aligned in the Y direction. A ground wire GND is provided between each pair of write bit lines WBL and read bit lines RBL. That is, in the memory region MR, multiple ground wires GND are aligned in the Y direction. The ground wire GND also extends in the Z direction. Each pair of write bit lines WBL and read bit lines RBL and their associated ground wire GND are electrically connected to one memory cell MC in each memory layer ML.

[0022] The structure of the memory device 100 according to the first embodiment is not limited to the structure shown in Figure 2. In the memory area MR, the number of write word lines WWL aligned in the Z direction and the number of read word lines RWL aligned in the Z direction may each be 2 or more. Similarly, in the memory area MR, the number of write bit lines WBL aligned in the Y direction and the number of read bit lines RBL aligned in the Y direction may each be 2 or more.

[0023] <1-1-3> Circuit configuration of memory cell MC Figure 3 is a circuit diagram showing an example of the circuit configuration of a memory cell MC in the memory device 100 according to the first embodiment. Figure 3 shows one memory cell MC, a pair of write word lines WWL and read word line RWL, a pair of write bit lines WBL and read bit line RBL, and a ground line GND. As shown in Figure 3, the memory cell MC has a 3T0C (3 transistors 0 capacitors) configuration. Specifically, the memory cell MC includes, for example, a write transistor WT, read transistors RT1 and RT2, and a storage node SN.

[0024] The write transistor WT is, for example, a field-effect NMOS transistor. The gate electrode of the write transistor WT is connected to the write word line WWL. One electrode of the write transistor WT is connected to the write bit line WBL. The other electrode of the write transistor WT is connected to the storage node SN. Each of the one and the other electrodes of the write transistor WT functions as either a source electrode or a drain electrode, depending on the voltage supplied (applied) to the write transistor WT.

[0025] The readout transistor RT1 is, for example, a field-effect NMOS transistor. The gate electrode of the readout transistor RT1 corresponds to the storage node SN. One electrode of the readout transistor RT1 is connected to the ground wire GND. The other electrode of the readout transistor RT1 is connected to one electrode of the readout transistor RT2. Each of the electrodes of the readout transistor RT1 functions as either a source electrode or a drain electrode, depending on the voltage supplied (applied) to the readout transistor RT1.

[0026] The readout transistor RT2 is, for example, a field-effect NMOS transistor. The gate electrode of the readout transistor RT2 is connected to the readout word line RWL. The other electrode of the readout transistor RT2 is connected to the readout bit line RBL. Each of the electrodes of the readout transistor RT2 functions as either a source electrode or a drain electrode, depending on the voltage supplied (applied) to the readout transistor RT2.

[0027] The storage node SN has, for example, parasitic capacitance (<1fF). The memory cell MC can store data according to the potential of the parasitic capacitance of the storage node SN, i.e., the amount of charge stored in the storage node SN. In this way, data is written to the parasitic capacitance of the storage node SN. The leakage current from the storage node SN is limited by the leakage current of the write transistor WT. Therefore, in a read operation, the memory device 100 can read the data from the memory cell MC non-destructively by reading the current of the read transistor RT1 according to the potential of the storage node SN.

[0028] In the memory device 100 according to the first embodiment, a shield electrode SH is provided near the memory cell MC. The shield electrode SH is electrically connected to the ground wire GND. The shield electrode SH is positioned opposite the storage node SN to suppress interference between two adjacent memory cells MC in the Z direction. In Figure 3, the parasitic capacitance between the storage node SN and the shield electrode SH is shown as the parasitic capacitance SC. The detailed arrangement of two adjacent memory cells MC in the Z direction and the shield electrode SH will be described later.

[0029] During a write operation, the control circuit 160 applies a predetermined voltage VON1, for example, that is higher than the power supply voltage VDD and above the threshold voltage of the write transistor WT, to the write word line WWL that is the target of the write operation, and applies the ground voltage VSS or a voltage VOFF1 lower than VSS to the other write word lines WWL. This can cause the write transistor WT to which the predetermined voltage VON1 is applied to turn ON. The control circuit 160 then applies the power supply voltage VDD or the ground voltage VSS to the write bit line WBL that is the target of the write operation, depending on the data to be written. Note that during a write operation, all write bit lines WBL in the memory cell array 110 may be the target of the write operation, or some of the write bit lines WBL may be the target of the write operation. The control circuit 160 may leave the write bit lines WBL that are not the target of the write operation in a floating state.

[0030] In a read operation, the control circuit 160 applies, for example, the power supply voltage VDD or a predetermined voltage VON2 higher than VDD and above the threshold voltage of the read transistor RT2 to the read word line RWL that is the target of the read operation, and applies the ground voltage VSS or a voltage VOFF2 lower than VSS to the other read word lines RWL. This can cause the read transistor RT2 to turn ON when the power supply voltage VDD is applied. The control circuit 160 also sets the read bit line RBL to be read, for example, to a floating state after applying VDD to it. Alternatively, the control circuit 160 may fix the ground line GND to VDD and set the read bit line RBL to be read to a floating state after applying, for example, VSS. Here, if the storage node SN of the memory cell MC that is the target of the read operation is charged by the power supply voltage VDD, the read transistor RT1 turns ON. Then, current flows from the read bit line RBL to the ground line GND via the read transistors RT1 and RT2, or the read bit line RBL is discharged. On the other hand, if the storage node SN of the memory cell MC that is the target of the read operation is discharged by the ground voltage VSS, the read transistor RT1 will be in the off state. In this case, no current flows through the read bit line RBL via the read transistors RT1 and RT2, and the read bit line RBL is not discharged. Note that in the read operation, all read bit lines RBL in the memory cell array 110 may be the target of the read operation, or some of the read bit lines RBL may be the target of the read operation. The control circuit 160 may apply, for example, the power supply voltage VDD or the ground voltage VSS to the read bit lines RBL that are not the target of the read operation.

[0031] <1-1-4> Structure of the memory cell array 110 Figures 4 to 6 are cross-sectional views showing an example of the structure of a memory cell array 110 provided in the memory device 100 according to the first embodiment. Figure 4 corresponds to the XZ cross-section of the memory cell array 110 provided in the memory area MR in the first embodiment, and shows an extracted region containing two adjacent memory cells MC in the Z direction. Figure 5 corresponds to the cross-section along the VV line in Figure 4. Figure 6 corresponds to the cross-section along the VI-VI line in Figure 4.

[0032] As shown in Figure 4, in the memory region MR, a separation layer SL is provided between two adjacent memory cells MC in the Z direction. In other words, in the memory region MR, the memory layer ML and the separation layer SL are stacked alternately in the Z direction. The separation layer SL is configured to separate two adjacent memory cells MC in the Z direction. Two adjacent memory cells MC in the Z direction are separated and insulated via the separation layer SL. The memory cell array 110 also includes, for example, an insulating layer 10, conductive members 20, 21 and 22, semiconductor layers 30 and 31, insulating layers 40 and 41, conductive layers 50 and 51, conductive layer 60, insulating layer 61, and conductive layers 70 to 73 in the memory region MR.

[0033] The insulating layer 10 is provided on each of the multiple separation layers SL that are aligned in the Z direction. In other words, in the memory area MR, multiple insulating layers 10 are aligned in the Z direction. The insulating layer 10 includes an insulator such as silicon oxide (SiO2).

[0034] Each of the conductive members 20, 21, and 22 is a cylindrical via wiring that extends in the Z direction and penetrates the alternately stacked memory layer ML and separation layer SL. The conductive members 20, 21, and 22 are aligned in the X direction. Conductive member 20 functions as a write bit line WBL. Conductive member 21 functions as a ground line GND. Conductive member 22 functions as a read bit line RBL. Each of the conductive members 20, 21, and 22 has, for example, a metal provided in the center in a plan view, a barrier conductive film provided on the side surface of the metal column, and a conductive oxide film provided on the side surface of the barrier conductive film. For example, in each of the conductive members 20, 21, and 22, the metal in the center contains tungsten (W), the barrier conductive film contains titanium nitride (TiN), and the conductive oxide film contains a conductive oxide.

[0035] In each of the conductive members 20, 21, and 22, the central metal is stretched in the Z direction and provided in a columnar shape. In each of the conductive members 20, 21, and 22, the barrier conductive film is stretched in the Z direction and provided in a substantially cylindrical shape. In each of the conductive members 20, 21, and 22, the conductive oxide is stretched in the Z direction along the outer surface (side surface) and provided in a substantially cylindrical shape. Note that each of the conductive members 20, 21, and 22 may contain ruthenium (Ru), iridium (Ir), or other metals instead of the conductive oxide film. Alternatively, each of the conductive members 20, 21, and 22 may contain only the conductive oxide, or only ruthenium (Ru), iridium (Ir), or other metals.

[0036] The semiconductor layer 30 has a cylindrical first portion that is stretched in the Z direction and provided on the side surface of the conductive member 20, and a second portion that is stretched in the X direction in the memory layer ML. The semiconductor layer 30 is an oxide semiconductor containing, for example, at least one element from gallium (Ga) and aluminum (Al), as well as indium (In), zinc (Zn), and oxygen (O). The semiconductor layer 30 may be any other oxide semiconductor.

[0037] The insulating layer 40 has a cylindrical first portion that extends in the Z direction and is provided on the side surface of the first portion of the semiconductor layer 30, and a second portion that is provided on the upper surface, lower surface, both sides in the Y direction, and one side in the X direction (conductive layer 70 side) of the second portion of the semiconductor layer 30 in the memory layer ML. The insulating layer 40 contains an insulator such as silicon oxide (SiO2).

[0038] The conductive layer 50 is provided for each memory layer ML and surrounds the conductive member 20 in a plan view. Specifically, the conductive layer 50 of each memory layer ML has a disc-shaped structure that surrounds a part of the semiconductor layer 30 and the insulating layer 40 and is penetrated by the conductive member 20. More specifically, the conductive layer 50 is provided on the upper surface, lower surface, both sides in the Y direction, and one side in the X direction (conductive layer 70 side) of the second portion of the insulating layer 40 in each memory layer ML. The conductive layer 50 faces the upper surface, lower surface, both sides in the Y direction, and one side in the X direction (conductive layer 70 side) of the second portion of the semiconductor layer 30 via the insulating layer 40. The conductive layer 50 includes, for example, a conductive material such as titanium nitride (TiN) or a conductive oxide such as indium tin oxide (ITO).

[0039] In each memory layer ML, the set of semiconductor layer 30, insulator layer 40, and conductive layer 50 provided around the conductive member 20 constitutes a transistor having a disc-shaped GAA (Gate-All-Around) structure. The set of semiconductor layer 30, insulator layer 40, and conductive layer 50 provided around the conductive member 20 functions as a write transistor WT. Specifically, the portion of the semiconductor layer 30 facing the conductive layer 50 via the insulator layer 40 functions as the channel region of the write transistor WT. The portion of the insulator layer 40 sandwiched between the semiconductor layer 30 and the conductive layer 50 functions as the gate insulating film of the write transistor WT. The conductive layer 50 functions as the gate electrode of the write transistor WT.

[0040] The semiconductor layer 31 has a cylindrical first portion stretched in the Z direction and provided on the side surface of the conductive member 21, a second portion stretched in the X direction in the memory layer ML, and a cylindrical third portion stretched in the Z direction and provided on the side surface of the conductive member 22. The semiconductor layer 30 is an oxide semiconductor containing, for example, at least one element from gallium (Ga) and aluminum (Al), as well as indium (In), zinc (Zn), and oxygen (O). The semiconductor layer 31 may be made of other oxide semiconductors.

[0041] The insulating layer 41 has a cylindrical first portion that extends in the Z direction and is provided on the side surface of the third portion of the semiconductor layer 31, and a second portion that is provided on the upper surface, lower surface, both sides in the Y direction, and both sides in the X direction of the second portion of the semiconductor layer 31 in the memory layer ML. The insulating layer 41 contains an insulator such as silicon oxide (SiO2).

[0042] A conductive layer 51 is provided for each memory layer ML and surrounds the conductive member 21 in a plan view. A conductive layer 52 is provided for each memory layer ML and surrounds the conductive member 22 in a plan view. In each memory layer ML, the conductive layers 51 and 52 are separated in the X direction.

[0043] Each memory layer ML has a disc-shaped structure that surrounds a portion of the semiconductor layer 31 and the insulating layer 41 and is penetrated by the conductive member 21. Specifically, the conductive layer 51 is provided on the upper surface, lower surface, both sides in the Y direction near the conductive member 21, and one side in the X direction (conductive layer 70 side) of the second portion of the insulating layer 41. The conductive layer 51 faces the upper surface, lower surface, both sides in the Y direction near the conductive member 21, and one side in the X direction (conductive layer 70 side) of the second portion of the semiconductor layer 31 via the insulating layer 41. One side of the conductive layer 51 in the X direction is connected to the semiconductor layer 30. Therefore, multiple conductive layers 51 aligned in the Z direction are commonly connected to the conductive member 20 via the semiconductor layer 30. The conductive layer 51 includes, for example, a conductive material such as titanium nitride (TiN), or a conductive oxide such as indium tin oxide (ITO). The conductive layer 51 may also contain ruthenium (Ru), iridium (Ir), or other metals.

[0044] Each memory layer ML has a conductive layer 52 that surrounds the semiconductor layer 31 and the other parts of the insulating layer 41 and has a disc-shaped structure that is penetrated by the conductive member 22. Specifically, the conductive layer 52 is provided on the upper surface, lower surface, both sides in the Y direction near the conductive member 22, and the other side in the X direction (conductive layer 72 side) of the second part of the insulating layer 41. The conductive layer 52 faces the upper surface, lower surface, both sides in the Y direction near the conductive member 22, and the other side in the X direction (conductive layer 72 side) of the second part of the semiconductor layer 31 via the insulating layer 41. The conductive layer 52 includes, for example, a conductive material such as titanium nitride (TiN) or a conductive oxide such as indium tin oxide (ITO).

[0045] In each memory layer ML, the set of semiconductor layer 31, insulator layer 41, and conductive layer 51 surrounding the conductive member 21 constitutes a transistor having a disc-shaped GAA structure. The set of semiconductor layer 31, insulator layer 41, and conductive layer 51 surrounding the conductive member 21 functions as a read transistor RT1. Specifically, the portion of the semiconductor layer 31 facing the conductive layer 51 via the insulator layer 41 functions as the channel region of the read transistor RT1. The portion of the insulator layer 41 sandwiched between the semiconductor layer 31 and the conductive layer 51 functions as the gate insulating film of the read transistor RT1. The conductive layer 51 functions as the gate electrode of the read transistor RT1. Furthermore, the conductive layer 51 also functions as a storage node SN.

[0046] In each memory layer ML, the set of semiconductor layer 31, insulator layer 41, and conductive layer 52 provided around the conductive member 22 constitutes a transistor having a disc-shaped GAA structure. The set of semiconductor layer 31, insulator layer 41, and conductive layer 52 provided around the conductive member 22 functions as a read transistor RT2. Specifically, the portion of the semiconductor layer 31 facing the conductive layer 52 via the insulator layer 41 functions as the channel region of the read transistor RT2. The portion of the insulator layer 41 sandwiched between the semiconductor layer 31 and the conductive layer 52 functions as the gate insulating film of the read transistor RT2. The conductive layer 52 functions as the gate electrode of the read transistor RT2. Thus, the read transistors RT1 and RT2 may be configured by sharing the semiconductor layer 31 and the insulator layer 41.

[0047] In each memory layer ML, the configuration corresponding to the write transistor WT, the configuration corresponding to the read transistor RT1, and the configuration corresponding to the read transistor RT2 are aligned in the X direction. In each memory layer ML, the pairs of write transistor WT and read transistors RT1 and RT2 aligned in the X direction constitute the memory cell MC.

[0048] The conductive layer 60 is provided for each separation layer SL and surrounds the conductive member 21 in a plan view. In other words, the conductive layer 60 of each separation layer SL has a disc-shaped structure that is penetrated by the conductive member 21. Specifically, the conductive layer 60 is provided extending in the X direction and is in contact with the side surface of the semiconductor layer 31. The conductive layer 60 of each separation layer SL is electrically connected to the conductive member 21 via the semiconductor layer 31. The conductive layer 60 is provided so as to overlap with the conductive layer 51 (storage node SN) in a plan view. It is more preferable that the conductive layer 60 completely overlaps with the conductive layer 51 in a plan view. The conductive layer 60 includes, for example, a conductive material such as titanium nitride (TiN) or a conductive oxide such as indium tin oxide (ITO).

[0049] An insulating layer 61 is provided for each separation layer SL. The insulating layer 61 of each separation layer SL is provided so as to cover the portion of the conductive layer 60 excluding the portion penetrated by the conductive member 21 and the semiconductor layer 31. Specifically, in each separation layer SL, the insulating layer 61 is provided on the upper surface, lower surface, both sides in the Y direction, and both sides in the X direction of the conductive layer 60. In each separation layer SL, the insulating layer 61 is in contact with the side surface of the first portion of the semiconductor layer 31. The conductive layer 60 is separated and insulated from the semiconductor layer 30, the second portion of the semiconductor layer 31 of two adjacent memory layers ML, the third portion of the semiconductor layer 31, and the conductive layers 50 and 51 of two adjacent memory layers ML, respectively, via the insulating layer 61. The insulating layer 61 has a different composition from the respective compositions of the insulating layers 40 and 41. The insulating layer 61 includes, for example, silicon nitride (SiN), silicon oxynitride (SiON), hafnium oxide (HfO2), or aluminum oxide (Al2O3).

[0050] Thus, conductive layers 60 and 51, separated from each other in the Z direction via an insulating layer 61, are alternately provided in the Z direction. In other words, in two adjacent memory cells MC in the Z direction, two adjacent conductive layers 51 (storage nodes SN) in the Z direction are adjacent via a conductive layer 60. The conductive layer 60 is then electrically connected to the conductive member 21. As a result, the conductive layer 60 can function as a shield electrode SH. In a plan view, it is more preferable that the shield electrode SH is larger than the storage node SN (conductive layer 51) and overlaps with the entire storage node SN.

[0051] A conductive layer 70 is provided for each memory layer ML. In each memory layer ML, the conductive layer 70 is provided on one side in the X direction. Conductive layers 71 are provided, for example, on the top surface, bottom surface, both sides in the Y direction, and the other side in the X direction of the conductive layer 70. In each memory layer ML, the other side in the X direction of the conductive layer 71 is in contact with the conductive layer 50. As a result, the conductive layer 70 is electrically connected to the conductive layer 50 (gate electrode of the write transistor WT) via the conductive layer 71. The pair of conductive layers 70 and 71 functions as a write word line WWL. The conductive layer 70 is, for example, a conductor such as tungsten (W). The conductive layer 71 is, for example, a barrier conductive film such as titanium nitride (TiN).

[0052] A conductive layer 72 is provided for each memory layer ML. In each memory layer ML, the conductive layer 72 is provided on the other side in the X direction. The conductive layer 73 is provided, for example, on the top surface, bottom surface, both sides in the Y direction, and one side in the X direction of the conductive layer 72. In each memory layer ML, one side of the conductive layer 73 in the X direction is in contact with the conductive layer 52. As a result, the conductive layer 72 is electrically connected to the conductive layer 52 (gate electrode of the read transistor RT2) via the conductive layer 73. The pair of conductive layers 72 and 73 functions as a read word line RWL. The conductive layer 72 is, for example, a conductor such as tungsten (W). The conductive layer 73 is, for example, a barrier conductive film such as titanium nitride (TiN).

[0053] As shown in Figure 5, the memory cell array 110 includes a plurality of insulating members 11 in the memory layer ML. Each insulating member 11 is provided extending in the X direction along the memory cell MC. The plurality of insulating members 11 are arranged in the Y direction. Although not shown, each insulating member 11 is further provided extending in the Z direction and penetrating the memory layer ML and the separation layer SL, which are stacked alternately in the Z direction. As a result, each insulating member 11 electrically separates the plurality of memory cells MC (not shown) arranged in the Y direction. In this specification, the region extending in the X direction and containing the memory cells MC is referred to as the "memory area MA". The region extending in the X direction and containing the insulating members 11 is referred to as the "trench area TA". In other words, the memory area MA and the trench area TA are arranged alternately in the Y direction.

[0054] In the XY cross-section, the conductive layers 70 and 71 corresponding to the write word line WWL have portions that extend in the Y direction across the alternately arranged memory area MA and trench area TA in the Y direction. In the XY cross-section, the conductive layers 72 and 73 corresponding to the read word line RWL have portions that extend in the Y direction across the alternately arranged memory area MA and trench area TA in the Y direction. One side of each insulating member 11 (the conductive layer 70 side) is in contact with the write word line WWL (e.g., conductive layer 71). The other side of each insulating member 11 (the conductive layer 72 side) is in contact with the read word line RWL (e.g., conductive layer 73).

[0055] In the XY cross-section, one side portion of the semiconductor layer 30 in the X direction is formed in a straight line along the conductive layer 70, for example. In the XY cross-section, the other side portion of the semiconductor layer 30 in the X direction is formed in an arc shape along a circle centered on the center position of the conductive member 21 (via wiring). In the XY cross-section, the portion of the insulator layer 40 provided near the boundary between the write transistor WT and the read transistor RT1 is in contact with two adjacent insulating members 11 in the Y direction. In the XY cross-section, the conductive layer 50 is in contact with two adjacent insulating members 11 in the Y direction.

[0056] In the XY cross-section, one side portion of the semiconductor layer 31 in the X direction is formed in an arc shape along a circle centered on the center position of the conductive member 21 (via wiring). In the XY cross-section, the other side portion of the semiconductor layer 31 in the X direction is formed in a straight line, for example, along the conductive layer 72. In the XY cross-section, the portion of the insulator layer 41 provided near the boundary between the readout transistors RT1 and RT2 is in contact with two adjacent insulating members 11 in the Y direction. In the XY cross-section, both side portions of the conductive layer 51 in the Y direction are in contact with two adjacent insulating members 11 in the Y direction. Also, in the XY cross-section, one side portion of the conductive layer 51 in the X direction is formed in an arc shape along a circle centered on the center position of the conductive member 21 (via wiring). In the XY cross-section, both side portions of the conductive layer 52 in the Y direction are in contact with two adjacent insulating members 11 in the Y direction. Furthermore, in the XY cross-section, the other side portion of the conductive layer 52 in the X direction is formed in a straight line along the conductive layer 72.

[0057] Although not shown in the illustration, in the XY cross-section, the other side portion of the conductive layer 50 in the X direction is formed in an arc shape along a circle centered on the center position of the conductive member 21 (via wiring). Although not shown in the illustration, in the XY cross-section, the side portions on both sides of the conductive layer 51 in the X direction are formed in an arc shape along a circle centered on the center position of the conductive member 21 (via wiring). Although not shown in the illustration, in the XY cross-section, the one side portion of the conductive layer 52 in the X direction is formed in an arc shape along a circle centered on the center position of the conductive member 21 (via wiring).

[0058] As shown in Figure 6, the memory cell array 110 includes a plurality of insulating members 11 in the separation layer SL, similar to the memory layer ML. The insulating layer 10 is provided in the separation layer SL overlapping the write word line WWL, the read word line RWL, and the memory cell MC in the Z direction. The insulating layer 10 has portions that are penetrated by the conductive member 20, the semiconductor layer 30, and the insulating layer 40, and portions that are penetrated by the conductive member 22, the semiconductor layer 31, and the insulating layer 41. Furthermore, the insulating layer 10 is divided into one side and the other side in the X direction via a pair of conductive layers 60 and insulating layers 61.

[0059] In the XY cross-section, the side portions of the conductive layer 60 on both sides in the Y direction are formed linearly along two adjacent insulating members 11 in the Y direction. Also, in the XY cross-section, one side portion of the conductive layer 60 in the X direction and the other side portion of the conductive layer 60 in the X direction are each formed in an arc shape along a circle centered on the center position of the conductive member 21 (via wiring). In the XY cross-section, the insulating layer 61 is provided so as to surround the outer circumference of the conductive layer 60. Specifically, in the XY cross-section, the insulating layer 61 has a portion sandwiched between the insulating member 11 and the conductive layer 60 on one side in the Y direction, a portion sandwiched between the insulating member 11 and the conductive layer 60 on the other side in the Y direction, and a portion sandwiched between the insulating layer 10 and the conductive layer 60. The width in the Y direction between the two ends of the insulating layer 61 in the Y direction is approximately equal to the width in the Y direction of the memory area MA. The width in the X direction between the two ends of the insulating layer 61 in the X direction is wider than the width in the Y direction of the memory area MA.

[0060] In this specification, "conductive oxide" includes, for example, indium tin oxide (ITO), indium zinc oxide (IZO), ruthenium oxide (RuO2), iridium oxide (IrO2), or other oxygen-containing conductive materials. In the memory cell array 110, the gate electrode of the write transistor WT and the write word line WWL may be connected via a conductive oxide. Similarly, the gate electrode of the read transistor RT2 and the read word line RWL may be connected via a conductive oxide.

[0061] <1-2> Manufacturing method Next, the process of forming the memory cell array 110 as a method for manufacturing the memory device 100 according to the first embodiment will be described using Figures 7 to 24. Each of Figures 7 to 24 is a cross-sectional view showing an example of the structure in the manufacturing process of the memory device 100 according to the first embodiment. Each of Figures 7 to 24 shows the same region as either the memory area MR shown in Figure 4, the memory layer ML shown in Figure 5, or the separation layer SL shown in Figure 6. In this specification, "processing through a predetermined hole" corresponds to performing processing while other holes are covered with a mask, sacrificial member, etc. That is, when processing through a predetermined hole is performed, processing of the components associated with other holes is not performed or is suppressed.

[0062] First, as shown in Figure 7, the insulating layer 10 and the sacrificial member 12 are stacked alternately. In this process, the layer on which the insulating layer 10 is provided corresponds to the separation layer SL, and the layer on which the sacrificial member 12 is provided corresponds to the memory layer ML. The insulating layer 10 is, for example, silicon oxide (SiO2). The sacrificial member 12 is, for example, silicon nitride (SiN).

[0063] Next, as shown in Figure 8, insulating members 11 are formed in the trench region TA, separating the stacked insulating layer 10 and sacrificial member 12. Specifically, first, the insulating layer 10 and sacrificial member 12 provided in the region corresponding to the insulating member 11 are removed by an anisotropic etching process such as RIE (Reactive Ion Etching). Then, an insulator is embedded in the trench portion formed by the etching process by CVD (Chemical Vapor Deposition) or the like. As a result, insulating members 11 are formed in each trench region TA. The insulating member 11 is, for example, silicon oxide (SiO2).

[0064] Next, as shown in Figure 9, (1) at least two slits SLT are formed, (2) a recess is formed by selectively removing a portion of the sacrificial member 12 in the memory region MA, and (3) a sacrificial member 80 is embedded in the formed recess. In this step, the two slits SLT are formed by an anisotropic etching process such as RIE, so as to remove the alternately stacked insulating layers 10 and sacrificial members 12 in the vicinity of the region corresponding to the write word line WWL and the region corresponding to the read word line RWL, respectively. In this step, the recess is formed by a wet etching process or the like so as to separate the sacrificial member 12 of each memory layer ML in each of the multiple memory regions MA arranged in the Y direction. Figure 10 corresponds to a cross-section along the XX line in Figure 9. As shown in Figure 10, the sacrificial members 80 provided on each side in the X direction are formed to fill the recess of each memory layer ML. The sacrificial member 80 is, for example, amorphous silicon (aSi).

[0065] Next, as shown in Figure 11, a hole HGND is formed in the memory region MA in the portion corresponding to the ground line GND. Figure 12 corresponds to a cross-section along the line XII-XII in Figure 11. As shown in Figure 12, the hole HGND is formed by an anisotropic etching process such as RIE, so as to penetrate the insulator layer 10 and sacrificial member 12 that are extended in the Z direction and stacked.

[0066] Next, as shown in Figure 13, (1) a recess is formed by selectively removing a portion of the sacrificial member 12 of each memory layer ML via the hole HGND, and (2) a sacrificial member 81 is embedded in the formed recess. The recess formed in this step corresponds to the location where the read transistor RT1 is formed. The sacrificial member 81 covers the side surface of the insulator layer 10 within the hole HGND. In this step, the sacrificial member 81 may be formed to embed the hole HGND. The sacrificial member 81 is, for example, amorphous silicon (aSi).

[0067] Next, as shown in Figure 14, in the memory area MA, (1) a hole HWBL is formed in the portion corresponding to the write bit line WBL, and (2) a hole HRBL is formed in the portion corresponding to the read bit line RBL. Figure 15 corresponds to a cross-section along the XV-XV line in Figure 14. As shown in Figure 15, each of the holes HWBL and HRBL is formed by an anisotropic etching process such as RIE, so as to penetrate the insulator layer 10 and sacrificial member 12 that are stretched in the Z direction and stacked.

[0068] Next, as shown in Figure 16, (1) recesses are formed by selectively removing the sacrificial members 12 of each memory layer ML via the holes HWBL and HRBL, and (2) conductive films 82 and sacrificial members 83 are sequentially formed to fill the formed recesses. In this process, for example, wet etching is used to form the recesses. The recesses formed in correspondence with the holes HWBL correspond to the locations where the write transistor WT is formed. In this process, the recesses formed in correspondence with the holes HRBL correspond to the locations where the read transistor RT2 is formed. The conductive films 82 of the holes HWBL and HRBL are in contact with the sacrificial members 80 and 81, respectively, in the memory layer ML. The conductive films 82 also cover the upper surface, lower surface, both sides in the X direction, and both sides in the Y direction of the insulator layer 10 in correspondence with the holes HWBL and HRBL, respectively. In this process, the sacrificial members 83 may be formed to fill the holes HWBL and HRBL. The conductive films 82 and sacrificial members 83 are formed by, for example, CVD. The conductive film 82 is, for example, titanium nitride (TiN). The sacrificial member 83 is, for example, amorphous silicon (aSi).

[0069] Next, as shown in Figure 17, (1) the sacrificial member 81 provided in correspondence with the hole HGND is selectively removed, and (2) a sacrificial member 84 is formed so as to fill the recess in each memory layer ML that is in contact with the hole HGND. In this step, for example, wet etching is used to remove the sacrificial member 81. The sacrificial member 84 is in contact with the conductive film 82 provided in the recess in contact with the hole HWBL and the conductive film 82 provided in the recess in contact with the hole HRBL in each memory layer ML. The sacrificial member 84 is, for example, silicon nitride (SiN). In this step, the sacrificial member 84 may be formed to fill the hole HGND.

[0070] Next, as shown in Figure 18, (1) a portion of the sacrificial member 84 provided in the hole HGND is removed, exposing the insulating layer 10 on the side surface of the hole HGND, and (2) a portion of the insulating layer 10 of each separation layer SL is selectively removed via the hole HGND. In this process, for example, wet etching is used to remove the sacrificial member 84. In this process, the recess portion that is in contact with the hole HGND and formed in the separation layer SL corresponds to the location where the shield electrode SH is formed.

[0071] Next, as shown in Figure 19, (1) an insulating film corresponding to the insulating layer 61 and a conductive film corresponding to the conductive layer 60 are formed, and (2) the insulating film and conductive film provided on the side portion of the hole HGND are removed. This forms the structure corresponding to the shield electrode SH. In addition, this process exposes the side portions of the sacrificial members 84 of each memory layer ML within the hole HGND. In this process, for example, CVD is used to form the insulating film and conductive film.

[0072] Next, as shown in Figure 20, the sacrificial members 84 of each memory layer ML are selectively removed via the hole HGND, and conductive layers 50, 51, and 52 are formed in each memory layer ML, an insulating layer 40 is formed, and sacrificial members 85 and 86 are formed. The structure shown in Figure 20 can be formed by appropriately performing etching and film deposition processes using the hole HGND, HWBL, and HRBL. The conductive layer 51 is, for example, a conductive oxide such as indium tin oxide (ITO). The conductive layers 50 and 52 of each memory layer ML are formed by processing a conductive film 82. The sacrificial member 85 is provided so as to cover the insulating layer 40 within the hole HWBL. The sacrificial member 86 is provided in each memory layer ML so as to fill the space sandwiched between the disc-shaped conductive layers 51, the space sandwiched between the disc-shaped conductive layers 52, and the space between the conductive layers 51 and 52. Each of the sacrificial members 85 and 86 is, for example, amorphous silicon (aSi).

[0073] Next, as shown in Figure 21, (1) a portion of the conductive layer 51 provided on the memory layer ML is removed via the hole HGND, (2) the sacrificial members 86 of each memory layer ML are selectively removed, and (3) an insulating layer 41 is formed via the hole HGND and HRBL. The conductive layer 51 processed in this process corresponds to the shape of the conductive layer 51 (storage node SN) shown in Figure 4. For example, wet etching is used to remove the conductive layer 51. The insulating layer 41 is formed by, for example, CVD.

[0074] Next, as shown in Figure 22, the sacrificial member 87 is embedded in the space sandwiched in the Z direction by the insulating layer 41 in each memory layer ML. The sacrificial member 87 is formed by, for example, CVD. In this process, the sacrificial member 87 formed on the side portions of the holes HGND and HRBL is removed by etch-back processing. The sacrificial member 87 is, for example, amorphous silicon (aSi).

[0075] Next, as shown in Figure 23, the insulating layer 41 formed on the side portion of each separation layer SL is selectively removed via the hole HGND. As a result, a portion of the conductive layer 60 is exposed in the portion of the hole HGND corresponding to each separation layer SL. For example, wet etching is used to remove the insulating layer 41.

[0076] Next, as shown in Figure 24, (1) sacrificial members 85 and 87 are selectively removed, (2) semiconductor layers 30 and 31 are formed, and (3) conductive members 20, 21, and 22 are embedded in the holes HWBL, HGND, and HRBL, respectively. Subsequently, sacrificial member 80 is removed, and the configuration corresponding to the write word line WWL and the read word line RWL is formed. As a result, the structure of the memory cell array 110 shown in Figures 4 to 6 is completed.

[0077] <1-3> Effects of the First Embodiment The memory device 100 according to the first embodiment provides a low-cost three-dimensional stacked memory. The effects of the memory device 100 according to the first embodiment will be explained in detail below using comparative examples.

[0078] As a memory cell with a gain cell structure, a memory cell MC with a 3T0C (3 transistors 0 capacitors) configuration is known. Compared to a memory cell with a 1T1C configuration, the 3T0C configuration is expected to offer (1) improved tWT (write time), (2) lower power consumption, and (3) improved cell size scalability for high stacking due to the elimination of capacitors.

[0079] Figure 25 is a circuit diagram showing an example of the circuit configuration of a memory cell MCz in the comparative example memory device 100. As shown in Figure 25, the memory cell MCz has a configuration in which the shield electrode SH is omitted from the circuit configuration of the memory cell MC shown in Figure 3. Figure 26 is a cross-sectional view showing an example of the structure of a memory cell array 110 in the comparative example memory device 100. As shown in Figure 26, in the comparative example memory device 100, the shield electrode SH is not placed in the separation layer SL. That is, two adjacent memory cells MCz in the Z direction are adjacent to each other with an insulating layer 10 in between.

[0080] In the comparative example, when the signals ("0" or "1") of the upper and lower memory cells MCz change due to writing, the potential of the storage node SN is affected by coupling. Therefore, in the comparative example, the potential of the storage node SN interferes with two adjacent memory cells MCz in the Z direction. When stacking such memory cells MCz in high density, it is necessary to widen the stacking spacing of the memory cells MCz to suppress the effects of interference. However, widening the stacking spacing of memory cells MCz can lead to an increase in the size of the memory cell array and an increase in cost.

[0081] In contrast, the memory device 100 according to the first embodiment has a configuration in which a shield electrode SH is formed on each of the two separation layers SL adjacent to the storage node SN in the Z direction, and the shield electrode SH is electrically connected to the ground line GND. The shield electrode SH can suppress the effects of changes in the potential of the storage node SN due to writing to adjacent memory cells MC in the Z direction. In other words, it can suppress interference between the two memory cells MC arranged above and below the shield electrode SH.

[0082] As a result, the memory device 100 according to the first embodiment can reduce the pitch of memory cells MC arranged in the Z direction, providing a high-density and low-cost three-dimensional stacked memory. Furthermore, the shield electrode SH can add capacitance (<1fF) between the storage node SN and the ground line GND, thereby improving noise immunity. Since the shield electrode SH is formed only in the upper and lower regions of the storage node SN, the parasitic capacitance of the write word line WWL and the read word line RWL does not increase. In other words, the degradation of the characteristics of the memory cells MC due to the addition of the shield electrode SH can be suppressed.

[0083] <2> Second Embodiment In the memory device 100 according to the second embodiment, both sides of the shield electrode SH in the X direction are provided in a concave lens shape (arc shape) when viewed from above. The details of the memory device 100 according to the second embodiment will be described below, mainly focusing on the differences from the first embodiment.

[0084] <2-1> Composition First, the configuration of the memory device 100 according to the second embodiment will be described using Figures 27 to 29. Each of Figures 27 to 29 is a cross-sectional view showing an example of the structure of the memory cell array 110 provided in the memory device 100 according to the second embodiment. Figure 27 corresponds to the XZ cross-section of the memory cell array 110 provided in the memory area MR in the second embodiment, and shows an extracted area containing two adjacent memory cells MC in the Z direction. Figure 28 corresponds to the cross-section along the line XXVIII-XXVIII in Figure 27. Figure 29 corresponds to the cross-section along the line XXIX-XXIX in Figure 27.

[0085] The memory device 100 according to the second embodiment has the same configuration as the memory device 100 according to the first embodiment. On the other hand, the memory device 100 according to the second embodiment differs from the memory device 100 according to the first embodiment mainly in the shape of the conductive layers 50, 51 and 60 and the insulating layer 61. Hereinafter, the conductive layers 50, 51 and 60 and the insulating layer 61 of the memory device 100 according to the second embodiment will be referred to as conductive layers 50a, 51a and 60a and insulating layer 61a, respectively.

[0086] As shown in Figure 27, in each memory layer ML, the conductive layer 50a and conductive layer 52a have a shape that extends beyond the separation layer SL described in the first embodiment. Specifically, the width in the Z direction between the upper and lower ends of conductive layer 50a is wider than the width in the Z direction of the write word line WWL (conductive layers 70 and 71). The width in the Z direction between the upper and lower ends of conductive layer 52a is wider than the width in the Z direction of the read word line RWL (conductive layers 72 and 73). Note that the width in the Z direction between the upper and lower ends of conductive layer 50a and the width in the Z direction between the upper and lower ends of conductive layer 52a are, for example, approximately equal.

[0087] Therefore, the thickness in the Z direction of the portion of the insulating layer 10 sandwiched between two adjacent conductive layers 50a in the Z direction is thinner in the Z direction than the thickness in the Z direction of the portion sandwiched between two adjacent write word lines WWL in the Z direction. Similarly, the thickness in the Z direction of the portion of the insulating layer 10 sandwiched between two adjacent conductive layers 52a in the Z direction is thinner in the Z direction than the thickness in the Z direction of the portion sandwiched between two adjacent read word lines RWL in the Z direction. In addition, the distance between the upper and lower ends of the conductive layer 51a in the Z direction is narrower than the distance between the upper and lower ends of the conductive layer 50a in the Z direction and the distance between the upper and lower ends of the conductive layer 52a in the Z direction.

[0088] Furthermore, the insulating layer 61a is provided in a closed manner in the portion sandwiched between two adjacent conductive layers 50a in the Z direction and in the portion sandwiched between two adjacent conductive layers 52a in the Z direction. Therefore, in a plan view, the conductive layer 60a is positioned at a distance from each of the conductive layers 50a and 52a by the amount by which the insulating layer 61a closes off. As a result, the conductive layer 60a is not included in the portion sandwiched between two adjacent conductive layers 50a in the Z direction and in the portion sandwiched between two adjacent conductive layers 52a in the Z direction.

[0089] As shown in Figure 28, in the XY cross-section, the side portion of the semiconductor layer 30 in the second embodiment on the other side in the X direction (conductor layer 72) is formed in an arc shape along a circle centered on the center position of the conductive member 20 (via wiring). Although not shown, in the XY cross-section, the side portion of the conductive layer 50a on the other side in the X direction is formed in an arc shape along a circle centered on the center position of the conductive member 20 (via wiring). In the XY cross-section, the side portion of the semiconductor layer 31 in the second embodiment on one side in the X direction (conductor layer 70 side) is formed in an arc shape along a circle centered on the center position of the conductive member 20 (via wiring). Although not shown, in the XY cross-section, the side portion of the conductive layer 51a on one side in the X direction is formed in an arc shape along a circle centered on the center position of the conductive member 20 (via wiring). Although not shown, the other end of the conductive layer 50a in the X direction and the one end of the conductive layer 51a in the X direction face each other while maintaining a certain distance. Although not shown in the illustration, in the XY cross-section, the other side portion of the conductive layer 51a in the X direction is formed in an arc shape along a circle centered on the center position of the conductive member 22 (via wiring). Although not shown in the illustration, in the XY cross-section, the one side portion of the conductive layer 52a in the X direction is formed in an arc shape along a circle centered on the center position of the conductive member 22 (via wiring).

[0090] As shown in Figure 29, in the XY cross-section, one side portion of the conductive layer 60a in the X direction is formed in an arc shape along a circle centered on the center position of the conductive member 20 (via wiring). In the XY cross-section, the other side portion of the conductive layer 60a in the X direction is formed in an arc shape along a circle centered on the center position of the conductive member 22 (via wiring). In the XY cross-section, both the one side portion of the insulating layer 61a in the X direction and the other side portion of the insulating layer 61a in the X direction are formed in an arc shape along a circle centered on the center position of the conductive member 21 (via wiring). Furthermore, in the XY cross-section, the shapes of both the one portion of the insulating layer 61a in the X direction and the other portion of the insulating layer 61a in the X direction are convex lens-shaped. The width in the Y direction between the two ends of the insulating layer 61a in the Y direction is approximately equal to the width in the Y direction of the memory area MA. The width in the X direction between the two ends of the insulating layer 61a is wider than the width in the Y direction of the memory area MA. Furthermore, the width in the X direction of the portion of the insulating layer 61a sandwiched between the conductive layer 60a and the insulating layer 10 is narrower than the width in the X direction of the portion sandwiched between the conductive layer 60a and the insulating member 11.

[0091] Other configurations of the memory device 100 according to the second embodiment are the same as those of the memory device 100 according to the first embodiment.

[0092] <2-2> Manufacturing method Next, the process of forming the memory cell array 110 as a method for manufacturing the memory device 100 according to the second embodiment will be explained using Figures 30 to 41. Each of Figures 30 to 41 is a cross-sectional view showing an example of the structure in the manufacturing process of the memory device according to the second embodiment. Each of Figures 30 to 41 shows the same region as either the memory area MR shown in Figure 27, the memory layer ML shown in Figure 28, or the separation layer SL shown in Figure 29.

[0093] In the manufacturing method of the memory device 100 according to the second embodiment, first, the process described with reference to Figures 7 to 10 in the first embodiment is performed, and the structure shown in Figure 10 is formed.

[0094] Next, as shown in Figure 30, in the memory area MA, a hole HWBL is formed in the portion corresponding to the write bit line WBL, a hole HGND is formed in the portion corresponding to the ground line GND, and a hole HRBL is formed in the portion corresponding to the read bit line RBL. Figure 31 corresponds to a cross-section along the line XXXI-XXXI in Figure 30. As shown in Figure 31, Each of the holes HWBL, HGND, and HRBL is formed by an anisotropic etching process such as RIE, so as to penetrate the insulator layer 10 and sacrificial member 12 that are stretched in the Z direction and stacked.

[0095] Next, as shown in Figure 32, a sacrificial member 81a is embedded in the hole HGND. In this step, for example, CVD is used to form the sacrificial member 81a. In this step, it is sufficient that the sacrificial member 81a is formed to cover at least the insulating layer 10 and the sacrificial member 12 on the side surface of the hole HGND. The sacrificial member 81a is, for example, amorphous silicon (aSi).

[0096] Next, as shown in Figure 33, recesses are formed by selectively removing the sacrificial member 12 of each memory layer ML through the holes HWBL and HRBL. In this process, for example, wet etching is used to form the recesses. The recess formed corresponding to the hole HWBL corresponds to the location where the write transistor WT is formed. In this process, the recess formed corresponding to the hole HRBL corresponds to the location where the read transistor RT2 is formed. In the recesses of the holes HWBL and HRBL, a portion of the sacrificial member 80 is exposed. Figure 34 corresponds to a cross-section along the line XXXIV-XXXIV in Figure 33. As shown in Figure 34, in this process, the sacrificial member 12 of each memory region MA is processed in an arc shape along a circle centered on the center position of the hole HWBL on one side in the X direction (hole HWBL side) and on an arc shape along a circle centered on the center position of the hole HRBL on the other side in the X direction (hole HRBL side).

[0097] Next, as shown in Figure 35, isotropic etching is performed through the holes HWBL and HRBL, causing the insulating layer 10 of each separation layer SL to be recessed. As a result, in each memory layer ML, the recesses of the holes HWBL and HRBL are enlarged in the Z direction. In this process, the recesses enlarged in the Z direction of the holes HWBL and HRBL are processed so that they do not connect between two adjacent memory layers ML. For example, wet etching is used in this process. Figure 36 corresponds to a cross-section along the line XXXVI-XXXVI in Figure 35. As shown in Figure 36, in this process, the diameters of the holes HWBL and HRBL can be enlarged by recessing the insulating layer 10.

[0098] Next, as shown in Figure 37, the conductive film 82a and the sacrificial member 83a are formed in sequence so as to fill the recesses of the holes HWBL and HRBL, respectively. The conductive film 82a of the holes HWBL and HRBL are in contact with the sacrificial members 80 and 12, respectively, in the memory layer ML. The conductive film 82a also covers the top surface, bottom surface, both sides in the X direction, and both sides in the Y direction of the insulator layer 10 in the holes HWBL and HRBL, respectively. In this step, the sacrificial member 83a may be formed to fill the holes HWBL and HRBL, respectively. The conductive film 82a and the sacrificial member 83a are formed by, for example, CVD. The conductive film 82a is, for example, titanium nitride (TiN). The sacrificial member 83a is, for example, amorphous silicon (aSi).

[0099] Next, as shown in Figure 38, a portion of the insulating layer 10 of each separation layer SL is selectively removed via the hole HGND. For example, wet etching is used in this step. Figure 39 corresponds to a cross-section along the line XXXIX-XXXIX in Figure 38. As shown in Figure 39, in this step, the portion of the insulating layer 10 of each separation layer SL that is located on the hole HGND side is processed into an arc shape along a circle centered on the center position of the hole HGND in the XY cross-section.

[0100] Next, as shown in Figure 40, (1) an insulating film corresponding to the insulating layer 61a and a conductive film corresponding to the conductive layer 60a are formed, and (2) the insulating film and conductive film provided on the side surface of the hole HGND are removed. In this step, the insulating film corresponding to the insulating layer 61a is formed such that the portion sandwiched in the Z direction by the conductive film 82a is filled. This forms a structure corresponding to the shield electrode SH. In this step, the side surface of the sacrificial member 12 of each memory layer ML is exposed within the hole HGND. In this step, for example, CVD is used to form the insulating film and the conductive film. Figure 41 corresponds to a cross-section along the XLI-XLI line in Figure 40. As shown in Figure 41, the portion of the insulating layer 61a sandwiched in the Z direction by the conductive film 82a is formed in a convex lens shape in the XY cross-section. Therefore, the conductive layer 60a is formed in a constricted shape along the insulating layer 61a in the separation layer SL.

[0101] Subsequently, a process similar to that described with reference to Figures 20 to 24 in the first embodiment is performed, and structures corresponding to the write bit line WBL, ground line GND, read bit line RBL, write transistor WT, and read transistors RT1 and RT2 are formed. Then, the sacrificial member 80 is removed, and a configuration corresponding to the write word line WWL and read word line RWL is formed. As a result, the structure of the memory cell array 110 shown in Figures 27 to 29 is completed.

[0102] <2-3> Effects of the second embodiment In the memory device 100 according to the second embodiment, the insulating layer 10 of the separation layer SL is recessed by etching through holes HWBL and HRBL. Then, the shield electrode SH is formed by self-alignment using the difference in thickness of the cavity. Specifically, the conductive layer 51a corresponding to the storage node SN and the conductive layer 60a corresponding to the shield electrode SH are formed by self-alignment.

[0103] By forming the conductive layer 51a and the conductive layer 60a in a self-aligned manner, the shapes of the shield electrode SH (conductive layer 60a) and the conductive layer 50a connected to the write word line WWL match. In other words, the manufacturing method of the memory device 100 according to the second embodiment allows the shield electrode SH and the write word line WWL to be formed without overlapping in the Z direction. As a result, an increase in parasitic capacitance between the shield electrode SH and the write word line WWL can be suppressed.

[0104] Similarly, by forming the conductive layer 52a and the conductive layer 60a in a self-aligned manner, the shapes of the shield electrode SH (conductive layer 60a) and the conductive layer 52a connected to the read word line RWL match. That is, in the memory device 100 according to the second embodiment, the shield electrode SH and the read word line RWL can be formed without overlapping in the Z direction. As a result, an increase in parasitic capacitance between the shield electrode SH and the read word line RWL can be suppressed.

[0105] As described above, the memory device 100 according to the second embodiment can suppress the overlap between the shield electrode SH and other electrodes, thereby suppressing the increase in parasitic capacitance. Furthermore, by forming the conductive layers 50a, 51a, 52a, and 60a in a self-aligned manner, the area of ​​the memory cell MC that does not function as a channel can be reduced. As a result, the gate electrode of the write transistor WT, the shield electrode SH, and the storage node SN can be efficiently arranged, and the area of ​​the memory cell MC can be reduced. Therefore, the memory device 100 according to the second embodiment can reduce the size of the memory cell array 110 and reduce the manufacturing cost of the memory device 100.

[0106] <3> Third Embodiment In the memory device 100 according to the third embodiment, in a plan view, one side of the shield electrode SH in the X direction is provided in a concave lens shape (arc shape), and the other side of the shield electrode SH in the X direction is provided in a convex lens shape (arc shape). The details of the memory device 100 according to the third embodiment will be described below, mainly focusing on the differences from the first and second embodiments.

[0107] <3-1> Composition First, the configuration of the memory device 100 according to the third embodiment will be described using Figures 42 to 44. Each of Figures 42 to 44 is a cross-sectional view showing an example of the structure of the memory cell array 110 provided in the memory device 100 according to the third embodiment. Figure 42 corresponds to the XZ cross-section of the memory cell array 110 provided in the memory area MR in the third embodiment, and shows an extracted region containing two adjacent memory cells MC in the Z direction. Figure 43 corresponds to the cross-section along the line XLIII-XLIII in Figure 42. Figure 44 corresponds to the cross-section along the line XLIV-XLIV in Figure 42.

[0108] The memory device 100 according to the third embodiment has the same configuration as the memory device 100 according to the first embodiment. On the other hand, the memory device 100 according to the third embodiment differs from the memory device 100 according to the first embodiment mainly in the shape of the conductive layers 50, 51 and 60 and the insulating layer 61. Hereinafter, the conductive layers 50, 51 and 60 and the insulating layer 61 of the memory device 100 according to the third embodiment will be referred to as conductive layers 50b, 51b and 60b and insulating layer 61b, respectively.

[0109] As shown in Figure 42, in each memory layer ML, the conductive layer 50b and conductive layer 52b have a shape that extends beyond the separation layer SL described in the first embodiment. Specifically, the width in the Z direction between the upper and lower ends of conductive layer 50b is wider than the width in the Z direction of the write word line WWL (conductive layers 70 and 71). The width in the Z direction between the upper and lower ends of conductive layer 52b is wider than the width in the Z direction of the read word line RWL (conductive layers 72 and 73). Note that the width in the Z direction between the upper and lower ends of conductive layer 50b and the width in the Z direction between the upper and lower ends of conductive layer 52b are, for example, approximately equal.

[0110] Therefore, the thickness in the Z direction of the portion of the insulating layer 10 sandwiched between two adjacent conductive layers 50b in the Z direction is thinner in the Z direction than the thickness in the Z direction of the portion sandwiched between two adjacent write word lines WWL in the Z direction. Similarly, the thickness in the Z direction of the portion of the insulating layer 10 sandwiched between two adjacent conductive layers 52b in the Z direction is thinner in the Z direction than the thickness in the Z direction of the portion sandwiched between two adjacent read word lines RWL in the Z direction. In addition, the distance between the upper and lower ends of conductive layer 51b in the Z direction is narrower than the distance between the upper and lower ends of conductive layer 50b in the Z direction and the distance between the upper and lower ends of conductive layer 52b in the Z direction.

[0111] Furthermore, the insulating layer 61b is provided in a closed manner in the portion sandwiched between two adjacent conductive layers 50b in the Z direction and in the portion sandwiched between two adjacent conductive layers 52b in the Z direction. Therefore, in a plan view, the conductive layer 60b is positioned at a distance from each of the conductive layers 50b and 52b by the amount by which the insulating layer 61b closes it. As a result, the conductive layer 60b is not included in the portion sandwiched between two adjacent conductive layers 50b in the Z direction and in the portion sandwiched between two adjacent conductive layers 52b in the Z direction.

[0112] As shown in Figure 43, in the XY cross-section, the side portion of the semiconductor layer 30 in the third embodiment on the other side in the X direction (conductor layer 72) is formed in an arc shape along a circle centered on the center position of the conductive member 20 (via wiring). Although not shown, in the XY cross-section, the side portion of the conductive layer 50b on the other side in the X direction is formed in an arc shape along a circle centered on the center position of the conductive member 20 (via wiring). In the XY cross-section, the side portion of the semiconductor layer 31 in the third embodiment on one side in the X direction (conductor layer 70 side) is formed in an arc shape along a circle centered on the center position of the conductive member 20 (via wiring). Although not shown, in the XY cross-section, the side portion of the conductive layer 51b on one side in the X direction is formed in an arc shape along a circle centered on the center position of the conductive member 20 (via wiring). Although not shown in the illustration, in the XY cross-section, the other side portion of the conductive layer 51b in the X direction is formed in an arc shape along a circle centered on the center position of the conductive member 21 (via wiring). Although not shown in the illustration, in the XY cross-section, the one side portion of the conductive layer 52b in the X direction is formed in an arc shape along a circle centered on the center position of the conductive member 21 (via wiring).

[0113] As shown in Figure 44, in the XY cross-section, one side portion of the conductive layer 60b in the X direction is formed in an arc shape along a circle centered on the center position of the conductive member 20 (via wiring). In the XY cross-section, the other side portion of the conductive layer 60b in the X direction is formed in an arc shape along a circle centered on the center position of the conductive member 21 (via wiring). In the XY cross-section, both the one side portion of the insulating layer 61b in the X direction and the other side portion of the insulating layer 61b in the X direction are formed in an arc shape along a circle centered on the center position of the conductive member 21 (via wiring). Furthermore, in the XY cross-section, the shape of one side portion of the insulating layer 61b in the X direction is convex lens-shaped. The width in the Y direction between the two ends of the insulating layer 61b in the Y direction is approximately equal to the width in the Y direction of the memory area MA. The width in the X direction between the two ends of the insulating layer 61b in the X direction is wider than the width in the Y direction of the memory area MA. The width in the X direction of the portion of the insulating layer 61b sandwiched between the conductive layer 60b and the insulating layer 10 is narrower than the width in the X direction of the portion sandwiched between the conductive layer 60b and the insulating member 11.

[0114] The other configurations of the memory device 100 according to the third embodiment are the same as those of the memory device 100 according to the first embodiment.

[0115] <3-2> Manufacturing method Next, the process of forming the memory cell array 110 as a method for manufacturing the memory device 100 according to the third embodiment will be described using Figures 45 to 62. Each of Figures 45 to 62 is a cross-sectional view showing an example of the structure in the manufacturing process of the memory device 100 according to the third embodiment. Each of Figures 45 to 62 shows the same region as either the memory area MR shown in Figure 42, the memory layer ML shown in Figure 43, or the separation layer SL shown in Figure 44. In the method for manufacturing the memory device 100 according to the third embodiment, first, the process described in the first embodiment using Figures 7 to 10 is performed.

[0116] In the manufacturing method of the memory device 100 according to the third embodiment, first, the process described with reference to Figures 7 to 10 in the first embodiment is performed to form the structure shown in Figure 10. Then, the process described with reference to Figures 30 and 31 in the second embodiment is performed to form the structures shown in Figures 30 and 31.

[0117] Next, as shown in Figure 45, the sacrificial member 81b is embedded in the holes HGND and HRBL. In this step, for example, CVD is used to form the sacrificial member 81b. In this step, it is sufficient that the sacrificial member 81b is formed to cover at least the insulating layer 10 and the sacrificial member 12 on the sides of the holes HGND and HRBL. The sacrificial member 81b is, for example, amorphous silicon (aSi).

[0118] Next, as shown in Figure 46, a recess is formed by selectively removing the sacrificial member 12 of each memory layer ML through the hole HWBL. In this process, for example, wet etching is used to form the recess. The recess formed in correspondence with the hole HWBL corresponds to the location where the write transistor WT is formed. In each recess of the hole HWBL, a portion of the sacrificial member 80 is exposed. Figure 47 is a cross-sectional view along the line XLVII-XLVII in Figure 46. As shown in Figure 47, in this process, the sacrificial member 12 of each memory region MA is processed in an arc shape along a circle centered on the center position of the hole HWBL on one side in the X direction (hole HWBL side) in the XY cross section.

[0119] Next, as shown in Figure 48, isotropic etching is performed through the holes HWBL, and the insulating layer 10 of each separation layer SL is recessed. As a result, the recessed portion of the holes HWBL in each memory layer ML is expanded in the Z direction. In this process, the recessed portion of the holes HWBL expanded in the Z direction is processed so that it does not connect between two adjacent memory layers ML. For example, wet etching is used in this process. Figure 49 corresponds to a cross-section along the XLIX-XLIX line in Figure 48. As shown in Figure 49, in this process, the diameter of the holes HWBL can be expanded by recessing the insulating layer 10.

[0120] Next, as shown in Figure 50, the sacrificial member 88 is embedded in the hole HWBL. In this step, for example, CVD is used to form the sacrificial member 88. In this step, it is sufficient that the sacrificial member 88 is formed to cover at least the insulating layer 10, sacrificial member 12, and sacrificial member 80 on the side surface of the hole HWBL. The material of the sacrificial member 88 is different from that of the sacrificial member 81b. The sacrificial member 88 is, for example, amorphous carbon (aC). Next, as shown in Figure 51, (1) the sacrificial member 81b in the hole HGND is removed, and (2) a recess is formed by selectively removing a portion of the sacrificial member 12 of each memory layer ML through the hole HGND. As a result, the side surface of the sacrificial member 88 is exposed in the portion of the hole HGND corresponding to each memory layer ML. Figure 52 corresponds to a cross-section along the LII-LII line in Figure 50. As shown in Figure 52, on one side of the recess of the hole HGND in the X direction, the sacrificial member 12 is almost completely removed. On the other hand, on the other end of the recess of the hole HGND in the X direction, in the XY cross-section, the sacrificial member 12 is processed into an arc shape centered on the center position of the hole HGND.

[0121] Next, as shown in Figure 53, (1) a sacrificial member 89 is formed so as to fill the recess of the hole HGND, and (2) the hole HGND is filled by the sacrificial member 90. Each of the sacrificial members 89 and 90 is formed by, for example, CVD. The sacrificial members 89 and 90 are made of different materials. The sacrificial member 89 is, for example, amorphous silicon (aSi). The sacrificial member 90 is, for example, amorphous carbon (aC).

[0122] Next, as shown in Figure 54, a recess is formed by (1) removing the sacrificial member 81b in the hole HRBL and (2) selectively removing the sacrificial member 12 of each memory layer ML through the hole HRBL. As a result, the respective sides of the sacrificial members 80 and 89 are exposed in the portion of the hole HRBL corresponding to each memory layer ML. Figure 55 corresponds to the cross-section along the LV-LV line in Figure 54. As shown in Figure 55, on one side of the recess of the hole HRBL in the X direction, an arc-shaped sacrificial member 89 centered on the center position of the hole HGND is exposed in the XY cross-section. On the other hand, on the other side of the recess of the hole HRBL in the X direction, a linear sacrificial member 80 is exposed in the XY cross-section.

[0123] Next, as shown in Figure 56, isotropic etching is performed through the hole HRBL, and the insulating layer 10 of each separation layer SL is recessed. As a result, the recessed portion of the hole HRBL in each memory layer ML is expanded in the Z direction. In this process, the recessed portion of the hole HRBL expanded in the Z direction is processed so that it does not connect between two adjacent memory layers ML. For example, wet etching is used in this process. Figure 57 corresponds to a cross-section along the line XVII-XVII in Figure 56. As shown in Figure 57, in this process, the diameter of the hole HRBL can be expanded by recessing the insulating layer 10.

[0124] Next, as shown in Figure 58, the sacrificial member 91 is embedded in the hole HRBL. In this step, for example, CVD is used to form the sacrificial member 91. In this step, it is sufficient that the sacrificial member 91 is formed to cover at least the insulating layer 10 on the side surface of the hole HRBL, and the sacrificial members 80 and 89. The material of the sacrificial member 91 is different from that of the sacrificial members 80 and 89. The sacrificial member 91 is, for example, amorphous carbon (aC). Next, as shown in Figure 59, (1) the sacrificial member 90 in the hole HGND is selectively removed, and (2) the sacrificial member 89 in the hole HGND is removed such that the sacrificial member 89 in the recess of the hole HGND remains. In this step, for example, a wet etching process is used. This separates the sacrificial member 89 formed in the recess of the hole HGND between the memory layers ML. Then, within the hole HGND, the sides of the insulating layer 10 of each separation layer SL are exposed.

[0125] Next, as shown in Figure 60, a portion of the insulating layer 10 of each separation layer SL is selectively removed via the hole HGND. For example, wet etching is used in this step. In this step, the portion of the insulating layer 10 of each separation layer SL that is located on the hole HGND side is processed in an arc shape along a circle centered on the center position of the hole HGND in the XY cross-section (not shown).

[0126] Next, as shown in Figure 61, (1) an insulating film corresponding to the insulating layer 61b and a conductive film corresponding to the conductive layer 60b are formed, and (2) the insulating film and conductive film provided on the side surface of the hole HGND are removed. In this step, the insulating film corresponding to the insulating layer 61b is formed such that the portion sandwiched in the Z direction by the sacrificial members 88 or 91 is filled. This forms the structure corresponding to the shield electrode SH. In this step, the side surface of the sacrificial member 89 of each memory layer ML is exposed within the hole HGND. In this step, for example, CVD is used to form the insulating film and conductive film. Figure 62 corresponds to a cross-section along the LXII-LXII line in Figure 61. As shown in Figure 62, the portion of the insulating layer 61b sandwiched in the Z direction by the sacrificial member 88 is formed in a convex lens shape in the XY cross-section. Also, the portion of the insulating layer 61b sandwiched in the Z direction by the sacrificial member 91 is formed in an arc shape in the XY cross-section that is thicker than the thickness of the insulating layer 61b formed in this step.

[0127] Next, although not shown in the diagram, the sacrificial member 88 is removed via the hole HWBL, and the sacrificial member 91 is removed via the hole HRBL. Then, as explained with reference to Figure 37 in the second embodiment, the conductive film 82a and the sacrificial member 83a are formed in sequence so that the recesses of the holes HWBL and HRBL are filled. Subsequently, the same process as when the sacrificial member 84 was replaced with the sacrificial member 89 in the process explained with reference to Figures 20 to 24 in the first embodiment is performed, and structures corresponding to the write bit line WBL, ground line GND, read bit line RBL, write transistor WT, and read transistors RT1 and RT2 are formed. Then, the sacrificial member 80 is removed, and the configuration corresponding to the write word line WWL and read word line RWL is formed. As a result, the structure of the memory cell array 110 shown in Figures 42 to 44 is completed.

[0128] <3-3> Effects of the Third Embodiment In the memory device 100 according to the third embodiment, similar to the second embodiment, the insulating layer 10 of the separation layer SL is recessed by etching through holes HWBL and HRBL. Then, the shield electrode SH is formed by self-alignment using the difference in thickness of the cavity. Specifically, the conductive layer 51b corresponding to the storage node SN and the conductive layer 60b corresponding to the shield electrode SH are formed by self-alignment.

[0129] As a result, the memory device 100 according to the third embodiment can suppress the overlap between the shield electrode SH and other electrodes, and suppress the increase in parasitic capacitance, similar to the second embodiment. Furthermore, by forming the conductive layers 50b, 51b, 52b, and 60b in a self-aligned manner, the area of ​​the memory cell MC that does not function as a channel can be reduced. As a result, the gate electrode of the write transistor WT, the shield electrode SH, and the storage node SN can be efficiently arranged, and the area of ​​the memory cell MC can be reduced. Therefore, the memory device 100 according to the third embodiment can reduce the size of the memory cell array 110 and reduce the manufacturing cost of the memory device 100.

[0130] <3-4> Modified example of the third embodiment In the memory device 100 according to the third embodiment, the shape of the shield electrode SH may be inverted in the X direction. A modified example of the third embodiment will be described below with reference to Figures 63 and 64. In the modified example of the third embodiment, the shape of the XY cross-section in the memory region MR of the memory cell array 110 is assumed to be the same as in Figure 27.

[0131] Figures 63 and 64 are cross-sectional views showing an example of the structure of a memory cell array 110 provided in a modified memory device 100 according to the third embodiment. Figure 63 shows a cross-section at a similar location to the cross-section along line XXVIII-XXVIII in Figure 27. Figure 64 shows a cross-section at a similar location to the cross-section along line XXIX-XXIX in Figure 27.

[0132] As shown in Figure 63, in the XY cross-section, the side portion of the semiconductor layer 30 in the modified third embodiment on the other side in the X direction (the side with the conductor layer 72) is formed in an arc shape along a circle centered on the center position of the conductive member 21 (via wiring). Although not shown, in the XY cross-section, the side portion of the conductive layer 50b on the other side in the X direction is formed in an arc shape along a circle centered on the center position of the conductive member 21 (via wiring). In the XY cross-section, the side portion of the semiconductor layer 31 in the modified third embodiment on one side in the X direction (the side with the conductor layer 70) is formed in an arc shape along a circle centered on the center position of the conductive member 21 (via wiring). Although not shown, in the XY cross-section, the side portion of the conductive layer 51b on one side in the X direction is formed in an arc shape along a circle centered on the center position of the conductive member 21 (via wiring). Although not shown in the illustration, in the XY cross-section, the other side portion of the conductive layer 51b in the X direction is formed in an arc shape along a circle centered on the center position of the conductive member 22 (via wiring). Although not shown in the illustration, in the XY cross-section, the one side portion of the conductive layer 52b in the X direction is formed in an arc shape along a circle centered on the center position of the conductive member 22 (via wiring).

[0133] As shown in Figure 64, in the XY cross-section, one side portion in the X direction of the conductive layer 60b of the modified example of the third embodiment is formed in an arc shape along a circle centered on the center position of the conductive member 21 (via wiring). In the XY cross-section, the other side portion in the X direction of the conductive layer 60b of the modified example of the third embodiment is formed in an arc shape along a circle centered on the center position of the conductive member 22 (via wiring). In the XY cross-section, one side portion in the X direction of the insulator layer 61b of the modified example of the third embodiment is formed in an arc shape along a circle centered on the center position of the conductive member 21 (via wiring). In the XY cross-section, the other side portion in the X direction of the insulator layer 61b of the modified example of the third embodiment is formed in an arc shape along a circle centered on the center position of the conductive member 21 (via wiring). Furthermore, in the XY cross-section, the shape of the other portion in the X direction of the insulator layer 61b of the modified example of the third embodiment is convex lens-shaped.

[0134] Other configurations of the memory device 100 according to the modified example of the third embodiment are the same as those of the memory device 100 according to the third embodiment. The memory device 100 according to the modified example of the third embodiment can obtain the same effects as the third embodiment.

[0135] <4> Fourth Embodiment In the memory device 100A according to the fourth embodiment, a DRAM having a memory cell with a 2T0C (2 transistors 0 capacitors) structure is combined with a shield electrode SH similar to that of the first embodiment. The details of the memory device 100A according to the fourth embodiment will be described below, mainly focusing on the differences from the first to third embodiments.

[0136] <4-1> Composition First, the configuration of the memory device 100A according to the fourth embodiment will be explained using Figures 65 to 69.

[0137] <4-1-1> Structure of memory device 100A Figure 65 is a perspective view showing an example of the structure of a memory device 100A according to the fourth embodiment. As shown in Figure 65, the memory device 100A has a configuration in which the memory cell MC is replaced with a memory cell MCa, and the multiple ground lines GND are omitted, compared to the memory device 100 of the first embodiment. Specifically, the memory area MR of the fourth embodiment includes a plurality of memory cells MCa, a plurality of write word lines WWL, and a plurality of read word lines RWL. The memory area MR also includes a plurality of memory layers ML arranged in the Z direction.

[0138] Each memory layer ML of the fourth embodiment includes a pair of write word lines WWL and read word lines RWL aligned in the X direction, and a plurality of memory cells MCa aligned in the Y direction. In each memory layer ML of the fourth embodiment, each of the plurality of memory cells MCa is positioned between the pair of write word lines WWL and read word lines RWL and is electrically connected to each of the pair of write word lines WWL and read word lines RWL.

[0139] In the memory region MR of the fourth embodiment, a pair of write bit lines WBL and read bit lines RBL are aligned in the X direction. In the memory region MR, multiple write bit lines WBL are aligned in the Y direction. In the memory region MR, multiple read bit lines RBL are aligned in the Y direction. A pair of write bit lines WBL and read bit lines RBL are electrically connected to one memory cell MCa in each memory layer ML.

[0140] The structure of the memory device 100A according to the fourth embodiment is not limited to the structure shown in Figure 65. In the memory area MR, the number of write word lines WWL aligned in the Z direction and the number of read word lines RWL aligned in the Z direction may each be 2 or more. Similarly, in the memory area MR, the number of write bit lines WBL aligned in the Y direction and the number of read bit lines RBL aligned in the Y direction may each be 2 or more.

[0141] <4-1-2> Circuit configuration of memory cells Figure 66 is a circuit diagram showing an example of the circuit configuration of a memory cell MCa provided in the memory device 100A according to the fourth embodiment. Figure 66 shows one memory cell MCa, a pair of write word lines WWL and read word line RWL, and a pair of write bit lines WBL and read bit line RBL. As shown in Figure 66, the memory cell MCa is configured in a 2T0C structure. Specifically, the memory cell MCa includes, for example, a write transistor WT, a read transistor RT, and a storage node SN.

[0142] The configuration of the write transistor WT for the memory cell MCa is the same as that of the write transistor WT for the memory cell MC described in the first embodiment.

[0143] The readout transistor RT is, for example, a field-effect NMOS transistor. The gate electrode of the readout transistor RT is connected to the storage node SN. One electrode of the readout transistor RT is connected to the readout bit line RBL. The other electrode of the readout transistor RT is connected to the readout word line RWL. Each of the two electrodes of the readout transistor RT functions as either a source electrode or a drain electrode, depending on the voltage supplied to the readout transistor RT.

[0144] The storage node SN of the memory cell MCa has parasitic capacitance (<1fF), similar to the memory cell MC in the first embodiment. The memory cell MCa can store data according to the potential of the parasitic capacitance of the storage node SN, i.e., the amount of charge accumulated in the storage node SN. The leakage current from the storage node SN is limited by the leakage current of the write transistor WT. Therefore, in a read operation, the memory device 100A can read the data from the memory cell MCa non-destructively by reading the current of the read transistor TR corresponding to the potential of the storage node SN.

[0145] In the memory device 100A according to the fourth embodiment, a shield electrode SH is provided near the memory cell MCa. The shield electrode SH is electrically connected to the read bit line RBL. The shield electrode SH is positioned opposite the storage node SN to suppress interference between two adjacent memory cells MCa in the Z direction. In Figure 66, the parasitic capacitance between the storage node SN and the shield electrode SH is shown as the parasitic capacitance SC. The detailed arrangement of two adjacent memory cells MCa in the Z direction and the shield electrode SH will be described later.

[0146] <4-1-3> Structure of the memory cell array 110 Figures 67 to 69 are cross-sectional views showing an example of the structure of a memory cell array 110 provided in the memory device 100A according to the fourth embodiment. Figure 67 corresponds to the XZ cross-section of the memory cell array 110 provided in the memory area MR in the fourth embodiment, and shows an extracted region containing two adjacent memory cells MCa in the Z direction. Figure 68 corresponds to the cross-section along the LXVIII-LXVIII line in Figure 67. Figure 69 corresponds to the cross-section along the LXIX-LXIX line in Figure 67.

[0147] The memory device 100A according to the fourth embodiment includes a configuration in which the configuration relating to the read transistor RT2 is omitted from the memory device 100 according to the first embodiment. In the memory device 100A according to the fourth embodiment, the configuration corresponding to the read transistor RT1 of the first embodiment is used for the read transistor RT. Hereinafter, the semiconductor layer 31 and the insulating layer 41 provided in the memory device 100A according to the fourth embodiment will be referred to as semiconductor layer 31a and insulating layer 41a, respectively.

[0148] As shown in Figure 67, the conductive member 21 of the fourth embodiment has the same structure as the first embodiment and functions as a read bit line RBL. The semiconductor layer 31a has a cylindrical first portion that extends in the Z direction and is provided on the side surface of the conductive member 21, and a second portion that extends in the X direction in the memory layer ML. The insulating layer 40a has a cylindrical first portion that extends in the Z direction and is provided on the side surface of the first portion of the semiconductor layer 30a, and a second portion that is provided on the upper surface, lower surface, both sides in the Y direction, and one side in the X direction (conductive layer 70 side) of the second portion of the semiconductor layer 30a in the memory layer ML. The read word line RWL of the fourth embodiment further includes a conductive layer 74. The conductive layer 74 is provided, for example, on the upper surface, lower surface, both sides in the Y direction, and one side in the X direction of the conductive layer 73. In each memory layer ML, the second portion of the semiconductor layer 31a is connected to the read word line RWL (for example, the conductive layer 74) provided in the same layer. The semiconductor layer 31a is then electrically connected to the conductive layer 72 via the conductive layers 74 and 73.

[0149] As shown in Figure 68, in the XY cross-section, one side portion of the semiconductor layer 31a in the X direction is formed in an arc shape along a circle centered on the center position of the conductive member 20 (via wiring). In the XY cross-section, the other side portion of the semiconductor layer 31a in the X direction is formed in a straight line, for example, along the conductive layer 72. In the XY cross-section, the portion of the insulator layer 41a provided near the boundary between the read transistor RT and the read word line RWL is in contact with two adjacent insulating members 11 in the Y direction. Although not shown, in the XY cross-section, the other side portion of the conductive layer 50 in the X direction is formed in an arc shape along a circle centered on the center position of the conductive member 20 (via wiring). Although not shown, in the XY cross-section, one side portion of the conductive layer 51 in the X direction is formed in an arc shape along a circle centered on the center position of the conductive member 20 (via wiring).

[0150] As shown in Figure 69, in the XY cross-section, the side portions of the conductive layer 60 on both sides in the Y direction are formed linearly along two adjacent insulating members 11 in the Y direction. Also, in the XY cross-section, one side portion of the conductive layer 60 in the X direction and the other side portion of the conductive layer 60 in the X direction are each formed in an arc shape along a circle centered on the center position of the conductive member 21 (via wiring). In the XY cross-section, the insulating layer 61 is provided so as to surround the outer circumference of the conductive layer 60. Specifically, in the XY cross-section, the insulating layer 61 has a portion sandwiched between the insulating member 11 and the conductive layer 60 on one side in the Y direction, and a portion sandwiched between the insulating member 11 and the conductive layer 60 on the other side in the Y direction.

[0151] As described above, in two adjacent memory cells MCa in the Z direction, two adjacent conductive layers 51 (storage nodes SN) in the Z direction are adjacent via a conductive layer 60, similar to the first embodiment. The conductive layer 60 is provided so as to overlap with the conductive layer 51 (storage nodes SN) in a plan view. It is more preferable that the conductive layer 60 completely overlaps with the conductive layer 51 in a plan view. The conductive layer 60 is then electrically connected to the conductive member 21. As a result, the conductive layer 60 can function as a shield electrode SH.

[0152] The other configurations of the memory device 100A according to the fourth embodiment are the same as those of the memory device 100 according to the first embodiment.

[0153] <4-2> Manufacturing method Next, the process of forming the memory cell array 110 as a method for manufacturing the memory device 100A according to the fourth embodiment will be explained using Figures 70 to 79. Each of Figures 70 to 79 shows the same region as either the memory area MR shown in Figure 67, the memory layer ML shown in Figure 68, or the separation layer SL shown in Figure 69. Each of Figures 70 to 79 is a cross-sectional view showing an example of the structure in the manufacturing process of the memory device 100A according to the fourth embodiment.

[0154] In the manufacturing method of the memory device 100A according to the fourth embodiment, first, the same process as described with reference to Figures 7 to 10 in the first embodiment is performed. This forms the structure shown in Figure 70.

[0155] Next, as shown in Figure 71, in the memory area MA, a hole HWBL is formed in the portion corresponding to the write bit line WBL, and a hole HRBL is formed in the portion corresponding to the read bit line RBL. Although not shown in the figure, each of the holes HWBL and HRBL is formed by an anisotropic etching process such as RIE, so as to penetrate the insulator layer 10 and sacrificial member 12 that are stretched in the Z direction and stacked.

[0156] Next, as shown in Figure 72, (1) recesses are formed by selectively removing the sacrificial members 12 of each memory layer ML via the holes HWBL, and (2) conductive films 82 and sacrificial members 83 are sequentially formed to fill the formed recesses. In this process, for example, wet etching is used to form the recesses. The recesses formed in correspondence with the holes HWBL correspond to the locations where the write transistors WT are formed. Each conductive film 82 of the holes HWBL is in contact with the sacrificial members 12 and 80, respectively, in the memory layer ML. The conductive film 82 also covers the top surface, bottom surface, both sides in the X direction, and both sides in the Y direction of the insulator layer 10 with the holes HWBL. In this process, the sacrificial members 83 may be formed to fill the holes HGND. The conductive films 82 and sacrificial members 83 are formed by, for example, CVD. The conductive film 82 is, for example, titanium nitride (TiN). The sacrificial member 83 is, for example, amorphous silicon (aSi).

[0157] Next, as shown in Figure 73, a portion of the insulating layer 10 is selectively removed through the hole HRBL. In this step, for example, wet etching is used to remove the insulating layer 10. In this step, the recess formed in the separation layer SL that is in contact with the hole HRBL corresponds to the location where the shield electrode SH is formed.

[0158] Next, as shown in Figure 74, (1) an insulating film corresponding to the insulating layer 61 and a conductive film corresponding to the conductive layer 60 are formed, and (2) the insulating film and conductive film provided on the side portion of the hole HRBL are removed. This forms the structure corresponding to the shield electrode SH. In addition, this process exposes the side surfaces of the sacrificial members 12 of each memory layer ML within the hole HRBL. In this process, for example, CVD is used to form the insulating film and conductive film.

[0159] Next, as shown in Figure 75, the sacrificial members 12 of each memory layer ML are selectively removed through the hole HRBL, and conductive layers 50 and 51 are formed in each memory layer ML, an insulating layer 40 is formed, and sacrificial members 85 and 92 are formed. The structure shown in Figure 75 can be formed by appropriately performing etching and film deposition processes using the hole HWBL and HRBL and the slit SLT on the other side in the X direction. The conductive layer 50 of each memory layer ML is formed by processing a conductive film 82. The conductive layer 51 is, for example, a conductive oxide such as indium tin oxide (ITO). The sacrificial member 85 is provided so as to cover the insulating layer 40 within the hole HWBL. The sacrificial member 92 is provided in each memory layer ML so as to fill the space sandwiched between the disc-shaped conductive layers 51 and the space where the read word line RWL is formed. Each of the sacrificial members 85 and 92 is, for example, amorphous silicon (aSi).

[0160] Next, as shown in Figure 76, (1) a portion of the sacrificial member 92 provided in the memory layer ML is selectively removed through the hole HRBL, and (2) an insulating layer 41a is formed through the hole HRBL. The conductive layer 51 processed in this step corresponds to the shape of the conductive layer 51 (storage node SN) shown in Figure 67. For example, wet etching is used to remove the sacrificial member 92. The insulating layer 41 is formed by, for example, CVD.

[0161] Next, as shown in Figure 77, the sacrificial member 87 is embedded in the space sandwiched in the Z direction by the insulating layer 41 in each memory layer ML. The sacrificial member 87 is formed by, for example, CVD. In this process, the sacrificial member 87 formed on the side surface of the hole HRBL is removed by etch-back treatment. The sacrificial member 87 is, for example, amorphous silicon (aSi).

[0162] Next, as shown in Figure 78, the insulating layer 41a formed on the side portion of the hole HRBL in each separation layer SL is selectively removed through the hole HRBL. As a result, a portion of the conductive layer 60 is exposed in the portion of the hole HRBL corresponding to each separation layer SL. For example, wet etching is used to remove the insulating layer 41a.

[0163] Next, as shown in Figure 79, (1) sacrificial members 85 and 87 are selectively removed, (2) semiconductor layers 30 and 31a are formed, and (3) conductive members 20 and 21 are embedded in the holes HWBL and HRBL, respectively. Subsequently, sacrificial member 80 and a portion of the insulating layer 41a on the read bit line RBL side are removed, forming a configuration corresponding to the write word line WWL and the read word line RWL. As a result, the structure of the memory cell array 110 shown in Figures 67 to 69 is completed.

[0164] <4-3> Effects of the fourth embodiment The memory device 100A according to the fourth embodiment has a configuration in which a memory cell MC with a 2T0C (2 transistors 0 capacitors) configuration is combined with a shield electrode SH described in the first embodiment. The shield electrode SH of the fourth embodiment can suppress interference between two memory cells MCa arranged above and below the shield electrode SH.

[0165] As a result, the memory device 100A according to the fourth embodiment, like the first embodiment, can reduce the pitch of memory cells MCa aligned in the Z direction, and can provide a high-density and low-cost three-dimensional stacked memory. Furthermore, the shield electrode SH of the fourth embodiment, like the first embodiment, can add capacitance (<1fF) between the storage node SN and the conductive member 21, thereby improving noise immunity.

[0166] <5> others In the memory device 100 according to the above embodiment, multiple memory cells MC, each consisting of at least two transistors arranged horizontally (X direction), are stacked vertically (Z direction) on a semiconductor substrate SUA. Each of the write transistor WT and read transistor RT is formed in a disk-shaped GAA structure. A shield electrode SH is placed between two adjacent storage nodes SN in the Z direction. The shield electrode SH is connected to an electrode in a vertical hole (hole HGND or HRBL).

[0167] In the above embodiment, the vertical wiring located in the center of the memory cell MC is referred to as the ground wire GND, Hall HGND, etc., using the name "GND". However, these wires are not necessarily grounded. In the above embodiment, the ground wire GND may be referred to as the "power line PL (Power Line)", "center line", etc. Similarly, Hall HGND may be referred to as "Hall HPL", "Hall HCL", etc.

[0168] In this specification, the direction intersecting a predetermined plane may be referred to as the "first direction," the direction intersecting the first direction along this predetermined plane may be referred to as the "second direction," and the direction intersecting the second direction along this predetermined plane may be referred to as the "third direction." Each of the first, second, and third directions may or may not correspond to the X, Y, and Z directions. The gate electrode may be referred to as the "gate." One-end electrode may be referred to as the "one-end." The other-end electrode may be referred to as the "other-end." The manufacturing method described in the above embodiments is merely an example. Other manufacturing methods may be used as long as they are capable of forming the structures described in each embodiment.

[0169] In this specification, “connection” means that the elements are electrically connected, and does not exclude, for example, the intervening element. “Electrically connected” may be via an insulator, as long as it is possible to operate as if the elements were electrically connected. The write word line WWL, read word line RWL, write bit line WBL, read bit line RBL, etc., may be referred to as “wiring.” The conductive layer may be referred to as “conductive film.” The insulating layer may be referred to as “insulating film.”

[0170] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0171] 1...Memory system, 100, 100A...Memory device, 110...Memory cell array, 120...Row control circuit, 130...Column control circuit, 140...Read / write circuit, 150...Input / output circuit, 160...Control circuit, 200...Memory controller, WT...Write transistor, RT, RT1, RT2...Read transistor, SN...Storage node, SH...Shield electrode, 10 40, 40a, 41, 41a, 61, 61a, 61b…insulating layer, 11…insulating member, 12, 80, 81, 81a, 81b, 83, 83a, 84~92…sacrificial member, 20, 21, 22…conductive member, 30, 30a, 31, 31a…semiconductor layer, 50, 50a, 50b, 51, 51a, 51b, 52, 52a, 52b, 60, 60a, 60b, 70~74…conductive layer, 82, 82a…conductive film

Claims

1. circuit board and Each of the first conductive member and the second conductive member is provided extending in a first direction intersecting the surface of the substrate and arranged in a second direction parallel to the surface of the substrate, A plurality of memory cells arranged in the first direction, each including a first transistor and a second transistor arranged in the second direction, wherein the first transistor has a gate electrode and a channel region electrically connected to the first conductive member, and the second transistor has a channel region electrically connected to the second conductive member and a gate electrode electrically connected to the channel region of the first transistor, Between each of the two memory cells adjacent to each other in the first direction among the plurality of memory cells, there is a shield electrode that is electrically connected to the second conductive member and is provided so as to overlap with the gate electrode of the second transistor in the first direction, Memory device.

2. The channel region of the first transistor covers the periphery of the first conductive member when viewed from the first direction. The channel region of the second transistor covers the periphery of the second conductive member when viewed from the first direction. The shield electrode covers the periphery of the second conductive member when viewed from the first direction. The memory device according to claim 1.

3. The first transistor includes a first semiconductor layer that functions as the channel region, a first insulating layer that covers the upper surface, lower surface, and one side in the second direction of the first semiconductor layer, and a first conductive layer that covers the upper surface, lower surface, and one side in the second direction of the first insulating layer and functions as the gate electrode. The second transistor includes a second semiconductor layer that functions as the channel region, a second insulating layer that covers the upper surface, lower surface, and one side in the second direction of the second semiconductor layer, and a second conductive layer that covers the upper surface, lower surface, and one side in the second direction of the second insulating layer, is connected to the first semiconductor layer, and functions as the gate electrode. The memory device according to claim 2.

4. The second conductive layer is used as a storage node for the memory cell. The memory device according to claim 3.

5. The shield electrode, when viewed from the first direction, is larger than the second conductive layer and overlaps with the entirety of the second conductive layer. The memory device according to claim 3.

6. The shield electrode and the second conductive layer are separated and insulated from each other, and the insulating film further comprises an insulating film having a composition different from that of the first insulating layer and the second insulating layer. The memory device according to claim 3.

7. Each of the first insulating layer and the second insulating layer contains silicon oxide, The insulating film comprises one of silicon nitride, silicon oxide nitride, hafnium oxide, or aluminum oxide. The memory device according to claim 6.

8. Each of the first semiconductor layer and the second semiconductor layer includes an oxide semiconductor. The memory device according to claim 3.

9. The oxide semiconductor comprises at least one element from gallium and aluminum, as well as indium, zinc, and oxygen. The memory device according to claim 8.

10. The shield electrode contains a conductive oxide, The memory device according to claim 1.

11. The conductive oxide includes indium tin oxide. The memory device according to claim 10.

12. A third conductive member extending in the first direction and provided on the other side of the second direction relative to the second conductive member, A first word line is provided for each of the plurality of memory cells and is electrically connected to the gate electrode of the first transistor, A second word line is provided for each of the aforementioned plurality of memory cells, Furthermore, Each of the plurality of memory cells further includes a third transistor provided on the other side of the second direction relative to the second transistor, the third transistor having a channel region electrically connected to the third conductive member and electrically connected to the channel region of the second transistor, and a gate electrode electrically connected to the second word line. The memory device according to claim 1.

13. A third conductive member extending in the first direction and provided on the other side of the second direction relative to the second conductive member, A first word line is provided for each of the plurality of memory cells and is electrically connected to the gate electrode of the first transistor, A second word line is provided for each of the aforementioned plurality of memory cells, Furthermore, Each of the plurality of memory cells further includes a third transistor provided on the other side of the second direction relative to the second transistor, the third transistor having a channel region that covers and is electrically connected to the third conductive member when viewed from the first direction and is electrically connected to the channel region of the second transistor, and a gate electrode electrically connected to the second word line. The memory device according to claim 2.

14. The first transistor includes a first semiconductor layer that functions as a channel region, a first insulating layer that covers the upper surface, lower surface, and one side in the second direction of the first semiconductor layer, and a first conductive layer that covers the upper surface, lower surface, and one side in the second direction of the first insulating layer and functions as a gate electrode. The second transistor includes a second semiconductor layer that functions as a channel region, a second insulating layer that covers the upper surface, lower surface, and one side in the second direction of the second semiconductor layer, and a second conductive layer that covers the upper surface, lower surface, and one side in the second direction of the second insulating layer, is connected to the first semiconductor layer, and functions as a gate electrode. The third transistor includes a third semiconductor layer that functions as a channel region, a third insulating layer that covers the upper surface, lower surface, and the other side in the second direction of the third semiconductor layer, and a third conductive layer that covers the upper surface, lower surface, and the other side in the second direction of the third insulating layer, is electrically connected to the second word line, and functions as a gate electrode. The memory device according to claim 13.

15. The other end of the first conductive layer in the second direction and the one end of the second conductive layer in the second direction face each other while maintaining a certain distance. The memory device according to claim 14.

16. Each of the shield electrode and the second conductive layer, when viewed from the first direction, has a portion on one side in the second direction that is provided in an arc shape along a circle centered on the central position of the second conductive member, and a portion on the other side in the second direction that is provided in an arc shape along a circle centered on the central position of the second conductive member. The memory device according to claim 14.

17. Each of the shield electrode and the second conductive layer, when viewed from the first direction, has a portion on one side in the second direction that is provided in an arc shape along a circle centered on the central position of the first conductive member, and a portion on the other side in the second direction that is provided in an arc shape along a circle centered on the central position of the third conductive member. The memory device according to claim 14.

18. The shield electrode, when viewed from the first direction, has a portion provided in an arc shape along a circle centered on the center position of the first conductive member on one side of the second direction, or has a portion provided in an arc shape along a circle centered on the center position of the third conductive member on the other side of the second direction. The memory device according to claim 14.

19. When the shield electrode is viewed from the first direction, it has a portion that is provided in an arc shape along a circle centered on the central position of the first conductive member on one side of the second direction, The shield electrode, when viewed from the first direction, further has a portion provided in an arc shape along a circle centered on the central position of the second conductive member on the other side of the second direction, The second conductive layer, when viewed from the first direction, has a portion provided in an arc shape along a circle centered on the central position of the first conductive member on one side in the second direction, and a portion provided in an arc shape along a circle centered on the central position of the second conductive member on the other side in the second direction. When the shield electrode is viewed from the first direction, it has a portion that is provided in an arc shape along a circle centered on the central position of the third conductive member on the other side of the second direction, The shield electrode, when viewed from the first direction, further has a portion provided in an arc shape along a circle centered on the central position of the second conductive member on one side of the second direction, The second conductive layer, when viewed from the first direction, has a portion provided in an arc shape along a circle centered on the center position of the third conductive member on the other side of the second direction, and a portion provided in an arc shape along a circle centered on the center position of the second conductive member on one side of the second direction. The memory device according to claim 18.

20. The distance between the upper and lower ends of the second conductive layer in the first direction is narrower than the distance between the upper and lower ends of the first conductive layer in the first direction and the distance between the upper and lower ends of the third conductive layer in the first direction. The memory device according to any one of claims 15, 17 to 19.

21. Each of the first conductive layer and the third conductive layer does not have a portion that overlaps with the shield electrode in the first direction. The memory device according to claim 14.

22. A first word line is provided for each of the plurality of memory cells and is electrically connected to the gate electrode of the first transistor, The system further comprises a second word line provided for each of the plurality of memory cells and electrically connected to the channel region of the second transistor, The memory device according to claim 1.

23. The channel region of the first transistor covers the periphery of the first conductive member when viewed from the first direction. The channel region of the second transistor covers the periphery of the second conductive member when viewed from the first direction. The shield electrode covers the periphery of the second conductive member when viewed from the first direction. The memory device according to claim 22.

24. The first transistor includes a first semiconductor layer that functions as the channel region, a first insulating layer that covers the upper surface, lower surface, and one side in the second direction of the first semiconductor layer, and a first conductive layer that covers the upper surface, lower surface, and one side in the second direction of the first insulating layer and functions as the gate electrode. The second transistor includes a second semiconductor layer that functions as the channel region, a second insulating layer that covers the upper surface, lower surface, and one side in the second direction of the second semiconductor layer, and a second conductive layer that covers the upper surface, lower surface, and one side in the second direction of the second insulating layer, is connected to the first semiconductor layer, and functions as the gate electrode. The memory device according to claim 23.

25. The shield electrode, when viewed from the first direction, has portions provided in an arc shape along a circle centered on the central position of the second conductive member on both the one side and the other side of the second direction, The first conductive layer, when viewed from the first direction, has a portion provided in an arc shape along a circle centered on the central position of the first conductive member on the other side in the second direction. The memory device according to claim 24.

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