Semiconductor device and method for manufacturing a semiconductor device.

Abstract

The present invention provides a power MOS transistor and a method for manufacturing the same that reduce gate electrode-drain electrode capacitance by controlling the thickness of the oxide between the gate electrode and the drain electrode. [Solution] The semiconductor device includes a silicon carbide epitaxy layer 101 having a p-type well region PW, a junction field-effect region JF2 adjacent to the p-type well region, a heavily doped n-type region 107 on the surface of the p-type well region, and a heavily doped p-type region 105 located below the heavily doped n-type region and within the p-type well region. The semiconductor device also includes an island oxide 109A on the junction field-effect region, a gate pole oxide layer 102B covering the p-type well region, the junction field-effect region, the heavily doped n-type region, the heavily doped p-type region and the island oxide, and a polysilicon layer 103 located on the gate pole oxide layer and not in contact with the island oxide.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to a power MOS (Metal Oxide Semiconductor) transistor.

Background Art

[0002] In a conventional power MOS transistor, the gate-drain capacitance (Cgd) affects the switching energy loss of the device, but it has not yet been possible to effectively reduce the gate-drain capacitance by controlling the thickness of the oxide between the gate and drain electrodes respectively. In order to overcome these problems, a new semiconductor device and a method for manufacturing the semiconductor device are required.

Summary of the Invention

[0003] In view of this, the semiconductor device provided by the present invention includes a p-type well region, a junction field effect region adjacent to the p-type well region, a heavily doped n-type region on the surface of the p-type well region, and a heavily doped p-type region below the heavily doped n-type region and within the p-type well region, and includes a silicon carbide epitaxial layer having these regions. The semiconductor device further includes an island oxide on the junction field effect region, a gate oxide layer covering the p-type well region, the junction field effect region, the heavily doped n-type region, the heavily doped p-type region, and the island oxide, and a polysilicon layer on the gate oxide layer and not in contact with the island oxide.

[0004] The present invention provides a silicon carbide epitaxy layer in which a p-type well region, a heavily doped n-type region on the surface of the p-type well region, a heavily doped p-type region located below the heavily doped n-type region and within the p-type well region, and a junction field-effect region adjacent to the p-type well region are predetermined; depositing an oxide layer; subjecting the oxide layer to a patterning process to form island-shaped oxides on the junction field-effect region; depositing a gate pole oxide layer so as to cover the p-type well region, the junction field-effect region, the heavily doped n-type region, the heavily doped p-type region, and the island-shaped oxides; and depositing a polysilicon layer on the gate pole oxide layer.

[0005] In summary, when the goal is to reduce the gate-source on-resistance (Rdson) by decreasing the width of the junction field-effect region and thereby reducing the overall cell spacing, the formation of island oxides and the deposition of a gate electrode oxide layer can maintain the spacing between the polysilicon layer and the junction field-effect region, thereby maintaining a low gate-drain electrode capacitance. Furthermore, the formation of island oxides and the deposition of a gate electrode oxide layer can increase the spacing between the polysilicon layer and the junction field-effect region, reducing the gate-drain electrode capacitance and further improving switching energy loss. [Brief explanation of the drawing]

[0006] [Figure 1] Based on several embodiments of the present invention, these are cross-sectional views of a manufactured semiconductor device at different manufacturing stages. [Figure 2] Based on several embodiments of the present invention, these are cross-sectional views of a manufactured semiconductor device at different manufacturing stages. [Figure 3] Based on several embodiments of the present invention, these are cross-sectional views of a manufactured semiconductor device at different manufacturing stages. [Figure 4] Based on several embodiments of the present invention, these are cross-sectional views of a manufactured semiconductor device at different manufacturing stages. [Figure 5]Based on several embodiments of the present invention, these are cross-sectional views of a manufactured semiconductor device at different manufacturing stages.

[0007] [Figure 6] This is a flowchart of a method for manufacturing a semiconductor device according to the present invention, based on several embodiments of the present invention.

[0008] [Figure 7] Based on several embodiments of the present invention, these are cross-sectional views of a manufactured semiconductor device at different manufacturing stages. [Figure 8] Based on several embodiments of the present invention, these are cross-sectional views of a manufactured semiconductor device at different manufacturing stages. [Figure 9] Based on several embodiments of the present invention, these are cross-sectional views of a manufactured semiconductor device at different manufacturing stages. [Figure 10] Based on several embodiments of the present invention, these are cross-sectional views of a manufactured semiconductor device at different manufacturing stages. [Figure 11] Based on several embodiments of the present invention, these are cross-sectional views of a manufactured semiconductor device at different manufacturing stages.

[0009] [Figure 12] This is a flowchart of a method for manufacturing a semiconductor device according to the present invention, based on several embodiments of the present invention. [Modes for carrying out the invention]

[0010] Figures 1 to 5 are cross-sectional views of a semiconductor device manufactured according to the present invention at different manufacturing stages, based on method 600 shown in Figure 6. In step 601, a silicon carbide epitaxy layer 101 is provided. As shown in Figure 1, a p-type well region PW, a heavily doped n-type region 107 on the surface of the p-type well region PW, a heavily doped p-type region 105 located below the heavily doped n-type region 107 and within the p-type well region PW, and a junction field-effect region JF1 located between two adjacent p-type well regions PW and adjacent to the p-type well region PW are predefined on the silicon carbide epitaxy layer 101. The width W1 of the junction field-effect region JF1 can be 1.2 μm. As shown in Figure 2, in step 602, an oxide layer 108 is deposited. As shown in Figure 3, in step 603, the oxide layer 108 is subjected to a patterning process to form island oxides 108A. The patterning process may include a lithography process and an etching process. In some embodiments, the etching step may include a wet etching step and a photoresist removal step. The island oxide layer 108A is located on the junction field-effect region JF1, and the thickness T1 of the island oxide layer 108A is approximately 900 Å, and the width of the island oxide layer 108A is smaller than the width W1 of the junction field-effect region JF1.

[0011] In step 604, a thermal oxidation process is performed to form the gate pole oxide layer 102A. As shown in Figure 4, the gate pole oxide layer 102A is located on the p-type well region PW, the heavily doped n-type region 107, the heavily doped p-type region 105, and the junction field-effect region JF1, and is in contact with the p-type well region PW, the heavily doped n-type region 107, the heavily doped p-type region 105, and the junction field-effect region JF1. The gate pole oxide layer 102A is in contact with only a portion of the side of the island oxide layer 108A, but does not cover the upper surface of the island oxide layer 108A. The thickness T2 of the gate pole oxide layer 102A is approximately 400 Å, and the thickness of the oxide in the area DA1 above the drain electrode is approximately 900 Å. In step 605, a polysilicon layer 103 is deposited on the gate pole oxide layer 102A and the island oxide layer 108A. As shown in Figure 5, the polysilicon layer 103 is located on the gate electrode oxide layer 102A and the island oxide layer 108A, and is in contact with the gate electrode oxide layer 102A and the island oxide layer 108A. Once the polysilicon layer 103 is patterned, it can become the gate electrode of the transistor. Furthermore, a first metal layer (not shown) is formed at the source and gate electrodes, so once the metal layer is patterned, it can be formed at the source electrode contact and the gate electrode contact. The source electrode contact is in contact with the heavily doped n-type region 107 via a metal silicide and a heavily doped p-type region 105, and the gate electrode contact is in contact with the polysilicon layer 103. For the drain electrode, a silicon carbide substrate (not shown) is formed below the silicon carbide epitaxy layer 101, and a second metal layer (not shown) can be formed below the silicon carbide substrate as the drain electrode contact.

[0012] In a silicon carbide planar metal oxide field-effect transistor (SiC planar MOSFET), the gate-drain capacitance (Cgd) affects the switching energy consumption of the device. As shown in Figure 5, the gate-drain capacitance of a metal oxide field-effect transistor is determined by the thickness of the gate oxide (e.g., island oxide 108A), and the thicker the gate oxide, the lower the gate-drain capacitance. A low gate-drain capacitance can improve the switching energy consumption of the device, but since the thickness T1 of the island oxide 108A in Figure 5 is approximately 900 Å, the resulting gate-drain capacitance is low. To reduce the drain-source on-resistance (Rdson), the cell pitch can be reduced, but typically, reducing the cell pitch involves reducing the width W1 of the junction field-effect region JF1. While the metal oxide field-effect transistor with the configuration shown in Figure 5 can achieve a lower gate-drain capacitance, reducing the junction field-effect region JF1 risks delaminating the photoresist on the oxide layer 108 in order to form island-shaped oxides 108A with a width narrower than the width of the junction field-effect region JF1. Furthermore, even in the thermal oxidation process, it is not easy to increase the thickness of the oxide layer at the extreme drain oxide (e.g., island-shaped oxides 108A). Therefore, with the configuration shown in Figure 5, it is difficult to maintain a low gate-drain capacitance or reduce the gate-drain capacitance when reducing the drain-source on-resistance (Rdson).

[0013] Figures 7 to 11 are cross-sectional views of a manufactured semiconductor device in the present invention at different manufacturing stages, based on method 1200 shown in Figure 12. Figure 7 is similar to Figure 1, and in step 1201, a silicon carbide epitaxy layer 101 is provided. On the silicon carbide epitaxy layer 101, a p-type well region PW, a heavily doped n-type region 107 on the surface of the p-type well region PW, a heavily doped p-type region 105 located below the heavily doped n-type region 107 and within the p-type well region PW, and a junction field-effect region JF2 located between two adjacent p-type well regions PW and adjacent to the p-type well region PW are predefined. The difference between the junction field-effect region JF2 and the junction field-effect region JF1 is that the junction field-effect region JF2 is narrower than the junction field-effect region JF1, and the width W2 of the junction field-effect region JF2 can be reduced to 0.8 μm. As shown in Figure 8, in step 1202, an oxide layer 109 is deposited. Note that the thickness of the oxide layer 109 in Figure 8 is thinner than the thickness of the oxide layer 108 in Figure 2. As shown in Figure 9, in step 1203, a patterning process is performed on the oxide layer 109 to form island oxides 109A. The patterning process may include a lithography process and an etching process. In some embodiments, the etching process may include a wet etching process and a photoresist removal process. The island oxide layer 109A is located on the junction field-effect region JF2, and the thickness T3 of the island oxide layer 109A is approximately 500 Å, and the width of the island oxide layer 109A is smaller than the width W2 of the junction field-effect region JF2.

[0014] In step 1204, a gate pole oxide layer 102B is deposited so as to cover the p-type well region PW, the junction field-effect region JF2, the heavily doped n-type region 107, the heavily doped p-type region 105, and the island oxide 109A. As shown in Figure 10, the gate pole oxide layer 102B is located on top of the p-type well region PW, the heavily doped n-type region 107, the heavily doped p-type region 105, the junction field-effect region JF2, and the island oxide 109A, and is in contact with the p-type well region PW, the heavily doped n-type region 107, the heavily doped p-type region 105, the junction field-effect region JF2, and the island oxide 109A. The thickness T4 of the gate pole oxide layer 102B is approximately 400 Å. Therefore, the thickness of the oxide in area DA2 above the drain electrode is 500 Å (thickness T3 of island oxide 109A) + 400 Å (thickness T4 of gate electrode oxide layer 102B) = 900 Å. In step 1205, a polysilicon layer 103 is deposited on the gate electrode oxide layer 102B. As shown in Figure 11, the polysilicon layer 103 is on the gate electrode oxide layer 102B and in contact with the gate electrode oxide layer 102B, but not in contact with the island oxide layer 109A. Once the polysilicon layer 103 is patterned, it can become the gate electrode of the transistor. Similarly, a first metal layer (not shown) is further formed at the source and gate electrodes, so once the first metal layer is patterned, it can be formed at the source electrode contact and gate electrode contact. The source electrode contact is in contact with the heavily doped n-type region 107 via the metal silicide and the heavily doped p-type region 105, and the gate electrode contact is in contact with the polysilicon layer 103. Regarding the drain electrode, a silicon carbide substrate (not shown) can be formed below the silicon carbide epitaxy layer 101, and a second metal layer (not shown) can be formed below the silicon carbide substrate as a drain electrode contact point.

[0015] In the configuration shown in Figure 11, all gate pole oxide layers are deposited oxide layers and not produced by a thermal oxidation process. Therefore, when reducing the width W2 of the junction field-effect region JF2 to reduce the oxide at the drain extreme (e.g., area DA2) (e.g., island oxide 109A), the gate pole oxide layer 102B can replenish the thickness of the oxide at the drain extreme. Regarding the ratio of the thickness of the oxide at the drain extreme to the width of the junction field-effect region, in Figure 5, the ratio of the maximum distance between the polysilicon layer 103 and the junction field-effect region JF1 (approximately 900 Å, i.e., the thickness T1 of the island oxide 108A) to the width W1 of the junction field-effect region JF1 (approximately 1.2 μm) is 0.075. In Figure 11, the ratio of the maximum distance between the polysilicon layer 103 and the junction field-effect region JF2 (approximately 900 Å, i.e., the sum of the thickness T3 of the island oxide 109A and the thickness T4 of the gate pole oxide layer 102B) to the width W2 of the junction field-effect region JF2 (approximately 0.8 μm) is 0.1125, which is greater than 0.075. In some embodiments, the width W2 of the junction field-effect region JF2 can be further reduced while maintaining the maximum distance between the polysilicon layer 103 and the junction field-effect region JF2 (approximately 900 Å). Also, when increasing the maximum distance between the polysilicon layer 103 and the junction field-effect region JF2 (approximately 900 Å), the width W2 of the junction field-effect region JF2 (approximately 0.8 μm) can be maintained. Therefore, the ratio of the maximum distance to the width W2 of the junction field-effect region JF2 can be greater than 0.1125, for example, greater than 0.2 or 0.3. In summary, according to the configuration shown in Figure 11, when we want to reduce the gate-source on-resistance (Rdson) by reducing the width of the junction field-effect region and thus reducing the overall spacing of the cells, we can further improve switching energy loss by keeping the gate-drain capacitance low or by reducing the gate-drain capacitance (increasing the maximum spacing between the polysilicon layer 103 and the junction field-effect region JF2).

[0016] As described above, to better enable those skilled in the art to understand this specification, the features of some embodiments have been outlined. As those skilled in the art can understand, based on the content disclosed in the present invention, other processes and structures can be designed or modified to achieve the same purpose and / or the same advantages as the above embodiments. Also, as those skilled in the art can understand, for equivalent structures that do not deviate from the spirit and scope of the present invention, various changes, substitutions, and modifications can be made without departing from the spirit and scope of the present invention.

Description of Reference Numerals

[0017] 101: Silicon carbide epitaxial layer 102A: Gate oxide layer 102B: Gate oxide layer 103: Polysilicon layer 105: Heavily doped p-type region 107: Heavily doped n-type region 108: Oxide layer 108A: Island-shaped oxide layer 109: Oxide layer 109A: Island-shaped oxide layer PW: p-type well region JF1: Junction field effect region JF2: Junction field effect region W1: Width W2: Width T1: Thickness T2: Thickness T3: Thickness T4: Thickness DA1: Area DA2: Area 600: Method 601: Step 602: Step 603: Step 604: Step 605: Step 606: Step 1200: Method 1201: Step 1202: Step 1203: Steppe 1204: Steppe 1205: Steppe 1206: Steppe

Claims

1. A semiconductor device, p-type well region, The junction field effect region adjacent to the p-type well region, A heavily doped n-type region on the surface of the aforementioned p-type well region, A silicon carbide epitaxy layer comprising a heavily doped p-type region below the heavily doped n-type region and within the p-type well region, Island-shaped oxide on the junction field effect region, The gate electrode oxide layer covering the p-type well region, the junction field effect region, the heavily doped n-type region, the heavily doped p-type region, and the island oxide, A semiconductor device having a polysilicon layer located on the gate polar oxide layer and not in contact with the island oxide.

2. The semiconductor device according to claim 1, wherein the width of the island oxide is smaller than the width of the junction field effect region.

3. The semiconductor device according to claim 1, wherein the maximum distance between the polysilicon layer and the junction field-effect region, the width of the junction field-effect region, and the ratio between the two exceed 0.

075.

4. Furthermore, The semiconductor device according to claim 1, having a first metal layer that contacts the heavily doped p-type region and the heavily doped n-type region via a metal silicide.

5. Furthermore, A silicon carbide substrate located below the silicon carbide epitaxy layer, The semiconductor device according to claim 1, further comprising a second metal layer located below the silicon carbide substrate.

6. A method for manufacturing a semiconductor device, To provide a silicon carbide epitaxy layer in which a p-type well region, a heavily doped n-type region on the surface of the p-type well region, a heavily doped p-type region located below the heavily doped n-type region and within the p-type well region, and a junction field effect region adjacent to the p-type well region are predetermined, Depositing an oxide layer, The oxide layer is subjected to a patterning process to form island-shaped oxides on the junction field effect region, Depositing a gate electrode oxide layer so as to cover the p-type well region, the junction field effect region, the heavily doped n-type region, the heavily doped p-type region, and the island oxide, A method comprising depositing a polysilicon layer on the gate polar oxide layer.

7. The method according to claim 6, wherein the width of the island-shaped oxide is smaller than the width of the junction field effect region.

8. The method according to claim 6, wherein the maximum distance between the polysilicon layer and the junction field-effect region, the width of the junction field-effect region, and the ratio between the two exceed 0.

075.

9. Furthermore, To form the first metal layer, The method according to claim 6, further comprising patterning the first metal layer to form a source electrode contact and a gate electrode contact.

10. Furthermore, A silicon carbide substrate is formed below the silicon carbide epitaxy layer, The method according to claim 6, further comprising forming a second metal layer below the silicon carbide substrate.

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