Hybrid gain cell with back-end obline field-effect transistor

Abstract

One aspect of this disclosure relates to a device. [Solution] A device comprising a first transistor and a second transistor coupled in series, a third transistor and a fourth transistor coupled in series, and a fifth transistor whose first terminal is coupled to the first terminal of the first transistor and the first terminal of the second transistor, respectively, and whose control terminal is coupled to the second terminal of the second transistor in a memory node, wherein the control terminal of the fourth transistor is coupled to the memory node, and at least one of the first to fifth transistors is located in a layer above the other one of the first to fifth transistors.

Description

Background Art

[0001] Gain cell embedded memory (e.g., GC-eDRAM) has emerged as a promising candidate to replace conventional SRAM (e.g., 6-transistor bit cell SRAM) in certain applications. Compared to SRAM, gain cell embedded memory is smaller in size and allows non-destructive readout due to its two-port operation. Also, compared to SRAM, gain cell embedded memory may operate at low power consumption and low leakage current levels (e.g., due to fewer leakage paths). Although SRAM still has certain advantages such as faster access speed and robust static data retention function, the power consumption budget of SRAM cells is high and their size is relatively large, so they cannot keep up with device miniaturization.

[0002] However, there is still room for improvement in gain cell embedded memory, particularly in data retention characteristics, threshold voltage variation, memory access time, and reduction of the device footprint. Therefore, although existing gain cell designs and structures are generally sufficient for their intended uses, they are not completely satisfactory in all aspects.

Prior Art Documents

Non-Patent Documents

[0003] Giterman et al., "4T Gain Cell with Internal Feedback for Ultra-Low Retention Power at Scaled CMOS Nodes", Research Gate, June 2014. https: / / www.researchgate.net / publication / 269273975_4T_Gain-Cell_with_internal-feedback_for_ultra-low_retention_power_at_scaled_CMOS_nodes

Brief Description of the Drawings

[0004] This disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, various features are not depicted to scale and are used for illustrative purposes only. For practical and clear consideration, the dimensions of various features may be arbitrarily enlarged or reduced. Furthermore, it should be emphasized that the accompanying drawings are merely for illustrating typical embodiments of the invention and should not be considered limiting to the scope of the invention, as the invention is equally suitably applicable to other embodiments. Also, the accompanying drawings may implicitly illustrate features not explicitly described in the detailed description. [Figure 1A] Various configurations of gain cell circuits according to each embodiment of this disclosure are shown. [Figure 1B] Various configurations of gain cell circuits according to each embodiment of this disclosure are shown. [Figure 1C] Various configurations of gain cell circuits according to each embodiment of this disclosure are shown. [Figure 1D] Various configurations of gain cell circuits according to each embodiment of this disclosure are shown. [Figure 1E] Various configurations of gain cell circuits according to each embodiment of this disclosure are shown. [Figure 2] This invention illustrates a gain cell circuit having five transistors (5T), including four front-end-of-line (FEOL) transistors and one back-end-of-line (BEOL) transistor, according to one embodiment of the present disclosure. [Figure 3A] This is a simplified cross-sectional view showing the gain cell circuit of Figure 2 according to one embodiment of the present disclosure. [Figure 3B] This is a simplified cross-sectional view showing the gain cell circuit of Figure 2 according to one embodiment of the present disclosure. [Figure 4A] This is a top layout diagram showing a gain cell circuit at different layer levels (for example, different layer levels of the gain cell circuit of Figure 2 having the cross-sectional views of Figures 3A and 3B) according to one embodiment of the present disclosure. [Figure 4B]This is a top layout diagram showing a gain cell circuit at different layer levels (for example, different layer levels of the gain cell circuit of Figure 2 having the cross-sectional views of Figures 3A and 3B) according to one embodiment of the present disclosure. [Figure 4C] This is a top layout diagram showing a gain cell circuit at different layer levels (for example, different layer levels of the gain cell circuit of Figure 2 having the cross-sectional views of Figures 3A and 3B) according to one embodiment of the present disclosure. [Figure 4D] This is a top layout diagram showing a gain cell circuit at different layer levels (for example, different layer levels of the gain cell circuit of Figure 2 having the cross-sectional views of Figures 3A and 3B) according to one embodiment of the present disclosure. [Figure 5] Figures 4A to 4D show a perspective view of a gain cell circuit according to one embodiment of the present disclosure. [Figure 6] Figures 4A to 4D show a perspective view of a gain cell circuit according to another embodiment of the present disclosure. [Figure 7] This invention illustrates a gain cell circuit having five transistors (5T), including two front-end-of-line (FEOL) transistors and three back-end-of-line (BEOL) transistors, according to one embodiment of the present disclosure. [Figure 8] This is a simplified cross-sectional view showing the gain cell circuit of Figure 7 according to one embodiment of the present disclosure. [Figure 9] This is a simplified cross-sectional view showing the gain cell circuit of Figure 7 according to another embodiment of the present disclosure. [Figure 10] Another embodiment of the present disclosure shows a gain cell circuit having five transistors (5T), including two front-end-of-line (FEOL) transistors and three back-end-of-line (BEOL) transistors. [Figure 11] This is a simplified cross-sectional view showing the gain cell circuit of Figure 10 according to one embodiment of the present disclosure. [Figure 12A] This is a perspective view showing a gain cell circuit according to one embodiment of the present disclosure (for example, the gain cell circuit of Figure 10 having the cross-sectional view of Figure 11), and highlighting different layer levels. [Figure 12B]This is a perspective view showing a gain cell circuit according to one embodiment of the present disclosure (for example, the gain cell circuit of Figure 10 having the cross-sectional view of Figure 11), and highlighting different layer levels. [Figure 12C] This is a perspective view showing a gain cell circuit according to one embodiment of the present disclosure (for example, the gain cell circuit of Figure 10 having the cross-sectional view of Figure 11), and highlighting different layer levels. [Figure 12D] This is a perspective view showing a gain cell circuit according to one embodiment of the present disclosure (for example, the gain cell circuit of Figure 10 having the cross-sectional view of Figure 11), and highlighting different layer levels. [Figure 12E] This is a perspective view showing a gain cell circuit according to one embodiment of the present disclosure (for example, the gain cell circuit of Figure 10 having the cross-sectional view of Figure 11), and highlighting different layer levels. [Figure 12F] This is a perspective view showing a gain cell circuit according to one embodiment of the present disclosure (for example, the gain cell circuit of Figure 10 having the cross-sectional view of Figure 11), and highlighting different layer levels. [Figure 13A] These are top layout diagrams showing gain cell circuits at different layer levels, highlighted in Figures 12A to 12F, according to one embodiment of the present disclosure. [Figure 13B] These are top layout diagrams showing gain cell circuits at different layer levels, highlighted in Figures 12A to 12F, according to one embodiment of the present disclosure. [Figure 13C] These are top layout diagrams showing gain cell circuits at different layer levels, highlighted in Figures 12A to 12F, according to one embodiment of the present disclosure. [Figure 13D] These are top layout diagrams showing gain cell circuits at different layer levels, highlighted in Figures 12A to 12F, according to one embodiment of the present disclosure. [Figure 13E] These are top layout diagrams showing gain cell circuits at different layer levels, highlighted in Figures 12A to 12F, according to one embodiment of the present disclosure. [Figure 13F]It is a top view layout diagram showing gain cell circuits at different layer levels highlighted in FIGS. 12A to 12F according to an embodiment of the present disclosure. [Figure 14A] A general-purpose gain cell circuit arrangement having five transistors (5T) including two front-end-of-line (FEOL) transistors and three back-end-of-line (BEOL) transistors according to an embodiment of the present disclosure is shown. [Figure 14B] A general-purpose gain cell circuit arrangement having five transistors (5T) including two front-end-of-line (FEOL) transistors and three back-end-of-line (BEOL) transistors according to an embodiment of the present disclosure is shown. [Figure 15] A gain cell circuit having five transistors (5T) including two front-end-of-line (FEOL) transistors and three back-end-of-line (BEOL) transistors according to another embodiment of the present disclosure is shown. [Figure 16] The operation of a gain cell according to an embodiment of the present disclosure is shown. [Figure 17] A memory system having an array of 5T gain cells according to an embodiment of the present disclosure is shown.

Embodiments for Carrying out the Invention

[0005] The present disclosure provides many different embodiments or exemplifications to achieve different features of the provided subject matter. To simplify the present disclosure, specific exemplifications of members and arrangements are described below. Of course, these are merely exemplifications and not for limitation. For example, in the following description, forming the first feature above or on the second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features are formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. Also, the present disclosure may repeat reference signs and / or letters in various exemplifications. Such repetition is for simplification and clarification and does not itself define the relationship between the various embodiments and / or arrangements being considered.

[0006] Furthermore, for ease of explanation, spatial relative terms such as “below,” “below,” “below,” “lower,” “up,” “above,” and “upper” may be used herein to describe the relationship between one element or feature and another element or feature(s) shown in the accompanying drawings. The spatial relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation shown in the accompanying drawings. The device may be positioned in other orientations (rotated 90 degrees or other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0007] Furthermore, when describing numerical values ​​or ranges using terms such as "approximately," "roughly," or "substantially," the terms are intended to include numerical values ​​within a reasonable range encompassing the described value, such as values ​​within ±10% of the described value, or other numerical values ​​understood by a person skilled in the art. For example, the term "approximately 5 nm" may include a dimensional range of 4.5 nm to 5.5 nm if it is known to a person skilled in the art that the structural tolerance related to the deposition of the material layer is ±10%. Also, when comparing the dimensions or size of one feature with another, phrases such as "substantially the same," "essentially the same," or "similar in size" may be understood to mean within ±10% of the difference between the features being compared. Additionally, disclosed dimensions of different features may implicitly disclose the dimensional ratio between the different features.

[0008] This disclosure relates to memory devices and structures, and more specifically to a gain cell circuit having five transistors (5T), at least one of which is formed as a back-end obline (BEOL). One or more BEOL transistors may be present in the 5T gain cell, but at least one of the BEOL transistors is a feedback transistor that is part of a feedback loop coupled to the memory node, in order to improve charge retention of the memory node. The feedback loop includes a feedback transistor, a read transistor, and a write transistor, each of which has a terminal connected to the memory node. The feedback transistor formed as a BEOL transistor takes advantage of several advantages. Compared to a front-end process (FEOL) transistor, the BEOL transistor allows for an increase in the total capacitance of the transistor due to its larger device area (which improves charge retention of the memory node), and provides an area advantage by allowing the 5T circuit to fit within the occupied area of ​​a 4T. Also, since the BEOL transistor is not used for writing / reading, it does not suffer performance loss due to variations in drive current and threshold voltage. Conversely, the BEOL transistor is used only to enhance the polarity of stored bits when the write operation is turned off. Thus, concerns regarding reliability and variability are not an issue. BEOL transistors may be achieved by BEOL-compatible materials (e.g., amorphous oxides, two-dimensional materials, carbon nanotubes). In another embodiment, a 5T gain cell is composed of two FEOL transistors and three BEOL transistors. This allows for further miniaturization to achieve increased area savings. The two additional BEOL transistors may include write transistors having a large bandgap material to reduce leakage and read transistors having a high-mobility material such as carbon nanotubes to achieve high speed.

[0009] It should be noted that, when describing the various embodiments of this disclosure, the polarity of different transistors (i.e., FETs) in the corresponding gain cell circuit may change, as long as the correct operation of the corresponding gain cell circuit is maintained. For example, the read transistor may be an n-type FET and the write transistor may be a p-type FET, or vice versa. Also, for example, both the read transistor and the write transistor may be n-type FETs, or both may be p-type FETs. The polarity of the signal line (SL) may also change in order to maintain correct operation. For example, the signal line may change from a high voltage (e.g., VDD) to a low voltage (e.g., GND), or vice versa. Furthermore, the gain cell circuits described herein have corresponding gain cell structures (or devices), and the terms gain cell circuit, gain cell structure, and gain cell device may be used interchangeably.

[0010] The embodiments described herein are achieved by fin-type field-effect transistors (FinFETs), but the disclosure is not limited thereto. For example, the disclosure may be achieved by all-around gate (GAA) FETs. A FinFET is a transistor having a gate stack (gate electrode and gate dielectric layer) in which conductive channels are formed on three sides of a fin-shaped structure. A GAA FET is a transistor having a gate stack (gate electrode and gate dielectric layer) surrounding a transistor channel, such as a vertically stacked all-around gate horizontal nanowire or nanosheet MOSFET device. Those skilled in the art should understand that the disclosure can be readily used as a basis when designing or modifying other structures to carry out the same objectives and / or achieve the same advantages as the embodiments described herein. For example, the disclosure may be achieved by planar MOSFETs.

[0011] Figures 1A to 1E show gain cell circuits in various configurations according to embodiments of the present disclosure. These gain cell circuits may also be called embedded dynamic random access memory (eDRAM). Figures 1A to 1C show silicon-only (Si-only) gain cell circuits in which the transistors are formed entirely in the front-end process (FEOL). FEOL generally refers to all circuit regions and associated processes that start from the substrate (e.g., silicon wafer) and include the substrate but do not include the metal wiring layer. These regions may include the substrate, the active region, the source / drain features of the active region, the channel region of the active region, the gate, and device-level metal features (e.g., device-level contacts and vias). A FEOL (or silicon-only) transistor is a transistor formed by epitaxial growth and having an active region made of crystalline silicon or crystalline silicon germanium. For example, a Si-only transistor includes source / drain epitaxial features doped with n-type or p-type dopants.

[0012] Figure 1A shows a Si-only 2T gain cell circuit having one write transistor and one read transistor. The write transistor and the read transistor are coupled at a memory node (code: SN), and data can be written to or read from the memory node. The write transistor has a first terminal electrically connected to the write bit line (WBL), a gate terminal (or control terminal) electrically connected to the write word line (WWL), and a second terminal electrically connected to the memory node. The read transistor includes a first terminal coupled to the read bit line, a gate terminal (or control terminal) coupled to the memory node, and a second terminal coupled to the read word line (RWL). The first and second terminals of different transistors may be referred to as the first source / drain (S / D) feature or S / D electrode or the second S / D feature or S / D electrode of the corresponding transistor.

[0013] Figure 1B shows a Si-only 3T gain cell circuit having one write transistor and two read transistors. The first read transistor is coupled in series with the second read transistor. The first read transistor has a first terminal electrically connected to the RBL, a gate terminal electrically connected to the RWL, and a second terminal electrically connected to the first terminal of the second read transistor. The second read transistor has a first terminal, a gate terminal connected to a storage node (code: SN), and a second terminal connected to the signal line VDD. The write transistor and the second read transistor are coupled at a storage node, and data can be written to or read from the storage node. The write transistor has a first terminal electrically connected to the WBL, a gate terminal electrically connected to the WWL, and a second terminal electrically connected to the storage node. The first and second terminals of different transistors may be referred to as the first source / drain (S / D) feature or S / D electrode or the second S / D feature or S / D electrode of the corresponding transistor. Compared to a 2T gain cell, a 3T gain cell has an advantage because the additional read transistors improve the read access speed.

[0014] Figure 1C shows a Si-only 4T gain cell circuit having two write transistors, one feedback transistor, and one read transistor. The Si-only 4T gain cell circuit is similar to the Si-only 2T circuit, and the similar features will not be repeated. The differences are the addition of a second write transistor coupled in series with the first write transistor, and the addition of a feedback transistor coupled with the second write transistor and the read transistor to form a feedback loop. The gate terminals of the feedback transistor and the read transistor are electrically connected to the second terminal of the second write transistor at the memory node (sign: SN). The feedback transistor has a first terminal coupled to a common terminal between the first and second write transistors and a second terminal connected to the signal line VDD. The second write transistor has a first terminal coupled to a common terminal between the first write transistor and the feedback transistor and a second terminal coupled to the memory node. Compared to a 2T gain cell, a 4T gain cell has advantages because the transistors forming the feedback loop improve the retention time at the memory node (SN) (for example, extra or unwanted leakage signals do not enter the memory node but are driven to VDD via the feedback transistors).

[0015] Figures 1D to 1E illustrate hybrid gain cell circuits, which are gain cell circuits having one or more transistors formed in the back-end obline (BEOL). BEOL generally refers to circuit regions and associated processes other than the FEOL. These regions may include metal wiring layers, the back surface of a substrate, or another wafer as part of a three-dimensional IC structure. A BEOL transistor is a transistor whose active region is made of a different material than that of a FEOL transistor. For example, the active region of a BEOL transistor is not made of crystalline silicon or silicon germanium, but rather of a different BEOL-compatible semiconductor material such as amorphous silicon, amorphous oxide, two-dimensional material, or carbon nanotube. Figure 1D shows a hybrid 2T (Si+BEOL FET) gain cell circuit, where the write transistor is formed in the BEOL and the read transistor is formed in the FEOL. A hybrid 2T gain cell circuit, on the other hand, has the same or similar configuration as a Si-only 2T gain cell circuit. Figure 1E shows a hybrid 2T (two BEOL FET) gain cell circuit, where both the read and write transistors are formed in the BEOL. On the other hand, hybrid 2T gain cell circuits have the same or similar configuration as Si-only 2T gain cell circuits. Compared to Si-only gain cell circuits, hybrid gain cell circuits have advantages because they improve cell density. For example, by forming one or more transistors in the BEOL, the area on the FEOL can be reduced, thereby improving cell density. However, BEOL transistors generally perform worse than FEOL transistors due to their lower carrier mobility and drive strength. When read and write transistors are formed in the BEOL, it can negatively affect the variation in their threshold voltages.

[0016] Figure 2 shows a gain cell circuit having five transistors (5T) including four front-end-of-line (FEOL) transistors and one back-end-of-line (BEOL) transistor according to one embodiment of the present disclosure. Compared to a two-transistor gain cell (one transistor used for reading and one transistor used for writing), the 5T gain cell has additional read transistors and additional write transistors to improve memory access and control. Similar to the 4T gain cell circuit shown in Figure 1C, the 5T gain cell further includes a feedback transistor as part of a feedback loop to extend the hold time, except that the feedback transistor is a BEOL FET. For simplicity, the electrical connections to WBL, WWL, RBL, RWL and the signal line VDD (or GND) will not be described again.

[0017] By forming feedback transistors within the BEOL, the device footprint on the FEOL can be reduced, thereby achieving device density advantages. Furthermore, to increase the capacitance of the memory node, the BEOL feedback transistors may be formed to have a larger area; however, this cannot be achieved without increasing the device footprint in a Si-only gain cell. Moreover, because the requirements for leakage, variability, drive, and stability of the BEOL feedback transistors are less stringent (i.e., the feedback transistors are used for charge maintenance rather than read / write operations), the BEOL feedback transistors do not adversely affect critical read / write operations.

[0018] Continuing to refer to Figure 2, the hybrid 5T gain cell circuit includes a first write transistor TN1 and a second write transistor TN2 coupled in series, a first read transistor TP1 and a second read transistor TP2 coupled in series, and a BEOL feedback transistor formed in the upper layer of each of the transistors TN1, TN2, TP1, and TP2. The BEOL feedback transistor is electrically connected to a memory node SN, which is further electrically connected to the source / drain (S / D) terminal of the second write transistor TN2 and the gate terminal of the second read transistor TP2. In this embodiment, transistors TN1, TN2, and the BEOL FET are n-type transistors, and transistors TP1 and TP2 are p-type transistors, however, the polarity of any transistor can be changed while maintaining correct operation. In this case, only one power rail (or signal line) VDD is required, which has wiring advantages compared to when two power rails (or signal lines) (e.g., VDD and VSS (ground)) are required.

[0019] Figures 3A and 3B are simplified cross-sectional views showing a gain cell structure 200 (at least partially) corresponding to the gain cell circuit of Figure 2 according to one embodiment of the present disclosure. In the shown embodiment, Figure 3A shows transistors TN1 and TN2 and a feedback transistor BEOL FET, and Figure 3B shows transistors TP1 and TP2 and a feedback transistor BEOL FET. Transistors TN1 and TN2 are formed in an n-type active region 106 having an N-epi feature, and transistors TP1 and TP2 are formed in a p-type active region 106 having a P-epi feature. The n-type active region 106 and the p-type active region 106 are parallel along the x-direction, extend longitudinally, and are adjacent to each other along the y-direction (in and out of the page). It should be noted that while two adjacent gain cells are shown in Figures 3A and 3B (each gain cell has five transistors, including a feedback transistor BEOL FET), the present disclosure is not limited thereto. The feedback transistor BEOL FET can completely or partially cover transistors TN1, TN2, TP1, and TP2. Given the additional spacing at the BEOL, a larger size of the BEOL FET is advantageous for increasing the capacitance of the memory node.

[0020] The gain cell structure 200 comprises a substrate 102. The substrate 102 may be a silicon (Si) substrate, or a substrate having other semiconductor materials such as germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe), or diamond. The substrate 102 may be doped with a p-type dopant such as boron, or an n-type dopant such as phosphorus. The active region 106 protrudes from above the substrate 102 and may contain the same or similar material as the substrate 102. The active region 106 may be formed by patterning the substrate 102 to form a fin-shaped active region 106 protruding from the uppermost surface of the substrate 102. For example, the active region 106 may be formed by a patterning process including lithography and etching. In some embodiments, a patterning mask layer is formed by a lithography process to cover a region of the substrate 102 for forming the active region 106, and the exposed portion of the patterning mask layer is etched by an etching process using the patterning mask layer as an etching mask. The etching process forms recesses that separate and define the active region 106. The active region 106 extends longitudinally along the x-direction and may be called a fin-type active region or semiconductor fin.

[0021] Continuing with Figures 3A and 3B, the gain cell structure 200 includes an isolation structure 104 positioned and formed above the substrate 102 and between the active regions 106. The isolation structure 104 may be a shallow trench isolation (STI) layer and provide isolation between adjacent active regions 106 that are spaced apart along the x and y directions. The isolation structure 104 may be formed by any suitable process and may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), low-κ dielectric, combinations thereof, and / or other suitable materials.

[0022] Continuing to refer to Figures 3A and 3B, the active region 106 includes a channel region 107 between the source / drain (S / D) feature regions 108, and the metal gate stack 110 (gate electrode and gate dielectric layer) is located above the channel region 107 and is in interfacial contact with the channel region. As shown, the FEOL transistor includes transistors TN1, TN2, TP1, and TP2, each transistor defined by a gate stack 110 above the channel region 107 and an S / D feature region 108 adjacent to the channel region 107. The S / D feature regions 108 may be formed using epitaxial processes of CVD technology (e.g., VPE and / or UHV-CVD), molecular beam epitaxial, other suitable epitaxial growth processes, or a combination thereof. The epitaxial process may use gaseous and / or liquid precursors, which interact with the composition of the active region 106. The epitaxial S / D feature portion 108 is doped with an n-type dopant or a p-type dopant. In some embodiments, for n-type transistors TN1 and TN2, the epitaxial S / D feature portion 108 contains silicon and may be doped with carbon, phosphorus, arsenic, other n-type dopants, or combinations thereof (for example, forming a Si:C epitaxial source / drain feature portion, a Si:P epitaxial source / drain feature portion, or a Si:C:P epitaxial source / drain feature portion). In some embodiments, for p-type transistors TP1 and TP2, the epitaxial S / D feature portion 108 contains silicon germanium or germanium and may be doped with boron, other p-type dopants, or combinations thereof (for example, forming a Si:Ge:B epitaxial source / drain feature portion). Each of the S / D feature sections 108 may be provided above them with an S / D contact (unsigned) for electrical connection to an upper contact. These S / D contacts together with the S / D feature section 108 may be referred to as the S / D feature section 108.

[0023] Continuing to refer to Figures 3A and 3B, the gain cell structure 200 further includes a wiring structure 500 located above the FEOL transistor. The wiring structure 500 includes wiring metal wires and vias (collectively designated as a metallic feature 504) that are electrically connected to device-level contacts (e.g., S / D feature 108 and / or gate stack 110) depending on the desired gain cell circuit connection. The metallic feature 504 is formed within a dielectric feature 502 (e.g., an intermetallic dielectric layer) and embedded by these dielectric feature sections. In the illustrated embodiment, the wiring structure 500 includes intermetallic layers M1 to M4. Each intermetallic layer M1 to M4 may include a metal wire layer and a via layer connected perpendicularly to the metal wire layer. For example, intermetallic layer M1 has an M1 via that connects a device-level contact perpendicularly to the M1 metal wire, and the M1 metal wire extends longitudinally along the x-direction. In the intermetallic layer M2, there is a via to M2 that connects the M1 metal wire perpendicularly to the M2 metal wire, and the M2 metal wire extends longitudinally along the y-direction. In the intermetallic layer M3, there is a via to M3 that connects the M2 metal wire perpendicularly to the M3 metal wire, and the M3 metal wire extends longitudinally along the x-direction, and so on by analogy. Some vias can extend perpendicularly and penetrate multiple intermetallic layers to achieve direct connections (for example, connecting the M1 metal wire and the M3 metal wire).

[0024] As will be explained in more detail below, the intermetallic layer M1 may include a read word line (RWL) and a write word line (WWL). The intermetallic layer M2 may include a read bit line (RBL), a read word line (RWL), and a high-voltage line (VDD). Furthermore, the intermetallic layers M3 and M4 may include a feedback BEOL FET. Each BEOL FET may include a BEOL gate 210, a semiconductor layer 207, and two S / D electrodes 208. As shown in the figure, the BEOL gate 210 may be a back gate formed in the intermetallic layer M3, and the semiconductor layer 207 and S / D electrodes 208 may be formed in the intermetallic layer M4 above the intermetallic layer M3. The semiconductor layer is formed on the BEOL gate 210, and the S / D electrodes 208 are formed on opposite ends of the semiconductor layer 207. The semiconductor layer 207 may include, for example, amorphous silicon such as IWO, ITO, and IGZO, amorphous oxides, two-dimensional materials such as WSe2, MoS2, and WS2, carbon nanotubes, or BEOL-compliant materials such as low-temperature Si, SiGe, or Ge.

[0025] Figures 4A to 4D are top layout diagrams showing the gain cell structure 200 at different layer levels (e.g., different layer levels of the gain cell circuit of Figure 2 having the cross-sectional views in Figures 3A to 3B) according to one embodiment of the present disclosure. Figures 4A to 4D provide layer-by-layer detail diagrams showing how the gain cell circuit members of the gain cell structure 200 (e.g., as shown in Figures 3A to 3B) are wired and laid out. The electrical connections of these gain cell circuit members are consistent with the gain cell circuit shown in Figure 2. For ease of viewing, the intermetallic dielectric layers embedded surrounding the gain cell structure 200 are not shown.

[0026] Figure 4A shows a gain cell structure 200 that spans vertically from the FEOL to the intermetallic layer M1. The gain cell structure 200 includes two active regions 106 that extend longitudinally along the x-direction and penetrate the cell region. Each active region 106 includes two gate stacks 110 that extend longitudinally along the y-direction above the channel region of the corresponding active region 106. Adjacent to the channel region are the S / D feature region / contact 108. As shown, the first active region 106 (e.g., an n-type active region) and its corresponding gate stack 110 form FEOL transistors TN1 and TN2 (their corresponding gate stacks 110 are designated), and the second active region 106 (e.g., a p-type active region) and its corresponding gate stack 110 form FEOL transistors TP1 and TP2 (their corresponding gate stacks 110 are designated). The gain cell structure 200 has a FEOL gate distance x1, and this FEOL gate distance spans the distance between adjacent gate stacks 110.

[0027] Continuing to refer to Figure 4A, the gain cell structure 200 includes a plurality of M1 metal wires 114 above the FEOL transistors TN1, TN2, TP1, and TP2. The M1 metal wires 114 include a write word line (WWL) electrically connected to the gate 110 of transistor TN1 via a via 112 to M1. The WWL is further electrically connected to the gate 110 of transistor TN2 via another via 112 to M1. The M1 metal wires 114 further include a read word line (RWL) electrically connected to the gate 110 of transistor TP1 via another via 112 to M1. The M1 metal wires 114 further include M1 local wiring electrically connected to one of the corresponding S / D feature sections / contacts 108 of transistors TN1 and TN2 via an additional corresponding via 112 to M1. These M1 local wirings can route signals to desired locations in the gain cell structure 200 (e.g., above the gate stack 110) to achieve better spacing than when connected to a higher intermetallic layer. As shown in the figure, the gain cell structure 200 further includes vias 116 to M2 for skipping the intermetallic layer M1 and directly routing components in the FEOL (e.g., S / D feature / contact 108 and gate stack 110) to the metal wires in the intermetallic layer M2. As shown in the figure, the vias 116 to M2 are located on the shared S / D feature / contact 108 between transistors TN1 and TN2, on the gate stack 110 of transistor TP2, and on the corresponding far-end S / D feature / contact 108 of transistors TP1 and TP2. The gain cell structure 200 has an M1 distance y1 that spans the distance between adjacent M1 metal wires 114.

[0028] Figure 4B shows a gain cell structure 200 that spans vertically from intermetallic layer M1 to intermetallic layer M2. Figure 4B is superimposed on Figure 4A, and for simplicity, previously described components are not repeated. As shown, the gain cell structure 200 includes a plurality of M2 metal wires 118 above the M1 metal wire 114. The M2 metal wires 118 include read bit lines (RBL) electrically connected to the corresponding S / D feature / contact 108 of transistor TP1 via vias 116 to the corresponding M2. The M2 metal wires 118 further include write bit lines (WBL) electrically connected to the corresponding S / D feature / contact 108 of transistor TN1 via vias 116 to the corresponding M2 located in the corresponding M1 local wiring. The M2 metal wires 118 further include signal lines (VDD) electrically connected to the corresponding S / D feature / contact 108 of transistor TP2 via vias 116 to the corresponding M2. The M2 metal wire 118 further includes an M2 local wiring L1 that is electrically connected to a shared S / D feature / contact 108 between transistors TN1 and TN2 via a via 116 to the corresponding M2. The M2 metal wire 118 further includes an M2 local wiring L2 that electrically connects the metal gate stack 110 of transistor TP2 to the far end S / D feature / contact 108 of transistor TN2 via a via 116 to the corresponding M2.

[0029] Figure 4C shows a gain cell structure 200 that spans vertically from intermetallic layer M2 to intermetallic layer M3. Figure 4C is superimposed on Figure 4B, and for simplicity, previously described components will not be repeated. As shown, the gain cell structure 200 includes a plurality of M3 metal wires 122 above the M2 metal wire 118. The M3 metal wires 122 include the gate 210 of the BEOL FET, the gate 210 also corresponds to / connects to the memory node SN. The gate 210 may be called a back gate and can span an area of ​​more than twice the gate distance x1 in the x direction and an area of ​​three times the M1 distance y1 in the y direction. The gate 210 can be electrically connected to the M2 local wiring L2 via a via 120 to M3. The M3 metal wires 122 further include the M3 local wiring L3 which is electrically connected to the M2 local wiring L1 via a via 120 to M3. These M3 local connections L3 can be routed to desired locations in the gain cell structure 200 (e.g., above the RBL) to achieve better spacing than when connected to higher intermetallic layers. As shown in the figure, the gain cell structure 200 further includes vias 124 to M4 for skipping the intermetallic layer M3 and routing signal lines (VDD) in the intermetallic layer M2 directly to the metal wires in the intermetallic layer M4.

[0030] Figure 4D shows a gain cell structure 200 that spans vertically from intermetallic layer M3 to intermetallic layer M4. Figure 4D is superimposed on Figure 4C, and for simplicity, previously described components are not repeated. As shown, the gain cell structure 200 includes a plurality of M4 metal wires 126 above the M3 metal wire 122. The M4 metal wires 126 include two S / D electrodes 208 at opposing ends of the gate 210 along the x-direction. As previously stated, between the S / D electrodes 208 and the gate 210 is a semiconductor layer 207 having a BEOL-compatible semiconductor material. The gate 210, semiconductor layer 207, and the two S / D electrodes 208 together form a BEOL FET (i.e., a BEOL feedback transistor). In the S / D electrodes 208, one S / D electrode at one terminal is electrically connected to the M3 local wiring L3 via a via 124 to M4. Then, at the S / D electrode 208, another S / D electrode at the opposite terminal is electrically connected to the signal line VDD via via 124 to the corresponding M4 shown in Figure 4B.

[0031] Figure 5 is a three-dimensional perspective view showing the gain cell structure 200 of Figures 4A to 4D according to one embodiment of the present disclosure. The perspective view is consistent with the top layout views of Figures 4A to 4D and shows all components of the gain cell structure 200 from the front end level to the intermetallic layer M4. In the shown embodiment, the bottom FEOL transistor may be formed in an active region 106 having a plurality of fins. The RWL and WWL are above the active region 106. The RBL, WBL and VDD are formed above the RWL and WWL. The feedback BEOL transistor having a gate 210, a semiconductor layer 207 and an S / D electrode 208 is formed above the RBL, WBL and VDD. Although not shown in Figure 5 (as shown in Figure 6), a gate dielectric may be formed between the gate 210 and the semiconductor layer 207. The gate dielectric should be selected to maximize the gate capacitance and minimize gate leakage. A reasonable choice would be a high-κ material (e.g., HfO2) with an equivalent oxide thickness of less than 1 nm.

[0032] Figure 6 is a three-dimensional perspective view showing the gain cell structure 200 of Figures 4A to 4D according to another embodiment of the present disclosure. Figure 6 is similar to Figure 5, and for simplicity, similar features will not be repeated. The difference is that the gate 210 includes a back gate 210a (similar to the back gate shown in Figure 5), but further includes a top gate 210b positioned laterally between the S / D electrodes 208 and above the semiconductor layer 207. In other words, the feedback BEOL transistor has a dual-gate configuration to increase the total capacitance. Additional metal wiring (as shown) is configured to connect to the top gate 210b to achieve proper operation. Figure 6 further shows gate dielectric layers interfacially in contact with the corresponding top gate 210a and back gate 210b, with the semiconductor layer 207 in between.

[0033] Figure 7 shows a gain cell circuit having five transistors (5T), including two front-end process (FEOL) transistors and three back-end ob-line (BEOL) transistors, according to one embodiment of the present disclosure. Figure 7 is similar to Figure 2, except that the BEOL feedback transistor is designated TN3 (e.g., an n-type transistor) and is a first BEOL level transistor, while transistors TN2 and TP2 are second-level BEOL transistors. As further illustrated in the figure below, the first and second BEOL level transistors are located in different intermetallic layers (e.g., the second level is above the first level). Moving transistors TN2 and TP2 from FEOL to back-end ob-line (BEOL) can further improve cell density while maintaining a long retention time. In the shown embodiment, transistors TN1 and TP1 are still FEOL transistors.

[0034] Figure 8 is a simplified cross-sectional view showing a gain cell structure 300 corresponding (at least partially) to the gain cell circuit of Figure 7 according to one embodiment of the present disclosure. The gain cell structure 300 in Figure 8 may be similar to the gain cell structures 200 in Figures 3A-3B, and for simplicity, similar features will not be repeated. As shown, Figure 8 shows FEOL transistors TN1 and TN2 formed on an n-type active region 106 having an N-epi feature, a first-level BEOL transistor TN3 (i.e., a feedback transistor) formed above the FEOL transistors TN1 and TN2, and second-level BEOL transistors TP1 and TP2 formed above the first-level BEOL transistors. Each of the second-level BEOL transistors TP1 and TP2 may be formed in an intermetallic layer M5 / M6 and includes a BEOL gate 310, a semiconductor layer 307, and a pair of S / D electrodes 308. These second-level BEOL transistors may be structurally similar to first-level BEOL transistors (e.g., they have a back gate), but they span a smaller area (e.g., the area they span is about half or less of the area of ​​the first-level BEOL transistor). Compared to the gain cell structures 200 in Figures 3A and 3B, the gain cell structure 300 in Figure 8 shows a smaller cell occupancy area in the FEOL region because each gain cell has only two transistors formed within it (e.g., formed within a single n-type active region 106).

[0035] Figure 9 is a simplified cross-sectional view showing the gain cell circuit of Figure 7 according to another embodiment of the present disclosure. The gain cell structure 300 in Figure 9 may be similar to the gain cell structure 300 in Figure 8, and for simplicity, similar features will not be repeated. As shown, Figure 9 shows FEOL transistors TP1 and TP2 formed on a p-type active region 106 having a P-epi feature, a first-level BEOL transistor TN3 (i.e., a feedback transistor) formed above the FEOL transistors TP1 and TP2, and second-level BEOL transistors TN1 and TN2 formed above the first-level BEOL transistors. Each of the second-level BEOL transistors TN1 and TN2 may be formed in an intermetallic layer M5 / M6 and includes a BEOL gate 310, a semiconductor layer 307, and a pair of S / D electrodes 308. These second-level BEOL transistors may be structurally similar to first-level BEOL transistors, but they span a smaller area (for example, the area they span is about half or less of the area of ​​the first-level BEOL transistor). Compared to the gain cell structures 200 in Figures 3A and 3B, the gain cell structure 300 in Figure 9 shows a smaller cell occupancy area in the FEOL region because each gain cell has only two transistors formed within it (for example, formed within a single p-type active region 106).

[0036] Figure 10 shows a gain cell circuit having five transistors (5T), including two front-end process (FEOL) transistors and three back-end ob-line (BEOL) transistors, according to another embodiment of the present disclosure. Figure 10 is similar to Figure 7, except that the VDD and RBL nodes are inverted, and the first BEOL level transistor and the second BEOL level transistor are also inverted. The connections of VDD and RBL can be optimized to balance the gain cell hold time, noise during readout operation, and the bit cell area of ​​the gain cell.

[0037] Figure 11 is a simplified cross-sectional view showing a gain cell structure 300 corresponding (at least partially) to the gain cell circuit of Figure 10 according to one embodiment of the present disclosure. The gain cell structure 300 in Figure 11 may be similar to the gain cell structures 300 in Figures 8-9, and for simplicity, similar features will not be repeated. Since Figure 11 shows a cross-sectional view cut across the y-direction, two adjacent active regions 106 are shown extending vertically towards the front or back of the page. As shown in the gain cell structure 300, the active regions 106 are one n-type active region having an N-epi S / D feature and the other p-type active region having a P-epi S / D feature. The FEOL transistor TN1 is formed in the n-type active region, and the FEOL transistor TP1 is formed in the p-type active region. The first-level BEOL transistors TN2 and TP2 are formed above the BEOL transistors TN1 and TP1 in the intermetallic layers M3 / M4, and the second-level BEOL transistor TN3 (i.e., the feedback transistor) is formed above the first-level BEOL transistors TN2 and TP2 in the intermetallic layers M5 / M6. In this embodiment, the first-level BEOL transistors TN2 and TP2 may differ structurally from the second-level BEOL transistor TN3. For example, the first-level BEOL transistors TN2 and TP2 may be carbon nanotube transistors that span a smaller area (e.g., the area they span is about half or less of the area of ​​the second-level BEOL transistor). Each of the carbon nanotube transistors may include a semiconductor layer 507, a BEOL gate 510 located above the semiconductor layer 507 and enclosing the channel portion of the semiconductor layer, and a pair of S / D electrodes 208 located above the semiconductor layer 507 and enclosing the S / D portion of the semiconductor layer. Compared to the embodiments shown in Figures 8 and 9, the vertical arrangement of the BEOL feedback transistors is inverted relative to the other BEOL transistors.Furthermore, compared to the gain cell structures 200 in Figures 3A and 3B, the gain cell structure 300 in Figure 11 shows a smaller cell occupancy area in the FEOL region, because each gain cell has only two transistors formed within it (for example, one in the p-type active region 106 and the other in the adjacent n-type active region 106).

[0038] Figures 12A to 12F are three-dimensional perspective views showing a gain cell structure 300 according to one embodiment of the present disclosure (for example, the gain cell circuit of Figure 10 having a cross-sectional view in Figure 11), with different layer levels highlighted in blocks 402, 404, 406, 408, 410, and 412, respectively. Figures 13A to 13F are top layout views showing the gain cell structure 300 in Figures 12A to 12F at different layer levels highlighted in blocks 402, 404, 406, 408, 410, and 412, respectively, according to one embodiment of the present disclosure. The electrical connections of the gain cell circuit members in the gain cell structure 300 are consistent with the gain cell circuit shown in Figure 10. For ease of viewing, the intermetallic dielectric layers embedded surrounding the gain cell structure 300 are not shown.

[0039] Referring together to Figures 12A and 13A, the gain cell structure 300 in block 402 shows the gain cell circuit members from the FEOL to the intermetallic layer M1. In the FEOL, transistors TN1 and TP1 are formed on corresponding active regions 106 (e.g., p-type active region and n-type active region, respectively), and each FEOL transistor has a corresponding gate stack 110 formed above the channel region and an S / D feature / contact 108 adjacent to the channel region. The gain cell structure 300 includes a plurality of M1 metal wires 114 above the FEOL transistors TN1 and TP1. The M1 metal wires 114 include a write word line (WWL) electrically connected to the gate 110 of transistor TN1 via vias 112 to M1. The M1 metal wires 114 further include a read word line (RWL) electrically connected to the gate 110 of transistor TP1 via another via 112 to M1. The M1 metal wire 114 further includes a signal line (VDD) electrically connected to the S / D feature / contact 108 of transistor TP1 via a via 112 to another M1. The M1 metal wire 114 further includes an M1 local trace electrically connected to one of the corresponding S / D feature / contact 108s of transistors TN1 and TP1 via an additional corresponding M1 via 112. These M1 local traces can route signals to desired locations in the gain cell structure 200, such as above the gate stack 110, to achieve better spacing than would be achieved if connected to a higher intermetallic layer. As shown, the gain cell structure 200 further includes a via 116 to M2 for directly routing a component in the FEOL (e.g., S / D feature / contact 108) to a metal wire in the intermetallic layer M2, skipping the intermetallic layer M1. As shown, the via 116 to M2 is located at the S / D feature / contact 108 of transistor TN1.

[0040] Referring together to Figures 12B and 13B, the gain cell structure 300 in block 404 shows the gain cell circuit components from intermetallic layer M1 to intermetallic layer M2. Figure 13B is superimposed on Figure 13A, and for simplicity, the components described above will not be repeated. As shown, the gain cell structure 300 includes a plurality of M2 metal wires 118 above the M1 metal wire 114. The M2 metal wires 118 include write bit lines (WBLs) electrically connected to the corresponding S / D feature section / contact 108 of transistor TN1 via vias 116 to M2. The M2 metal wires 118 further include read bit lines (RBLs) superimposed on the M1 metal wire 114 and positioned without any electrical connection to the M1 metal wire. The gain cell structure 300 further includes vias 120 to M3 for skipping intermetallic layer M2 and directly routing the M1 metal wire to the metal wire in intermetallic layer M3. As shown in the figure, there are vias 120 to M3 located in the WWL, vias 120 to M3 located on one side of the M1 local wiring, and vias 120 to M3 located on the other side of the M1 local wiring.

[0041] Referring together to Figures 12C and 13C, the gain cell structure 300 in block 406 shows the gain cell circuit components from intermetallic layer M2 to intermetallic layer M3. Figure 13C is superimposed on Figure 13B, and for simplicity, previously described components will not be repeated. As shown, the gain cell structure 300 includes a plurality of M3 metal wires 122 above the M2 metal wire 118. The M3 metal wires include M3 local wiring electrically connected to vias 120 to M3, and as previously stated, these vias 120 to M3 are electrically connected to the corresponding S / D feature / contact 108 of transistor TN1, the corresponding S / D feature / contact 108 of transistor TP1, and WWL, respectively. These M3 local wirings can be routed to desired locations in the gain cell structure 300 (e.g., above the read bit line (RBL) and / or above the write bit line (WBL)) to achieve better spacing than when connected to higher intermetallic layers.

[0042] Referring together to Figures 12D and 13D, the gain cell structure 300 in block 408 shows the gain cell circuit members from intermetallic layer M3 to intermetallic layer M4. Figure 13D is superimposed on Figure 13C, and for simplicity, previously described members will not be repeated. As shown, the gain cell structure 300 includes a plurality of M4 metal wires 126 above the M3 metal wire 122. As shown, the M4 metal wires 126 include S / D electrodes 208 and BEOL gates 510 for the first BEOL level transistors TN2 and TP2. Since the corresponding semiconductor layer 507 is formed between the intermetallic layers M3 and M4, the semiconductor layer 507 is coupled to the corresponding BEOL gate 510 and S / D electrode 208 and is encased by the corresponding BEOL gate and S / D electrode. Thus, the first BEOL level transistors TN2 and TP2 can be formed as carbon nanotube transistors, and the semiconductor layer 507 is a carbon nanotube. It should be noted that the gain cell structure 300 further includes vias 124 to multiple M4s which electrically connect the corresponding downward M3 local wiring of the M3 metal wire 122 to the corresponding S / D electrode 508 and gate 510.

[0043] Referring together to Figures 12E and 13E, the gain cell structure 300 in block 410 shows the gain cell circuit components from intermetallic layer M4 to intermetallic layer M5. Figure 13E is superimposed on Figure 13D, and for simplicity, previously described components will not be repeated. As shown, the gain cell structure 300 includes the M5 metal wire 130 of the gate 210 corresponding to the second-level BEOL transistor. The gate 210 is further corresponding to / connected to the memory node SN. The gate 210 is located above the intermetallic layer M4 and may be configured similarly to the gate 210 shown in Figure 4C. However, in the gain cell structure 300, because the gain cell area of ​​the gain cell structure 300 is small and has only two FEOL transistors at the bottom, the gate 210 can span a smaller area. The gate 210 is electrically connected to the gate 510 of transistor TP2 via 124 to M4. The gate 210 is further electrically connected to the S / D electrode 508 of transistor TN2 via a via 124 to another M4. As shown in the figure, the gain cell structure 300 further includes a via 132 to M6 for skipping the intermetallic layer M5 and directly routing the corresponding S / D electrode 508 of transistor TN2 in the intermetallic layer M4 to the metal wire in the intermetallic layer M6.

[0044] Referring together to Figures 12F and 13F, the gain cell structure 300 in block 412 shows the gain cell circuit members from intermetallic layer M5 to intermetallic layer M6. Figure 13F is superimposed on Figure 13E, and for simplicity, previously described members will not be repeated. As shown, the gain cell structure 300 includes a plurality of M6 metal wires 134 above the M5 metal wire 130 (i.e., gate 210). The M6 ​​metal wires 134 include two S / D electrodes 208 at opposite ends of the gate 210 along the x-direction. As previously stated, between the S / D electrodes 208 and the gate 210 is a semiconductor layer 207 having a BEOL-compatible semiconductor material. The gate 210, semiconductor layer 207, and the two S / D electrodes 208 together form a second-level BEOL field-effect transistor (i.e., a BEOL feedback transistor). One of the S / D electrodes 208 at one end is electrically connected to via 132 to M6. The other terminal at the opposite end of the S / D electrode 208 is electrically connected to (or corresponds to) the signal line VDD. The signal line VDD can be extended longitudinally along the y-direction.

[0045] Figures 14A and 14B show a general-purpose gain cell circuit configuration having five transistors (5T), including two front-end-of-line (FEOL) transistors and three back-end-of-line (BEOL) transistors, according to one embodiment of the present disclosure. Figure 14A shows a gain cell circuit similar to the 5T gain cell circuits of Figures 7 and 10 described earlier, but differs in that the FEOL transistors, BEOL Level 1 transistors, and BEOL Level 2 transistors are not explicitly identified. Figure 14B corresponds to the gain cell circuit of Figure 14A and shows different combinations of transistor arrangements of transistors TN1, TN2, TN3, TP1, and TP2 in a general cross-sectional view. As shown, in the five transistors, two of the transistors TN1-TN3 and TP1-TP2 can be formed in the FEOL. Intermetallic layers M1 and M2 can form electrical wiring connections via vias and metal wires. Furthermore, three of the transistors TN1-TN3 and TP1-TP2 can be formed in the back-end-of-line (BEOL).

[0046] However, in order to obtain the advantages of memory capacitance, transistor TN3 (feedback loop transistor) is formed in the back-end of line (BEOL). In this case, transistor TN3 is formed above at least two of the other read / write transistors (e.g., TN1, TN2, TP1 and / or TP2) and can occupy an area / space equivalent to the sum of the area / space of these other read / write transistors. Alternatively, the three BEOL transistors may be formed in two different intermetallic layers, with transistor TN3 formed in one layer (e.g., M3 / M4) and the other two transistors formed in another layer (e.g., M5 / M6 or M3 / M4) above or below the aforementioned layer. Furthermore, one or more BEOL transistors may have a vertical gate enclosing a channel (e.g., a carbon nanotube as described herein or another type of channel), the channel extending between two S / D vertical electrodes, and one or more BEOL transistors may have a planar gate above a planar channel (e.g., an amorphous oxide or 2D material or another type of channel as described herein) and two electrodes above the terminals of the planar gate. Also, a feedback BEOL transistor TN3 can span a larger area than other BEOL transistors and FEOL transistors. In one example, transistor TN3 may occupy an area / space equivalent to the sum of the areas / spaces of two or more other transistors.

[0047] In a typical embodiment, the three BEOL transistors may include any of the BEOL-compatible materials described herein, which may include low-dimensional (LDM) materials, 2D materials, carbon nanotubes (CNTs), amorphous oxides, amorphous silicon, large bandgap materials, and the like. For example, the three BEOL transistors include transistor TN3 having an LDM material, transistor TP2 having CNTs, and transistor TN2 having a 2D material or CNTs.

[0048] Figure 15 shows a gain cell circuit having five transistors (5T), including two front-end process (FEOL) transistors and three back-end ob-line (BEOL) transistors, according to another embodiment of the present disclosure. Figure 15 shows an alternative gain cell circuit similar to Figure 14A but with different polarities, namely, the PFETs used in the writing circuit (i.e., transistors TP1, TP2, and TP3) and the NFETs used in the reading circuit (i.e., transistors TN1 and TN2) both maintain accurate gain cell operation.

[0049] Figure 16 shows the operation of a gain cell according to one embodiment of the present disclosure. As shown, the gain cell can perform write or read operations. During a write operation, the read operation is turned off (for example, by biasing RWL to a high potential to turn off the gate terminal of a p-type read transistor such as TP1), and the write operation is turned on (for example, by biasing WWL to a high potential to turn on the gate terminals of n-type write transistors such as TN1 and TN2). During a write operation, WBL may be biased to a high potential to store bits in the gain cell's memory node. During a read operation, the write operation is turned off (for example, by biasing WWL to a low potential to turn off the gate terminals of n-type write transistors such as TN1 and TN2), and the read operation is turned on (for example, by biasing RWL to a low potential to turn on the gate terminal of a p-type read transistor such as TP1). During a read operation, RBL may be biased to a high potential to read (or sense) bits from the gain cell's memory node.

[0050] Figure 17 shows a memory system 1000 having an array of 5T gain cells according to one embodiment of the present disclosure. As shown, the gain cell array includes a plurality of 5T gain cells arranged in a matrix, the 5T gain cells being adjacent to each other in the x and / or y directions. Each of the 5T gain cells may have a gain cell structure 200 or 300 as described herein. Although not explicitly shown, adjacent gain cells may share the same read word line (e.g., RWL1 or RWL2) and the same write word line (e.g., WWL1 or WWL2) extending across the gain cell along a first transverse direction, and adjacent gain cells may share the same read bit line (RBL1 or RBL2) and the same write bit line (WBL1 or WBL2) extending across the gain cell along a second transverse direction perpendicular to the first transverse direction. In a gain cell array, the gain cells can be addressed and controlled via bit line multiplexers (mux) and / or sense amplifiers for the bit lines (i.e., WBL, RBL). They can also be addressed and controlled via word line drivers and / or decoders for the word lines (i.e., WWL, RWL). The memory controller can provide input control signals and commands to the bit line mux and / or sense amplifiers and word line drivers and / or decoders to accurately select the gain cells for read / write operations.

[0051] This disclosure, though not limited to, provides advantages to gain cell circuits, particularly gain cell circuits having five transistors (5T). The gain cell circuit includes five transistors (5T) having two read transistors, two write transistors, and one feedback loop transistor. To maintain area and charge advantages, at least the feedback loop transistor is formed in the BEOL. Forming it in the BEOL makes it possible to fit the 5T circuit within a 4T occupied area, and also allows the feedback loop transistor to have a larger area, increasing the memory capacitance. In addition, since the BEOL transistor is not used for writing / reading, there is no performance loss due to variations in drive current and threshold voltage. In another embodiment, the 5T gain cell is composed of two FEOL transistors and three BEOL transistors. This allows for further miniaturization and achieves a reduction in occupied area. The two additional BEOL transistors may include write transistors having a large bandgap material to reduce leakage, and read transistors having a high-mobility material such as carbon nanotubes to achieve high speed.

[0052] One aspect of the present disclosure relates to a device. The device includes a first transistor and a second transistor coupled in series, a third transistor and a fourth transistor coupled in series, and a fifth transistor whose first terminal is coupled to the first terminal of the first transistor and the first terminal of the second transistor, respectively, and whose control terminal is coupled to the second terminal of the second transistor in a memory node. The control terminal of the fourth transistor is coupled to a memory node, and the device relates to a device in which at least one of the first to fifth transistors is located in a layer above the other one of the first to fifth transistors.

[0053] In one embodiment, the first and second transistors are arranged to write data to a storage node, the third and fourth transistors are arranged to read data from the storage node, and the fifth transistor is arranged to provide a feedback loop between the storage node and the first terminals of the first and second transistors.

[0054] In one embodiment, the fifth transistor is located above each of the first, second, third, and fourth transistors.

[0055] In one embodiment, the second, fourth, and fifth transistors are located above the first and third transistors, respectively. In a further embodiment, the fifth transistor occupies a larger area than the second and fourth transistors, respectively.

[0056] In one embodiment, each of the first, second, third, and fourth transistors includes a first active region, the fifth transistor includes a second active region, and the first and second active regions are made of different semiconductor materials. In a further embodiment, the first active region includes crystalline silicon or crystalline silicon germanium, and the second active region includes amorphous oxide, a two-dimensional material, or a carbon nanotube.

[0057] In one embodiment, the first and second transistors include n-type doped source / drain features, and the third and fourth transistors include p-type doped source / drain features.

[0058] Another aspect of the present disclosure relates to a device. The device includes a first write transistor and a second write transistor coupled in series, a first read transistor and a second read transistor coupled in series, and a feedback transistor whose first terminal is coupled to the first terminal of each of the first write transistor and the second write transistor, and whose control terminal is coupled to the second terminal of the second write transistor in a storage node, wherein the control terminal of the second read transistor is coupled to the storage node, and the feedback transistor is located in a layer above one of the first write transistors and the second write transistor or in a layer above one of the first read transistor and the second read transistor.

[0059] In one embodiment, the feedback transistor includes a back gate provided above the first readout transistor and the second readout transistor and the first write transistor and the second write transistor, a semiconductor layer on the back gate, and first source / drain (S / D) electrodes and second S / D electrodes at opposite ends of the semiconductor layer, wherein the back gate is electrically connected to the control terminals of the feedback transistor.

[0060] In further embodiments, the semiconductor layer of the feedback transistor comprises an amorphous oxide or a two-dimensional material.

[0061] In a further embodiment, each of the first read-out transistor and the second read-out transistor and the first write-out transistor and the second write-out transistor includes a channel region, a source / drain epitaxial feature region adjacent to the channel region, and a metal gate stack located above the channel region and interfacially in contact with the channel region, wherein the back gate occupies a larger area than each of the metal gate stacks.

[0062] In a further embodiment, the device further includes a first metal wire having a read word line located above the control terminal of a first read transistor and electrically connected to the control terminal of the first read transistor, and a write word line located above the control terminals of a first write transistor and a second write transistor and electrically connected to the control terminals of the first write transistor and the second write transistor. In a further embodiment, the device further includes a second metal wire located above the first metal wire and extending perpendicularly to the first metal wire, having a read bit line located above the first terminal of the first read transistor and electrically connected to the first terminal of the first read transistor, and a write bit line located above the second terminal of the first write transistor and electrically connected to the second terminal of the first write transistor. In a further embodiment, the device further includes a third metal wire located above the second metal wire and including a back gate. In a further embodiment, the device further includes a fourth metal wire located above the third metal wire and including a first source / drain (S / D) electrode and a second S / D electrode.

[0063] Another aspect of the present disclosure relates to a structure. The structure includes an array of memory gain cells having first transistors formed on a semiconductor substrate; a first layer above the first transistors having write word lines and read word lines electrically connected to one or more other source / drain feature portions of the first transistors; and a second layer above the first layer having write bit lines and read bit lines electrically connected to one or more source / drain feature portions of the first transistors, wherein each memory gain cell includes five transistors, including at least two first transistors; a second transistor formed above the second layer and having a gate structure covering an area equal to or larger than the area of ​​one or more first transistors; a semiconductor layer above the gate structure; and first source / drain (S / D) electrodes and second S / D electrodes at opposite ends of the semiconductor layer, wherein the gate structure of the second transistor is electrically connected to a storage node, and the storage node is electrically connected to the source / drain feature portions of the write transistors and the gate structures of the read transistors.

[0064] In one embodiment, the five transistors include four first transistors, and the second transistors are formed above the four first transistors.

[0065] In one embodiment, the five transistors include two first transistors, two second transistors formed above the two first transistors, and two third transistors formed above the second transistors.

[0066] In one embodiment, the five transistors include two first transistors, two third transistors formed above the two first transistors, and two second transistors formed above the two third transistors.

[0067] The above outlines the features of several embodiments so that those skilled in the art may better understand each aspect of the present disclosure. Those skilled in the art should understand that the present disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same objectives and / or advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent configurations do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions and modifications can be made herein without departing from the spirit and scope of the present disclosure. [Explanation of Symbols]

[0068] 102: Circuit board 104: Isolation structure 106: Active area 107: Channel area 108: S / D Features 110: Gate Stack 112: Beer to M1 114: M1 metal wire 116: Beer to M2 118:M2 metal wire 120: Via to M3 122:M3 metal wire 124: Via to M4 126:M4 metal wire 130:M5 metal wire 132: Beer to M6 134:M6 metal wire 200: Gain cell structure 207: Semiconductor layer 208:S / D electrode 210: Gate 210a: Back gate 210b: Top Gate 300: Gain cell structure 307: Semiconductor layer 308:S / D electrode 310: BEOL Gate 402: Blocked 404: Blocked 406: Block 408: Block 410: Block 412: Block 500: Wiring structure 502: Dielectric Features 504: Metallic Features 507: Semiconductor layer 508:S / D electrode 510: Gate 1000: Memory System L1:M2 local wiring L2:M2 local wiring L3: M3 local wiring RBL: Read bit line RBL1: Read bit line RBL2: Read bit line RWL: Word line RWL1: Read bit line RWL2: Read bit line SN: Memory Node TN1: Transistor TN2: Transistor TN3: Transistor TP1: Transistor TP2: Transistor TP3: Transistor VDD: Signal line WBL: Write bitline WBL1: Write bit line WBL2: Write bit line WWL: Word Line WWL1: Writing Word Line WWL2: Write word line x: direction x1: Distance between gates y: direction y1: Distance between M1

Claims

1. A first transistor and a second transistor are coupled in series, A third transistor and a fourth transistor are coupled in series, A fifth transistor whose first terminal is connected to the first terminal of the first transistor and the first terminal of the second transistor, and whose control terminal is connected to the second terminal of the second transistor in the memory node, Includes, The control terminal of the fourth transistor is coupled to the memory node, and at least one of the first to fifth transistors is located in a layer above the other one of the first to fifth transistors.

2. The device according to claim 1, wherein the first transistor and the second transistor are arranged to write data to the storage node, the third transistor and the fourth transistor are arranged to read the data from the storage node, and the fifth transistor is arranged to provide a feedback loop between the storage node and the first terminals of the first transistor and the second transistor.

3. The device according to claim 1, wherein each of the first transistor, the second transistor, the third transistor, and the fourth transistor includes a first active region, the fifth transistor includes a second active region, and the first active region and the second active region are made of different semiconductor materials.

4. The device according to claim 3, wherein the first active region comprises crystalline silicon or crystalline silicon germanium, and the second active region comprises amorphous oxide, a two-dimensional material, or a carbon nanotube.

5. A first writing transistor and a second writing transistor are connected in series, A first readout transistor and a second readout transistor are coupled in series, A feedback transistor whose first terminal is connected to the first terminal of the first writing transistor and the first terminal of the second writing transistor, and whose control terminal is connected to the second terminal of the second writing transistor in the memory node, Includes, The control terminal of the second readout transistor is connected to the memory node. The feedback transistor is a device located in a layer above one of the first write transistors and the second write transistor, or in a layer above one of the first read transistors and the second read transistor.

6. The aforementioned feedback transistor is A back gate provided above the first read transistor and the second read transistor, the first write transistor and the second write transistor, The semiconductor layer on the back gate, The semiconductor layer comprises a first source / drain (S / D) electrode and a second S / D electrode located at opposite ends, Includes, The device according to claim 5, wherein the back gate is electrically connected to the control terminal of the feedback transistor.

7. Each of the first read transistor and the second read transistor, the first write transistor and the second write transistor, Channel region and, The source / drain epitaxial feature region adjacent to the channel region, A metal gate stack located above the channel region and in interfacial contact with the channel region, Includes, The device according to claim 6, wherein the back gate occupies a larger area than each of the metal gate stacks.

8. The device described above, The device according to claim 6, further comprising a first metal wire having a read word line located above the control terminal of the first read transistor and electrically connected to the control terminal of the first read transistor, and a write word line located above the control terminals of the first write transistor and the second write transistor and electrically connected to the control terminals of the first write transistor and the second write transistor.

9. The device described above, The device according to claim 8, further comprising a read bit line located above the first terminal of the first read transistor and electrically connected to the first terminal of the first read transistor, and a write bit line located above the second terminal of the first write transistor and electrically connected to the second terminal of the first write transistor, the second metal wire located above the first metal wire and extending perpendicularly to the first metal wire.

10. An array of memory gain cells having a first transistor formed on a semiconductor substrate, A first layer located above the first transistor and having write word lines and read word lines electrically connected to one or more source / drain feature portions of the first transistor, Located above the first layer, and one or more other than the first transistor A second layer having write bit lines and read bit lines electrically connected to the source / drain feature section, Includes, Each of the memory gain cells includes five transistors, each comprising at least two of the first transistors, a second transistor formed above the second layer and having a gate structure covering an area equal to or larger than the area of ​​one or more of the first transistors, a semiconductor layer above the gate structure, and first source / drain (S / D) electrodes and second S / D electrodes at opposite ends of the semiconductor layer. The gate structure of the second transistor is electrically connected to a memory node, and the memory node is electrically connected to the source / drain feature section of the write transistor and the gate structure of the read transistor.

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