IGBT

Abstract

To provide an IGBT capable of improving the blocking capacity. [Solution] The IGBT comprises a collector electrode, a semiconductor portion disposed on the collector electrode, a plurality of emitter electrodes disposed on a part of the semiconductor portion and spaced apart from each other in a first direction, gate wiring disposed between the emitter electrodes in the first direction, a gate electrode connected to the gate wiring and insulated from the semiconductor portion, having two first portions arranged in a second direction intersecting the first direction and extending in the first direction, and a second portion connecting the ends of the two first portions, and an emitter contact whose upper end is connected to the emitter electrode and whose lower end is connected to the portion of the semiconductor portion between the area directly below the gate wiring and the second portion.

Description

Technical Field

[0001] The embodiment relates to an IGBT.

Background Art

[0002] As a type of semiconductor device for power control, an IGBT (insulated gate bipolar transistor) has been developed. In an IGBT, improvement of the blocking capability, which is a kind of breakdown resistance during turn-off, is desired.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] An embodiment aims to provide an IGBT capable of improving the blocking capability.

Means for Solving the Problems

[0005] The IGBT according to the embodiment includes a collector electrode, a semiconductor portion disposed on the collector electrode, a plurality of emitter electrodes disposed on a part of the semiconductor portion and spaced apart from each other in a first direction, a gate wiring disposed between the emitter electrodes in the first direction, two first portions arranged in a second direction intersecting the first direction and extending in the first direction, and a second portion connecting the tips of the two first portions. The IGBT further includes a gate electrode connected to the gate wiring and insulated from the semiconductor portion, and an emitter contact having an upper end connected to the emitter electrode and a lower end connected to a portion between a region directly below the gate wiring in the semiconductor portion and the second portion.

Brief Description of the Drawings

[0006] [Figure 1] Figure 1 is a top view showing an IGBT according to the first embodiment. [Figure 2] Figure 2 is a partially enlarged top view showing area A in Figure 1. [Figure 3] Figure 3 is a cross-sectional view taken along the line B-B' in Figure 2. [Figure 4] Figure 4 is a cross-sectional view taken along the line C-C' in Figure 2. [Figure 5] Figure 5 is a cross-sectional view showing the operation of an IGBT according to the first embodiment. [Figure 6] Figure 6 is a plan view showing an IGBT related to a comparative example. [Figure 7] Figure 7 is a plan view showing an IGBT according to the second embodiment. [Figure 8] Figure 8 is a plan view showing an IGBT according to the third embodiment. [Modes for carrying out the invention]

[0007] <First Embodiment> Figure 1 is a top view showing an IGBT according to this embodiment. Figure 2 is a partially enlarged top view showing area A in Figure 1. Figure 3 is a cross-sectional view taken along the line B-B' in Figure 2. Figure 4 is a cross-sectional view taken along the line C-C' in Figure 2. Note that each figure is schematic and has been emphasized or simplified as appropriate. For example, the insulating portion is omitted in Figure 2. The same applies to the other figures described later.

[0008] As shown in Figures 1 to 4, the IGBT1 according to this embodiment is provided with a collector electrode 10, a semiconductor portion 20, an insulating film 30, a plurality of emitter electrodes 40, and gate wiring 50. The collector electrode 10 is arranged on one surface of the semiconductor portion 20, and the emitter electrodes 40 and gate wiring 50 are arranged on the other surface of the semiconductor portion 20.

[0009] The collector electrode 10 is positioned across the entire lower surface of the semiconductor portion 20 and is in contact with the semiconductor portion 20. The insulating film 30 is positioned across the entire upper surface of the semiconductor portion 20. Multiple emitter electrodes 40 are positioned spaced apart from each other on a portion of the insulating film 30. The gate wiring 50 is positioned in a portion of the insulating film 30 where the emitter electrodes 40 are not located.

[0010] As shown in Figure 1, the emitter electrode 40 is located in the cell region of the IGBT 1, excluding the terminal region, and is arranged, for example, along one direction. Hereafter, for convenience of explanation, the XYZ Cartesian coordinate system will be adopted in this specification. The direction from the collector electrode 10 toward the emitter electrode 40 will be called the "Z direction," the direction in which the multiple emitter electrodes 40 are arranged will be called the "X direction," and the direction perpendicular to the Z direction and the X direction will be called the "Y direction." The Z direction will also be called "up," and the opposite direction will be called "down," but this expression is for convenience only and is unrelated to the direction of gravity.

[0011] Viewed from the Z direction, each emitter electrode 40 has the shape of a rectangle whose length in the Y direction is longer than its length in the X direction. Viewed from the Z direction, the gate wiring 50 has the shape of, for example, a ladder shape surrounding each emitter electrode 40. The emitter electrodes 40 may be arranged in a matrix along both the X and Y directions. In this case, viewed from the Z direction, the gate wiring 50 may have the shape of a grid surrounding each emitter electrode 40. Gate pads 51 are provided in the gate wiring 50 at the corners of the cell region.

[0012] As shown in FIG. 2, in the cell region of the IGBT1, the region directly below the central portion of the emitter electrode 40 in the X direction is defined as the "current-carrying region R1". In the current-carrying region R1, current can flow from the collector electrode 10 through the semiconductor portion 20 to the emitter electrode 40. Also, in the cell region, the region directly below the gate wiring 50 and the region directly below the vicinity of the gate wiring 50 in the emitter electrode 40 are defined as the "gate connection region R2". In the gate connection region R2, a gate electrode 52 described later is connected to the gate wiring 50. Note that in this specification, "connection" means electrical connection. In the cell region, the current-carrying region R1 and the gate connection region R2 are alternately arranged along the X direction.

[0013] The gate electrode 52 is arranged across the current-carrying region R1 and the gate connection region R2. When viewed from the Z direction, the shape of the gate electrode 52 is loop-shaped. That is, in the gate electrode 52, two first portions 52a mainly arranged in the current-carrying region R1 and extending in the X direction, and a second portion 52b arranged in the gate connection region R2, extending in the Y direction, and connecting the tips of the two first portions 52a on the gate connection region R2 side are provided.

[0014] As shown in FIGS. 2 and 3, in the current-carrying region R1, a trench electrode 41, a trench insulating film 42, the first portion 52a of the gate electrode 52, and a gate insulating film 53 are provided in the semiconductor portion 20. Also, emitter plugs 43 and 44 are provided in the insulating film 30. The gate insulating film 53 is arranged around the gate electrode 52, insulating the gate electrode 52 from the semiconductor portion 20. The emitter electrode 40 is connected to the trench electrode 41 through the emitter plug 43. Also, the emitter electrode 40 is connected to the semiconductor portion 20 through the emitter plug 44.

[0015] A plurality of trench electrodes 41 are provided and arranged along the Y direction. Each trench electrode 41 extends in the X direction. A trench insulating film 42 is disposed around the trench electrode 41 to insulate the trench electrode 41 from the semiconductor portion 20. The first portion 52a of the gate electrode 52 is arranged so as to interrupt the arrangement of the trench electrodes 41.

[0016] A plurality of trench electrodes 41 are respectively arranged inside the loop of the gate electrode 52 and between two adjacent gate electrodes 52 in the Y direction. In the example shown in FIG. 2, two trench electrodes 41 are arranged inside the loop of the gate electrode 52, and two trench electrodes 41 are arranged between two gate electrodes 52, but the present invention is not limited thereto. Three or more trench electrodes 41 may be arranged inside the loop of the gate electrode 52 and between the gate electrodes 52, or no trench electrode 41 may be arranged inside the loop of the gate electrode 52 or between the gate electrodes 52.

[0017] As shown in FIGS. 2 and 4, in the gate connection region R2, the second portion 52b of the gate electrode 52 and the gate insulating film 53 are arranged in the semiconductor portion 20. Further, an internal gate wiring 55, a gate plug 56, and an emitter contact 60 are provided in the insulating film 30. The gate wiring 50 is connected to the internal gate wiring 55 via the gate plug 56. The internal gate wiring 55 is connected to the second portion 52b of the gate electrode 52.

[0018] An opening 55a is formed in the internal gate wiring 55. The emitter contact 60 penetrates the opening 55a of the internal gate wiring 55 in the Z direction. The upper end of the emitter contact 60 is connected to the emitter electrode 40, and the lower end of the emitter contact 60 is connected to the semiconductor portion 20.

[0019] As shown in Figure 2, in this embodiment, in the gate connection region R2, a plurality of emitter contacts 60 are arranged, for example, at equal intervals along the Y direction. The shape of each emitter contact 60 is substantially cylindrical with its central axis extending in the Z direction. The emitter contacts 60 are positioned between two gate electrodes 52 located directly below two emitter electrodes 40 that are spaced apart in the X direction.

[0020] Some emitter contacts 60 are connected to the area between the region directly below the gate wiring 50 in the semiconductor portion 20 and the second portion 52b of the gate electrode 52. Other emitter contacts 60 are connected to the area between the trench electrode 41, which is located between the gate electrode 52s in the semiconductor portion 20, and the region directly below the gate wiring 50.

[0021] As shown in Figures 3 and 4, in the semiconductor portion 20, the conductivity type is p + A collector layer 21 of type n, a drift layer 22 of type n, and a p-type collector layer + The base layer 23 has a specific shape, and the conductive type is n + An emitter layer 24 of a certain type is provided. The drift layer 22 has a first layer 22a of the conductivity type n and a first layer 22a of the conductivity type n - A second layer 22b of the shape is provided.

[0022] Note that "n + The notation "shape" indicates a higher carrier concentration than the notation "n shape," and "n - The notation "shape" indicates a lower carrier concentration than the notation "n-shape". + ``shaped'', ``n-shaped'', ``n - The term "type" is also collectively referred to as "n-type." The same applies to p-type. "Carrier concentration" refers to the concentration of impurities that contribute to the conductivity of a semiconductor. If a certain part contains both acceptor and donor impurities, it refers to the effective concentration after removing the canceling-out components.

[0023] The collector layer 21 is in contact with the collector electrode 10 and is connected to the collector electrode 10. The first layer 22a of the drift layer 22 is located on the collector layer 21 and is in contact with the collector layer 21. The second layer 22b of the drift layer 22 is located on the first layer 22a. The base layer 23 is located on the drift layer 22 and is in contact with the drift layer 22. The emitter layer 24 is located on a portion of the base layer 23 in the current-carrying region R1. The emitter layer 24 is in contact with the gate insulating film 53 and faces the first portion 52a of the gate electrode 52 via the gate insulating film 53. The trench electrode 41 and trench insulating film 42, the gate electrode 52 and gate insulating film 53 are located within the base layer 23.

[0024] In the energized region R1, the emitter plug 44 is connected to the base layer 23 and the emitter layer 24. In other words, in the energized region R1, the base layer 23 and the emitter layer 24 are connected to the emitter electrode 40 via the emitter plug 44. In the gate connection region R2, the emitter contact 60 is connected to the base layer 23. In other words, in the gate connection region R2, the base layer 23 is connected to the emitter electrode 40 via the emitter contact 60. The gate electrode 52 is connected to the gate wiring 50 in the gate connection region R2 via the internal gate wiring 55 and the gate plug 56.

[0025] Next, we will explain examples of materials used for each part. The semiconductor portion 20 includes, for example, single-crystal silicon, as described above. The insulating film 30 includes, for example, silicon oxide (SiO2). The internal gate wiring 55 includes, for example, polysilicon. The collector electrode 10, emitter electrode 40, and gate wiring 50 include, for example, one or more materials selected from the group consisting of aluminum (Al), aluminum-copper alloy (AlCu), aluminum silicide (AlSi), titanium (Ti), and titanium nitride (TiN). The emitter contact 60, emitter plug 43, emitter plug 44, and gate plug 56 include, for example, one or more materials selected from the group consisting of titanium (Ti), titanium nitride (TiN), and tungsten (W).

[0026] Next, the operation of the IGBT1 according to this embodiment will be described. Figure 5 is a cross-sectional view showing the operation of the IGBT according to this embodiment. Figure 5 shows the same cross-section as Figure 4.

[0027] As shown in Figure 5, when IGBT1 is turned off, hole carriers h enter the semiconductor portion 20. The hole carriers h that entered the energized region R1 move to the emitter electrode 40 via the emitter plug 44 and are discharged to the outside of IGBT1. The hole carriers h that entered the gate connection region R2 move to the emitter electrode 40 via the emitter contact 60 and are discharged to the outside of IGBT1.

[0028] Next, the effects of this embodiment will be described. In this embodiment, an emitter contact 60 is provided outside the loop-shaped gate electrode 52 and gate insulating film 53 in the gate connection region R2. As a result, holes h in the gate connection region R2 are discharged to the emitter electrode 40 via the emitter contact 60. This makes it less likely for current to concentrate during turn-off, and the IGBT1 is less likely to be damaged. Therefore, the IGBT1 according to this embodiment has a high break-off withstand capability.

[0029] Furthermore, in the IGBT1 according to this embodiment, the gate electrode 52 is formed in a loop shape. As a result, the gate breakdown voltage is higher compared to the case where the gate electrode 52 is formed in a linear shape. Specifically, it has been experimentally confirmed that when the gate electrode 52 is provided with a second portion 52b, the rate of gate breakdown voltage failure may be reduced compared to the case where the gate electrode 52 is composed only of the first portion 52a without the second portion 52b.

[0030] <Comparative Example> Figure 6 is a plan view showing an IGBT related to a comparative example. As shown in Figure 6, the IGBT101 in this comparative example does not have an emitter contact 60. Therefore, when the IGBT101 is turned off, the holes h that have entered the gate connection region R2 need to move to the energized region R1 and then be discharged to the emitter electrode 40 via the emitter plug 44.

[0031] However, some of the holes h that enter the gate connection region R2 are prevented from moving by the loop-shaped gate electrode 52 and gate insulating film 53, thus increasing the distance they travel to the emitter plug 44. As a result, the discharge of holes h is suppressed. Consequently, current concentrates in the portion of the gate connection region R2 where holes h remain, making it highly likely that the IGBT 101 will be destroyed.

[0032] <Second Embodiment> Figure 7 is a plan view showing the IGBT according to this embodiment. As shown in Figure 7, the IGBT2 according to this embodiment has a different arrangement of emitter contacts 60 compared to the first embodiment. In the IGBT2, when viewed from the Z direction, the emitter contacts 60 are not located between the gate electrodes 52 and the gate wiring 50 in the semiconductor portion 20, but are located only between the gate electrodes 52 and the gate wiring 50 in the semiconductor portion 20. That is, in this embodiment, the lower end of the emitter contacts 60 is connected only to the area directly below the gate wiring 50 in the semiconductor portion 20 and the second portion 52b of the gate electrode 52.

[0033] According to this embodiment, holes h located between the area directly below the gate wiring 50 and the gate electrode 52 in the semiconductor portion 20 are easily discharged via the emitter contact 60. Also, holes h located between the area directly below the gate wiring 50 and the portion between the gate electrode 52 in the Y direction in the semiconductor portion 20 are easily discharged via the emitter plug 44. This also provides the same effects as in the first embodiment. The configuration, operation, and effects of this embodiment other than those described above are the same as in the first embodiment.

[0034] <Third Embodiment> Figure 8 is a plan view showing an IGBT according to this embodiment. As shown in Figure 8, the IGBT3 according to this embodiment has a different shape for the emitter contact 61 compared to the first embodiment.

[0035] As shown in Figure 8, the IGBT3 is provided with an emitter contact 61. The emitter contact 61 is plate-shaped, with a length in the Y direction greater than its length in the X direction. The upper end of the emitter contact 61 is connected to the emitter electrode 40, and the lower end of the emitter contact 61 is connected to the area between the area directly below the gate wiring 50 in the semiconductor portion 20 and the second portion 52b of the gate electrode 52. The configuration, operation, and effects in this embodiment other than those described above are the same as in the first embodiment.

[0036] According to the embodiments described above, it is possible to realize an IGBT with improved interruption resistance.

[0037] Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. Furthermore, the embodiments described above can be implemented in combination with each other.

[0038] For example, in each of the embodiments described above, the p-type and n-type configurations may be reversed to form a p-channel IGBT. In this case, the emitter contact functions as a contact for emitting electrons.

[0039] The present invention includes the following embodiments.

[0040] (Note 1) Collector electrode and A semiconductor portion disposed on the collector electrode, A plurality of emitter electrodes are arranged on a part of the semiconductor portion and are separated from each other in a first direction, A gate wiring arranged between the emitter electrodes in the first direction, A gate electrode is arranged in a second direction intersecting the first direction, having two first parts extending in the first direction and a second part connecting the ends of the two first parts, connected to the gate wiring, and insulated from the semiconductor portion, An emitter contact whose upper end is connected to the emitter electrode and whose lower end is connected to the area between the area directly below the gate wiring in the semiconductor portion and the second portion, Equipped with IGBT.

[0041] (Note 2) Viewed from above, the emitter contact is located between the gate electrode and the gate wiring in the IGBT described in Appendix 1.

[0042] (Note 3) Multiple gate electrodes are provided along the second direction, Viewed from above, the emitter contact is also located between the portion of the semiconductor portion between the gate electrodes and the gate wiring, as described in Appendix 2 of the IGBT.

[0043] (Note 4) The IGBT according to any one of appendices 1 to 3, wherein multiple emitter contacts are provided and arranged along the second direction.

[0044] (Note 5) The IGBT according to any one of the appendices 1 to 3, wherein the length of the emitter contact in the second direction is longer than the length of the emitter contact in the first direction.

[0045] (Note 6) Multiple gate electrodes are provided along the second direction, A first trench electrode is disposed within the semiconductor portion between the gate electrodes in the second direction and connected to the emitter electrode, A first plug, the upper end of which is connected to the emitter electrode and the lower end of which is connected to the portion between the gate electrode and the first trench electrode in the semiconductor portion, An IGBT as described in any one of the appendices 1 to 5, further comprising the above.

[0046] (Note 7) A second trench electrode is positioned between the two first portions belonging to one of the gate electrodes within the semiconductor portion and connected to the emitter electrode, A second plug, the upper end of which is connected to the emitter electrode and the lower end of which is connected to the portion between the gate electrode and the second trench electrode in the semiconductor portion, An IGBT as described in Appendix 6, further comprising the above.

[0047] (Note 8) The aforementioned semiconductor portion is A p-type first semiconductor layer connected to the collector electrode, An n-type second semiconductor layer disposed on the first semiconductor layer, A p-type third semiconductor layer is disposed on the second semiconductor layer and connected to the emitter contact, An n-type fourth semiconductor layer is disposed on a portion of the third semiconductor layer, facing the first portion via a gate insulating film, and connected to the emitter electrode, An IGBT having any one of the appendices 1 to 7. [Explanation of symbols]

[0048] 1, 2, 3 IGBT 10 Collector electrodes 20 Semiconductor part 21. Collector layer (first semiconductor layer) 22. Drift layer (second semiconductor layer) 22a 1st layer 22b 2nd layer 23 Base layer (third semiconductor layer) 24. Emitter layer (fourth semiconductor layer) 30 insulating film 40 Emitter Electrode 41 Trench electrodes 42 Trench Insulator 43, 44 Emitter Plug 50 gate wiring 51 Gate Pad 52 Grid gate 52a Part 1 52b Part 2 53 Gate insulating film 55 Internal gate wiring 55a opening 56 Gate Plug 60 Emitter Contacts 61 Emitter Contact 101 IGBT R1 Current carrying area R2 Gate Connection Region h hole

Claims

1. Collector electrode and A semiconductor portion disposed on the collector electrode, A plurality of emitter electrodes are arranged on a part of the semiconductor portion and are separated from each other in a first direction, A gate wiring arranged between the emitter electrodes in the first direction, A gate electrode is arranged in a second direction intersecting the first direction, having two first parts extending in the first direction and a second part connecting the ends of the two first parts, connected to the gate wiring, and insulated from the semiconductor portion, An emitter contact whose upper end is connected to the emitter electrode and whose lower end is connected to the area between the area directly below the gate wiring in the semiconductor portion and the second portion, IGBT equipped with [a specific feature].

2. The IGBT according to claim 1, wherein, when viewed from above, the emitter contact is positioned between the gate electrode and the gate wiring.

3. Multiple gate electrodes are provided along the second direction, The IGBT according to claim 2, wherein, when viewed from above, the emitter contact is also located between the portion of the semiconductor portion between the gate electrodes and the gate wiring.

4. The IGBT according to claim 1, wherein a plurality of emitter contacts are provided and are arranged along the second direction.

5. The IGBT according to claim 1, wherein the length of the emitter contact in the second direction is longer than the length of the emitter contact in the first direction.

6. Multiple gate electrodes are provided along the second direction, A first trench electrode is disposed within the semiconductor portion between the gate electrodes in the second direction and connected to the emitter electrode, A first plug, the upper end of which is connected to the emitter electrode and the lower end of which is connected to the portion between the gate electrode and the first trench electrode in the semiconductor portion, The IGBT according to claim 1, further comprising the features described above.

7. A second trench electrode is positioned between the two first portions belonging to one of the gate electrodes within the semiconductor portion and connected to the emitter electrode, A second plug, the upper end of which is connected to the emitter electrode and the lower end of which is connected to the portion between the gate electrode and the second trench electrode in the semiconductor portion, The IGBT according to claim 6, further comprising the above.

8. The aforementioned semiconductor portion is A p-type first semiconductor layer connected to the collector electrode, An n-type second semiconductor layer disposed on the first semiconductor layer, A p-type third semiconductor layer is disposed on the second semiconductor layer and connected to the emitter contact, An n-type fourth semiconductor layer is disposed on a portion of the third semiconductor layer, facing the first portion via a gate insulating film, and connected to the emitter electrode, An IGBT according to any one of claims 1 to 7, having the following characteristics.

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