Semiconductor equipment

Abstract

To provide a semiconductor device capable of suppressing the growth of stacking faults. [Solution] The semiconductor device of the embodiment comprises an element region and a termination region surrounding the element region. The element region includes a silicon carbide region of a first conductivity type, a silicon carbide layer having a plurality of silicon carbide regions of a second conductivity type, and a gate electrode. The termination region includes a silicon carbide layer having a silicon carbide region of a first conductivity type, a first silicon carbide region of a second conductivity type outside the plurality of silicon carbide regions of the second conductivity type, and a second silicon carbide region of a second conductivity type separated from the first silicon carbide region and surrounding the first silicon carbide region. In the termination region, one contact portion of the wiring layer is connected to the first silicon carbide region, and another contact portion of the wiring layer is connected to the second silicon carbide region. The concentration of second conductivity type impurities in the portion where one contact portion is connected to the first silicon carbide region is lower than the concentration of second conductivity type impurities in the portion where the other contact portion is connected to the second silicon carbide region.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices.

Background Art

[0002] A vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor) using silicon carbide has a pn junction diode as a built-in diode. For example, the MOSFET is used as a switching element connected to an inductive load. In this case, even when the MOSFET is in an off state, it is possible to flow a reflux current by using the pn junction diode.

[0003] However, when a reflux current is flowed using a pn junction diode that operates in bipolar mode, stacking defects grow in the silicon carbide layer due to the recombination energy of carriers. When stacking defects grow in the silicon carbide layer, there arises a problem that the on-resistance of the MOSFET increases. The increase in the on-resistance of the MOSFET leads to a decrease in the reliability of the MOSFET. For example, by providing a Schottky Barrier Diode (SBD) that operates in unipolar mode as a built-in diode in the MOSFET, it becomes possible to suppress the growth of stacking defects in the silicon carbide layer. [[ID=I8]]

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] The problem to be solved by the present invention is to provide a semiconductor device capable of suppressing the growth of stacking defects.

Means for Solving the Problems

[0006] The semiconductor device of the embodiment comprises an element region and a termination region surrounding the element region, the element region comprising a first electrode, a second electrode, a gate electrode, and a silicon carbide layer provided between the first electrode and the second electrode, having a first surface on the side of the first electrode and a second surface on the side of the second electrode, the first silicon carbide region having a first conductivity type having a first portion in contact with the first surface and facing the gate electrode, and a second portion in contact with the first surface and in contact with the first electrode, and a second conductivity type provided between the first silicon carbide region and the first surface A second silicon carbide region, a third silicon carbide region of second conductivity type provided between the first silicon carbide region and the first surface, provided on the terminal side of the second silicon carbide region and electrically connected to the first electrode, a fourth silicon carbide region of second conductivity type provided between the first silicon carbide region and the first surface, provided between the second silicon carbide region and the third silicon carbide region, facing the gate electrode and electrically connected to the first electrode, and provided between the first silicon carbide region and the first surface, and the second silicon carbide region and the front A fifth silicon carbide region of second conductivity type is provided between the fourth silicon carbide region, facing the gate electrode, and electrically connected to the first electrode; a sixth silicon carbide region of second conductivity type is provided between the first silicon carbide region and the first surface, provided between the third silicon carbide region and the fourth silicon carbide region, in contact with the third and fourth silicon carbide regions, and shallower in depth than the depth of the third and fourth silicon carbide regions; and a sixth silicon carbide region of second conductivity type is provided between the fifth silicon carbide region and the first surface, and electrically connected to the first electrode. A silicon carbide layer comprising a seventh silicon carbide region of a first conductivity type that is precisely connected, an eighth silicon carbide region of a second conductivity type having a higher concentration of second conductivity type impurities than the sixth silicon carbide region, provided between the sixth silicon carbide region and the first surface, a first silicide layer provided between the eighth silicon carbide region and the first electrode, and a gate insulating layer provided between the gate electrode and the fifth silicon carbide region, and between the gate electrode and the first portion, wherein the termination region comprises a wiring layer electrically connected to the first electrode, and the second electrode,A first silicon carbide region having a third portion that contacts the first surface and the wiring layer; a ninth silicon carbide region of a second conductivity type provided between the first silicon carbide region and the first surface, surrounding the element region and in contact with the third silicon carbide region; a tenth silicon carbide region of a second conductivity type provided between the first silicon carbide region and the first surface, surrounding the ninth silicon carbide region, separated from the ninth silicon carbide region, and electrically connected to the wiring layer; and an eleventh silicon carbide region of a second conductivity type provided between the tenth silicon carbide region and the first surface, having a higher concentration of second conductivity type impurities than the ninth silicon carbide region and the tenth silicon carbide region. A semiconductor device comprising: a silicon carbide layer including; a second silicide layer provided between the 11th silicon carbide region and the wiring layer; the first electrode comprising a first contact portion in contact with the second portion and a second contact portion in contact with the first silicide layer; the wiring layer comprising a third contact portion in contact with the third portion and a fourth contact portion in contact with the second silicide layer; the termination region further comprising a third silicide layer provided between the 9th silicon carbide region and the first surface and in contact with the 9th silicon carbide region; and the wiring layer further comprising a fifth contact portion in contact with the third silicide layer. [Brief explanation of the drawing]

[0007] [Figure 1] A schematic top view of the semiconductor device according to the first embodiment. [Figure 2] A schematic top view of the semiconductor device according to the first embodiment. [Figure 3] A schematic cross-sectional view of the semiconductor device according to the first embodiment. [Figure 4] Equivalent circuit diagram of the semiconductor device of the first embodiment. [Figure 5] Schematic cross-sectional view of a comparative semiconductor device. [Figure 6] Diagram illustrating the problems of the semiconductor device in the comparative example. [Figure 7] A diagram illustrating the operation and effects of the semiconductor device according to the first embodiment. [Figure 8]Explanatory drawing of the operation and effects of the semiconductor device of the first embodiment. [Figure 9] Schematic cross-sectional view of the semiconductor device of the second embodiment. [Figure 10] Schematic cross-sectional view of the semiconductor device of a modified example of the second embodiment. [Figure 11] Schematic cross-sectional view of the semiconductor device of the third embodiment. [Figure 12] Schematic cross-sectional view of the semiconductor device of the fourth embodiment. [Figure 13] Schematic cross-sectional view of the semiconductor device of the fifth embodiment.

Modes for Carrying Out the Invention

[0008] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same or similar members are denoted by the same reference numerals, and the description of the members once described may be omitted as appropriate.

[0009] Also, in the following description, when there are notations of n + , n, n - and, p + , p, p - , these notations represent the relative levels of the impurity concentrations in each conductivity type. That is, n + indicates that the n-type impurity concentration is relatively higher than that of n, and n - indicates that the n-type impurity concentration is relatively lower than that of n. Also, p + indicates that the p-type impurity concentration is relatively higher than that of p, and p - indicates that the p-type impurity concentration is relatively lower than that of p. Note that the n + type and n - type may be simply referred to as the n-type, and the p + type and p - type may be simply referred to as the p-type.

[0010] Unless otherwise specified in this specification, "impurity concentration" means the concentration after compensating for the concentration of the opposite conductive type of impurity. That is, the n-type impurity concentration in the n-type silicon carbide region means the concentration obtained by subtracting the concentration of p-type impurities from the concentration of n-type impurities. Similarly, the p-type impurity concentration in the p-type silicon carbide region means the concentration obtained by subtracting the concentration of n-type impurities from the concentration of p-type impurities. Unless otherwise specified in this specification, "impurity concentration in the silicon carbide region" refers to the maximum impurity concentration in the corresponding silicon carbide region.

[0011] Impurity concentrations can be measured, for example, by Secondary Ion Mass Spectrometry (SIMS). The relative levels of impurity concentrations can also be determined, for example, from the carrier concentrations obtained by Scanning Capacitance Microscopy (SCM). Furthermore, distances such as depth and thickness of impurity regions can be determined, for example, by SIMS or Scanning Electron Microscope (SEM). Additionally, distances such as depth, thickness, width, and spacing of impurity regions can be determined, for example, from a composite image of SCM and Atomic Force Microscope (AFM) images.

[0012] (First embodiment) The semiconductor device of the first embodiment comprises an element region and a termination region surrounding the element region. The element region comprises a first electrode, a second electrode, a gate electrode, a silicon carbide layer provided between the first electrode and the second electrode, having a first surface on the side of the first electrode and a second surface on the side of the second electrode, having a first silicon carbide region of a first conductivity type having a first portion in contact with the first surface and facing the gate electrode, and a second portion in contact with the first surface and in contact with the first electrode, a second silicon carbide region of a second conductivity type provided between the first silicon carbide region and the first surface, and the first silicon carbide layer A third silicon carbide region of second conductivity type is provided between the silicon carbide region and the first surface, located on the terminal side of the second silicon carbide region, and electrically connected to the first electrode; a fourth silicon carbide region of second conductivity type is provided between the first silicon carbide region and the first surface, located between the second silicon carbide region and the third silicon carbide region, facing the gate electrode, and electrically connected to the first electrode; and a fourth silicon carbide region of second conductivity type is provided between the first silicon carbide region and the first surface, located between the second silicon carbide region and the fourth A fifth silicon carbide region of second conductivity type is provided between the silicon carbide region and the first surface, facing the gate electrode and electrically connected to the first electrode; a sixth silicon carbide region of second conductivity type is provided between the first silicon carbide region and the first surface, provided between the third silicon carbide region and the fourth silicon carbide region, in contact with the third and fourth silicon carbide regions, and shallower in depth than the depth of the third and fourth silicon carbide regions; and between the fifth silicon carbide region and the first surface The silicon carbide layer includes a seventh silicon carbide region of a first conductivity type provided therein and electrically connected to the first electrode, and an eighth silicon carbide region of a second conductivity type provided between the sixth silicon carbide region and the first surface, having a higher concentration of second conductivity type impurities than the sixth silicon carbide region; a first silicide layer provided between the eighth silicon carbide region and the first electrode; and a gate insulating layer provided between the gate electrode and the fifth silicon carbide region, and between the gate electrode and the first portion.The termination region includes a silicon carbide layer comprising: a wiring layer electrically connected to a first electrode; a second electrode; a first silicon carbide region having a third portion in contact with a first surface and the wiring layer; a ninth silicon carbide region of a second conductivity type provided between the first silicon carbide region and the first surface, surrounding the element region and in contact with the third silicon carbide region; a tenth silicon carbide region of a second conductivity type provided between the first silicon carbide region and the first surface, surrounding the ninth silicon carbide region, separated from the ninth silicon carbide region and electrically connected to the wiring layer; an eleventh silicon carbide region of a second conductivity type provided between the tenth silicon carbide region and the first surface, having a higher concentration of second conductivity type impurities than the ninth and tenth silicon carbide regions; and a second silicide layer provided between the eleventh silicon carbide region and the wiring layer. The first electrode includes a first contact portion in contact with a second portion and a second contact portion in contact with a first silicide layer; the wiring layer includes a third contact portion in contact with a third portion and a fourth contact portion in contact with a second silicide layer; the termination region is provided between a ninth silicon carbide region and a first surface and further includes a third silicide layer in contact with the ninth silicon carbide region; and the wiring layer further includes a fifth contact portion in contact with the third silicide layer.

[0013] Figures 1(a) and 1(b) are schematic top views of a semiconductor device according to the first embodiment. Figure 1(a) shows the layout patterns of the element region and the termination region. Figure 1(b) shows the layout patterns of the source electrode, source electrode wiring layer, gate pad electrode, and gate electrode wiring layer.

[0014] Figures 2(a) and 2(b) are schematic top views of a semiconductor device according to the first embodiment. Figure 2(a) shows the layout patterns of the element region and the termination region. Figure 2(b) shows the layout patterns of the gate electrode, gate connection layer, and gate pad layer.

[0015] Figure 3 is a schematic cross-sectional view of the semiconductor device according to the first embodiment. Figure 3 is the AA' cross-section shown in Figures 1 and 2.

[0016] The semiconductor device of the first embodiment is a planar gate type vertical MOSFET 100 using silicon carbide. The MOSFET 100 is a Double Implantation MOSFET (DIMOSFET) in which the base region and source region are formed by ion implantation, for example. The semiconductor device of the first embodiment also includes an SBD as an internal diode.

[0017] The following explanation will use the case where the first conductivity type is n-type and the second conductivity type is p-type as an example. MOSFET100 is a vertical n-channel MOSFET that uses electrons as carriers.

[0018] The MOSFET 100 comprises a silicon carbide layer 10, a source electrode 12 (first electrode), a source electrode wiring layer 13 (wiring layer), a first silicide layer 14a, a second silicide layer 14b, a third silicide layer 14c, a drain electrode 15 (second electrode), a gate insulating layer 16, a gate electrode 18, a gate connection layer 20, a gate pad layer 21, a gate electrode pad 22, a gate electrode wiring layer 23, a field insulating layer 24, and an interlayer insulating layer 26.

[0019] The source electrode 12 includes a first contact portion 12x and a second contact portion 12y. The source electrode wiring layer 13 includes a third contact portion 13x, a fourth contact portion 13y, and a fifth contact portion 13z.

[0020] Hereinafter, the first silicide layer 14a, the second silicide layer 14b, and the third silicide layer 14c may be referred to individually or collectively simply as the silicide layer 14.

[0021] The silicon carbide layer 10 is n + Drain region 30 of the n-shape, drift region 31 (first silicon carbide region) of the n-shape, outer p-shape region 32 (third silicon carbide region) of the p-shape, first base region 33a (fourth silicon carbide region) of the p-shape, second base region 33b (fifth silicon carbide region) of the p-shape, third base region 33c (second silicon carbide region) of the p-shape, first p-shape region 34 (sixth silicon carbide region) of the p-shape, n + Source region 35 of the shape (7th silicon carbide region), p+ The first high-concentration p-region of the p-form 36 (the eighth silicon carbide region), the second p-region of the p-form 37 (the ninth silicon carbide region), the third p-region of the p-form 38 (the tenth silicon carbide region), p + It includes the second high-concentration p-region 39 (11th silicon carbide region) of the form and the fourth p-region 40 (12th silicon carbide region) of the p-form. The drift region 31 (1st silicon carbide region) of the n-form is n - It has a low-concentration region 31a (low-concentration region) of type n and a high-concentration region 31b (high-concentration region) of type n. The drift region 31 of type n has a first part 31x, a second part 31y, and a third part 31z.

[0022] Hereinafter, the first base region 33a (fourth silicon carbide region), the second base region 33b (fifth silicon carbide region), and the third base region 33c (second silicon carbide region) may be referred to individually or collectively simply as base region 33.

[0023] The MOSFET 100 comprises an element region 101 and a termination region 102. The termination region 102 surrounds the element region 101.

[0024] The element region 101 includes multiple MOSFETs and multiple SBDs. The termination region 102 includes an SBD.

[0025] The termination region 102 reduces the intensity of the electric field applied to the termination of the pn junction of the element region 101 when the MOSFET 100 is in the off state. The termination region 102 also has the function of improving the dielectric breakdown voltage of the MOSFET 100.

[0026] The device region 101 includes a silicon carbide layer 10, a source electrode 12, a first silicide layer 14a, a drain electrode 15, a gate insulating layer 16, a gate electrode 18, a field insulating layer 24, and an interlayer insulating layer 26. The source electrode 12 of the device region 101 includes a first contact portion 12x and a second contact portion 12y.

[0027] The silicon carbide layer 10 of the element region 101 is n +Drain region 30 of the n-shape, drift region 31 (first silicon carbide region) of the n-shape, outer p-shape region 32 (third silicon carbide region) of the p-shape, first base region 33a (fourth silicon carbide region) of the p-shape, second base region 33b (fifth silicon carbide region) of the p-shape, third base region 33c (second silicon carbide region) of the p-shape, first p-shape region 34 (sixth silicon carbide region) of the p-shape, n + Source region 35 of the shape (7th silicon carbide region), p + It includes the first high-concentration p region 36 (eighth silicon carbide region) of the shape. The drift region 31 of the element region 101 is n - It has a low-density region 31a of type n and a high-density region 31b of type n. The drift region 31 of the element region 101 has a first portion 31x and a second portion 31y.

[0028] The termination region 102 includes a silicon carbide layer 10, a source electrode wiring layer 13, a second silicide layer 14b, a third silicide layer 14c, a drain electrode 15, a gate connection layer 20, a gate pad layer 21, a gate electrode pad 22, a gate electrode wiring layer 23, a field insulating layer 24, and an interlayer insulating layer 26. The source electrode wiring layer 13 of the termination region 102 includes a third contact portion 13x, a fourth contact portion 13y, and a fifth contact portion 13z.

[0029] The silicon carbide layer 10 in the terminal region 102 is n + Drain region 30 of type n, drift region 31 (first silicon carbide region) of type n, second p region 37 (ninth silicon carbide region) of type p, third p region 38 (tenth silicon carbide region) of type p + It includes a second high-concentration p-region 39 (11th silicon carbide region) of the form and a fourth p-region 40 (12th silicon carbide region) of the p-form. The drift region 31 of the terminal region 102 has a third portion 31z.

[0030] The silicon carbide layer 10 is provided between the source electrode 12 and the drain electrode 15. The silicon carbide layer 10 is single-crystal SiC. For example, the silicon carbide layer 10 is 4H-SiC.

[0031] The silicon carbide layer 10 comprises a first surface ("F1" in Figure 3) and a second surface ("F2" in Figure 3). The first surface F1 is the surface of the silicon carbide layer. The second surface F2 is the back surface of the silicon carbide layer. Hereinafter, the first surface F1 may be referred to as the surface and the second surface F2 as the back surface. The first surface F1 is located on the source electrode 12 side of the silicon carbide layer 10. The second surface F2 is located on the drain electrode 15 side of the silicon carbide layer 10. The first surface F1 and the second surface F2 face each other. Hereinafter, "depth" refers to the depth in the direction toward the second surface with respect to the first surface. The "surfaces" of the first surface F1 and the second surface F2 refer to, for example, the interface between the silicon carbide layer and the insulating film, or between the silicon carbide layer and the metal.

[0032] The first face is parallel to the first and second directions. The second direction is perpendicular to the first direction.

[0033] The first surface F1 is, for example, a surface inclined at an angle of 0 to 8 degrees relative to the (0001) surface. The second surface F2 is, for example, a surface inclined at an angle of 0 to 8 degrees relative to the (000-1) surface. The (0001) surface is referred to as the silicon surface. The (000-1) surface is referred to as the carbon surface.

[0034] The thickness of the silicon carbide layer 10 is, for example, 5 μm to 350 μm.

[0035] n + The drain region 30 is provided on the back side of the silicon carbide layer 10. The drain region 30 contains, for example, nitrogen (N) as an n-type impurity. The concentration of n-type impurities in the drain region 30 is, for example, 1 × 10⁻⁶ 18 cm -3 The above 1 x 10 21 cm -3 The following applies:

[0036] An n-shaped drift region 31 is provided between the drain region 30 and the first surface F1. An n-shaped drift region 31 is provided between the source electrode 12 and the drain electrode 15. An n-shaped drift region 31 is provided between the gate electrode 18 and the drain electrode 15. An n-shaped drift region 31 is provided on the drain region 30.

[0037] The drift region 31 contains, for example, nitrogen (N) as an n-type impurity. The concentration of n-type impurities in the drift region 31 is lower than the concentration of n-type impurities in the drain region 30. The concentration of n-type impurities in the drift region 31 is, for example, 4 × 10⁻⁶. 14 cm -3 The above 5 x 10 17 cm -3 The following applies: The thickness of the drift region 31 is, for example, between 3 μm and 100 μm.

[0038] The drift region 31 is in the element region 101, n - It has a low-concentration region 31a of a certain shape and a high-concentration region 31b of an n-shape. The high-concentration region 31b is provided between the low-concentration region 31a and the first surface F1.

[0039] n - Having a low-concentration region 31a of the n-type improves, for example, the dielectric breakdown voltage of the MOSFET 100. Also, having a high-concentration region 31b of the n-type increases, for example, the on-current of the MOSFET 100.

[0040] The drift region 31 includes a first portion 31x and a second portion 31y in the element region 101. The first portion 31x and the second portion 31y are contained within the high-concentration region 31b.

[0041] The first portion 31x is in contact with the first surface F1 and faces the gate electrode 18 with the gate insulating layer 16 in between. The first portion 31x functions, for example, as a current path for the MOSFET in the element region 101.

[0042] The second portion 31y is in contact with the first surface F1 and with the source electrode 12. The second portion 31y functions, for example, as a current path for the SBD in the element region 101. A silicide layer, not shown, is provided in the second direction of the second portion 31y.

[0043] The p-shaped base region 33 is provided between the drift region 31 and the first surface F1. The base region 33 is provided between the high-concentration region 31b and the first surface F1.

[0044] The base region 33 extends, for example, in a second direction. For example, multiple base regions 33 are repeatedly arranged in a first direction.

[0045] The base region 33 includes, for example, a first base region 33a, a second base region 33b, and a p-shaped third base region 33c. The first base region 33a is provided between the third base region 33c and the outer p-region 32. The second base region 33b is provided between the third base region 33c and the first base region 33a.

[0046] The base region 33 functions, for example, as the channel region of the MOSFET 100.

[0047] The width of the base region 33 is, for example, 0.5 μm or more and 2.0 μm or less. The width of the first base region 33a in the first direction is, for example, 0.5 μm or more and 2.0 μm or less.

[0048] The distance in the first direction between two adjacent base regions 33 is, for example, 0.5 μm or more and 2.0 μm or less. The distance in the first direction between the first base region 33a and the second base region 33b is, for example, 0.5 μm or more and 2.0 μm or less.

[0049] The depth of the base region 33 is, for example, 1.0 μm or more and 2.0 μm or less. By making the base region 33 deeper, for example, the amount of current when a short-circuit current flows through the MOSFET 100 is suppressed, and the short-circuit withstand capability of the MOSFET 100 is improved.

[0050] The base region 33 is electrically connected to the source electrode 12. The base region 33 is fixed at the potential of the source electrode 12.

[0051] A portion of the base region 33 is in contact with the first surface F1. A portion of the base region 33 faces the gate electrode 18. For example, a portion of the first base region 33a faces the gate electrode 18. For example, a portion of the second base region 33b faces the gate electrode 18. A gate insulating layer 16 is sandwiched between a portion of the base region 33 and the gate electrode 18.

[0052] The base region 33 contains, for example, aluminum (Al) as a p-type impurity. The concentration of p-type impurities in the base region 33 is, for example, 5 × 10⁻⁶ 17 cm -3 The above 1 x 10 20 cm -3 The following applies:

[0053] The outer p region 32 of the p shape is provided between the drift region 31 and the first surface F1. The outer p region 32 is provided between the high-concentration region 31b and the first surface F1.

[0054] The outer peripheral region p 32 is provided on the outer periphery of the base region 33. The outer peripheral region p 32 is provided on the side of the end region 102 of the base region 33. The outer peripheral region p 32 is provided on the side of the end region 102 of the third base region 33c. For example, the outer peripheral region p 32 surrounds the base region 33 on the first surface F1.

[0055] The width of the outer p region 32 in the first direction is, for example, 0.5 μm or more and 2.0 μm or less. The width of the outer p region 32 in the first direction is, for example, substantially the same as the width of the base region 33 in the first direction.

[0056] The distance in the first direction between the outer p region 32 and the first base region 33a is, for example, between 0.5 μm and 2.0 μm. For example, the distance in the first direction between the outer p region 32 and the first base region 33a is substantially equal to the distance in the first direction between two adjacent base regions 33 in the first direction.

[0057] The depth of the outer p region 32 is, for example, 1.0 μm or more and 2.0 μm or less. The depth of the outer p region 32 is, for example, substantially the same as the depth of the base region 33.

[0058] The outer p region 32 is electrically connected to the source electrode 12. The outer p region 32 is fixed at the potential of the source electrode 12.

[0059] The outer p region 32 contains, for example, aluminum (Al) as a p-type impurity. The concentration of p-type impurities in the outer p region 32 is, for example, 5 × 10⁻⁶ 17 cm -3 The above 1 x 10 20 cm -3 The following applies: The concentration of p-type impurities in the outer p-region 32 is substantially the same as, for example, the concentration of p-type impurities in the base region 33.

[0060] The outer peripheral region p 32 is formed, for example, using the same manufacturing process as the base region 33, with the same mask pattern.

[0061] The first p-shaped p-region 34 is provided between the drift region 31 and the first surface F1. The first p-region 34 is provided between the high-concentration region 31b and the first surface F1.

[0062] The first p-region 34 is provided, for example, between two adjacent base regions 33 in a first direction. The first p-region 34 is provided between the outer peripheral p-region 32 and the first base region 33a. The first p-region 34 is in contact with the outer peripheral p-region 32 and the first base region 33a.

[0063] The first p region 34 is provided between the first high-concentration p region 36 and the high-concentration region 31b. The first p region 34 is provided between the silicide layer 14 and the high-concentration region 31b.

[0064] The depth of the first p region 34 is shallower than the depth of the outer p region 32 and the depth of the base region 33. The depth of the first p region 34 is, for example, shallower than the depth of the first base region 33a. The depth of the first p region 34 is, for example, 0.5 μm or more and 1 μm or less.

[0065] By providing a first p-region 34 that is shallower than the depth of the base region 33, the current that flows back to the bottom of the base region 33 when a forward current flows through the SBD of the element region 101 is promoted. Therefore, the operating start voltage of the pn junction diode with the base region 33 as the anode can be increased.

[0066] The first p-region 34 is electrically connected to the source electrode 12. The first p-region 34 is fixed at the potential of the source electrode 12.

[0067] The first p-region 34 contains, for example, aluminum (Al) as a p-type impurity. The concentration of the p-type impurity in the first p-region 34 is, for example, 5 × 10⁻⁶ 17 cm -3 The above 1 x 10 20 cm -3 The following applies:

[0068] The drift region 31 includes a third portion 31z in the termination region 102. The third portion 31z is in contact with the first surface F1 and the source electrode wiring layer 13. The third portion 31z functions, for example, as a current path for the SBD in the termination region 102.

[0069] The second p-shaped p-region 37 is provided between the drift region 31 and the first surface F1. The second p-region 37 is provided between the low-concentration region 31a and the first surface F1.

[0070] The second p-region 37 surrounds the element region 101. The second p-region 37 is in contact with the outer p-region 32.

[0071] The depth of the second p region 37 is shallower than the depth of the outer p region 32 and the depth of the base region 33. The depth of the second p region 37 is, for example, shallower than the depth of the first base region 33a. The depth of the second p region 37 is, for example, 0.5 μm or more and 1 μm or less.

[0072] The depth of the second p-region 37 is substantially the same as, for example, the depth of the first p-region 34.

[0073] The second p region 37 is electrically connected to the source electrode wiring layer 13. The second p region 37 is fixed to the potential of the source electrode wiring layer 13. The second p region 37 is fixed to the potential of the source electrode 12.

[0074] The second p-region 37 contains, for example, aluminum (Al) as a p-type impurity. The concentration of p-type impurities in the second p-region 37 is, for example, 5 × 10⁻⁶ 17 cm -3 The above 1 x 10 20 cm -3 The following applies: The concentration of p-type impurities in the second p-region 37 is substantially the same as, for example, the concentration of p-type impurities in the first p-region 34.

[0075] The second p region 37 is formed, for example, by the same manufacturing process using the same mask pattern as the first p region 34.

[0076] The third p-shaped p-region 38 is provided between the drift region 31 and the first surface F1. The third p-region 38 is provided between the low-concentration region 31a and the first surface F1.

[0077] The third p-region 38 surrounds the second p-region 37. The third p-region 38 separates from the second p-region 37 in the first direction.

[0078] A drift region 31 is provided between the third p region 38 and the second p region 37. A third portion 31z of the drift region 31 is provided between the third p region 38 and the second p region 37.

[0079] The depth of the third p region 38 is shallower than the depth of the outer p region 32 and the depth of the base region 33. The depth of the third p region 38 is, for example, shallower than the depth of the first base region 33a. The depth of the third p region 38 is, for example, 0.5 μm or more and 1 μm or less.

[0080] The depth of the third p-region 38 is substantially the same as, for example, the depth of the first p-region 34 and the depth of the second p-region 37.

[0081] The third p region 38 is electrically connected to the source electrode 12. The third p region 38 is fixed to the potential of the source electrode 12.

[0082] The third p-region 38 contains, for example, aluminum (Al) as a p-type impurity. The concentration of the p-type impurity in the third p-region 38 is, for example, 5 × 10⁻⁶ 17 cm -3 The above 1 x 10 20 cm -3 The following applies: The concentration of p-type impurities in the third p-region 38 is substantially the same as, for example, the concentration of p-type impurities in the first p-region 34 and the concentration of p-type impurities in the second p-region 37.

[0083] The third p region 38 is formed, for example, by the same manufacturing process using the same mask pattern as the first p region 34 and the second p region 37.

[0084] The fourth p-shaped p-region 40 is provided between the drift region 31 and the first surface F1. The fourth p-region 40 is provided between the drift region 31 and the second p-region 37.

[0085] The fourth p region 40 is provided, for example, between the low-concentration region 31a and the first surface F1. The fourth p region 40 is provided, for example, between the low-concentration region 31a and the second p region 37. The fourth p region 40 is in contact with the low-concentration region 31a.

[0086] The fourth p region 40 is provided on the outer periphery of the outer p region 32. The fourth p region 40 is provided on the side of the terminal region 102 of the outer p region 32. The fourth p region 40 is separated from the outer p region 32 in the first direction. For example, the fourth p region 40 surrounds the outer p region 32 on the first surface F1.

[0087] The width of the fourth p-region 40 in the first direction is, for example, 0.5 times or more and 3 times or less the width of the base region 33 in the first direction. The width of the fourth p-region 40 in the first direction is, for example, 0.5 times or more and 3 times or less the width of the first base region 33a in the first direction. The width of the fourth p-region 40 in the first direction is, for example, 0.5 μm or more and 10 μm or less. The width of the fourth p-region 40 in the first direction is, for example, substantially the same as the width of the base region 33 in the first direction.

[0088] The distance in the first direction between the fourth p region 40 and the outer p region 32 is between 0.5 and 3 times the distance in the first direction between the first base region 33a and the second base region 33b. For example, the distance in the first direction between the fourth p region 40 and the outer p region 32 is between 0.5 μm and 2.0 μm.

[0089] The fourth p-region 40 is provided, for example, on the side of the element region 101 that is closer to the element region 101 than the end of the field insulating layer 24 of the termination region 102 on the element region 101 side.

[0090] The depth of the fourth p-region 40 is greater than the depth of the second p-region 37. The depth of the fourth p-region 40 is, for example, between 1.0 μm and 2.0 μm. The depth of the fourth p-region 40 is, for example, between 1.5 and 5 times the depth of the second p-region 37.

[0091] The depth of the fourth p-region 40 is, for example, 0.5 times or more and 2 times or less than the depth of the base region 33. The depth of the fourth p-region 40 is, for example, greater than or equal to the depth of the base region 33. The first depth of the fourth p-region 40 is, for example, deeper than the depth of the base region 33.

[0092] The depth of the fourth p-region 40 is, for example, 0.5 times or more and 2 times or less the depth of the outer p-region 32. The depth d1 of the fourth p-region 40 is, for example, greater than or equal to the depth of the outer p-region 32. The depth of the fourth p-region 40 is, for example, greater than or equal to the depth d2 of the outer p-region 32.

[0093] The fourth p region 40 is electrically connected to the source electrode 12. The fourth p region 40 is fixed at the potential of the source electrode 12.

[0094] The fourth p-region 40 contains, for example, aluminum (Al) as a p-type impurity. The concentration of the p-type impurity in the fourth p-region 40 is, for example, 1 × 10⁻⁶ 17 cm -3 The above 1 x 10 20 cm -3 The following applies:

[0095] The p-type impurity concentration in the fourth p-region 40 is, for example, 0.1 times or more and 2 times or less than the p-type impurity concentration in the base region 33. The p-type impurity concentration in the fourth p-region 40 is, for example, substantially the same as the p-type impurity concentration in the base region 33.

[0096] The p-type impurity concentration in the fourth p-region 40 is, for example, 0.1 times or more and 2 times or less than the p-type impurity concentration in the outer p-region 32. The p-type impurity concentration in the fourth p-region 40 is, for example, substantially the same as the p-type impurity concentration in the outer p-region 32.

[0097] The fourth p region 40 is formed, for example, using the same manufacturing process as the base region 33 and the outer p region 32, with the same mask pattern.

[0098] By providing the fourth p-region 40, the intensity of the electric field applied to the termination of the pn junction of the element region 101 is further reduced. Therefore, by providing the fourth p-region 40, the dielectric breakdown voltage of the MOSFET 100 is further improved.

[0099] n +The source region 35 of the shape is provided between the base region 33 and the first surface F1. The source region 35 is provided, for example, between the second base region 33b and the first surface F1. The source region 35 extends, for example, in a first direction.

[0100] Source region 35 contains, for example, phosphorus (P) or nitrogen (N) as n-type impurities. The concentration of n-type impurities in source region 35 is higher than the concentration of n-type impurities in drift region 31.

[0101] The n-type impurity concentration in source region 35 is, for example, 1 × 10⁻⁶ 19 cm -3 The above 1 x 10 21 cm -3 The following applies: The depth of the source region 35 is shallower than the depth of the first p region 34. The depth of the source region 35 is, for example, between 0.05 μm and 0.2 μm.

[0102] The source region 35 is electrically connected to the source electrode 12. The source region 35 is in contact with the silicide layer 14. The contact between the source region 35 and the source electrode 12 is, for example, an ohmic contact. The source region 35 is fixed at the potential of the source electrode 12.

[0103] p + The first high-concentration p-region 36 is provided between the first p-region 34 and the first surface F1. The first high-concentration p-region 36 is provided between the first p-region 34 and the first silicide layer 14a.

[0104] The first high-concentration p-region 36 contains, for example, aluminum (Al) as a p-type impurity. The concentration of p-type impurities in the first high-concentration p-region 36 is higher than the concentration of p-type impurities in the first p-region 34. For example, the concentration of p-type impurities in the first high-concentration p-region 36 is between 10 and 1000 times the concentration of p-type impurities in the first p-region 34.

[0105] The p-type impurity concentration in the first high-concentration p-region 36 is, for example, 1 × 10⁻⁶ 19 cm -3 The above 1 x 10 21 cm-3 The following applies: The depth of the first high-concentration p region 36 is, for example, 0.1 μm to 0.2 μm.

[0106] The first high-concentration p region 36 is electrically connected to the source electrode 12. The first high-concentration p region 36 is in contact with the first silicide layer 14a.

[0107] p + The second high-density p-region 39 is provided between the third p-region 38 and the first surface F1. The second high-density p-region 39 is provided between the third p-region 38 and the second silicide layer 14b.

[0108] The second high-concentration p-region 39 contains, for example, aluminum (Al) as a p-type impurity. The concentration of p-type impurities in the second high-concentration p-region 39 is higher than the concentration of p-type impurities in the second p-region 37 and the third p-region 38. The concentration of p-type impurities in the second high-concentration p-region 39 is, for example, 10 to 1000 times higher than the concentration of p-type impurities in the third p-region 38.

[0109] The p-type impurity concentration in the second high-concentration p-region 39 is, for example, 1 × 10⁻⁶ 19 cm -3 The above 1 x 10 21 cm -3 The following applies: The depth of the second high-concentration p region 39 is, for example, between 0.1 μm and 0.2 μm.

[0110] The second high-concentration p-region 39 is electrically connected to the source electrode wiring layer 13. The second high-concentration p-region 39 is in contact with the second silicide layer 14b.

[0111] The second high-concentration p-region 39 is formed, for example, by the same manufacturing process using the same mask pattern as the first high-concentration p-region 36.

[0112] The first silicide layer 14a is provided between the first high-concentration p region 36 and the source electrode 12. The first silicide layer 14a is in contact with the first high-concentration p region 36 and the source region 35.

[0113] The second silicide layer 14b is provided between the second high-concentration p-region 39 and the source electrode wiring layer 13. The second silicide layer 14b is in contact with the second high-concentration p-region 39.

[0114] The third silicide layer 14c is provided between the second p region 37 and the source electrode wiring layer 13. The third silicide layer 14c is in contact with the second p region 37.

[0115] The silicide layer 14 contains silicide. The silicide layer 14 contains, for example, nickel (Ni) or titanium (Ti). The silicide layer 14 is, for example, nickel silicide or titanium silicide.

[0116] The gate electrode 18 is provided on the side of the first surface F1 of the silicon carbide layer 10. The gate electrode 18 extends, for example, in a second direction. Multiple gate electrode 18s are arranged, for example, parallel to each other in the first direction. The gate electrode 18 has, for example, a stripe shape.

[0117] The gate electrode 18 is a conductive layer. The gate electrode 18 is, for example, polycrystalline silicon containing p-type or n-type impurities.

[0118] The gate electrode 18 faces the base region 33. The gate electrode 18 faces the first portion 31x.

[0119] The gate connection layer 20 is provided on the side of the first surface F1 of the silicon carbide layer 10. The gate connection layer 20 is provided on top of the gate insulating layer 16 or the field insulating layer 24.

[0120] A portion of the gate connection layer 20 extends, for example, in a direction perpendicular to the gate electrode 18. The gate connection layer 20 has the function of electrically connecting the gate electrode 18 and the gate electrode pad 22.

[0121] The gate connection layer 20 is formed from, for example, the same material as the gate electrode 18.

[0122] The gate pad layer 21 is provided on the side of the first surface F1 of the silicon carbide layer 10. The gate pad layer 21 is provided on top of the field insulating layer 24.

[0123] The gate pad layer 21 is physically and electrically connected to the gate connection layer 20. The gate pad layer 21 has the function of electrically connecting the gate electrode 18 and the gate electrode pad 22.

[0124] The gate pad layer 21 is formed from, for example, the same material as the gate electrode 18 and the gate connection layer 20.

[0125] The gate insulating layer 16 is provided between the gate electrode 18 and the base region 33. The gate insulating layer 16 is provided between the gate electrode 18 and the first portion 31x. The gate insulating layer 16 is provided between the gate electrode 18 and the source region 35.

[0126] The gate insulating layer 16 is, for example, silicon oxide. For the gate insulating layer 16, for example, a high-k insulating material (high dielectric constant insulating material) can be applied.

[0127] The field insulating layer 24 is provided on the silicon carbide layer 10 of the terminal region 102. The field insulating layer 24 is, for example, silicon oxide.

[0128] The interlayer insulating layer 26 is provided on the gate electrode 18 and the silicon carbide layer 10. The interlayer insulating layer 26 is, for example, silicon oxide.

[0129] The source electrode 12 is provided on the side of the first surface F1 of the silicon carbide layer 10 of the element region 101. The source electrode 12 is provided on the interlayer insulating layer 26.

[0130] The source electrode 12 contains a metal. The source electrode 12 is, for example, a laminated structure of a first film containing titanium (Ti) and a second film containing aluminum (Al). The source electrode 12 is, for example, a laminated film of titanium and aluminum. The source electrode 12 does not contain, for example, silicide.

[0131] The source electrode 12 includes a first contact portion 12x and a second contact portion 12y.

[0132] The first contact portion 12x is in contact with the second portion 31y of the drift region 31. No silicide layer is provided between the first contact portion 12x and the second portion 31y. The contact between the first contact portion 12x and the second portion 31y is a Schottky contact.

[0133] A portion of the first contact area 12x is in contact with, for example, the base area 33.

[0134] The first contact portion 12x functions as the anode electrode of the SBD in the element region 101.

[0135] The second contact portion 12y is in contact with the first silicide layer 14a. The first silicide layer 14a is in contact with the first high-concentration p region 36 and the source region 35.

[0136] The contact resistance between the second contact portion 12y and the first high-concentration p region 36 is reduced by sandwiching the first silicide layer 14a in between. The contact between the second contact portion 12y and the first high-concentration p region 36 becomes, for example, an ohmic contact.

[0137] The contact resistance between the second contact portion 12y and the source region 35 is reduced by the placement of the first silicide layer 14a in between. The contact between the second contact portion 12y and the source region 35 becomes, for example, an ohmic contact.

[0138] The second contact portion 12y has the function of fixing the potentials of, for example, the base region 33, the first p region 34, and the second p region 37 to the potential of the source electrode 12.

[0139] The source electrode wiring layer 13 is provided on the side of the first surface F1 of the silicon carbide layer 10 in the termination region 102. The source electrode wiring layer 13 is provided on top of the interlayer insulating layer 26.

[0140] The source electrode wiring layer 13 is physically and electrically connected to the source electrode 12. The source electrode wiring layer 13 surrounds the source electrode 12, for example.

[0141] The source electrode wiring layer 13 contains a metal. The source electrode wiring layer 13 is, for example, a laminated structure of a first film containing titanium (Ti) and a second film containing aluminum (Al). The source electrode wiring layer 13 is, for example, a laminated film of a titanium film and an aluminum film. The source electrode wiring layer 13 does not contain, for example, silicide.

[0142] The source electrode wiring layer 13 is formed from, for example, the same material as the source electrode 12.

[0143] The source electrode wiring layer 13 includes a third contact portion 13x, a fourth contact portion 13y, and a fifth contact portion 13z.

[0144] The fourth contact portion 13y is provided, for example, at the end of the third p region 38 on the side of the second p region 37. The fifth contact portion 13z is provided, for example, at the end of the second p region 37 on the side of the third p region 38.

[0145] The third contact portion 13x is provided between the fourth contact portion 13y and the fifth contact portion 13z. Between the third contact portion 13x and the fourth contact portion 13y, for example, an interlayer insulating layer 26 is provided. Between the third contact portion 13x and the fifth contact portion 13z, for example, an interlayer insulating layer 26 is provided.

[0146] The distance in the first direction between the third contact portion 13x and the fourth contact portion 13y is substantially the same as, for example, the distance in the first direction between the third contact portion 13x and the fifth contact portion 13z. The distance in the first direction between the third contact portion 13x and the fourth contact portion 13y is, for example, 0.5 times or more and 2 times or less the distance in the first direction between the third contact portion 13x and the fifth contact portion 13z.

[0147] The third contact portion 13x is in contact with the third portion 31z of the drift region 31. No silicide layer is provided between the third contact portion 13x and the third portion 31z. The contact between the third contact portion 13x and the third portion 31z is a Schottky contact.

[0148] A portion of the third contact portion 13x is in contact with, for example, the second p region 37. Another portion of the third contact portion 13x is in contact with, for example, the third p region 38.

[0149] The third contact portion 13x functions as the anode electrode of the SBD in the terminal region 102.

[0150] The fourth contact portion 13y is in contact with the second silicide layer 14b. The second silicide layer 14b is in contact with the second high-concentration p region 39 and the third p region 38.

[0151] The contact resistance between the fourth contact portion 13y and the second high-concentration p region 39 is reduced by inserting the second silicide layer 14b in between. The contact between the fourth contact portion 13y and the second high-concentration p region 39 becomes, for example, an ohmic contact.

[0152] The fourth contact portion 13y has the function of fixing the potential of the third p region 38 to the potential of the source electrode 12 and the source electrode wiring layer 13, for example.

[0153] The fifth contact portion 13z is in contact with the third silicide layer 14c. The third silicide layer 14c is in contact with the second p region 37.

[0154] The contact resistance between the fifth contact portion 13z and the second p region 37 is reduced by inserting the third silicide layer 14c in between.

[0155] The fifth contact portion 13z has the function of fixing the potential of the second p region 37 to the potential of the source electrode 12 and the source electrode wiring layer 13.

[0156] The electrical resistance between the fifth contact portion 13z and the second p-region 37 of MOSFET 100 is higher than the electrical resistance between the fourth contact portion 13y and the third p-region 38. The electrical resistance is higher because there is no region with a high concentration of p-type impurities between the fifth contact portion 13z and the second p-region 37.

[0157] The third silicide layer 14c is in contact with the second p-region 37. The p-type impurity concentration in the second p-region 37 is lower than the p-type impurity concentration in the second high-concentration p-region 39. The p-type impurity concentration in the portion of the second p-region 37 in contact with the third silicide layer 14c is, for example, between 1 / 1000 and 1 / 10 of the p-type impurity concentration in the portion of the second high-concentration p-region 39 in contact with the second silicide layer 14b.

[0158] The gate electrode pad 22 is provided on the side of the first surface F1 of the silicon carbide layer 10 in the termination region 102. The gate electrode pad 22 is provided on the interlayer insulating layer 26.

[0159] The gate electrode pad 22 contains metal. The gate electrode pad 22 is formed from the same material as the source electrode 12 and the source electrode wiring layer 13, for example.

[0160] The gate electrode wiring layer 23 is provided on the side of the first surface F1 of the silicon carbide layer 10 in the termination region 102. The gate electrode wiring layer 23 is provided on top of the interlayer insulating layer 26.

[0161] The gate electrode wiring layer 23 is physically and electrically connected to the gate electrode pad 22. The gate electrode wiring layer 23 is physically and electrically connected to the gate connection layer 20.

[0162] The gate electrode wiring layer 23 contains a metal. The gate electrode wiring layer 23 is formed from the same material as, for example, the source electrode 12, the source electrode wiring layer 13, and the gate electrode pad 22.

[0163] The drain electrode 15 is provided on the back surface of the silicon carbide layer 10. The drain electrode 15 is in contact with the drain region 30.

[0164] The drain electrode 15 is, for example, a metal or a metal-semiconductor compound. The drain electrode 15 includes, for example, at least one material selected from the group consisting of nickel silicide, titanium (Ti), nickel (Ni), silver (Ag), and gold (Au).

[0165] In the element region 101, the gate electrode 18, gate insulating layer 16, base region 33, source region 35, first portion 31x of the drift region 31, drain region 30, second contact portion 12y of the source electrode 12, and drain electrode 15 form a MOSFET. When the MOSFET 100 is ON, current flows from the drain electrode 15 to the source electrode 12 due to the MOSFET in the element region 101.

[0166] In the element region 101, the first contact portion 12x of the source electrode 12, the second portion 31y of the drift region 31, the drain region 30, and the drain electrode 15 form an SBD. When the MOSFET 100 is in the off state and a positive voltage is applied to the drain electrode 15 from the source electrode 12, current flows from the source electrode 12 to the drain electrode 15 due to the SBD in the element region 101.

[0167] In the termination region 102, the third contact portion 13x of the source electrode wiring layer 13, the third portion 31z of the drift region 31, the drain region 30, and the drain electrode 15 form an SBD. When the MOSFET 100 is in the off state and a positive voltage is applied to the drain electrode 15 from the source electrode 12, current flows from the source electrode wiring layer 13 to the drain electrode 15 due to the SBD in the termination region 102.

[0168] Next, the operation and effects of the MOSFET 100 of the first embodiment will be described.

[0169] Figure 4 is an equivalent circuit diagram of the semiconductor device according to the first embodiment. In the MOSFET 100, a pn junction diode and an SBD are connected in parallel with the transistor as built-in diodes between the source electrode 12 and the drain electrode 15 of the element region 101. The base region 33 is the anode side of the pn junction diode, and the drift region 31 is the cathode side of the pn junction diode. The source electrode 12 is the anode of the SBD, and the drain electrode 15 is the cathode of the SBD.

[0170] For example, consider a case where MOSFET 100 is used as a switching element connected to an inductive load. When MOSFET 100 is off, an induced current caused by the inductive load may apply a positive voltage to the source electrode 12 relative to the drain electrode 15. In this case, a forward current flows through the built-in diode. This state is also called a reverse conduction state.

[0171] If a MOSFET does not have an SBD, forward current flows through the pn junction diode. The pn junction diode operates bipolar. When a freewheel current flows through a bipolar pn junction diode, stacking faults grow in the silicon carbide layer due to the carrier recombination energy. The growth of stacking faults in the silicon carbide layer leads to an increase in the on-resistance of the MOSFET. An increase in the on-resistance of the MOSFET leads to a decrease in the reliability of the MOSFET.

[0172] MOSFET100 is equipped with an SBD. The forward voltage (Vf) at which forward current begins to flow through the SBD is lower than the forward voltage (Vf) of the pn junction diode. Therefore, forward current flows through the SBD before it flows through the pn junction diode.

[0173] The forward voltage (Vf) of an SBD is, for example, between 1.0V and less than 2.0V. The forward voltage (Vf) of a pn junction diode is, for example, between 2.0V and 3.0V.

[0174] The SBD operates unipolar. Therefore, even when a forward current flows, stacking faults do not grow in the silicon carbide layer 10 due to carrier recombination energy. Consequently, the increase in the on-resistance of the MOSFET 100 is suppressed. Thus, the reliability of the MOSFET 100 is improved.

[0175] Furthermore, the forward current flowing through the SBD increases the voltage on the N side of the pn junction diode, effectively reducing the voltage applied to the pn junction near the SBD. Therefore, by providing an SBD, the forward voltage (Vf) of the pn junction diode near the SBD can be effectively increased. Consequently, the flow of forward current through the pn junction diode is suppressed. In other words, the operating start voltage of the pn junction diode can be increased. Thus, the reliability of MOSFET 100 is improved.

[0176] Figure 5 is a schematic cross-sectional view of a comparative example semiconductor device. The comparative example semiconductor device is a MOSFET 900. Figure 5 corresponds to Figure 3 of the first embodiment.

[0177] In the comparative example MOSFET900, between the third silicide layer 14c and the second p-type p-region 37, + This differs from the MOSFET 100 of the first embodiment in that a third high-concentration p-region 41 (13th silicon carbide region) of the shape is provided.

[0178] p +The third high-density p-region 41 is provided between the second p-region 37 and the first surface F1. The third high-density p-region 41 is provided between the second p-region 37 and the third silicide layer 14c.

[0179] The third high-concentration p-region 41 contains, for example, aluminum (Al) as a p-type impurity. The concentration of p-type impurities in the third high-concentration p-region 41 is higher than the concentration of p-type impurities in the second p-region 37 and the third p-region 38. The concentration of p-type impurities in the third high-concentration p-region 41 is, for example, 10 to 1000 times higher than the concentration of p-type impurities in the second p-region 37.

[0180] The concentration of p-type impurities in the third high-concentration p-region 41 is, for example, 1 × 10⁻⁶ 19 cm -3 The above 1 x 10 21 cm -3 The following applies: The depth of the third high-concentration p region 41 is, for example, between 0.1 μm and 0.2 μm.

[0181] The third high-concentration p-region 41 is electrically connected to the source electrode wiring layer 13. The third high-concentration p-region 41 is in contact with the second silicide layer 14b.

[0182] The third high-concentration p-region 41 is formed, for example, by the same manufacturing process using the same mask pattern as the first high-concentration p-region 36 and the second high-concentration p-region 39.

[0183] Figure 6 is an explanatory diagram of the operation and effects of the comparative semiconductor device. Figure 6 is a schematic cross-sectional view of the comparative semiconductor device. Figure 6 corresponds to Figure 5.

[0184] Figure 6 shows the pn junction diode and SBD inherent in MOSFET 900 using circuit symbols. Figure 6 also shows the current flowing through the drift region 31 of MOSFET 900 when a positive voltage is applied to the source electrode 12 relative to the drain electrode 15, indicated by arrows.

[0185] As shown in Figure 6, in element region 101, a forward current flows through the SBD including the first contact portion 12x of the source electrode 12 and the second portion 31y of the drift region 31. The forward current passes between the base region 33 and wraps around to the bottom of the base region 33. The forward current that wraps around to the bottom of the base region 33 increases the N-side voltage of the pn junction diode formed by the base region 33 and the drift region 31, effectively decreasing the voltage applied to the pn junction near the SBD. Therefore, the forward voltage (Vf) of the pn junction diode in element region 101 can be effectively increased. Thus, the flow of forward current through the pn junction diode in element region 101 is suppressed.

[0186] As shown in Figure 6, in the termination region 102, a forward current flows through the SBD including the third contact portion 13x of the source electrode wiring layer 13 and the third portion 31z of the drift region 31. The forward current passes between the second p region 37 and the third p region 38 and wraps around to the bottoms of the second p region 37, the third p region 38, and the fourth p region 40. However, because there is a distance from the SBD in the termination region 102 to the second p region 37 or the fourth p region 40 that is closer to the element region 101, the current wrapping around to the bottoms of the second p region 37 or the fourth p region 40 that is closer to the element region 101 is suppressed.

[0187] Therefore, in the portion close to the element region 101, the voltage on the N side of the pn junction diode formed by the second p region 37 and the drift region 31, or the fourth p region 40 and the drift region 31, is less likely to rise. In other words, the decrease in voltage applied to the pn junction due to forward current is suppressed. Consequently, the pn junction diode in the termination region 102 close to the element region 101 operates, and bipolar current flows more easily into the drift region 31. Therefore, there is concern that the reliability of the MOSFET 900 will decrease due to the increase in on-resistance.

[0188] Figure 7 is an explanatory diagram of the problems of the comparative semiconductor device. Figure 7 is a schematic cross-sectional view of the comparative semiconductor device. Figure 7 corresponds to Figure 5.

[0189] Figure 7 shows the pn junction diode and SBD inherent in MOSFET 900 using circuit symbols. Figure 7 also shows the current flowing into the second p-region 37 of the p-type MOSFET 900 when a positive voltage relative to the drain electrode 15 is applied to the source electrode 12 and source electrode wiring layer 13 of MOSFET 900, indicated by arrows.

[0190] In the comparative example MOSFET900, the fifth contact portion 13z is in contact with the third silicide layer 14c. The third silicide layer 14c is in contact with the third high-concentration p region 41 and the second p region 37.

[0191] The contact resistance between the fifth contact portion 13z and the third high-concentration p-region 41 is reduced by the presence of the third silicide layer 14c. The contact between the fifth contact portion 13z and the third high-concentration p-region 41 becomes, for example, an ohmic contact. Furthermore, the electrical resistance between the fifth contact portion 13z and the second p-region 37 is also reduced by the presence of the third silicide layer 14c and the third high-concentration p-region 41. Therefore, for example, the contact between the fifth contact portion 13z and the second p-region 37 becomes an ohmic contact.

[0192] As indicated by the arrow, current flows into the second p-region 37 from the source electrode 12 via the second contact portion 12y. In other words, holes are supplied to the second p-region 37 from the source electrode 12 via the second contact portion 12y.

[0193] Furthermore, current flows into the second p-region 37 from the source electrode wiring layer 13 via the fifth contact portion 13z, as indicated by the arrow. In other words, holes are supplied to the second p-region 37 from the source electrode wiring layer 13 via the fifth contact portion 13z.

[0194] When the amount of holes supplied to the second p-region 37 increases, the operation of the pn junction diode in the termination region 102, which is close to the element region 101, is accelerated. Also, when the pn junction diode is operating, the bipolar current flowing through the drift region 31 increases. Therefore, there is a concern that the reliability of the MOSFET 900 will decrease due to the increase in on-resistance.

[0195] In the MOSFET 100 of the first embodiment, similar to the MOSFET 900, the pn junction diode in the termination region 102 close to the element region 101 operates, making it easier for bipolar current to flow into the drift region 31. Therefore, there is concern that the reliability of the MOSFET 100 will decrease due to the increase in on-resistance.

[0196] Figure 8 is an explanatory diagram of the operation and effects of the semiconductor device of the first embodiment. Figure 8 is a schematic cross-sectional view of the semiconductor device of the first embodiment. Figure 8 corresponds to Figure 3. Also, Figure 8 corresponds to Figure 7 of the comparative example.

[0197] Figure 8 shows the pn junction diode and SBD inherent in MOSFET 100 using circuit symbols. Figure 8 also shows the current flowing into the second p-region 37 of the p-type MOSFET 100 when a positive voltage relative to the drain electrode 15 is applied to the source electrode 12 of MOSFET 100, indicated by arrows.

[0198] In the MOSFET 100 of the first embodiment, unlike the comparative example MOSFET 900, a p-type high-concentration region is not provided beneath the third silicide layer 14c. In MOSFET 100, the third silicide layer 14c is in contact only with the second p-region 37.

[0199] Compared to MOSFET900, the concentration of p-type impurities in the p-region in contact with the third silicide layer 14c is lower, resulting in higher electrical resistance between the fifth contact portion 13z and the second p-region 37.

[0200] Therefore, the current flowing from the source electrode wiring layer 13 through the fifth contact portion 13z into the second p region 37, as indicated by the dotted arrow, is smaller compared to the MOSFET 900. The amount of holes supplied from the source electrode wiring layer 13 through the fifth contact portion 13z into the second p region 37 is reduced.

[0201] Therefore, the start of operation of the pn junction diode in the termination region 102, which is close to the element region 101, is suppressed. Also, the bipolar current flowing through the drift region 31 when the pn junction diode is operating is reduced. As a result, the growth of stacking faults is suppressed, and the increase in on-resistance is suppressed, thereby improving the reliability of the MOSFET 100.

[0202] From the viewpoint of increasing the contact resistance between the fifth contact portion 13z and the second p region 37, the p-type impurity concentration in the portion of the second p region 37 in contact with the third silicide layer 14c is preferably one-tenth or less of the p-type impurity concentration in the portion of the second high-concentration p region 39 in contact with the second silicide layer 14b, and more preferably one-hundredth or less.

[0203] As described above, according to the first embodiment, forward current flow in the pn junction diode is suppressed, and a MOSFET with improved reliability is realized.

[0204] (Second embodiment) The semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment in that the wiring layer does not include any portion that is in direct contact with the ninth silicon carbide region or in contact with a silicide layer in between, other than the third contact portion. Hereafter, some descriptions that overlap with the first embodiment may be omitted.

[0205] The semiconductor device of the second embodiment is a planar gate type vertical MOSFET 200 using silicon carbide.

[0206] Figure 9 is a schematic cross-sectional view of the semiconductor device according to the second embodiment. Figure 9 corresponds to Figure 3 of the first embodiment.

[0207] As shown in Figure 9, the source electrode wiring layer 13 of the MOSFET 200 does not include any portion that is in direct contact with the second p region 37 or in contact with a silicide layer in between, other than the third contact portion 13x.

[0208] The source electrode wiring layer 13 of MOSFET200 does not have the fifth contact portion 13z that the comparative example MOSFET900 shown in Figure 5 has. Therefore, when a voltage positive to the drain electrode 15 is applied to the source electrode 12 and the source electrode wiring layer 13, current flows into the second p region 37 only from the source electrode 12 through the second contact portion 12y.

[0209] Therefore, compared to MOSFET900, the current flowing into the second p-region 37 is smaller. As a result, the growth of stacking faults is suppressed, and the increase in on-resistance is suppressed, improving the reliability of MOSFET200.

[0210] (modified version) The semiconductor device of the modified second embodiment differs from the semiconductor device of the second embodiment in that the silicon carbide layer in the terminal region is provided between the ninth silicon carbide region and the first surface and further includes a thirteenth silicon carbide region of a second conductivity type having a higher concentration of second conductivity type impurities than the ninth and tenth silicon carbide regions, and the third contact portion is in contact with the thirteenth silicon carbide region.

[0211] A modified semiconductor device of the second embodiment is a planar gate type vertical MOSFET 201 using silicon carbide.

[0212] Figure 10 is a schematic cross-sectional view of a modified semiconductor device of the second embodiment. Figure 10 corresponds to Figure 9 of the second embodiment.

[0213] As shown in Figure 10, similar to the MOSFET 200 of the second embodiment, the source electrode wiring layer 13 does not include any portion that is in direct contact with the second p region 37 or in contact with a silicide layer in between, other than the third contact portion 13x. Therefore, the reliability of the MOSFET 201 is improved.

[0214] As shown in Figure 10, MOSFET 201 has a p-type impurity concentration higher between the second p-region 37 and the first surface F1 than between the second p-region 37 and the third p-region 38. + A third high-concentration p-region 41 (the 13th silicon carbide region) is provided in the shape.

[0215] A portion of the third contact area 13x is in contact with the third high-concentration p-region 41. Because the third contact area 13x is in contact with the third high-concentration p-region 41, the contact resistance between the source electrode wiring layer 13 and the second p-region 37 is reduced compared to the MOSFET 200.

[0216] The electrical resistance between the third contact portion 13x and the second p region 37 of MOSFET201 is higher than the electrical resistance between the fourth contact portion 13y and the third p region 38.

[0217] In MOSFET201, compared to MOSFET200, the degree to which the potential of the second p-region 37 is fixed to the potential of the source electrode wiring layer 13 is enhanced. Therefore, compared to MOSFET200, for example, the dielectric breakdown voltage of MOSFET201 is more stable.

[0218] As described above, according to the second embodiment and its modifications, a MOSFET is realized in which forward current flow in the pn junction diode is suppressed and reliability is improved.

[0219] (Third embodiment) The semiconductor device of the third embodiment differs from the semiconductor device of the first embodiment in that the wiring layer further includes a fifth contact portion in contact with the ninth silicon carbide region. Hereafter, some descriptions that overlap with the first embodiment may be omitted.

[0220] The semiconductor device of the third embodiment is a planar gate type vertical MOSFET 300 using silicon carbide.

[0221] Figure 11 is a schematic cross-sectional view of a semiconductor device according to the third embodiment. Figure 11 corresponds to Figure 3 of the first embodiment.

[0222] As shown in Figure 11, the fifth contact portion 13z of the MOSFET 300 is in direct contact with the second p region 37. The fifth contact portion 13z is not in contact with the drift region 31.

[0223] Compared to the comparative example MOSFET900, the MOSFET300 has a third silicide layer 14c and p between the fifth contact portion 13z and the second p region 37. + A third high-concentration p-region 41 (13th silicon carbide region) of the shape is not provided. Therefore, the electrical resistance between the fifth contact portion 13z of MOSFET 300 and the second p-region 37 is higher than that between the fifth contact portion 13z of MOSFET 900 and the second p-region 37.

[0224] For example, the electrical resistance between the fifth contact portion 13z and the second p region 37 of MOSFET 300 is higher than the electrical resistance between the fourth contact portion 13y and the third p region 38.

[0225] In MOSFET300, compared to MOSFET900, when a positive voltage is applied to the drain electrode 15 on the source electrode 12 and source electrode wiring layer 13, the current flowing into the second p-region 37 is smaller. Therefore, the growth of stacking faults is suppressed, and the increase in on-resistance is suppressed, thereby improving the reliability of MOSFET300.

[0226] As described above, according to the third embodiment, a MOSFET is realized in which forward current flow in the pn junction diode is suppressed, thereby improving reliability.

[0227] (Fourth embodiment) The semiconductor device of the fourth embodiment differs from the semiconductor device of the first embodiment in that the silicon carbide layer in the terminal region is provided between the ninth silicon carbide region and the first surface, and further includes a thirteenth silicon carbide region of a second conductivity type having a higher concentration of second conductivity type impurities than the ninth and tenth silicon carbide regions, and the wiring layer further includes a fifth contact portion in contact with the thirteenth silicon carbide region. Hereafter, some descriptions that overlap with the first embodiment may be omitted.

[0228] The semiconductor device of the fourth embodiment is a planar gate type vertical MOSFET 400 using silicon carbide.

[0229] Figure 12 is a schematic cross-sectional view of the semiconductor device according to the fourth embodiment. Figure 12 corresponds to Figure 3 of the first embodiment.

[0230] As shown in Figure 12, between the third silicide layer 14c and the p-shaped second p-region 37, + A third high-concentration p-region 41 (13th silicon carbide region) is provided. The p-type impurity concentration in the third high-concentration p-region 41 is higher than that in the second p-region 37 and the third p-region 38. The fifth contact portion 13z of the MOSFET 400 is in direct contact with the third high-concentration p-region 41.

[0231] Compared to the comparative example MOSFET 900, the MOSFET 400 does not have a third silicide layer 14c between the fifth contact portion 13z and the second p region 37. Therefore, the electrical resistance between the fifth contact portion 13z and the second p region 37 of MOSFET 400 is higher than that between the fifth contact portion 13z and the second p region 37 of MOSFET 900.

[0232] For example, the electrical resistance between the fifth contact portion 13z and the second p region 37 of MOSFET 400 is higher than the electrical resistance between the fourth contact portion 13y and the third p region 38.

[0233] In the MOSFET400, compared to the MOSFET900, when a positive voltage is applied to the drain electrode 15 on the source electrode 12 and source electrode wiring layer 13, the current flowing into the second p-region 37 is smaller. Therefore, the growth of stacking faults is suppressed, and the increase in on-resistance is suppressed, improving the reliability of the MOSFET400.

[0234] As described above, according to the fourth embodiment, a MOSFET is realized in which forward current flow in the pn junction diode is suppressed, thereby improving reliability.

[0235] (Fifth embodiment) The semiconductor device of the fifth embodiment differs from the semiconductor device of the first embodiment in that the silicon carbide layer in the terminal region is provided between the ninth silicon carbide region and the first surface, and further includes a thirteenth silicon carbide region of a second conductivity type having a higher concentration of second conductivity type impurities than the ninth silicon carbide region and the tenth silicon carbide region, and the ninth silicon carbide region includes a first region in contact with the third silicon carbide region and a second region surrounding the first region, separated from the first region, and in contact with the thirteenth silicon carbide region.Hereafter, some descriptions that overlap with the first embodiment may be omitted.

[0236] The semiconductor device of the fifth embodiment is a planar gate type vertical MOSFET 500 using silicon carbide.

[0237] Figure 13 is a schematic cross-sectional view of a semiconductor device according to the fifth embodiment. Figure 13 corresponds to Figure 3 of the first embodiment.

[0238] As shown in Figure 13, in MOSFET 500, between the third silicide layer 14c and the p-type second p-region 37, + A third high-concentration p-region 41 (the 13th silicon carbide region) is provided. The concentration of p-type impurities in the third high-concentration p-region 41 is higher than the concentration of p-type impurities in the second p-region 37 and the third p-region 38.

[0239] For example, the electrical resistance between the fifth contact portion 13z and the second p region 37 of MOSFET 500 is substantially the same as the electrical resistance between the fourth contact portion 13y and the third p region 38.

[0240] Furthermore, in the MOSFET500, the second p-region 37 of the p-type comprises an inner region 37a (first region) and an outer region 37b (second region). The second p-region 37 is divided into an inner region 37a and an outer region 37b.

[0241] The inner region 37a surrounds the element region 101. The inner region 37a is in contact with the outer region p 32.

[0242] The outer region 37b surrounds the inner region 37a. The outer region 37b is separated from the inner region 37a. A drift region 31 is provided between the inner region 37a and the outer region 37b. The outer region 37b is in contact with the third high-concentration p region 41.

[0243] The end of the inner region 37a on the outer region 37b side is, for example, located on the opposite side of the element region 101 from the end of the field insulating layer 24 of the termination region 102 on the element region 101 side. In other words, the end of the inner region 37a on the outer region 37b side is, for example, located on the third p region 38 side from the end of the field insulating layer 24 of the termination region 102 on the element region 101 side.

[0244] The first distance between the inner region 37a and the outer region 37b in a first direction parallel to the first plane is, for example, 0.5 to 3 times the second distance in the first direction between adjacent base regions 33 in the first direction. The first distance is, for example, 0.5 to 3 times the second distance in the first direction between the first base region 33a and the second base region 33b.

[0245] The fourth p-shaped p-region 40 is located between the drift region 31 and the inner region 37a. The fourth p-region 40 is in contact with the inner region 37a.

[0246] Compared to the comparative example MOSFET900, MOSFET500 differs in that its second p-region 37 is divided into an inner region 37a and an outer region 37b. Therefore, current flowing from, for example, the second contact portion 12y of MOSFET500 to the outer region 37b is blocked from the source electrode 12 and the source electrode wiring layer 13. Also, current flowing from, for example, the fifth contact portion 13z of MOSFET500 to the inner region 37a is blocked from the source electrode 12 and the source electrode wiring layer 13.

[0247] Therefore, compared to MOSFET900, the current flowing into the second p-region 37 from the source electrode 12 and the source electrode wiring layer 13 is reduced. As a result, the growth of stacking faults is suppressed, and the increase in on-resistance is suppressed, improving the reliability of MOSFET500.

[0248] From the viewpoint of reducing the current flowing into the second p region 37, the first distance is preferably 0.5 times or more the second distance, and more preferably 1 time or more.

[0249] Furthermore, from the viewpoint of suppressing failure during dynamic operation of the MOSFET 500, it is preferable that the end of the inner region 37a on the outer region 37b side be provided on the opposite side of the element region 101 from the end of the field insulating layer 24 of the termination region 102 on the element region 101 side.

[0250] As described above, according to the fifth embodiment, forward current flow in the pn junction diode is suppressed, and a MOSFET with improved reliability is realized.

[0251] In the first to fifth embodiments, the case of 4H-SiC as the crystal structure of SiC was described as an example, but the present invention can also be applied to devices using SiC with other crystal structures such as 6H-SiC and 3C-SiC. Furthermore, it is possible to apply a plane other than the (0001) plane to the surface of the silicon carbide layer 10.

[0252] In the first to fifth embodiments, the case where the first conductivity type is n-type and the second conductivity type is p-type has been described as an example. However, it is also possible to set the first conductivity type as p-type and the second conductivity type as n-type.

[0253] In the first to fifth embodiments, aluminum (Al) has been exemplified as the p-type impurity. However, it is also possible to use boron (B). Further, nitrogen (N) and phosphorus (P) have been exemplified as the n-type impurities. However, it is also possible to apply arsenic (As), antimony (Sb), etc.

[0254] In the first to fifth embodiments, the case where the gate electrode 18 has a stripe shape in the element region 101 has been described as an example. However, for example, the gate electrode 18 may have a mesh shape.

[0255] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. For example, the components of one embodiment may be replaced or changed with those of another embodiment. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and its equivalent scope.

Explanation of Reference Numerals

[0256] 10 Silicon carbide layer 12 Source electrode (first electrode) 12x First contact portion 12y Second contact portion 13 Source electrode wiring layer (wiring layer) 13x Third contact portion 13y Fourth contact portion 13z Fifth contact portion 14a First silicide layer 14b Second silicide layer 14c Third silicide layer 15. Drain electrode (second electrode) 16 Gate Insulation Layer 18 Guard gate 31 n-type drift region (first silicon carbide region) 31a n - Low concentration region of shape (low concentration region) 31b n-type high-concentration region (high-concentration region) 31x Part 1 31y Part 2 31z Third part 32. Outer p-region of the p-shape (third silicon carbide region) 33a p-type first base region (fourth silicon carbide region) 33b p-type second base region (fifth silicon carbide region) 33c p-type third base region (second silicon carbide region) 34. The first p-region of the p-type (the sixth silicon carbide region) 35 n + Source region of shape (7th silicon carbide region) 36 p + The first high-concentration p-region of the shape (the eighth silicon carbide region) 37. The second p-region of the p-type (the ninth silicon carbide region) 38. The third p-region of the p-type (the tenth silicon carbide region) 39 p + The second high-concentration p-region of the shape (the 11th silicon carbide region) 40 The fourth p-region of the p-type (the twelfth silicon carbide region) 41 p + The third high-concentration p-region of the shape (the 13th silicon carbide region) 100 MOSFETs (Semiconductor Devices) 101 Element Region 102 Termination area 200 MOSFETs (Semiconductor Equipment) 201 MOSFET (Semiconductor Device) 300 MOSFETs (semiconductor equipment) 400 MOSFETs (Semiconductor Devices) 500 MOSFETs (Semiconductor Devices) F1 First Side F2 Second side

Claims

1. Element region and, The system comprises a termination region surrounding the aforementioned element region, The aforementioned element region is The first electrode and The second electrode and Terminal gate and, A silicon carbide layer provided between the first electrode and the second electrode, having a first surface on the side of the first electrode and a second surface on the side of the second electrode, A first silicon carbide region of a first conductivity type having a first portion in contact with the first surface and facing the gate electrode, and a second portion in contact with the first surface and in contact with the first electrode, A second silicon carbide region of a second conductive type is provided between the first silicon carbide region and the first surface, A third silicon carbide region of second conductivity is provided between the first silicon carbide region and the first surface, and is located on the terminal side of the second silicon carbide region, and is electrically connected to the first electrode. A fourth silicon carbide region of second conductivity is provided between the first silicon carbide region and the first surface, and between the second silicon carbide region and the third silicon carbide region, facing the gate electrode and electrically connected to the first electrode, A fifth silicon carbide region of second conductivity is provided between the first silicon carbide region and the first surface, and between the second silicon carbide region and the fourth silicon carbide region, facing the gate electrode and electrically connected to the first electrode, A sixth silicon carbide region of second conductivity is provided between the first silicon carbide region and the first surface, and between the third silicon carbide region and the fourth silicon carbide region, in contact with the third silicon carbide region and the fourth silicon carbide region, and having a depth shallower than the depth of the third silicon carbide region and the depth of the fourth silicon carbide region. A seventh silicon carbide region of first conductivity type is provided between the fifth silicon carbide region and the first surface and is electrically connected to the first electrode, An eighth silicon carbide region of second conductivity, provided between the sixth silicon carbide region and the first surface, having a higher concentration of second conductivity type impurities than the sixth silicon carbide region, A silicon carbide layer containing, A first silicide layer is provided between the eighth silicon carbide region and the first electrode, A gate insulating layer is provided between the gate electrode and the fifth silicon carbide region, and between the gate electrode and the first portion. Includes, The aforementioned termination region is A wiring layer electrically connected to the first electrode, The first electrode 2, The first silicon carbide region having a third portion that is in contact with the first surface and in contact with the wiring layer, A ninth silicon carbide region of second conductivity is provided between the first silicon carbide region and the first surface, surrounding the element region and in contact with the third silicon carbide region, A second conductivity type 10 silicon carbide region is provided between the first silicon carbide region and the first surface, surrounding the 9th silicon carbide region, separated from the 9th silicon carbide region, and electrically connected to the wiring layer, A silicon carbide region is provided between the 10th silicon carbide region and the first surface, and an 11th silicon carbide region of a second conductivity type has a higher concentration of second conductivity type impurities than the 9th silicon carbide region and the 10th silicon carbide region, The silicon carbide layer containing, A second silicide layer is provided between the 11th silicon carbide region and the wiring layer, Includes, The first electrode includes a first contact portion that contacts the second portion and a second contact portion that contacts the first silicide layer. The wiring layer includes a third contact portion that contacts the third portion and a fourth contact portion that contacts the second silicide layer. The terminal region is provided between the ninth silicon carbide region and the first surface and further includes a third silicide layer in contact with the ninth silicon carbide region. A semiconductor device wherein the wiring layer further includes a fifth contact portion in contact with the third silicide layer.

2. The semiconductor device according to claim 1, wherein the concentration of second conductivity type impurities in the portion of the ninth silicon carbide region in contact with the third silicide layer is one-tenth or less of the concentration of second conductivity type impurities in the portion of the eleventh silicon carbide region in contact with the second silicide layer.

3. The semiconductor device according to claim 1, wherein the electrical resistance between the fifth contact portion and the ninth silicon carbide region is higher than the electrical resistance between the fourth contact portion and the tenth silicon carbide region.

4. The semiconductor device according to claim 1, wherein the first silicon carbide region of the element region comprises a low-concentration region and a high-concentration region provided between the low-concentration region and the first surface, the first conductivity type impurity concentration being higher than that of the low-concentration region, and the second silicon carbide region, the third silicon carbide region, the fourth silicon carbide region, and the fifth silicon carbide region are provided between the high-concentration region and the first surface.

5. The semiconductor device according to claim 1, wherein the silicon carbide layer in the terminal region further includes a twelfth silicon carbide region of second conductivity, provided between the first silicon carbide region and the ninth silicon carbide region, and separated from the third silicon carbide region in a first direction parallel to the first plane.

6. Element region and, The system comprises a termination region surrounding the aforementioned element region, The aforementioned element region is The first electrode and The second electrode and Terminal gate and, A silicon carbide layer provided between the first electrode and the second electrode, having a first surface on the side of the first electrode and a second surface on the side of the second electrode, A first silicon carbide region of a first conductivity type having a first portion in contact with the first surface and facing the gate electrode, and a second portion in contact with the first surface and in contact with the first electrode, A second silicon carbide region of a second conductive type is provided between the first silicon carbide region and the first surface, A third silicon carbide region of second conductivity is provided between the first silicon carbide region and the first surface, and is provided on the terminal side of the second silicon carbide region, and is electrically connected to the first electrode. A fourth silicon carbide region of second conductivity is provided between the first silicon carbide region and the first surface, and between the second silicon carbide region and the third silicon carbide region, facing the gate electrode and electrically connected to the first electrode, A fifth silicon carbide region of second conductivity is provided between the first silicon carbide region and the first surface, and between the second silicon carbide region and the fourth silicon carbide region, facing the gate electrode and electrically connected to the first electrode, A sixth silicon carbide region of second conductivity is provided between the first silicon carbide region and the first surface, and between the third silicon carbide region and the fourth silicon carbide region, in contact with the third silicon carbide region and the fourth silicon carbide region, and having a depth shallower than the depth of the third silicon carbide region and the depth of the fourth silicon carbide region. A seventh silicon carbide region of first conductivity type is provided between the fifth silicon carbide region and the first surface and is electrically connected to the first electrode, An eighth silicon carbide region of second conductivity, provided between the sixth silicon carbide region and the first surface, having a higher concentration of second conductivity type impurities than the sixth silicon carbide region, A silicon carbide layer containing, A first silicide layer is provided between the eighth silicon carbide region and the first electrode, A gate insulating layer is provided between the gate electrode and the fifth silicon carbide region, and between the gate electrode and the first portion. Includes, The aforementioned termination region is A wiring layer electrically connected to the first electrode, The first electrode 2, The first silicon carbide region having a third portion that is in contact with the first surface and in contact with the wiring layer, A ninth silicon carbide region of second conductivity is provided between the first silicon carbide region and the first surface, surrounding the element region and in contact with the third silicon carbide region, A second conductivity type 10 silicon carbide region is provided between the first silicon carbide region and the first surface, surrounding the 9th silicon carbide region, separated from the 9th silicon carbide region, and electrically connected to the wiring layer, A silicon carbide region is provided between the 10th silicon carbide region and the first surface, and an 11th silicon carbide region of a second conductivity type has a higher concentration of second conductivity type impurities than the 9th silicon carbide region and the 10th silicon carbide region, The silicon carbide layer containing, A second silicide layer is provided between the 11th silicon carbide region and the wiring layer, Includes, The first electrode includes a first contact portion that contacts the second portion and a second contact portion that contacts the first silicide layer. The wiring layer includes a third contact portion that contacts the third portion and a fourth contact portion that contacts the second silicide layer. A semiconductor device wherein the wiring layer does not include any portion that is in direct contact with the ninth silicon carbide region or with a silicide layer in between, other than the third contact portion.

7. The silicon carbide layer in the terminal region further includes a thirteenth silicon carbide region of a second conductivity type having a higher concentration of second conductivity type impurities than the ninth silicon carbide region and the tenth silicon carbide region, provided between the ninth silicon carbide region and the first surface. The semiconductor device according to claim 6, wherein the third contact portion is in contact with the thirteenth silicon carbide region.

8. The semiconductor device according to claim 7, wherein the electrical resistance between the third contact portion and the ninth silicon carbide region is higher than the electrical resistance between the fourth contact portion and the tenth silicon carbide region.

9. The semiconductor device according to claim 6, wherein the first silicon carbide region of the element region has a low-concentration region and a high-concentration region provided between the low-concentration region and the first surface, the first conductivity type impurity concentration being higher than that of the low-concentration region, and the second silicon carbide region, the third silicon carbide region, the fourth silicon carbide region, and the fifth silicon carbide region are provided between the high-concentration region and the first surface.

10. The semiconductor device according to claim 6, wherein the silicon carbide layer in the terminal region further includes a twelfth silicon carbide region of second conductivity, provided between the first silicon carbide region and the ninth silicon carbide region, and separated from the third silicon carbide region in a first direction parallel to the first plane.

11. Element region and, The system comprises a termination region surrounding the aforementioned element region, The aforementioned element region is The first electrode and The second electrode and Terminal gate and, A silicon carbide layer provided between the first electrode and the second electrode, having a first surface on the side of the first electrode and a second surface on the side of the second electrode, A first silicon carbide region of a first conductivity type having a first portion in contact with the first surface and facing the gate electrode, and a second portion in contact with the first surface and in contact with the first electrode, A second silicon carbide region of a second conductive type is provided between the first silicon carbide region and the first surface, A third silicon carbide region of second conductivity is provided between the first silicon carbide region and the first surface, and is provided on the terminal side of the second silicon carbide region, and is electrically connected to the first electrode. A fourth silicon carbide region of second conductivity is provided between the first silicon carbide region and the first surface, and between the second silicon carbide region and the third silicon carbide region, facing the gate electrode and electrically connected to the first electrode, A fifth silicon carbide region of second conductivity is provided between the first silicon carbide region and the first surface, and between the second silicon carbide region and the fourth silicon carbide region, facing the gate electrode and electrically connected to the first electrode, A sixth silicon carbide region of second conductivity is provided between the first silicon carbide region and the first surface, and between the third silicon carbide region and the fourth silicon carbide region, in contact with the third silicon carbide region and the fourth silicon carbide region, and having a depth shallower than the depth of the third silicon carbide region and the depth of the fourth silicon carbide region. A seventh silicon carbide region of first conductivity type is provided between the fifth silicon carbide region and the first surface and is electrically connected to the first electrode, An eighth silicon carbide region of second conductivity, provided between the sixth silicon carbide region and the first surface, having a higher concentration of second conductivity type impurities than the sixth silicon carbide region, A silicon carbide layer containing, A first silicide layer is provided between the eighth silicon carbide region and the first electrode, A gate insulating layer is provided between the gate electrode and the fifth silicon carbide region, and between the gate electrode and the first portion. Includes, The aforementioned termination region is A wiring layer electrically connected to the first electrode, The first electrode 2, The first silicon carbide region having a third portion that is in contact with the first surface and in contact with the wiring layer, A ninth silicon carbide region of second conductivity is provided between the first silicon carbide region and the first surface, surrounding the element region and in contact with the third silicon carbide region, A second conductivity type 10 silicon carbide region is provided between the first silicon carbide region and the first surface, surrounding the 9th silicon carbide region, separated from the 9th silicon carbide region, and electrically connected to the wiring layer, A silicon carbide region is provided between the 10th silicon carbide region and the first surface, and an 11th silicon carbide region of a second conductivity type has a higher concentration of second conductivity type impurities than the 9th silicon carbide region and the 10th silicon carbide region, The silicon carbide layer containing, A second silicide layer is provided between the 11th silicon carbide region and the wiring layer, Includes, The first electrode includes a first contact portion that contacts the second portion and a second contact portion that contacts the first silicide layer. The wiring layer includes a third contact portion that contacts the third portion and a fourth contact portion that contacts the second silicide layer. The semiconductor device further includes a fifth contact portion in contact with the ninth silicon carbide region, wherein the wiring layer is in contact with the ninth silicon carbide region.

12. The semiconductor device according to claim 11, wherein the fifth contact portion does not come into contact with the first silicon carbide region.

13. The semiconductor device according to claim 11, wherein the electrical resistance between the fifth contact portion and the ninth silicon carbide region is higher than the electrical resistance between the fourth contact portion and the tenth silicon carbide region.

14. The semiconductor device according to claim 11, wherein the first silicon carbide region of the element area comprises a low-concentration region and a high-concentration region provided between the low-concentration region and the first surface, having a higher concentration of the first conductive type impurity than the low-concentration region, and the second silicon carbide region, the third silicon carbide region, the fourth silicon carbide region, and the fifth silicon carbide region are provided between the high-concentration region and the first surface.

15. The semiconductor device according to claim 11, wherein the silicon carbide layer in the terminal region further includes a twelfth silicon carbide region of second conductivity, provided between the first silicon carbide region and the ninth silicon carbide region, and separated from the third silicon carbide region in a first direction parallel to the first plane.

16. Element region and, The system comprises a termination region surrounding the aforementioned element region, The aforementioned element region is The first electrode and The second electrode and Terminal gate and, A silicon carbide layer provided between the first electrode and the second electrode, having a first surface on the side of the first electrode and a second surface on the side of the second electrode, A first silicon carbide region of a first conductivity type having a first portion in contact with the first surface and facing the gate electrode, and a second portion in contact with the first surface and in contact with the first electrode, A second silicon carbide region of a second conductive type is provided between the first silicon carbide region and the first surface, A third silicon carbide region of second conductivity is provided between the first silicon carbide region and the first surface, and is provided on the terminal side of the second silicon carbide region, and is electrically connected to the first electrode. A fourth silicon carbide region of second conductivity is provided between the first silicon carbide region and the first surface, and between the second silicon carbide region and the third silicon carbide region, facing the gate electrode and electrically connected to the first electrode, A fifth silicon carbide region of second conductivity is provided between the first silicon carbide region and the first surface, and between the second silicon carbide region and the fourth silicon carbide region, facing the gate electrode and electrically connected to the first electrode, A sixth silicon carbide region of second conductivity is provided between the first silicon carbide region and the first surface, and between the third silicon carbide region and the fourth silicon carbide region, in contact with the third silicon carbide region and the fourth silicon carbide region, and having a depth shallower than the depth of the third silicon carbide region and the depth of the fourth silicon carbide region. A seventh silicon carbide region of first conductivity type is provided between the fifth silicon carbide region and the first surface and is electrically connected to the first electrode, An eighth silicon carbide region of second conductivity, provided between the sixth silicon carbide region and the first surface, having a higher concentration of second conductivity type impurities than the sixth silicon carbide region, A silicon carbide layer containing, A first silicide layer is provided between the eighth silicon carbide region and the first electrode, A gate insulating layer is provided between the gate electrode and the fifth silicon carbide region, and between the gate electrode and the first portion. Includes, The aforementioned termination region is A wiring layer electrically connected to the first electrode, The first electrode 2, The first silicon carbide region having a third portion that is in contact with the first surface and in contact with the wiring layer, A ninth silicon carbide region of second conductivity is provided between the first silicon carbide region and the first surface, surrounding the element region and in contact with the third silicon carbide region, A second conductivity type 10 silicon carbide region is provided between the first silicon carbide region and the first surface, surrounding the 9th silicon carbide region, separated from the 9th silicon carbide region, and electrically connected to the wiring layer, A silicon carbide region is provided between the 10th silicon carbide region and the first surface, and an 11th silicon carbide region of a second conductivity type has a higher concentration of second conductivity type impurities than the 9th silicon carbide region and the 10th silicon carbide region, The silicon carbide layer containing, A second silicide layer is provided between the 11th silicon carbide region and the wiring layer, Includes, The first electrode includes a first contact portion that contacts the second portion and a second contact portion that contacts the first silicide layer. The wiring layer includes a third contact portion that contacts the third portion and a fourth contact portion that contacts the second silicide layer. The silicon carbide layer in the terminal region further includes a thirteenth silicon carbide region of a second conductivity type having a higher concentration of second conductivity type impurities than the ninth silicon carbide region and the tenth silicon carbide region, provided between the ninth silicon carbide region and the first surface. The semiconductor device further includes a fifth contact portion in contact with the thirteenth silicon carbide region of the wiring layer.

17. The semiconductor device according to claim 16, wherein no silicide layer is provided between the fifth contact portion and the ninth silicon carbide region.

18. The semiconductor device according to claim 16, wherein the electrical resistance between the fifth contact portion and the ninth silicon carbide region is higher than the electrical resistance between the fourth contact portion and the tenth silicon carbide region.

19. The semiconductor device according to claim 16, wherein the first silicon carbide region of the element area has a low-concentration region and a high-concentration region provided between the low-concentration region and the first surface, the first conductivity type impurity concentration being higher than that of the low-concentration region, and the second silicon carbide region, the third silicon carbide region, the fourth silicon carbide region, and the fifth silicon carbide region are provided between the high-concentration region and the first surface.

20. The semiconductor device according to claim 16, wherein the silicon carbide layer in the terminal region further includes a twelfth silicon carbide region of second conductivity, provided between the first silicon carbide region and the ninth silicon carbide region, and separated from the third silicon carbide region in a first direction parallel to the first plane.

21. Element region and, The system comprises a termination region surrounding the aforementioned element region, The aforementioned element region is The first electrode and The second electrode and Terminal gate and, A silicon carbide layer provided between the first electrode and the second electrode, having a first surface on the side of the first electrode and a second surface on the side of the second electrode, A first silicon carbide region of a first conductivity type having a first portion in contact with the first surface and facing the gate electrode, and a second portion in contact with the first surface and in contact with the first electrode, A second silicon carbide region of a second conductive type is provided between the first silicon carbide region and the first surface, A third silicon carbide region of second conductivity is provided between the first silicon carbide region and the first surface, and is provided on the terminal side of the second silicon carbide region, and is electrically connected to the first electrode. A fourth silicon carbide region of second conductivity is provided between the first silicon carbide region and the first surface, and between the second silicon carbide region and the third silicon carbide region, facing the gate electrode and electrically connected to the first electrode, A fifth silicon carbide region of second conductivity is provided between the first silicon carbide region and the first surface, and between the second silicon carbide region and the fourth silicon carbide region, facing the gate electrode and electrically connected to the first electrode, A sixth silicon carbide region of second conductivity is provided between the first silicon carbide region and the first surface, and between the third silicon carbide region and the fourth silicon carbide region, in contact with the third silicon carbide region and the fourth silicon carbide region, and having a depth shallower than the depth of the third silicon carbide region and the depth of the fourth silicon carbide region. A seventh silicon carbide region of first conductivity type is provided between the fifth silicon carbide region and the first surface and is electrically connected to the first electrode, An eighth silicon carbide region of second conductivity, provided between the sixth silicon carbide region and the first surface, having a higher concentration of second conductivity type impurities than the sixth silicon carbide region, A silicon carbide layer containing, A first silicide layer is provided between the eighth silicon carbide region and the first electrode, A gate insulating layer is provided between the gate electrode and the fifth silicon carbide region, and between the gate electrode and the first portion. Includes, The aforementioned termination region is A wiring layer electrically connected to the first electrode, The first electrode 2, The first silicon carbide region having a third portion that is in contact with the first surface and in contact with the wiring layer, A ninth silicon carbide region of second conductivity is provided between the first silicon carbide region and the first surface, surrounding the element region and in contact with the third silicon carbide region, A second conductivity type 10 silicon carbide region is provided between the first silicon carbide region and the first surface, surrounding the 9th silicon carbide region, separated from the 9th silicon carbide region, and electrically connected to the wiring layer, A silicon carbide region is provided between the 10th silicon carbide region and the first surface, and an 11th silicon carbide region of a second conductivity type has a higher concentration of second conductivity type impurities than the 9th silicon carbide region and the 10th silicon carbide region, A thirteenth silicon carbide region of a second conductivity type is provided between the ninth silicon carbide region and the first surface, and has a higher concentration of second conductivity type impurities than the ninth silicon carbide region and the tenth silicon carbide region. The silicon carbide layer containing, A second silicide layer is provided between the 11th silicon carbide region and the wiring layer, Includes, A third silicide layer is provided between the 13th silicon carbide region and the wiring layer, Includes, The first electrode includes a first contact portion that contacts the second portion and a second contact portion that contacts the first silicide layer. The wiring layer includes a third contact portion in contact with the third portion, a fourth contact portion in contact with the second silicide layer, and a fifth contact portion in contact with the third silicide layer. A semiconductor device wherein the ninth silicon carbide region includes a first region adjacent to the third silicon carbide region and a second region surrounding the first region, separated from the first region, and adjacent to the thirteenth silicon carbide region.

22. The semiconductor device according to claim 21, wherein the first silicon carbide region is provided between the first region and the second region.

23. The semiconductor device according to claim 21, wherein the first distance between the first region and the second region in a first direction parallel to the first plane is 0.5 to 3 times the second distance between the fourth silicon carbide region and the fifth silicon carbide region in the first direction.

24. The semiconductor device according to claim 21, wherein the first silicon carbide region of the element region has a low-concentration region and a high-concentration region provided between the low-concentration region and the first surface, the first conductivity type impurity concentration being higher than that of the low-concentration region, and the second silicon carbide region, the third silicon carbide region, the fourth silicon carbide region, and the fifth silicon carbide region are provided between the high-concentration region and the first surface.

25. The semiconductor device according to claim 21, wherein the silicon carbide layer in the terminal region further includes a twelfth silicon carbide region of second conductivity, provided between the first silicon carbide region and the first silicon carbide region, in contact with the first region, and separated from the third silicon carbide region in a first direction parallel to the first plane.

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