Semiconductor equipment

Abstract

To provide a semiconductor device with reduced on-resistance. [Solution] The semiconductor device of the embodiment includes a first silicon carbide region of a first conductivity type, a second silicon carbide region of a second conductivity type extending in a first direction and above the first silicon carbide region, a third silicon carbide region of a second conductivity type extending in a first direction and above the first silicon carbide region, a fifth silicon carbide region of a first conductivity type above the second silicon carbide region, a sixth silicon carbide region of a first conductivity type above the third silicon carbide region, and the second silicon carbide region and the third silicon carbide The silicon carbide layer includes an eighth silicon carbide region of a second conductivity type between it and an elementary region, and a ninth silicon carbide region of a second conductivity type located between the second silicon carbide region and the third silicon carbide region and separated from the eighth silicon carbide region in a first direction; a first electrode including a first portion in contact with the eighth silicon carbide region and a second portion in contact with the ninth silicon carbide region; a gate electrode surrounding the first portion and the second portion; and a second electrode.

Description

[Technical Field]

[0001] Embodiments of the present invention relate to semiconductor devices. [Background technology]

[0002] Silicon carbide is a material used in semiconductor devices. Compared to silicon, silicon carbide has superior physical properties, with a band gap approximately three times larger, a breakdown field strength approximately ten times greater, and a thermal conductivity approximately three times greater. By utilizing these properties, it is possible to realize, for example, metal oxide semiconductor field effect transistors (MOSFETs) that are capable of high voltage resistance, low loss, and high-temperature operation. To improve the characteristics of vertical MOSFETs using silicon carbide, it is desirable to reduce the on-resistance of the MOSFET. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Patent No. 5036479 [Patent Document 2] Patent No. 6687476 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] The problem that this invention aims to solve is to provide a semiconductor device with reduced on-resistance. [Means for solving the problem]

[0005] The semiconductor device of the embodiment is a silicon carbide layer having a first surface and a second surface facing the first surface, comprising: a first silicon carbide region of a first conductivity type; a second silicon carbide region of a second conductivity type provided between the first silicon carbide region and the first surface and extending in a first direction parallel to the first surface; a third silicon carbide region of a second conductivity type provided between the first silicon carbide region and the first surface and extending in a first direction, and separated from the second silicon carbide region in a second direction parallel to the first surface and perpendicular to the first direction; and the first silicon carbide region and the first surface A fourth silicon carbide region of a second conductivity type is provided between the first and second silicon carbide regions, extending in the first direction and separated from the third silicon carbide region in the second direction; a fifth silicon carbide region of a first conductivity type is provided between the second silicon carbide region and the first surface and extending in the first direction; a sixth silicon carbide region of a first conductivity type is provided between the third silicon carbide region and the first surface and extending in the first direction; a seventh silicon carbide region of a first conductivity type is provided between the fourth silicon carbide region and the first surface and extending in the first direction; and between the first silicon carbide region and the first surface A silicon carbide layer comprising: an eighth silicon carbide region of second conductivity provided between the second silicon carbide region and the third silicon carbide region and in contact with the second and third silicon carbide regions; a ninth silicon carbide region of second conductivity provided between the first silicon carbide region and the first surface and between the second and third silicon carbide regions and in contact with the second and third silicon carbide regions and separated from the eighth silicon carbide region in the first direction; a first portion in contact with the eighth silicon carbide region; and the ninth silicon carbide region of second conductivity provided between the first and first surfaces and between the second and third silicon carbide regions and in contact with the second and third silicon carbide regions and separated from the eighth silicon carbide region in the first direction; a first portion in contact with the eighth silicon carbide region; and the ninth A first electrode provided on the side of the first surface of the silicon carbide layer, which includes a second portion in contact with the silicon carbide region, is electrically connected to the fifth silicon carbide region, the sixth silicon carbide region, and the seventh silicon carbide region, and faces the first silicon carbide region, the second silicon carbide region, the third silicon carbide region, the fourth silicon carbide region, the fifth silicon carbide region, the sixth silicon carbide region, and the seventh silicon carbide region, and surrounds the first portion and the second portion, and the first silicon carbide region, the second silicon carbide region, the third silicon carbide region,A gate insulating layer provided between the fourth silicon carbide region, the fifth silicon carbide region, the sixth silicon carbide region, and the seventh silicon carbide region and the gate electrode, and a second electrode provided on the side of the second surface of the silicon carbide layer.

Brief Description of the Drawings

[0006] [Figure 1] Schematic cross-sectional view of the semiconductor device of the first embodiment. [Figure 2] Schematic cross-sectional view of the semiconductor device of the first embodiment. [Figure 3] Schematic cross-sectional view of the semiconductor device of the first embodiment. [Figure 4] Schematic top view of the semiconductor device of the first embodiment. [Figure 5] Schematic top view of the semiconductor device of the first embodiment. [Figure 6] Schematic cross-sectional view of the semiconductor device of the comparative example. [Figure 7] Schematic top view of the semiconductor device of the comparative example. [Figure 8] Schematic top view of the semiconductor device of the comparative example. <00#Schematic cross-sectional view of the semiconductor device of the first modification of the first embodiment. [Figure 10] Schematic cross-sectional view of the semiconductor device of the second modification of the first embodiment. [Figure 11] Schematic cross-sectional view of the semiconductor device of the second embodiment. [Figure 12] Schematic cross-sectional view of the semiconductor device of the second embodiment. [Figure 13] Schematic cross-sectional view of the semiconductor device of the second embodiment. <000# [Figure 14] Schematic top view of the semiconductor device of the second embodiment. [Figure 15] Schematic top view of the semiconductor device of the second embodiment. [Figure 16] Schematic cross-sectional view of the semiconductor device of the third embodiment. [Figure 17] Schematic cross-sectional view of the semiconductor device of the third embodiment. [Figure 18]Schematic cross-sectional view of the semiconductor device of the third embodiment. [Figure 19] Schematic top view of the semiconductor device of the third embodiment. [Figure 20] Schematic top view of the semiconductor device of the third embodiment.

Embodiments for Carrying Out the Invention

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same or similar members are denoted by the same reference numerals, and the description of the members once described may be omitted as appropriate.

[0008] Also, in the following description, n + 、n、n - and, p + 、p、p - When there is such notation, these notations represent the relative levels of impurity concentrations in each conductivity type. That is, n + has a relatively higher n-type impurity concentration than n, and n - has a relatively lower n-type impurity concentration than n. Also, p + has a relatively higher p-type impurity concentration than p, and p - has a relatively lower p-type impurity concentration than p. Note that n + type, n - type may be simply referred to as n-type, p + type, p - type may be simply referred to as p-type.

[0009] Impurity concentration can be measured, for example, by Secondary Ion Mass Spectrometry (SIMS). The relative levels of impurity concentration can also be determined, for example, from the carrier concentration obtained by Scanning Capacitance Microscopy (SCM). Furthermore, distances such as the width and depth of impurity regions can be determined, for example, by SIMS. Also, distances such as the width and depth of impurity regions can be determined, for example, from SCM images or Scanning Electron Microscope (SEM) images. In addition, the thickness of the insulating layer can be measured, for example, on images from SIMS, SEM, or Transmission Electron Microscope (TEM).

[0010] In this specification, "p-type impurity concentration" in the p-type silicon carbide region refers to the net p-type impurity concentration obtained by subtracting the n-type impurity concentration in that region from the p-type impurity concentration in that region. Similarly, "n-type impurity concentration" in the n-type silicon carbide region refers to the net n-type impurity concentration obtained by subtracting the p-type impurity concentration in that region from the n-type impurity concentration in that region.

[0011] Furthermore, unless otherwise stated in the specification, the impurity concentration in a particular region shall mean the maximum impurity concentration in that region.

[0012] (First embodiment) The semiconductor device of the first embodiment is a silicon carbide layer having a first surface and a second surface facing the first surface, comprising: a first silicon carbide region of a first conductivity type; a second silicon carbide region of a second conductivity type provided between the first silicon carbide region and the first surface and extending in a first direction parallel to the first surface; a third silicon carbide region of a second conductivity type provided between the first silicon carbide region and the first surface and extending in a first direction, and separated from the second silicon carbide region in a second direction parallel to the first surface and perpendicular to the first direction; a fourth silicon carbide region of a second conductivity type provided between the first silicon carbide region and the first surface and extending in a first direction, and separated from the third silicon carbide region in a second direction; and a fifth silicon carbide region of a first conductivity type provided between the second silicon carbide region and the first surface and extending in a first direction. A silicon carbide region, a sixth silicon carbide region of first conductivity type provided between the third silicon carbide region and the first surface and extending in the first direction, a seventh silicon carbide region of first conductivity type provided between the fourth silicon carbide region and the first surface and extending in the first direction, a second silicon carbide region provided between the second silicon carbide region and the third silicon carbide region and the second silicon carbide region The silicon carbide layer includes an eighth silicon carbide region of a second conductivity type that is in contact with the silicon carbide region and the third silicon carbide region, and a ninth silicon carbide region of a second conductivity type that is provided between the first silicon carbide region and the first surface, and between the second silicon carbide region and the third silicon carbide region, is in contact with the second and third silicon carbide regions, and is separated from the eighth silicon carbide region in a first direction. Furthermore, the semiconductor device of the first embodiment includes a first portion in contact with the eighth silicon carbide region and a second portion in contact with the ninth silicon carbide region, and is electrically connected to the fifth silicon carbide region, the sixth silicon carbide region and the seventh silicon carbide region, and includes a first electrode provided on the first surface side of the silicon carbide layer, and the first silicon carbide region, the second silicon carbide region, the third silicon carbide region, the fourth silicon carbide region and the fifth silicon carbide region The device comprises a gate electrode facing the region, the sixth silicon carbide region, and the seventh silicon carbide region, and surrounding the first and second portions; a gate insulating layer provided between the first silicon carbide region, the second silicon carbide region, the third silicon carbide region, the fourth silicon carbide region, the fifth silicon carbide region, the sixth silicon carbide region, and the seventh silicon carbide region and the gate electrode; and a second electrode provided on the side of the second surface of the silicon carbide layer.

[0013] Furthermore, in the semiconductor device of the first embodiment, the silicon carbide layer comprises: a 10th silicon carbide region of second conductivity type provided between the first silicon carbide region and the first surface, extending in a first direction and separated from the fourth silicon carbide region in a second direction; an 11th silicon carbide region of first conductivity type provided between the 10th silicon carbide region and the first surface, extending in a first direction; and a 4th silicon carbide region and a 10th silicon carbide region provided between the first silicon carbide region and the first surface, and between the fourth silicon carbide region and the 10th silicon carbide region. The first electrode further includes a twelfth silicon carbide region of second conductivity that is in contact with the first silicon carbide region and the first surface, and a thirteenth silicon carbide region of second conductivity that is located between the first silicon carbide region and the first surface, and between the fourth silicon carbide region and the tenth silicon carbide region, in contact with the fourth silicon carbide region and the tenth silicon carbide region, and separated from the twelfth silicon carbide region in a first direction, and the first electrode further includes a third portion in contact with the twelfth silicon carbide region and a fourth portion in contact with the thirteenth silicon carbide region, and the gate electrode surrounds the third portion and the fourth portion.

[0014] Furthermore, in the semiconductor device of the first embodiment, the third portion is located in the second direction of the first portion, and the fourth portion is located in the second direction of the first portion.

[0015] The semiconductor device of the first embodiment is a planar gate type vertical MOSFET 100 using silicon carbide. The MOSFET 100 of the first embodiment is a Double Implantation MOSFET (DIMOSFET) in which the base region and source region are formed by ion implantation, for example.

[0016] The following explanation will use the case where the first conductivity type is n-type and the second conductivity type is p-type as an example. MOSFET100 is a vertical n-channel MOSFET that uses electrons as carriers.

[0017] Figures 1, 2, and 3 are schematic cross-sectional views of a semiconductor device according to the first embodiment. Figures 4 and 5 are schematic top views of a semiconductor device according to the first embodiment. Figure 4 is a schematic diagram showing the gate electrode and source electrode patterns on the upper surface of the silicon carbide layer. Figure 5 is a schematic diagram showing the silicon carbide region and source electrode patterns on the first surface of the silicon carbide layer. Figure 1 is a cross-sectional view AA' of Figures 4 and 5. Figure 2 is a cross-sectional view BB' of Figures 4 and 5. Figure 3 is a cross-sectional view CC' of Figures 4 and 5.

[0018] The MOSFET 100 comprises a silicon carbide layer 10, a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a gate insulating layer 16, a gate electrode 18, and an interlayer insulating layer 20. The source electrode 12 includes a metal silicide layer 12s and a metal layer 12m. The source electrode 12 includes a contact portion 12x. The contact portion 12x includes a first contact portion 12x1 (first part), a second contact portion 12x2 (second part), a third contact portion 12x3 (third part), and a fourth contact portion 12x4 (fourth part).

[0019] Within the silicon carbide layer 10, n + Shape of drain region 22, n - The drift region 24 of the p-type (first silicon carbide region), the base region 26 of the p-type, the base connection region 28 of the p-type, the source region 30 of the n-type, n + The p-shaped base region 26 includes a contact region 32. The p-shaped base region 26 includes a first base region 26a (second silicon carbide region), a second base region 26b (third silicon carbide region), a third base region 26c (fourth silicon carbide region), and a fourth base region 26d (tenth silicon carbide region). The p-shaped base connection region 28 includes a first base connection region 28a (eighth silicon carbide region), a second base connection region 28b (ninth silicon carbide region), a third base connection region 28c (twelfth silicon carbide region), and a fourth base connection region 28d (thirteenth silicon carbide region). The n-type source region 30 includes the first source region 30a (the fifth silicon carbide region), the second source region 30b (the sixth silicon carbide region), the third source region 30c (the seventh silicon carbide region), and the fourth source region 30d (the eleventh silicon carbide region).

[0020] The silicon carbide layer 10 is provided between the source electrode 12 and the drain electrode 14. The silicon carbide layer 10 is single-crystal SiC. For example, the silicon carbide layer 10 is 4H-SiC.

[0021] The silicon carbide layer 10 comprises a first surface ("F1" in Figure 1) and a second surface ("F2" in Figure 1). The first surface F1 is the surface of the silicon carbide layer. The second surface F2 is the back surface of the silicon carbide layer. Hereinafter, the first surface F1 may be referred to as the surface and the second surface F2 as the back surface. The first surface F1 is located on the source electrode 12 side of the silicon carbide layer 10. The second surface F2 is located on the drain electrode 14 side of the silicon carbide layer 10. The first surface F1 and the second surface F2 face each other. Hereinafter, "depth" refers to the depth in the direction toward the second surface with respect to the first surface. The "surfaces" of the first surface F1 and the second surface F2 refer to, for example, the interface between the silicon carbide layer and the insulating film, or between the silicon carbide layer and the metal.

[0022] The first and second directions are parallel to the first face F1. The second direction is perpendicular to the first direction. The third direction is perpendicular to the first face F1.

[0023] The first surface F1 is, for example, a surface inclined at an angle of 0 to 8 degrees relative to the (0001) surface. The second surface F2 is, for example, a surface inclined at an angle of 0 to 8 degrees relative to the (000-1) surface. The (0001) surface is referred to as the silicon surface. The (000-1) surface is referred to as the carbon surface.

[0024] n + The drain region 22 is provided on the back side of the silicon carbide layer 10. The drain region 22 contains, for example, nitrogen (N) as an n-type impurity. The concentration of n-type impurities in the drain region 22 is, for example, 1 × 10⁻⁶ 18 cm -3 The above 1 x 10 21 cm -3 The following applies:

[0025] n -The shaped drift region 24 is provided between the drain region 22 and the first surface F1. - The drift region 24 is provided between the source electrode 12 and the drain electrode 14. - The drift region 24 is provided between the gate electrode 18 and the drain electrode 14.

[0026] n - The drift region 24 is located on the drain region 22. The drift region 24 contains, for example, nitrogen (N) as an n-type impurity. The concentration of n-type impurities in the drift region 24 is lower than the concentration of n-type impurities in the drain region 22. The concentration of n-type impurities in the drift region 24 is, for example, 4 × 10⁻⁶. 14 cm -3 The above 5 x 10 17 cm -3 The following applies: The thickness of the drift region 24 is, for example, between 3 μm and 150 μm.

[0027] A portion of the drift region 24 is in contact with the first surface F1.

[0028] The drift region 24 has the function of supplying current when the MOSFET 100 is ON.

[0029] The p-shaped base region 26 is provided between the drift region 24 and the first surface F1. The base region 26 extends linearly in the first direction. The base region 26 is repeatedly arranged in the second direction. A drift region 24 is provided between two adjacent base regions 26 in the second direction.

[0030] The base region 26 functions as the channel region of the MOSFET 100.

[0031] The first base region 26a is provided between the drift region 24 and the first surface F1. The second base region 26b is provided between the drift region 24 and the first surface F1. The third base region 26c is provided between the drift region 24 and the first surface F1. The fourth base region 26d is provided between the drift region 24 and the first surface F1.

[0032] The second base region 26b separates from the first base region 26a in a second direction. The third base region 26c separates from the second base region 26b in a second direction. The fourth base region 26d separates from the third base region 26c in a second direction.

[0033] The base region 26 contains, for example, aluminum (Al) as a p-type impurity. The concentration of p-type impurities in the base region 26 is, for example, 5 × 10⁻⁶. 16 cm -3 The above 5 x 10 18 cm -3 The following applies:

[0034] The length of the base region 26 in the second direction is, for example, 0.5 μm or more and 2 μm or less. The distance between two adjacent base regions in the second direction is, for example, 0.5 μm or more and 2 μm or less.

[0035] The depth of the base region 26 is, for example, between 1 μm and 2 μm.

[0036] The base region 26 is electrically connected to the source electrode 12. The base region 26 is fixed at the potential of the source electrode 12.

[0037] A portion of the base region 26 is in contact with the first surface F1. A portion of the base region 26 faces the gate electrode 18. A portion of the base region 26 becomes the channel region of the MOSFET 100. A gate insulating layer 16 is sandwiched between a portion of the base region 26 and the gate electrode 18.

[0038] The p-shaped base connection region 28 is provided between the drift region 24 and the first surface F1. The base connection region 28 is provided between two adjacent base regions 26 in the second direction. The base connection region 28 is in contact with two adjacent base regions 26 in the second direction.

[0039] The base connection regions 28 are repeatedly arranged in a first direction. A drift region 24 is provided between two adjacent base connection regions 28 in the first direction.

[0040] The first base connection region 28a is provided between the first base region 26a and the second base region 26b. The first base connection region 28a is in contact with the first base region 26a and the second base region 26b.

[0041] The second base connection region 28b is provided between the first base region 26a and the second base region 26b. The second base connection region 28b is in contact with both the first base region 26a and the second base region 26b.

[0042] The second base connection region 28b is separated from the first base connection region 28a in a first direction. A drift region 24 is provided between the second base connection region 28b and the first base connection region 28a.

[0043] The third base connection region 28c is provided between the third base region 26c and the fourth base region 26d. The third base connection region 28c is in contact with the third base region 26c and the fourth base region 26d.

[0044] The fourth base connection region 28d is provided between the third base region 26c and the fourth base region 26d. The fourth base connection region 28d is in contact with the third base region 26c and the fourth base region 26d.

[0045] The fourth base connection region 28d is separated from the third base connection region 28c in a first direction. A drift region 24 is provided between the fourth base connection region 28d and the third base connection region 28c.

[0046] The third base connection region 28c is provided in a first direction relative to the first base connection region 28a. The fourth base connection region 28d is provided in a first direction relative to the second base connection region 28b.

[0047] Two base regions 26, each with a base connection region 28 between them, and two base regions 26, each without a base connection region 28 between them, are repeatedly arranged in a second direction. For example, no base connection region 28 is provided between the second base region 26b and the third base region 26c.

[0048] The base connection region 28 contains, for example, aluminum (Al) as a p-type impurity. The concentration of p-type impurities in the base connection region 28 is, for example, 5 × 10⁻⁶ 16 cm -3 The above 5 x 10 18 cm -3 The following applies:

[0049] For example, a portion of the base connection region 28 that is in contact with the source electrode may have a high concentration of p-type impurities. The concentration of p-type impurities in the portion with a high concentration of p-type impurities may be, for example, 1 × 10⁻⁶. 19 cm -3 The above 5 x 10 21 cm -3 The following applies:

[0050] The length of the base connection region 28 in the first direction is, for example, 2 μm or more and 5 μm or less. The distance in the first direction between two adjacent base connection regions 28 is, for example, 5 μm or more and 100 μm or less.

[0051] The distance in the first direction between two adjacent base connection regions 28 is, for example, 1.5 times or more and 50 times or less the length of the base connection region 28 in the first direction.

[0052] The distance in the first direction between the first base connection region 28a and the second base connection region 28b (D1 in Figure 3) is, for example, 1.5 to 50 times the length of the first base connection region 28a in the first direction (L1 in Figure 3). Also, the distance in the first direction between the third base connection region 28c and the fourth base connection region 28d is, for example, 1.5 to 50 times the length of the third base connection region 28c in the first direction.

[0053] The distance in the first direction between two adjacent base connection regions 28 is, for example, between 2 and 50 times the distance in the second direction between two adjacent base regions 26.

[0054] The distance in the first direction between the first base connection region 28a and the second base connection region 28b (D1 in Figure 3) is, for example, between 2 and 50 times the distance in the second direction between the first base region 26a and the second base region 26b (D2 in Figure 2). Also, the distance in the first direction between the third base connection region 28c and the fourth base connection region 28d is, for example, between 2 and 50 times the distance in the second direction between the third base region 26c and the fourth base region 26d.

[0055] The depth of the base connection region 28 is, for example, shallower than the depth of the base region 26. The depth of the base connection region 28 is, for example, between one-tenth and one-half of the depth of the base region 26. The depth of the base connection region 28 is, for example, between 0.5 μm and 1 μm.

[0056] The base connection region 28 is electrically connected to the source electrode 12. The base connection region 28 is fixed at the potential of the source electrode 12.

[0057] A portion of the base connection region 28 is in contact with, for example, the first surface F1. The base connection region 28 does not function as, for example, the channel region of the MOSFET 100.

[0058] n + The source region 30 of the shape is provided between the base region 26 and the first surface F1. The source region 30 extends linearly in a first direction. The source region 30 is repeatedly arranged in a second direction. In the second direction, the base region 26 is provided between the source region 30 and the drift region 24.

[0059] The first source region 30a is provided between the first base region 26a and the first surface F1. The second source region 30b is provided between the second base region 26b and the first surface F1. The third source region 30c is provided between the third base region 26c and the first surface F1. The fourth source region 30d is provided between the fourth base region 26d and the first surface F1.

[0060] Source region 30 contains, for example, phosphorus (P) or nitrogen (N) as n-type impurities. The concentration of n-type impurities in source region 30 is higher than the concentration of n-type impurities in drift region 24.

[0061] The concentration of n-type impurities in source region 30 is, for example, 1 × 10⁻⁶. 19 cm -3 The above 5 x 10 21 cm -3 The following conditions apply: The depth of the source region 30 is shallower than the depth of the base region 26. For example, the depth of the source region 30 is between 80 nm and 200 nm.

[0062] The source region 30 is electrically connected to the source electrode 12. The potential of the source region 30 is fixed at that of the source electrode 12.

[0063] n + The contact region 32 is provided between the base connection region 28 and the first surface F1. The contact region 32 is provided between two adjacent source regions 30 in a second direction. The contact region 32 is in contact with, for example, two adjacent source regions 30 in a second direction.

[0064] For example, in the first direction, a base connection region 28 is provided between the contact region 32 and the drift region 24. The contact region 32 is in contact with, for example, the source electrode 12.

[0065] The contact region 32 contains, for example, phosphorus (P) or nitrogen (N) as n-type impurities. The concentration of n-type impurities in the contact region 32 is higher than the concentration of n-type impurities in the drift region 24. The concentration of n-type impurities in the contact region 32 is higher than, for example, the concentration of n-type impurities in the source region 30.

[0066] The n-type impurity concentration in the contact region 32 is, for example, 1 × 10⁻⁶. 19 cm -3 The above 5 x 10 21 cm -3 The following applies: The depth of the contact region 32 is shallower than the depth of the base region 26. For example, the depth of the contact region 32 is between 80 nm and 200 nm.

[0067] The contact region 32 is electrically connected to the source electrode 12. The contact region 32 is fixed at the potential of the source electrode 12.

[0068] The contact region 32 has the function of reducing the electrical resistance between the source electrode 12 and the source region 30, for example.

[0069] The source electrode 12 is provided on the side of the first surface F1 of the silicon carbide layer 10. The source electrode 12 is in contact with the silicon carbide layer 10. The source electrode 12 is in contact with the base connection region 28. The source electrode 12 is in contact with, for example, the source region 30 and the contact region 32.

[0070] The source electrode 12 includes contact portions 12x. Each contact portion 12x is in contact with the base connection region 28. The first contact portion 12x1 is in contact with the first base connection region 28a. The second contact portion 12x2 is in contact with the second base connection region 28b. The third contact portion 12x3 is in contact with the third base connection region 28c. The fourth contact portion 12x4 is in contact with the fourth base connection region 28d.

[0071] For example, the interface between the contact portion 12x and the base connection region 28 is located on the side of the second surface F2 rather than the first surface F1 in a third direction perpendicular to the first surface F1. For example, the contact portion 12x is in contact with the source region 30 in the second direction. For example, the contact portion 12x is in contact with the contact region 32 in the first direction.

[0072] In MOSFET 100, the contact portions 12x are adjacent in a second direction. For example, the third contact portion 12x3 is located in the second direction relative to the first contact portion 12x1. Also, for example, the fourth contact portion 12x4 is located in the second direction relative to the second contact portion 12x2.

[0073] The source electrode 12 includes a metal silicide layer 12s and a metal layer 12m. The metal silicide layer 12s is provided between the silicon carbide layer 10 and the metal layer 12m. It is also possible to omit the metal silicide layer 12s from the source electrode 12.

[0074] The metal silicide layer 12s is in contact with, for example, the base connection region 28. The metal silicide layer 12s is in contact with, for example, the source region 30. The metal silicide layer 12s is in contact with, for example, the contact region 32.

[0075] The metal silicide layer 12s includes, for example, nickel (Ni), titanium (Ti), or cobalt (Co). The metal silicide layer 12s is, for example, a nickel silicide layer, a titanium silicide layer, or a cobalt silicide layer.

[0076] The metal layer 12m contains metal. The metal layer 12m has, for example, a laminated structure of a barrier metal film and a metal film.

[0077] The barrier metal film includes, for example, titanium (Ti), tungsten (W), or tantalum (Ta). The barrier metal film is, for example, a titanium film, a titanium nitride film, a tungsten nitride film, or a tantalum nitride film.

[0078] The metal film includes, for example, aluminum (Al). The metal film is, for example, an aluminum film.

[0079] The contact portion 12x includes a metal silicide layer 12s. The inclusion of the metal silicide layer 12s in the contact portion 12x results in ohmic contact between, for example, the source electrode 12 and the base connection region 28, and between the source electrode 12 and the source region 30.

[0080] The gate electrode 18 is provided on the side of the first surface F1 of the silicon carbide layer 10. The gate electrode 18 faces the drift region 24, the base region 26, and the source region 30 on the first surface F1.

[0081] The gate electrode 18 is provided between the source electrode 12 and the silicon carbide layer 10. As shown in Figure 4, the gate electrode 18 has an opening 18x. In Figure 5, the end 18xe of the opening 18x of the gate electrode 18 is shown by a dotted line.

[0082] The contact portion 12x of the source electrode 12 is provided in the opening 18x of the gate electrode 18. The gate electrode 18 surrounds the contact portion 12x in a plane parallel to the first plane F1.

[0083] A base connection region 28 exists on the first plane F1 in the third direction at the end of the gate electrode 18 in the first direction between two adjacent contact portions 12x in the first direction. In other words, the end of the gate electrode 18 in the first direction between two adjacent contact portions 12x in the first direction is directly above the base connection region 28 on the first plane F1. The end of the gate electrode 18 in the first direction between two adjacent contact portions 12x in the first direction overlaps with the base connection region 28 in the first direction.

[0084] For example, on the first surface F1 in the third direction of the end of the gate electrode 18 between the first contact portion 12x1 and the second contact portion 12x2 in the first direction, there is either a first base connection region 28a or a second base connection region 28b. For example, on the first surface F1 in the third direction of the first end (E1 in Figure 3) of the gate electrode 18 between the first contact portion 12x1 and the second contact portion 12x2 in the first direction, there is a first base connection region 28a. Also, for example, on the first surface F1 in the third direction of the second end (E2 in Figure 3) of the gate electrode 18 between the first contact portion 12x1 and the second contact portion 12x2 in the first direction, there is a second base connection region 28b.

[0085] For example, in the first direction of the first contact portion 12x1, n + The contact region 32 and the first end E1 of the gate electrode are separated, and the first base connection region 28a does not function as the channel region of the MOSFET 100. Also, in the first direction of the second contact portion 12x2, n + The contact region 32 and the second end E2 of the gate electrode are separated, and the second base connection region 28b does not function as the channel region of the MOSFET 100.

[0086] The gate electrode 18 is a conductive layer. The gate electrode 18 is, for example, polycrystalline silicon containing p-type or n-type impurities.

[0087] The gate insulating layer 16 is provided between the drift region 24, the base region 26, and the source region 30 and the gate electrode 18.

[0088] The gate insulating layer 16 includes, for example, silicon oxide. The gate insulating layer 16 includes, for example, a silicon oxide layer. For example, a high dielectric constant insulating material can be applied to the gate insulating layer 16. Furthermore, for example, a laminated structure of a silicon oxide layer and a high dielectric constant insulating layer can be applied to the gate insulating layer 16.

[0089] The thickness of the gate insulating layer 16 is, for example, 30 nm to 100 nm.

[0090] The interlayer insulating layer 20 is provided on the gate electrode 18. The interlayer insulating layer 20 is provided between the gate electrode 18 and the source electrode 12.

[0091] The interlayer insulating layer 20 electrically isolates the gate electrode 18 and the source electrode 12. The interlayer insulating layer 20 includes, for example, silicon oxide. The interlayer insulating layer 20 is, for example, a silicon oxide layer.

[0092] The drain electrode 14 is provided on the second surface F2 side of the silicon carbide layer 10. The drain electrode 14 is provided on the second surface F2 of the silicon carbide layer 10. The drain electrode 14 is in contact with the second surface F2.

[0093] The drain electrode 14 includes, for example, a metal or a metal-semiconductor compound. The drain electrode 14 includes, for example, a nickel silicide layer, a titanium layer, a nickel layer, a silver layer, or a gold layer.

[0094] The drain electrode 14 is electrically connected to the drain region 22. The drain electrode 14 is, for example, in contact with the drain region 22.

[0095] Next, the operation and effects of the MOSFET 100 of the first embodiment will be described.

[0096] Figure 6 is a schematic cross-sectional view of the comparative semiconductor device. Figures 7 and 8 are schematic top views of the comparative semiconductor device. Figure 7 is a schematic diagram showing the gate electrode and source electrode patterns on the upper surface of the silicon carbide layer. Figure 8 is a schematic diagram showing the silicon carbide region and source electrode patterns on the first surface of the silicon carbide layer. Figure 6 is a DD' cross-sectional view of Figures 7 and 8.

[0097] Figure 6 corresponds to Figure 1 of the first embodiment. Figure 7 corresponds to Figure 4 of the first embodiment. Figure 8 corresponds to Figure 5 of the first embodiment.

[0098] The semiconductor device of the comparative example is a MOSFET 900. The patterns of the base region 26 and source region 30 of the MOSFET 900 are the same as those of the MOSFET 100 of the first embodiment. The MOSFET 900 differs from the MOSFET 100 of the first embodiment in that the pattern of the gate electrode 18 is a stripe shape that extends in a first direction and is repeatedly arranged in a second direction. It also differs from the MOSFET 100 of the first embodiment in that the contact portion 12x of the source electrode 12 is a stripe shape that extends in a first direction and is repeatedly arranged in a second direction. In Figure 8, the end 18e of the gate electrode 18 is shown by a dotted line.

[0099] In MOSFET900, only the base region 26 facing the striped gate electrode 18 functions as the channel region. On the other hand, in MOSFET100 of the first embodiment, the contact portion 12x of the source electrode 12 is divided in a first direction. A gate electrode 18 is also provided between adjacent contact portions 12x in the first direction. Therefore, in MOSFET100, in addition to the channel region of MOSFET900, the base region 26 facing the gate electrode 18 between adjacent contact portions 12x in the first direction also functions as the channel region.

[0100] Therefore, compared to MOSFET900, MOSFET100 has an increased channel area and a larger effective MOSFET channel width. Consequently, the on-resistance of MOSFET100 is reduced.

[0101] From the viewpoint of increasing the effective channel width of the MOSFET 100 and reducing the on-resistance, the distance in the first direction between two adjacent base connection regions 28 in the first direction is preferably 1.5 times or more the length of the base connection region 28 in the first direction, more preferably 2 times or more, and even more preferably 3 times or more.

[0102] Furthermore, it is preferable that the depth of the base connection region 28 is shallower than the depth of the base region 26. In other words, it is preferable that the depth of the base region 26 is deeper than the depth of the base connection region 28. By increasing the depth of the base region 26, the short-circuit withstand capability of the MOSFET 100 is improved. Also, by making the depth of the base connection region 28 shallower, the on-current flowing from the channel region located in the first direction of the contact portion 12x to the drift region 24 is more easily diffused under the base connection region 28 within the drift region 24. Therefore, the on-resistance of the MOSFET 100 is reduced.

[0103] Furthermore, it is preferable that the base connection region 28 provided in the first direction of the contact portion 12x does not function as the channel region of the MOSFET 100. This is because providing a structure that allows the base connection region 28 to function as the channel region would increase the area consumed in the first direction of the contact portion 12x, making it difficult to increase the effective channel width of the MOSFET 100.

[0104] Therefore, it is preferable that a base connection region 28 exists on the first surface F1 in the third direction of the end of the gate electrode 18 in the first direction between two adjacent contact portions 12x in the first direction. In other words, it is preferable that the end of the gate electrode 18 in the first direction between two adjacent contact portions 12x in the first direction is directly above the base connection region 28 on the first surface F1.

[0105] Furthermore, suppose we consider making the base connection region 28 provided in the first direction of the contact portion 12x function as the channel region of the MOSFET 100, and widening the width of the base connection region 28 in the second direction in order to increase the on-current in this region. In this case, the repetition period of the gate electrode 18 in the second direction will be increased, which is contrary to the increase in on-current per unit area. Moreover, widening the width of the base connection region 28 in the second direction inevitably widens the spacing of the base region 26 in the second direction. When the spacing of the base region 26 in the second direction widens, the electric field relaxation effect in the part of the base region 26 of the MOSFET 100 and the short-circuit current suppression effect by the part of the base region 26 are not obtained, and the characteristics of the MOSFET 100 deteriorate.

[0106] Furthermore, if a drift region 24 exists on the first surface F1 in the third direction at the end of the gate electrode 18 in the first direction, the electric field strength applied to the gate insulating layer 16 between the end of the gate electrode 18 and the drift region 24 will increase, potentially degrading the reliability of the gate insulating layer 16. From the viewpoint of improving the reliability of the gate insulating layer 16, it is preferable that the end of the gate electrode 18 in the first direction between two adjacent contact portions 12x in the first direction is directly above the base connection region 28 of the first surface F1.

[0107] As described above, the MOSFET 100 of the first embodiment realizes a MOSFET with a larger effective channel width and reduced on-resistance.

[0108] (First variation) The semiconductor device of the first modified embodiment differs from the semiconductor device of the first embodiment in that the depths of the second silicon carbide region and the third silicon carbide region are the same as the depths of the eighth silicon carbide region and the ninth silicon carbide region.

[0109] Figure 9 is a schematic cross-sectional view of a semiconductor device of a first modification of the first embodiment. Figure 9 corresponds to Figure 1 of the first embodiment.

[0110] The MOSFET 101 of the first embodiment differs from the MOSFET 100 of the first embodiment in that the depth of the base connection region 28 is the same as the depth of the base region 26.

[0111] According to the MOSFET 101 of the first modification of the first embodiment, a MOSFET is realized that, similar to MOSFET 100, has a larger effective channel width and reduced on-resistance.

[0112] (Second variation) The semiconductor device of the second modification of the second embodiment differs from the semiconductor device of the first embodiment in that the interface between the contact portion 12x and the base connection region 28 is located on the first surface F1.

[0113] Figure 10 is a schematic cross-sectional view of a semiconductor device of a second modification of the first embodiment. Figure 10 corresponds to Figure 1 of the first embodiment.

[0114] In the second modification of the first embodiment, the MOSFET 102 has the interface between the contact portion 12x and the base connection region 28 on the first surface F1.

[0115] According to the MOSFET 102, a second modification of the first embodiment, a MOSFET is realized that, similar to MOSFET 100, has a larger effective channel width and reduced on-resistance.

[0116] As described above, according to the first embodiment and its modifications, a MOSFET is realized in which the effective channel width is increased and the on-resistance is reduced.

[0117] (Second embodiment) The semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment in that the position of the third portion in the first direction lies between the position of the first portion in the first direction and the position of the second portion in the first direction. Hereafter, some descriptions that overlap with the first embodiment may be omitted.

[0118] The semiconductor device of the first embodiment is a planar gate type vertical MOSFET 200 using silicon carbide.

[0119] Figures 11, 12, and 13 are schematic cross-sectional views of a semiconductor device according to the second embodiment. Figures 14 and 15 are schematic top views of a semiconductor device according to the second embodiment. Figure 14 is a schematic diagram showing the gate electrode and source electrode patterns on the upper surface of the silicon carbide layer. Figure 15 is a schematic diagram showing the silicon carbide region and source electrode patterns on the first surface of the silicon carbide layer. Figure 11 is a cross-sectional view EE' of Figures 14 and 15. Figure 12 is a cross-sectional view FF' of Figures 14 and 15. Figure 13 is a cross-sectional view GG' of Figures 14 and 15.

[0120] In MOSFET200, the contact portions 12x are arranged in a line in a first direction. The rows of contact portions 12x arranged in the first direction are offset by half a cycle in the first direction from the adjacent rows of contact portions 12x arranged in the first direction in the second direction. In other words, the contact portions 12x are arranged in a checkerboard pattern on the first surface F1.

[0121] For example, the position of the third contact portion 12x3 in the first direction is between the position of the first contact portion 12x1 in the first direction and the position of the second contact portion 12x2 in the first direction.

[0122] According to the MOSFET 200 of the second embodiment, similar to the MOSFET 100 of the first embodiment, a MOSFET is realized in which the effective channel width is increased and the on-resistance is reduced.

[0123] Furthermore, because the openings 18x of the gate electrode 18 are arranged in a checkerboard pattern, the distance between two openings 18x becomes larger compared to the MOSFET 100 of the first embodiment. Therefore, patterning of the gate electrode 18 becomes easier.

[0124] Furthermore, because the contact portion 12x of the source electrode 12 is arranged in a checkerboard pattern, the heat source in the event of a short circuit in the MOSFET 200 is more dispersed compared to the MOSFET 100. Therefore, the short-circuit withstand capability of the MOSFET 200 is improved.

[0125] Furthermore, the rows of contact portions 12x arranged in the first direction may be shifted, for example, by one-third of a period in the first direction, or by one-quarter of a period in the first direction, to create a repeating arrangement in the second direction.

[0126] As described above, according to the second embodiment, a MOSFET is realized in which the effective channel width is increased and the on-resistance is reduced.

[0127] (Third embodiment) The semiconductor device of the third embodiment has a silicon carbide layer provided between the first silicon carbide region and the first surface, provided between the third silicon carbide region and the fourth silicon carbide region, and a tenth silicon carbide region of a second conductive type that is in contact with the third and fourth silicon carbide regions, and provided between the first silicon carbide region and the first surface, provided between the third and fourth silicon carbide regions, and in contact with the third and fourth silicon carbide regions, and the tenth The semiconductor device of the first embodiment further includes an eleventh silicon carbide region of a second conductivity type that is separated from the silicon carbide region in a first direction, and the first electrode further includes a third portion in contact with the tenth silicon carbide region and a fourth portion in contact with the eleventh silicon carbide region, and the gate electrode surrounds the third portion and the fourth portion, and the position of the third portion in the first direction is between the position of the first portion in the first direction and the position of the second portion in the first direction, which is different from the semiconductor device of the first embodiment.Hereafter, some descriptions that overlap with the first embodiment may be omitted.

[0128] The semiconductor device of the third embodiment is a planar gate type vertical MOSFET 300 using silicon carbide.

[0129] The following explanation will use the case where the first conductivity type is n-type and the second conductivity type is p-type as an example. MOSFET300 is a vertical n-channel MOSFET that uses electrons as carriers.

[0130] Figures 16, 17, and 18 are schematic cross-sectional views of a semiconductor device according to the third embodiment. Figures 19 and 20 are schematic top views of a semiconductor device according to the third embodiment. Figure 16 is a schematic diagram showing the gate electrode and source electrode patterns on the upper surface of the silicon carbide layer. Figure 17 is a schematic diagram showing the silicon carbide region and source electrode patterns on the first surface of the silicon carbide layer. Figure 16 is a cross-sectional view of HH' in Figures 19 and 20. Figure 17 is a cross-sectional view of II' in Figures 19 and 20. Figure 18 is a cross-sectional view of JJ' in Figures 19 and 20.

[0131] The MOSFET 300 comprises a silicon carbide layer 10, a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a gate insulating layer 16, a gate electrode 18, and an interlayer insulating layer 20. The source electrode 12 includes a metal silicide layer 12s and a metal layer 12m. The source electrode 12 includes a contact portion 12x. The contact portion 12x includes a first contact portion 12x1 (first part), a second contact portion 12x2 (second part), a third contact portion 12x3 (third part), and a fourth contact portion 12x4 (fourth part).

[0132] Within the silicon carbide layer 10, n + Shape of drain region 22, n - The drift region 24 of the p-type (first silicon carbide region), the base region 26 of the p-type, the base connection region 28 of the p-type, the source region 30 of the n-type, n +The p-shaped base region 26 includes a contact region 32. The p-shaped base region 26 includes a first base region 26a (second silicon carbide region), a second base region 26b (third silicon carbide region), a third base region 26c (fourth silicon carbide region), and a fourth base region 26d. The p-shaped base connection region 28 includes a first base connection region 28a (eighth silicon carbide region), a second base connection region 28b (ninth silicon carbide region), a third base connection region 28c (tenth silicon carbide region), and a fourth base connection region 28d (eleventh silicon carbide region). The n-type source region 30 includes a first source region 30a (the fifth silicon carbide region), a second source region 30b (the sixth silicon carbide region), a third source region 30c (the seventh silicon carbide region), and a fourth source region 30d.

[0133] The p-shaped base connection region 28 is provided between the drift region 24 and the first surface F1. The base connection region 28 is provided between two adjacent base regions 26 in the second direction. The base connection region 28 is in contact with two adjacent base regions 26 in the second direction.

[0134] The base connection regions 28 are repeatedly arranged in a first direction. A drift region 24 is provided between two adjacent base connection regions 28 in the first direction.

[0135] The first base connection region 28a is provided between the first base region 26a and the second base region 26b. The first base connection region 28a is in contact with the first base region 26a and the second base region 26b.

[0136] The second base connection region 28b is provided between the first base region 26a and the second base region 26b. The second base connection region 28b is in contact with both the first base region 26a and the second base region 26b.

[0137] The second base connection region 28b is separated from the first base connection region 28a in a first direction. A drift region 24 is provided between the second base connection region 28b and the first base connection region 28a.

[0138] The third base connection region 28c is provided between the second base region 26b and the third base region 26c. The third base connection region 28c is in contact with the second base region 26b and the third base region 26c.

[0139] The fourth base connection region 28d is provided between the second base region 26b and the third base region 26c. The fourth base connection region 28d is in contact with the second base region 26b and the third base region 26c.

[0140] The fourth base connection region 28d is separated from the third base connection region 28c in a first direction. A drift region 24 is provided between the fourth base connection region 28d and the third base connection region 28c.

[0141] Two base regions 26, each with a base connection region 28 between them, are repeatedly arranged in a second direction. Base connection regions 28 are provided on both sides of a base region 26 in the second direction, adjacent to that base region 26. For example, base connection regions 28 are provided between all two adjacent base regions 26 in the second direction.

[0142] In MOSFET300, the contact portions 12x are arranged in a line in a first direction. The rows of contact portions 12x arranged in the first direction are offset by half a cycle in the first direction from the adjacent rows of contact portions 12x arranged in the first direction in the second direction. In other words, the contact portions 12x are arranged in a checkerboard pattern on the first surface F1.

[0143] For example, the position of the third contact portion 12x3 in the first direction is between the position of the first contact portion 12x1 in the first direction and the position of the second contact portion 12x2 in the first direction.

[0144] The distance in the first direction between two adjacent base connection regions 28 is, for example, between 3 and 100 times the length of the base connection region 28 in the first direction.

[0145] The distance in the first direction between the first base connection region 28a and the second base connection region 28b (D1 in Figure 18) is, for example, 3 to 100 times the length of the first base connection region 28a in the first direction (L1 in Figure 18). Also, the distance in the first direction between the third base connection region 28c and the fourth base connection region 28d is, for example, 3 to 100 times the length of the third base connection region 28c in the first direction.

[0146] The distance in the first direction between two adjacent base connection regions 28 is, for example, between 4 and 100 times the distance in the second direction between two adjacent base regions 26.

[0147] The distance in the first direction between the first base connection region 28a and the second base connection region 28b (D1 in Figure 18) is, for example, 4 to 100 times the distance in the second direction between the first base region 26a and the second base region 26b (D2 in Figure 17). Also, the distance in the first direction between the third base connection region 28c and the fourth base connection region 28d is, for example, 4 to 100 times the distance in the second direction between the third base region 26c and the fourth base region 26d.

[0148] A base connection region 28 exists on the first plane F1 in the third direction at the end of the gate electrode 18 in the first direction between two adjacent contact portions 12x in the first direction. In other words, the end of the gate electrode 18 in the first direction between two adjacent contact portions 12x in the first direction is directly above the base connection region 28 on the first plane F1. The end of the gate electrode 18 in the first direction between two adjacent contact portions 12x in the first direction overlaps with the base connection region 28 in the first direction.

[0149] For example, on the first surface F1 in the third direction of the end of the gate electrode 18 between the first contact portion 12x1 and the second contact portion 12x2 in the first direction, there is either a first base connection region 28a or a second base connection region 28b. For example, on the first surface F1 in the third direction of the first end (E1 in Figure 18) of the gate electrode 18 between the first contact portion 12x1 and the second contact portion 12x2 in the first direction, there is a first base connection region 28a. Also, for example, on the first surface F1 in the third direction of the second end (E2 in Figure 18) of the gate electrode 18 between the first contact portion 12x1 and the second contact portion 12x2 in the first direction, there is a second base connection region 28b.

[0150] For example, in the first direction of the first contact portion 12x1, n + The contact region 32 and the first end E1 of the gate electrode are separated, and the first base connection region 28a does not function as the channel region of the MOSFET 100. Also, in the first direction of the second contact portion 12x2, n + The contact region 32 and the second end E2 of the gate electrode are separated, and the second base connection region 28b does not function as the channel region of the MOSFET 300.

[0151] It is preferable that the base connection region 28 provided in the first direction of the contact portion 12x does not function as the channel region of the MOSFET 100. This is because providing a structure that allows the base connection region 28 to function as the channel region would increase the area consumed in the first direction of the contact portion 12x, making it difficult to increase the effective channel width of the MOSFET 300.

[0152] According to the MOSFET 300 of the third embodiment, similar to the MOSFET 100 of the first embodiment, a MOSFET is realized in which the effective channel width is increased and the on-resistance is reduced.

[0153] Furthermore, because the openings 18x of the gate electrode 18 are arranged in a checkerboard pattern, the distance between two openings 18x becomes larger compared to the MOSFET 100 of the first embodiment. Therefore, patterning of the gate electrode 18 becomes easier.

[0154] Furthermore, because the contact portion 12x of the source electrode 12 is arranged in a checkerboard pattern, the heat source in the event of a short circuit in the MOSFET 300 is more dispersed compared to the MOSFET 100. Therefore, the short-circuit withstand capability of the MOSFET 300 is improved.

[0155] Furthermore, the rows of contact portions 12x arranged in the first direction may be shifted by, for example, one-third of a cycle in the first direction, or by one-quarter of a cycle in the first direction, and repeated in the second direction.

[0156] As described above, according to the third embodiment, a MOSFET is realized in which the effective channel width is increased and the on-resistance is reduced.

[0157] In the first to third embodiments, the case of 4H-SiC as the crystal structure of SiC was described as an example, but the present invention can also be applied to devices using SiC with other crystal structures such as 6H-SiC and 3C-SiC. Furthermore, it is possible to apply a plane other than the (0001) plane to the surface of the silicon carbide layer 10.

[0158] In the first to third embodiments, the case where the first conductivity type is n-type and the second conductivity type is p-type was explained as an example, but it is also possible to have the first conductivity type be p-type and the second conductivity type be n-type.

[0159] In the first to third embodiments, aluminum (Al) was exemplified as a p-type impurity, but boron (B) can also be used. Similarly, nitrogen (N) and phosphorus (P) were exemplified as n-type impurities, but arsenic (As), antimony (Sb), etc., can also be applied.

[0160] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or modified with components of another embodiment. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]

[0161] 10. Silicon carbide layer 12 Source electrode (first electrode) 12x1 First contact area (first part) 12x2 Second contact area (second part) 12x3 Third contact area (third part) 12x4 Fourth contact area (fourth part) 14. Drain electrode (second electrode) 16 Gate Insulation Layer 18 Guard gate 24. Drift region (first silicon carbide region) 26a First base region (second silicon carbide region) 26b Second base region (third silicon carbide region) 26c Third base region (fourth silicon carbide region) 26d The fourth base region (the tenth silicon carbide region) 28a First base connection region (eighth silicon carbide region) 28b Second base connection region (ninth silicon carbide region) 28c Third base connection region (12th silicon carbide region, 10th silicon carbide region) 28d Fourth base connection region (13th silicon carbide region, 11th silicon carbide region) 30a First source region (fifth silicon carbide region) 30b Second source region (sixth silicon carbide region) 30c Third source region (seventh silicon carbide region) 30d Fourth source region (eleventh silicon carbide region) 100 MOSFETs (Semiconductor Devices) 101 MOSFET (Semiconductor Device) 102 MOSFET (Semiconductor Device) 200 MOSFETs (Semiconductor Equipment) 300 MOSFETs (semiconductor equipment) F1 First Side F2 Second side

Claims

1. A silicon carbide layer having a first surface and a second surface facing the first surface, The first silicon carbide region of the first conductivity type, A second silicon carbide region of a second conductive type is provided between the first silicon carbide region and the first surface, and extends in a first direction parallel to the first surface, A third silicon carbide region of a second conductivity type is provided between the first silicon carbide region and the first surface, extending in the first direction and separated from the second silicon carbide region in a second direction parallel to the first surface and perpendicular to the first direction, A fourth silicon carbide region of second conductivity is provided between the first silicon carbide region and the first surface, extending in the first direction and separated from the third silicon carbide region in the second direction, A fifth silicon carbide region of first conductivity type is provided between the second silicon carbide region and the first surface, and extends in the first direction, A sixth silicon carbide region of first conductivity type is provided between the third silicon carbide region and the first surface, and extends in the first direction, A seventh silicon carbide region of first conductivity type is provided between the fourth silicon carbide region and the first surface, and extends in the first direction, An eighth silicon carbide region of second conductivity, provided between the first silicon carbide region and the first surface, and provided between the second silicon carbide region and the third silicon carbide region, is in contact with the second silicon carbide region and the third silicon carbide region. A ninth silicon carbide region of second conductivity is provided between the first silicon carbide region and the first surface, and between the second silicon carbide region and the third silicon carbide region, and is in contact with the second silicon carbide region and the third silicon carbide region, and is separated from the eighth silicon carbide region in the first direction, A silicon carbide layer containing, The silicon carbide layer includes a first portion in contact with the eighth silicon carbide region and a second portion in contact with the ninth silicon carbide region, and is electrically connected to the fifth silicon carbide region, the sixth silicon carbide region, and the seventh silicon carbide region, and is provided on the side of the first surface of the silicon carbide layer, A gate electrode facing the first silicon carbide region, the second silicon carbide region, the third silicon carbide region, the fourth silicon carbide region, the fifth silicon carbide region, the sixth silicon carbide region, and the seventh silicon carbide region, and surrounding the first and second portions, A gate insulating layer is provided between the first silicon carbide region, the second silicon carbide region, the third silicon carbide region, the fourth silicon carbide region, the fifth silicon carbide region, the sixth silicon carbide region, and the seventh silicon carbide region and the gate electrode. A second electrode provided on the side of the second surface of the silicon carbide layer, A semiconductor device equipped with a semiconductor device.

2. The semiconductor device according to claim 1, wherein the depths of the second silicon carbide region and the third silicon carbide region are greater than the depths of the eighth silicon carbide region and the ninth silicon carbide region.

3. The semiconductor device according to claim 1, wherein the first surface in a third direction perpendicular to the first surface of the end of the gate electrode in the first direction between the first portion and the second portion has an eighth silicon carbide region or a ninth silicon carbide region.

4. The semiconductor device according to claim 1, wherein the distance in the first direction between the eighth silicon carbide region and the ninth silicon carbide region is 1.5 times or more the length of the eighth silicon carbide region in the first direction.

5. The semiconductor device according to claim 1, wherein the distance in the first direction between the eighth silicon carbide region and the ninth silicon carbide region is at least twice the distance in the second direction between the second silicon carbide region and the third silicon carbide region.

6. The aforementioned silicon carbide layer is A 10th silicon carbide region of second conductivity is provided between the first silicon carbide region and the first surface, extending in the first direction and separated from the fourth silicon carbide region in the second direction, A first conductive silicon carbide region is provided between the tenth silicon carbide region and the first surface, and extends in the first direction, A twelfth silicon carbide region of second conductivity is provided between the first silicon carbide region and the first surface, and between the fourth silicon carbide region and the tenth silicon carbide region, and is in contact with the fourth silicon carbide region and the tenth silicon carbide region. The present invention further includes a thirteenth silicon carbide region of second conductivity, provided between the first silicon carbide region and the first surface, provided between the fourth silicon carbide region and the tenth silicon carbide region, in contact with the fourth silicon carbide region and the tenth silicon carbide region, and separated from the twelfth silicon carbide region in the first direction, The first electrode further includes a third portion in contact with the 12th silicon carbide region and a fourth portion in contact with the 13th silicon carbide region. The semiconductor device according to claim 1, wherein the gate electrode surrounds the third portion and the fourth portion.

7. The semiconductor device according to claim 6, wherein the third portion is located in the second direction of the first portion, and the fourth portion is located in the second direction of the first portion.

8. The semiconductor device according to claim 6, wherein the position of the third portion in the first direction is between the position of the first portion in the first direction and the position of the second portion in the first direction.

9. The aforementioned silicon carbide layer is A 10th silicon carbide region of second conductivity is provided between the first silicon carbide region and the first surface, and between the third silicon carbide region and the fourth silicon carbide region, and is in contact with the third silicon carbide region and the fourth silicon carbide region. The present invention further includes an eleventh silicon carbide region of second conductivity, provided between the first silicon carbide region and the first surface, provided between the third silicon carbide region and the fourth silicon carbide region, in contact with the third silicon carbide region and the fourth silicon carbide region, and separated from the tenth silicon carbide region in the first direction, The first electrode further includes a third portion in contact with the tenth silicon carbide region and a fourth portion in contact with the eleventh silicon carbide region. The gate electrode surrounds the third portion and the fourth portion, The semiconductor device according to claim 1, wherein the position of the third portion in the first direction is between the position of the first portion in the first direction and the position of the second portion in the first direction.

10. The semiconductor device according to claim 9, wherein the distance in the first direction between the tenth silicon carbide region and the eleventh silicon carbide region is three times or more the length of the tenth silicon carbide region in the first direction.

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