IC package having a large-footprint glass core, a thin redistribution layer, and a substrate with electrical components.

Abstract

The present invention provides equipment and systems that reduce stress on the glass core, thereby reducing sewerage defects and improving manufacturing yield. [Solution] The IC package 702 comprises first IC dies 704A and 704B on a glass core substrate 502. The glass core 512 includes a first surface and a second surface opposite the first surface. The first surface has a thickness of at least 5,000 mm 2 It has the area of ​​. The redistribution layers 504 and 506 are located on the first and second surfaces, respectively. The redistribution layers have a thickness of 100 μm or less. The electrical components are located within the region of the glass core. Glass through vias (TGV) 222 extend between the first and second surfaces. The second IC dies 706A to 706F are located on the first IC die and are directly bonded to the first IC die.

Description

[Background technology]

[0001] In the manufacturing of electronic devices, integrated circuit (IC) packaging is a stage in semiconductor device fabrication where an IC, monolithically fabricated on a chip (or die), is assembled into a "package" that can protect the IC chip from physical damage. The package connects the IC chip to other packaged IC chips and / or scaled host components, such as a package substrate or printed circuit board. Multiple IC chips can be assembled into a single multi-die package.

[0002] In conventional methods, IC chips may be placed adjacent to each other on a substrate. To achieve denser integration than is possible using conventional methods, IC chips may be stacked on top of each other using three-dimensional (3D) packaging techniques. In heterogeneous architectures, different types of IC chips, which may be manufactured using different processes, may be integrated into a single IC package. Heterogeneous 3D IC packages may require a larger form factor than conventional IC packages.

[0003] Traditionally, package substrates have been made from organic materials. More recently, package substrates with a glass core between layers of organic material have been introduced. Substrates with a glass core may be used to accommodate larger form factors of dissimilar 3D IC packages. Glass core substrates may be stronger, flatter, and have better dimensional stability than conventional organic substrates.

[0004] One challenge associated with glass core substrates is seWaRe defects. These defects can form at the edges of the glass after the wafer has been cut into individual package substrates. SeWaRe defects are small cracks in the glass at the cut edges. These cracks can propagate inward from the edges during subsequent processing and handling. SeWaRe defects can significantly reduce manufacturing yield. [Brief explanation of the drawing]

[0005] The subjects described herein are shown in the accompanying drawings as examples, not as limitations. For simplicity and clarity in the illustrations, the elements shown in the drawings are not necessarily drawn to actual size. For example, the dimensions of some elements may be exaggerated compared to others for clarity. The drawings, called “section,” “side,” and “plan,” correspond to orthogonal planes in the Cartesian coordinate system. Thus, the section and side views are taken in the xz plane, and the plan view is taken in the xy plane. Typically, a side view in the xz plane is a section. Where appropriate, the drawings are numbered by axes to indicate the orientation of the drawing. Furthermore, where appropriate, reference numerals are repeated between multiple drawings to indicate corresponding or similar elements. The drawings are as follows:

[0006] [Figure 1] The flowcharts show methods for forming an IC device package, comprising a glass core substrate with a relatively large footprint, a relatively thin redistribution layer, electrical components within the glass core, and one or more IC dies on the substrate, according to several embodiments.

[0007] [Figure 2] These are cross-sectional views of glass panels received in the initial stages of fabrication according to several embodiments.

[0008] [Figure 3A] This is a cross-sectional view of a glass panel in a fabrication stage after alternative features have been formed on the glass panel, according to several embodiments. [Figure 3B] This is a cross-sectional view of a glass panel in a fabrication stage after alternative features have been formed on the glass panel, according to several embodiments.

[0009] [Figure 3C]This is a plan view of a glass panel in a manufacturing stage after various features have been formed on the glass panel, according to several embodiments.

[0010] [Figure 4A] This is a cross-sectional view of a glass panel during a fabrication stage after electrical components have been placed in a region within the glass panel and through-glass vias (TGVs) have been formed, according to several embodiments. [Figure 4B] This is a cross-sectional view of a glass panel during a fabrication stage after electrical components have been placed in a region within the glass panel and through-glass vias (TGVs) have been formed, according to several embodiments. [Figure 4C] This is a cross-sectional view of a glass panel during a fabrication stage after electrical components have been placed in a region within the glass panel and through-glass vias (TGVs) have been formed, according to several embodiments.

[0011] [Figure 5] This is a cross-sectional view of a glass core substrate during a fabrication stage after a redistribution layer and interconnection features have been formed on the surface of the glass core substrate, according to several embodiments.

[0012] [Figure 6] This is a cross-sectional view of a glass core substrate in a fabrication stage after a first IC die has been mounted on the surface of the glass core substrate, according to several embodiments.

[0013] [Figure 7] This is a cross-sectional view of a glass core substrate during a manufacturing stage in which a first IC die is mounted on the surface of the glass core substrate according to several embodiments, and a second IC die is mounted on the first IC die.

[0014] [Figure 8]A system is shown that includes one of the IC packages shown in FIG. 7 attached to a host component by an FLI feature, according to some embodiments.

[0015] [Figure 9] Mobile computing platforms and data server machines are shown that utilize one or more devices comprising an IC package having a glass core with a large footprint, one or more thin redistribution layers, and one or more electrical components, according to some embodiments.

[0016] [Figure 10] A functional block diagram of an electronic computing device, according to some embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Embodiments will be described with reference to the accompanying drawings. Specific configurations and arrangements are shown and discussed in detail, but this is for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements are possible without departing from the spirit and scope of the description. It will be apparent to those skilled in the art that the techniques and / or arrangements described herein may be utilized in a variety of other systems and applications other than those described in detail herein.

[0018] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof and illustrate exemplary embodiments. Further, it is to be understood that other embodiments may be utilized and structural and / or logical changes may be made without departing from the scope of the claimed subject matter. Also, directions and references such as up, down, upper, lower, etc. are used only to facilitate the description of features in the drawings. Therefore, the following detailed description should not be taken in a limiting sense, and the scope of the claimed subject matter is defined only by the appended claims and their equivalents.

[0019] Numerous details are described in the following description. However, it will be apparent to those skilled in the art that embodiments may be carried out without these specific details. In some examples, well-known methods and devices are shown in block diagram form rather than in detail, in order to avoid obscuring the embodiments. Throughout this specification, any reference to “embodiment,” “one embodiment,” or “several embodiments” means that a particular feature, structure, function, or characteristic described in relation to that embodiment is included in at least one embodiment. Thus, the phrases “in an embodiment,” “in one embodiment,” or “in several embodiments” appearing in various places throughout this specification do not necessarily refer to the same embodiment. Furthermore, a particular feature, structure, function, or characteristic may be combined in any suitable way in one or more embodiments. For example, the first embodiment may be combined with the second embodiment wherever the particular feature, structure, function, or characteristic associated with the two embodiments is not mutually exclusive.

[0020] When used in the description and appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms unless otherwise explicitly stated in the context. Furthermore, the terms "and / or" as used herein are understood to refer to and encompass all possible combinations of one or more of the listed related items.

[0021] The terms “joined” and “connected,” along with their derivatives, may be used herein to describe functional or structural relationships between components. These terms are not intended to be synonyms of each other. Rather, in particular embodiments, “connected” may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with one another. “Joined” may be used to indicate that two or more elements are in physical or electrical contact with one another, either directly or indirectly (with other intervening elements between them), and / or that two or more elements cooperate or interact with one another (e.g., as causally related).

[0022] As used herein, the terms “on,” “below,” “between,” and “above” refer to the relative position of one component or material to another component or material, where such a physical relationship is noteworthy. For example, in the context of materials, one material or layer above or below another may be in direct contact with it, or may have one or more intervening materials or layers. Furthermore, one material between two materials or layers may be in direct contact with both materials / layers, or may have one or more intervening materials / layers. In contrast, a first material or layer “on” a second material or layer is in direct physical contact with the second material / layer. A similar distinction is made in the context of component assemblies.

[0023] When used throughout this description and the claims, an enumeration of items connected by the terms “at least one of” or “one or more of” may mean any combination of the terms being enumerated. For example, the phrase “at least one of A, B, or C” may mean A; B; C; A and B; A and C; B and C; or A, B, and C.

[0024] Unless otherwise specified in the context of specific use, the term “majority” means more than 50% or more than half. For example, a composition that is predominantly the first component means that more than half of the composition is the first component (e.g., <50 atomic%). The term “primarily” means the most abundant or largest portion. For example, a composition that is primarily the first component means that the composition contains more of the first component than any other component. A composition that is primarily the first and second components means that the composition contains more of the first and second components than any other component. The term “substantially” means that only accidental variation exists. For example, a composition that is substantially the first component means that the composition may contain <1% of any other component. A composition that is substantially the first and second components means that the composition may contain <1% of any other component that replaces either the first or second component.

[0025] One challenge with glass core substrates is small cracks in the glass at the cut edges, such as sere defects. Sere defects can significantly reduce manufacturing yield. The susceptibility of glass cores to sere defects can increase with the thickness of the metallization and dielectric build-up layers formed on the glass surface. As the number of individual metallization and dielectric layers increases in the redistribution layer, the stress on the glass core can increase. Similarly, as the thickness of individual metallization and dielectric layers increases in the redistribution layer, the stress on the glass core can increase. The advantage of the embodiments described herein is that the stress on the glass core can be reduced, leading to a decrease in sere defects and an improvement in manufacturing yield.

[0026] Another advantage of the embodiments described herein is that the package substrate having a glass core is harder than substrates made from organic materials and can accommodate more IC dies. A further advantage of the embodiments described herein is that the voltage regulation (VR) circuit may be integrated within the IC package, and the IC dies may be stacked using hybrid junctions, thereby providing an IC package with a small form factor.

[0027] Embodiments disclosed herein relate to IC packages having a glass core substrate having a redistribution layer (RDL) on at least one surface of the glass core. The redistribution layer comprises one or more metal layers. Each metal layer comprises a conductive metal wire, such as a copper trace. Within the metal layer, a dielectric material separates the conductive metal wire. In addition, a dielectric layer is located above each metal layer in the RDL. The metal wires may be used to route electrical signals from contacts or features on the surface of the package substrate to other points on the surface or to other points within the package substrate. For example, the metal wires may be used to route electrical signals from a conductive feature on the front to another conductive feature on the front or back, or to an electrical component within the package substrate.

[0028] As used herein, a redistribution layer or RDL may refer to one or more individual metal layers. Where the context indicates the intended meaning, an RDL may also refer to a combined layer of metal and adjacent dielectric layers. For example, in some embodiments, an RDL (individual metal layer) may have a thickness of less than 10 μm. In some examples, the dielectric layer on the metal layer may have a thickness of 10 to 35 μm. In other examples, the dielectric layer on the metal layer may have a thickness of 10 to 20 μm. In one example, an RDL having a thickness of 100 μm or less may have 10 metal layers having a thickness of less than 5 μm and 10 adjacent dielectric layers having a thickness of less than 5 μm. In another example, an RDL having a thickness of 100 μm or less may have 12 metal layers having a thickness of less than 4 μm and 12 adjacent dielectric layers having a thickness of less than 4 μm.

[0029] As shown in Figure 1, various fabrication methods may be employed to form an IC device package structure having one or more of the features described herein. Figure 1 shows a flowchart of a method for forming an IC device package comprising a glass core substrate with a relatively large footprint, a relatively thin redistribution layer, electrical components within the glass core, and one or more IC dies on the substrate, according to several embodiments. Method 101 begins at input 110, where a workpiece including the thickness of the glass is received. The workpiece may be prepared upstream of Method 101 and may be in the form of a large panel, a wafer, or similar. The workpiece received at input 110 may be patterned with a plurality of holes, as described below, or the workpiece may not be patterned, for example, the workpiece may not have holes. The holes may have various shapes and sizes and may instead be referred to herein as “openings”.

[0030] Figure 2 is a cross-sectional view of a glass panel 204 received in an initial stage 202 of fabrication according to several embodiments. The advantages of fabricating IC device package structures on such glass are that the control of the flatness and / or thickness of the glass preform is better than that of starting a substrate based on an organic material (e.g., epoxy), and the cost can be significantly lower than with respect to a single-crystal material (e.g., silicon). The glass 204 is a solid bulk material layer which may be preformed into any shape, such as a rectangle, suitable for a packaging workpiece. The glass 204 includes a first surface 206 and a second surface 208 opposite the first surface. The glass 204 has a thickness T1 which may vary depending on the mounting configuration, for example, to keep thin enough to allow the formation of through vias at the smallest possible pitch due to the surface flatness of the glass 204, while limiting strain. In exemplary embodiments, the thickness T1 is advantageously 0.2 mm to 1.6 mm.

[0031] Although not shown, one or more material layers may coat either or both of the first surface 206 or the second surface 208 of the glass 204, thereby making the glass 204 a bulk or core layer of a multilayer substrate. Exemplary coating materials include inorganic materials such as silicon nitride (SiNx) or silicon oxynitride (SiOxNy). In other embodiments, a silicon layer (polycrystalline or monocrystalline) may coat one or both sides of the glass 204. An organic material layer, such as a polymer dielectric material, may also coat one or more sides of the glass 204. Thus, the glass 204 is advantageously substantially free of organic materials (e.g., no adhesives), although the workpiece in stage 202 may contain organic materials within the substrate stack containing the glass 204.

[0032] Glass 204 is advantageously composed of mostly silicon and oxygen. In some embodiments, glass 204 contains at least 23 percent silicon and at least 26 percent oxygen by weight (i.e., wt%). Glass 204 may further contain one or more additives, such as aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, or zinc. In some embodiments where glass 204 contains at least 23 wt% Si and at least 26 wt% O, glass 204 further contains at least 5 wt% Al. Additives in glass 204 may form suboxides (A2O), monooxides (AO), binary oxides (AO2), ternary oxides (ABO3), and mixtures thereof. For example, glass 204 may contain AlOx (e.g., Al2O3), BOx (e.g., B2O3), MgOx (e.g., MgO), CaOx (e.g., CaO), SrOx (e.g., SrO), BaOx (e.g., BaO), SnOx (e.g., SnO2), NaOx (e.g., Na2O), KOx (e.g., K2O), POx (e.g., P2O3), ZrOx (e.g., ZrO2), LiOx (e.g., Li2O), TiOx (e.g., TiO2), or ZnOx (e.g., ZnO2). Therefore, depending on the chemical composition, glass 204 may be called, for example, silica, fused silica, aluminosilicate, borosilicate, or aluminoborosilicate.

[0033] Glass 204 is advantageously a bulk material with a substantially homogeneous composition, in contrast to composite materials that may simply contain glass fillers and / or fibers. In some embodiments, glass 204 is substantially amorphous, but glass 204 may also have other forms or microstructures, such as polycrystalline (e.g., nanocrystalline).

[0034] Returning to Figure 1, method 101 proceeds to block 115, where features are formed in the unpatterned glass 204. The features may be fabricated by any process known to be suitable for bulk glass. In some embodiments, block 115 is accompanied by laser ablation, a glass etching process (laser-assisted or otherwise), or any other technique known to be suitable for forming features through the thickness of the glass at a desired diameter and feature pitch. Examples of features include holes and openings.

[0035] Figures 3A and 3B are cross-sectional views of a glass panel 204 in fabrication stage 210 after alternative features have been formed on the glass panel, according to several embodiments. The features may include through-holes 212 extending through a thickness T1 between the first and second surfaces 206, 208. In a later step, glass through-vias will be formed in the through-holes 212. As shown in Figure 3A, the features may include openings 216, which are blind holes or recesses that do not completely penetrate the thickness T1. In the example shown, the openings 216 are on the first surface 206, but in other examples, the openings 216 may be on the second surface 208. The features may also include openings 218, as shown in Figure 3B, which are through-holes extending through a thickness T1 between the first and second surfaces 206, 208. In a later step, the openings 216, 218 will receive electrical components. The openings 216 and 218 are formed in region 214 of the glass panel 204. Region 214 extends in the xy plane and vertically in the z direction through a thickness T1.

[0036] The examples shown in Figures 3A and 3B illustrate a substantially symmetrical hole formation process that results in through-holes 212 and openings 216, 218 in region 214 of the glass panel 204. Although the holes and openings are shown to have linear sidewalls, in other examples the through-holes and openings are asymmetrical about the longitudinal z-axis and have a tapered x-dimensional lateral width that is largest on the first surface 206 and smallest on the second surface 208. The dimensions of the through-holes 212 and openings 216, 218 may vary depending on the mounting configuration. The dimensions of the openings 216, 218 may be at least slightly larger than the dimensions of the electrical components that will be placed within the openings.

[0037] Figure 3C is a plan view of a glass panel 204 in manufacturing stage 210 after various features have been formed on the glass panel, according to several embodiments. The through-holes 212 may have any shape in the (xy) plane of the plan view, such as substantially circular, rectangular, or any other polygon. Similarly, the openings 216, 218 may have any shape in the plane of the plan view, such as rectangular or square. The openings 216, 218 may take shapes suitable for housing desired electrical components.

[0038] The glass panel 204 includes sides having lengths L1 and L2. The glass panel 204 may be used in a glass core substrate having a larger form factor than conventional IC packages. In some examples, an IC package having the glass panel 204 on its core has an ultra-large form factor (ULFF). Therefore, the glass panel 204 has a relatively large footprint, i.e., a surface area defined by L1 and L2. In some embodiments, the surface of the glass panel is at least 5,000 mm². 2 It has a footprint or area of ​​5,625 mm². For example, the side lengths L1 and L2 may each be 75 mm, thereby giving the footprint or area of ​​the glass panel 5,625 mm². 2The lengths of the sides L1 and L2 do not have to be equal. For example, L1 may be 60 mm and L2 may be 95 mm, resulting in 5,625 mm. 2 The footprint or area of ​​the glass panel is given. In some embodiments, the surface of the glass panel is at least 6,000 mm 2 It has a footprint or area of ​​6,400 mm². For example, the side lengths L1 and L2 may each be 80 mm, thereby giving the footprint or area of ​​the glass panel 6,400 mm². 2 That is the case.

[0039] According to some embodiments, returning to Figure 1, method 101 proceeds to block 120, where the TGV is formed and one or more electrical components are placed within the opening in the region of the glass panel. Figures 4A, 4B, and 4C are cross-sectional views of the glass panel 204 in stage 220 of fabrication, after the TGV has been formed and different electrical components have been placed in the region 214 within the glass panel 204, according to some embodiments. The TGV 222 may include any metallization suitable as a conductive path through the thickness T1 of the substrate. In some examples, the TGV 222 is filled with at least partially copper. The TGV 222 includes conductive features 422 on the first and second surfaces 206, 208. Any suitable electrical components, such as IC dies or electrical circuit devices such as capacitors or inductors, may be placed in the region 214 within the glass panel 204.

[0040] Figure 4A shows the glass panel 204 after the electrical component 402 has been placed in the region 214 of the opening 216. Since the opening 216 does not penetrate the thickness T1 completely, it includes a recessed surface 406 substantially parallel to the first surface 206. The electrical component 402 may be mechanically bonded to the glass panel 204 by an adhesive layer 408 on the recessed surface 406. An underfill material 410 may be formed around the electrical component 402. Exemplary materials for the underfill material 410 include dielectrics and epoxy materials that may be applied in a capillary process. The electrical component 402 includes a conductive feature 412 adjacent to the surface and a conductive feature 414 on the surface, for example, the first surface 206. Although Figure 4A shows the electrical component 402 in a bag-type opening, in other embodiments the electrical component may be placed in a through-type opening. In one example, the electrical component may be placed in a through-hole in the process of mounting the glass panel onto the sacrificial panel. In addition, although Figure 4A shows conductive features 412, 414 on or adjacent to the first surface 206, in other examples the conductive features 412, 414 may be on the second surface 208, or on both surfaces 206, 208.

[0041] In some examples, the electrical component 402 is an IC die. For example, the electrical component 402 may be an integrated voltage regulator (IVR) IC die. In other examples, the electrical component 402 may be an IC die having circuits for performing any desired function, such as input / output interface connections, security, memory, etc. In some embodiments, the electrical component 402 is an optical or photonic IC. In yet another example, the electrical component 402 is an IC die including an active or passive bridge circuit. For example, the electrical component 402 may be a low-cost interconnect bridge (LSI) IC die. In some embodiments, the electrical component 402 is a discrete capacitor or discrete inductor.

[0042] In various embodiments, instead of placing the electrical components in the opening of region 214, the electrical components are formed (or embedded) in the opening of region 214. For example, the electrical components may be embedded capacitors or embedded inductors.

[0043] Figure 4B shows the glass panel 204 after a capacitor 420 has been formed in the opening 216 of region 214. The capacitor 420 includes a dielectric layer 422 between a first electrode 424 and a second electrode 426. Any suitable metal may be used for the electrodes 424, 426. The capacitor 420 includes conductive features 428, 430 on the surface of the glass panel 204. In the example shown, the second electrode 426 is formed on the surface 406, and an underfill material 410 is placed around the capacitor 420. A capacitor of any type or design may be placed in region 214. Examples of capacitors that may be placed in region 214 include core trench capacitors (CTCs) and embedded deep trench capacitors (eDTCs). In some examples, the capacitor may be located in a through-hole in region 214, for example, in the opening 218. In various embodiments, the conductive features 428, 430 may be located on the second surface 208, or on both surfaces 206, 208.

[0044] Figure 4C shows the glass panel 204 after an inductor 440 has been formed in the opening 216 of region 214. The embedded inductor 440 is a coaxial metal loop type inductor. The inductor 440 includes a magnetic material 442 surrounding a plated hole 444. The plated hole 444 includes a conductive material, for example, a metal outer wall 446, which may be fabricated using a plating process. Within the outer wall 446 of the plated hole 444 is an inner core 448, which may be an insulating material, for example, a dielectric material, which may be fabricated using a deposition process. In various embodiments, the conductive material of the outer wall 446 may be copper or another suitable metal. The insulating or dielectric material of the inner core 448 may be an organic material such as epoxy. The magnetic material 442 may be any suitable material having magnetic properties. In some examples, the magnetic material 442 is a ferromagnetic material, a ferrimagnetic material, or a dielectric or organic material comprising a Heusla alloy. The embedded inductor 440 includes conductive features 450, 452 on the surface of the glass panel 204. In a cross-section in the yx plane, the embedded inductor 440 may generally have a cylindrical (or elliptical) shape, or a rectangular shape. Any suitable type or design of inductor may be embedded in region 214. For example, the embedded inductor in region 214 may be an air-core inductor.

[0045] According to some embodiments, returning to Figure 1, method 101 proceeds to block 130, where the redistribution layer (RDL) and interconnection features are formed on the glass panel. Figure 5 is a cross-sectional view of the glass core substrate 502 in fabrication stage 230, after the redistribution layers 504, 506 and interconnection features 508, 510 have been formed on the surface of the glass core substrate 502, according to some embodiments.

[0046] The glass core substrate 502 shown in Figure 5 includes a glass core 512 which may be the same as or similar to the glass panel 204 described above. The glass core 512 may have the same or similar composition, thickness T1, and footprint as the glass panel 204. In some examples, the glass core substrate 502 includes one or more TGV222 extending between the first and second surfaces of the glass core 512, and one or more electrical components 402 within the region of the glass core 512 between the first and second surfaces. In the example shown, five electrical components 402A, 402B, 402C, 402D, and 402D are illustrated. Each of the electrical components 402A, 402B, 402C, and 402D may be a different type of component. For example, any of the electrical components 402A, 402B, 402C, and 402D may be an IC die having an active or passive bridge circuit or a voltage regulation circuit. Furthermore, any of the electrical components 402 may be discrete capacitors or discrete inductors. In the example shown in Figure 5, an embedded inductor 440 is formed within the region of the glass core 512. The embedded inductor 440 extends between the first and second surfaces of the glass core 512. In other embodiments, an embedded capacitor, such as the one shown in Figure 4B, may be provided.

[0047] As shown in Figure 5, the first RDL 504 is formed on a first surface of the glass core 512, and the second RDL 506 is formed on a second surface of the glass core 512 opposite to the first surface. In some examples, the RDL may be formed on only one of the two surfaces. Each of the first and second RDLs 504, 506 includes one or more metal (or metallization) layers and one or more dielectric layers. Dielectric layers containing an organic dielectric material 516, such as Ajinomoto Build-up Film (ABF), polyimide, or other suitable material, are provided on each metallization layer in the RDL. Each metallization layer includes a metal feature, such as a conductive trace or interconnection line 514, e.g., a copper trace. The metal feature in the RDL also includes a conductive via 518.

[0048] In the example shown in Figure 5, the outer layer 520 (e.g., the top or bottom layer) of the glass core substrate 502 is formed on RDLs 504 and 506. The outer layer 520 may contain an organic dielectric material different from the dielectric layer of the RDL. For example, the dielectric material of the outer layer may be a solder resist material 522. As illustrated in Figure 5, interconnection features (or contact pads) 508 and 510 are formed within the outer layer 520 on the top and bottom surfaces of the glass core substrate 502. The interconnection features 508 and 510 may be coplanar with the top and bottom surfaces and may be separated by the solder resist material 522.

[0049] In some examples, the interconnection lines 514 have a pitch of 5 μm or less. Along with the pad size, the size and spacing of the interconnection lines may be designed to match the impedance of the source and load, thereby facilitating high-speed signaling. Within the metallization layer, the dielectric material 516 may isolate the interconnection lines 514. Conductive vias 518 extend through the dielectric layer to connect the interconnection lines 514 and metal features in different metal layers. The interconnection lines 514 may be used to route electrical signals from contacts or features on the surface of the glass core substrate to other points on the surface or to other points in the substrate. For example, the interconnection lines 514 may be used to route electrical signals from a conductive feature on the front to other conductive features on the front or back, or to and from electrical components in the substrate.

[0050] As illustrated in Figure 5, the first RDL504 has a thickness T2, and the second RDL506 has a thickness T3. As used herein, the thickness of a redistribution layer (RDL) may refer to the combined thickness of the metallization layer and the adjacent dielectric layer, e.g., thicknesses T2, T3. In various embodiments, the RDL has a thickness of 100 μm or less. For example, RDL504 has a thickness T2 of 100 μm or less, and RDL506 has a thickness T3 of 100 μm or less. In various embodiments, the individual metallization layers within the RDL may have a thickness of less than 10 μm, and the dielectric layers on the individual metallization layers may have a thickness of 10 to 20 μm. In one example, RDL504 includes five metallization layers, each with a thickness of 7 μm, and five adjacent dielectric layers, each with a thickness of 12 μm, for a combined thickness T2 of 95 μm. In various embodiments, the RDL has 12 or fewer metallization layers. For example, the RDL may have 10 metallization layers.

[0051] In some examples, at least one of the TGV222 extending between the first and second surfaces of the glass core 512 contacts both the first metal feature in RDL504 and the second metal feature in RDL506. The exemplary first and second metal features include an interconnection line 514, or a conductive surface in contact with the interconnection line 514.

[0052] According to some embodiments, returning to Figure 1, method 101 proceeds to block 140, where the first IC die is mounted on the glass core substrate. Figure 6 is a cross-sectional view of the glass core substrate in fabrication stage 240 after the first IC die has been mounted on the surface of the glass core substrate, according to some embodiments.

[0053] Figure 6 shows the glass core substrate 502 after the IC dies 604A, 604B, 604C, and 604D have been mounted on its surface, for example, the front surface 605. The assembly shown in Figure 6 may be referred to as the IC package 602. Each of the IC dies 604A, 604B, 604C, and 604D includes a conductive feature (or pad) 606 on each surface of the IC die facing the front surface 605. The conductive feature 606 is disposed in a layer 609, which may contain a dielectric material or a solder resist material. The conductive feature 606 is coupled to an interconnect feature 508. In some embodiments, the conductive feature 606 is coupled to the interconnect feature 508 by a solder feature 612. In some embodiments, the conductive feature 606 is directly bonded to the interconnect feature 508 using a hybrid bonding technique. When hybrid bonding is used, surface metal features embedded in the insulator of one IC die are directly fused to surface metal features embedded in the insulator (or in this case, within the RDL) of another die. The hybrid bonded interface between dies may include both metallurgically interdiffused metals and chemically bonded insulators. In the example shown in Figure 6, a first-level interconnect (FLI) is formed on the exposed surface of the interconnect feature 510 in preparation for packaging or assembly. In various embodiments, a solder feature 610 is formed as the FLI.

[0054] The IC dies 604A, 604B, 604C, and 604D may include circuits for performing any desired function. For example, any of the IC dies 604A, 604B, 604C, and 604D may be a logic circuit, a power management integrated circuit, a transmitter, a receiver, a memory controller, a communication controller, a controller, a processor, an application-specific integrated circuit (ASIC), or a memory. Any of the IC dies 604A, 604B, 604C, and 604D may be a photonic integrated circuit (PIC) or may include optical or photonic elements. The IC package 602 may include a power supply 620, which may be coupled to the glass core substrate 502. Power may be supplied from the power supply 620 to the IC dies 604A, 604B, 604C, and 604D by conductive structures within the glass core substrate 502, such as RDL504, 506, and TGV222.

[0055] According to some embodiments, returning to Figure 1, method 101 proceeds to block 150, where one or more second IC dies are mounted on a first IC die using hybrid bonding technology, where the first IC die was pre-mounted on the glass core substrate. Block 150 is shown as a dashed line because the operation in block 150 is optional. Figure 7 is a cross-sectional view of the glass core substrate in fabrication stage 250, after the first IC die 704 has been mounted on the surface of the glass core substrate 502 using hybrid bonding technology, according to some embodiments, and the second IC die 706 has been mounted on the first IC die 704.

[0056] As shown in Figure 7, IC dies 704A and 704B are mounted on the front surface 605 of the glass core substrate 502. The assembly shown in Figure 7 may be referred to as the IC package 702. Each of the IC dies 704A and 704B includes a conductive feature (or pad) 714 on the respective surface of the IC die facing the front surface 605. The conductive feature 714 is disposed in a layer 609, which may contain a dielectric material or a solder resist material. The conductive feature 714 is coupled to an interconnect feature 508. In some embodiments, the conductive feature 714 is coupled to the interconnect feature 508 by a solder feature 612. In some embodiments, the conductive feature 714 is directly bonded to the interconnect feature 508 using a hybrid bonding technique.

[0057] Each of the IC dies 704A and 704B includes an upper surface 710 opposite to the surface of the IC die facing the front surface 605. The IC dies 704A and 704B have metal features 714, such as contacts or pads, on the upper surface 710. The metal features 714 may be coplanar with the upper surface 710 and may be separated by a dielectric material 708.

[0058] Each of the IC dies 706A, 706B, 706C, 706D, 706E, and 706F includes a surface 712 facing the upper surface 710 of the IC die 704. Each of the IC dies 706A, 706B, 706C, 706D, 706E, and 706F includes a metal feature 716, such as a contact or pad, on its surface 712. The metal feature 716 may be coplanar with the surface 712 and may be separated by a dielectric material 718.

[0059] In some embodiments, IC die 704A and one or more of IC dies 706A, 706B, and 706C are electrically and mechanically coupled to one another using hybrid bonding technology. Similarly, IC die 704B and one or more of IC dies 706D, 706E, and 706F may be electrically and mechanically coupled to one another using hybrid bonding technology. As an example, referring to IC dies 704A and 706C, the interface between surfaces 710 and 712 may be a hybrid-bonded interface, and the respective metal features 714 and 716 on surfaces 710 and 712 are hybrid-bonded interconnections.

[0060] Any of IC dies 704A and 704B, and any of IC dies 706A, 706B, 706C, 706D, 706E, and 706F may have circuits for performing any desired function. In some examples, any of IC dies 704A and 704B, and any of IC dies 706A, 706B, 706C, 706D, and 706E may have memory circuits or logic circuits. In other examples, any of IC dies 704A and 704B, and any of IC dies 706A, 706B, 706C, 706D, and 706E may be logic circuits, power management integrated circuits, transmitters, receivers, memory controllers, communication controllers, controllers, processors, application-specific integrated circuits (ASICs), or memory. In further examples, any of the IC dies 704A, 704B, and any of the IC dies 706A, 706B, 706C, 706D, and 706E may be photonic integrated circuits (PICs) or may contain optical or photonic elements. The IC package 702 may include a power supply 620, which may be coupled to the glass core substrate 502. Power may be supplied from the power supply 620 to any of the IC dies 704A, 704B, and any of the IC dies 706A, 706B, 706C, 706D, and 706E by conductive structures within the glass core substrate 502, such as RDL504, 506, and TGV222.

[0061] In some embodiments, returning to Figure 1, method 101 proceeds to block 160, where one of the IC packages described herein is mounted to the host component. Figure 8 shows system 800 including IC package 702 in fabrication stage 260 after IC package 702 is mounted to host component 802 by reflowing the FLI interconnect (solder feature 610). In other examples, IC package 602 may be mounted to host component 802. In embodiments, the FLI interconnect 610 is a solder (e.g., SAC) microbump, but other interconnect features are also possible. Host component 802 may also have one or more materials known to be suitable as interposers or package substrates (e.g., epoxy preforms, cored or coreless laminates). Host component 802 may include one or more metallized redistribution levels (not shown) embedded in a dielectric material. Host component 802 may also include one or more IC dies embedded therein.

[0062] The host component 802 may further include a second-level interconnect (SLI) 804. The SLI 804 may have any solder (balls, bumps, etc.) suitable for a given host board architecture (e.g., surface mount FR4). One or more heat spreaders and / or heat sinks 806 may be further coupled to the system 800, as shown by the dashed lines, which may be advantageous, for example, if the IC dies 704, 706 have one or more CPU cores or other circuits of similar power density.

[0063] Figure 9 shows a mobile computing platform and data server machine utilizing one or more devices comprising an IC package 950 having a substrate with a large footprint glass core, one or more thin redistribution layers, and one or more electrical components, as described elsewhere in this specification, for example. The server machine 906 may be any commercial server, for example, comprising any number of high-performance computing platforms arranged in a rack and networked together for electronic data processing. The mobile computing platform 905 may be any portable device configured for electronic data display, electronic data processing, wireless electronic data transmission, or the like. For example, the mobile computing platform 905 may be a tablet, smartphone, laptop computer, etc., and may also include a display screen (e.g., capacitive, inductive, resistive, or optical touchscreen), a chip-level or package-level integration system 910, and a battery 915.

[0064] An IC package 950 having a large footprint glass core substrate, one or more thin redistribution layers, and one or more electrical components, whether or not it is located within an integrated system 910 as shown in enlarged figure 920, or as a standalone package within a server machine 906, as described elsewhere in this specification. The IC package 950 may be further coupled to a host board 960 together with one or more of the following: a power management integrated circuit (PMIC) 930, an RF integrated circuit (RFIC) 925 including a broadband RF (radio) transmitter and / or receiver (TX / RX) (e.g., including a digital baseband, with the analog front-end module further including a power amplifier on the transmit path and a low-noise amplifier on the receive path), and a controller 935. The PMIC 930 may perform battery power regulation, DC / DC conversion, etc., and has an input coupled to a battery 915, and an output that provides current to other functional modules. As further shown, in exemplary embodiments, the RFIC925 has an output coupled to an antenna (not shown) and implements any number of radio standards or protocols, including but not limited to Wi-Fi® (IEEE 802.11 family), WiMAX® (IEEE 802.16 family), IEEE 802.20, Long-Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM®, GPRS, CDMA, TDMA, DECT, Bluetooth®, their derivatives, and any other radio protocols designated as 3G, 4G, 4G, and above.

[0065] Figure 10 is a functional block diagram of an electronic computing device 1000 according to an embodiment of the present invention. The computing device may be found inside a mobile computing platform 905 or a server machine 906 as described elsewhere in this specification. The device 1000 further includes a package substrate 1002 that hosts a number of components, including but not limited to a processor 1004 (e.g., an application processor). The processor 1004 may be physically and / or electrically coupled to the package substrate 1002. In general, the terms “processor” or “microprocessor” may refer to any device or part of a device that processes electronic data from a number of registers and / or memories and converts such electronic data into other electronic data that can be further stored in the number of registers and / or memories. In some examples, one or more components of the computing device 1000 include an IC package 950 having a large footprint glass core substrate, one or more thin redistribution layers, and one or more electrical components as described elsewhere in this specification. In some examples, the package substrate 1002 includes a glass core substrate having a coupled inductor structure integrated on the substrate, as described elsewhere in this specification.

[0066] In various examples, one or more communication chips 1006 may also be physically and / or electrically coupled to the package substrate 1002. In further implementations, the communication chip 1006 may be part of the processor 1004. The computing device 1000 may include other components that may or may not be physically and electrically coupled to the package substrate 1002, depending on its application. These other components include, but are not limited to, volatile memory (e.g., DRAM 1032), non-volatile memory (e.g., ROM 1035), flash memory (e.g., NAND or NOR), magnetic memory (MRAM 1030), graphics processor 1022, digital signal processor, cryptographic processor, chipset 1012, antenna 1025, touchscreen display 1015, touchscreen controller 1065, battery 1016, audio codec, video codec, power amplifier 1021, global positioning system (GPS) device 1040, compass 1045, accelerometer, gyroscope, speaker 1020, camera 1041, and mass storage devices (e.g., hard disk drives, solid-state drives (SSDs), compact disks (CDs), digital versatile disks (DVDs), etc.) or similar.

[0067] The communication chip 1006 may enable wireless communication for data transfer to and from the computing device 1000. The term “wireless” and its derivatives may be used to describe the use of modulated electromagnetic radiation through non-solid media, such as circuits, devices, systems, methods, techniques, and communication channels. This term does not imply that the devices in question are entirely wireless, although this may not be the case in some embodiments. The communication chip 1006 may implement any of a number of wireless standards or protocols. As discussed, the computing device 1000 may include multiple communication chips 1006. For example, a first communication chip may be dedicated to short-range wireless communication such as Wi-Fi and Bluetooth, and a second communication chip may be dedicated to long-range wireless communication such as GPS, EDGE, GPRS, CDMA, WiMAX®, LTE, Ev-DO, and others.

[0068] While certain features described herein have been explained with reference to various implementations, this explanation is not intended to be constrained. Therefore, various modifications of the implementation examples described herein, as well as other implementation examples, are obvious to those skilled in the art to whom this disclosure relates, but are considered to be within the spirit and scope of this disclosure.

[0069] The present invention is not limited to the embodiments described, but it will be recognized that it can be implemented with modifications and changes without departing from the scope of the appended claims. For example, the embodiments described above may include certain combinations of features further provided below.

[0070] Example 1: Integrated circuit (IC) die on a substrate, the substrate having a glass core, the glass core including a first surface and a second surface opposite to the first surface, wherein the first surface is at least 5,000 mm 2An apparatus comprising: having an area of; electrical components within the region of the glass core between the first and second surfaces; and a redistribution layer on the first surface, wherein the redistribution layer has a thickness of 100 μm or less.

[0071] Example 2: The apparatus according to Example 1, wherein the redistribution layer is a first redistribution layer, and the apparatus further comprises a second redistribution layer on the second surface, the second redistribution layer having a thickness of 100 μm or less.

[0072] Example 3: The apparatus according to Example 1 or Example 2, further comprising glass through vias (TGVs) extending between the first and second surfaces, wherein the TGVs are in contact with a first metal feature in the first redistribution layer and a second metal feature in the second redistribution layer.

[0073] Example 4: The apparatus according to any one of Examples 1 to 3, wherein the IC die is a first IC die, and the apparatus further comprises a second IC die located on and directly bonded to the first IC die.

[0074] Example 5: The apparatus according to Example 4, wherein the second IC die has a memory circuit or a logic circuit.

[0075] Example 6: The apparatus according to any one of Examples 1 to 5, wherein the electrical component has a capacitor or an inductor.

[0076] Example 7: The apparatus according to any one of Examples 1 to 3, wherein the IC die is a first IC die and the electrical component has a second IC die.

[0077] Example 8: The apparatus according to Example 7, or any of Examples 1 to 3, wherein the second IC die includes a voltage regulation circuit or a bridge circuit.

[0078] Example 9: The apparatus according to Example 1 or any of Examples 4 to 8, wherein the redistribution layer has interconnection lines having a pitch of 5 μm or less.

[0079] Example 10: The apparatus according to any one of Examples 4 to 9, wherein the IC die is directly bonded to the substrate.

[0080] Example 11: The apparatus according to any one of Examples 4 to 10, wherein the thickness of the glass core is between 0.2 mm and 1.6 mm.

[0081] Example 12: Apparatus comprising a substrate having a glass core, the glass core including a first surface and a second surface opposite to the first surface; electrical components in a region of the glass core between the first and second surfaces; a first redistribution layer on the first surface and a second redistribution layer on the second surface, the first redistribution layer having a plurality of first metallization layers and the second redistribution layer having a plurality of second metallization layers, each of the first and second metallization layers having a thickness in the range of 0.1 μm to 10 μm; and glass through vias extending between the first and second surfaces, the glass through vias in contact with a first metal feature in the first redistribution layer and a second metal feature in the second redistribution layer.

[0082] Example 13: The substrate is at least 5,000 mm 2 The apparatus according to Example 12, having the footprint of the following:

[0083] Example 14: The apparatus according to Example 12 or Example 13, wherein the plurality of first metallization layers are less than 12 layers.

[0084] Example 15: The apparatus according to any one of Examples 12 to 14, further comprising the IC die bonded to a metal feature between the first face of the integrated circuit (IC) die and the first redistribution layer.

[0085] Example 16: The apparatus according to any one of Examples 12 to 15, wherein the IC die is a first IC die, the first IC die having a second face opposite to the first face, and the apparatus further comprises a second IC die bonded directly to a metal feature on the second face of the first IC die.

[0086] Example 17: The electrical component has a capacitor, an inductor, or an integrated circuit (IC) die, and the device according to any one of Examples 12 to 16.

[0087] Example 18: A substrate having a glass layer, the glass layer including a first surface and a second surface opposite the first surface; a first redistribution layer (RDL) adjacent to the first surface and a second RDL adjacent to the second surface, where the first RDL has a thickness of 100 μm or less; at least one glass via extending between the first and second RDLs; an integrated circuit (IC) die bonded to a metal feature on the first RDL; and a power supply coupled to the substrate to power the IC die.

[0088] Example 19: The first surface has an area of at least 5,000 mm 2 and the system according to Example 18.

[0089] Example 20: The system according to Example 18 or Example 19, further comprising an electrical component within a region of the glass core between the first and second surfaces. Other possible items (Item 1) An integrated circuit (IC) die on a substrate, the substrate having a glass core, the glass core including a first surface and a second surface opposite the first surface, where the first surface has an area of at least 5,000 mm 2 ; an electrical component within a region of the glass core between the first and second surfaces; and a redistribution layer on the first surface, where the redistribution layer has a thickness of 100 μm or less and the device comprising. (Item 2) The redistribution layer is a first redistribution layer, and the device further comprises a second redistribution layer on the second surface, where the second redistribution layer has a thickness of 100 μm or less, and the device according to Item 1. (Item 3) The apparatus according to item 2, further comprising glass through vias (TGVs) extending between the first and second surfaces, wherein the TGVs are in contact with a first metal feature in the first redistribution layer and a second metal feature in the second redistribution layer. (Item 4) The apparatus according to item 1, wherein the IC die is a first IC die, and the apparatus further comprises a second IC die located on and directly bonded to the first IC die. (Item 5) The apparatus according to item 4, wherein the second IC die has a memory circuit or a logic circuit. (Item 6) The device according to item 1, wherein the electrical component has a capacitor or an inductor. (Item 7) The apparatus according to item 1, wherein the IC die is a first IC die and the electrical component has a second IC die. (Item 8) The apparatus according to item 7, wherein the second IC die includes a voltage regulation circuit or a bridge circuit. (Item 9) The apparatus according to item 1, wherein the redistribution layer has interconnection lines having a pitch of 5 μm or less. (Item 10) The apparatus described in item 1, wherein the IC die is directly bonded to the substrate. (Item 11) The apparatus according to item 1, wherein the thickness of the glass core is between 0.2 mm and 1.6 mm. (Item 12) A substrate having a glass core, the glass core including a first surface and a second surface opposite to the first surface; Electrical components within the region of the glass core between the first and second surfaces; A first redistribution layer on the first surface, and a second redistribution layer on the second surface, the first redistribution layer having a plurality of first metallization layers, and the second redistribution layer having a plurality of second metallization layers, where each of the first and second metallization layers has a thickness in the range of 0.1 μm to 10 μm; and Glass through vias extending between the first and second surfaces, wherein the glass through vias are in contact with a first metal feature in the first redistribution layer and a second metal feature in the second redistribution layer. A device equipped with the following features. (Item 13) The substrate has a minimum of 5,000 mm 2 The apparatus described in item 12, having the footprint of the following: (Item 14) The apparatus according to item 12, wherein the plurality of first metallization layers are less than 12 layers. (Item 15) The apparatus according to item 12, further comprising the IC die bonded to a metal feature between the first face of the integrated circuit (IC) die and the first redistribution layer. (Item 16) The apparatus according to item 15, wherein the IC die is a first IC die, the first IC die having a second surface opposite to the first surface, and the apparatus further comprises a second IC die directly bonded to a metal feature on the second surface of the first IC die. (Item 17) The apparatus according to item 12, wherein the electrical component has a capacitor, an inductor, or an integrated circuit (IC) die. (Item 18) A substrate having a glass layer, the glass layer including a first surface and a second surface opposite to the first surface; A first redistribution layer (RDL) adjacent to the first surface, and a second RDL adjacent to the second surface, wherein the first RDL has a thickness of 100 μm or less; At least one glass-penetrating via extending between the first and second RDLs; An integrated circuit (IC) die bonded to a metal feature on the first RDL; and A power supply coupled to the substrate for supplying power to the IC die. A system equipped with these features. (Item 19) The first surface has a minimum thickness of 5,000 mm 2 The system described in item 18, having the area of ​​the above. (Item 20) The system according to item 18, further comprising electrical components in the region of the glass layer between the first and second surfaces.

Claims

1. An integrated circuit (IC) die on a substrate, the substrate having a glass core, the glass core including a first surface and a second surface opposite to the first surface, wherein the first surface is at least 5,000 mm ２ Having an area of; Electrical components within the region of the glass core between the first surface and the second surface; and The redistribution layer on the first surface, wherein the redistribution layer has a thickness of 100 μm or less. A device equipped with the following features.

2. The apparatus according to claim 1, wherein the redistribution layer is a first redistribution layer, and the apparatus further comprises a second redistribution layer on the second surface, the second redistribution layer having a thickness of 100 μm or less.

3. The apparatus according to claim 2, further comprising glass through vias (TGVs) extending between the first surface and the second surface, wherein the TGVs are in contact with a first metal feature in the first redistribution layer and a second metal feature in the second redistribution layer.

4. The apparatus according to any one of claims 1 to 3, wherein the IC die is a first IC die, and the apparatus further comprises a second IC die located on and directly bonded to the first IC die.

5. The apparatus according to claim 4, wherein the second IC die has a memory circuit or a logic circuit.

6. The apparatus according to any one of claims 1 to 3, wherein the electrical component comprises a capacitor or an inductor.

7. The apparatus according to any one of claims 1 to 3, wherein the electrical component has an inductor comprising a magnetic material surrounding a feature extending between the first surface and the second surface, the feature comprising an outer wall comprising a conductive material and an inner core comprising an insulating material.

8. The apparatus according to any one of claims 1 to 3, wherein the IC die is a first IC die, and the electrical component has a second IC die.

9. The apparatus according to claim 8, wherein the second IC die includes a voltage adjustment circuit or a bridge circuit.

10. The apparatus according to claim 2 or 3, wherein the redistribution layer has interconnection lines having a pitch of 5 μm or less.

11. The apparatus according to any one of claims 1 to 3, wherein the IC die is directly bonded to the substrate.

12. The apparatus according to claim 2 or 3, wherein the thickness of the glass core is between 0.2 mm and 1.6 mm.

13. The apparatus according to claim 2 or 3, wherein the first redistribution layer has a plurality of first metallization layers, the second redistribution layer has a plurality of second metallization layers, and each of the first metallization layers and the second metallization layers has a thickness in the range of 0.1 μm to 10 μm.

14. The apparatus according to claim 13, wherein the plurality of first metallization layers are less than 12 layers.

15. The apparatus according to any one of claims 1 to 3, further comprising a power supply coupled to the substrate for supplying power to the IC die.

16. A substrate having a glass core, the glass core including a first surface and a second surface opposite to the first surface; Electrical components within the region of the glass core between the first surface and the second surface; A first redistribution layer on the first surface, and a second redistribution layer on the second surface, the first redistribution layer having a plurality of first metallization layers, and the second redistribution layer having a plurality of second metallization layers, where each of the first metallization layer and the second metallization layer having a thickness in the range of 0.1 μm to 10 μm; and Glass through vias extending between the first surface and the second surface, wherein the glass through vias are in contact with a first metal feature in the first redistribution layer and a second metal feature in the second redistribution layer. A device equipped with the following features.

17. The substrate has a diameter of at least 5,000 mm ２ The apparatus according to claim 16, having the footprint of the following:

18. The apparatus according to claim 16 or claim 17, wherein the plurality of first metallization layers are less than 12 layers.

19. The apparatus according to claim 16 or 17, further comprising the IC die bonded to a first metal feature between the first surface of the integrated circuit (IC) die and the first redistribution layer.

20. The apparatus according to claim 19, wherein the IC die is a first IC die, the first IC die has a second surface opposite to the first surface, and the apparatus further comprises a second IC die directly bonded to a second metal feature on the second surface of the first IC die.

21. The apparatus according to claim 16 or 17, wherein the electrical component comprises a capacitor, an inductor, or an integrated circuit (IC) die.

22. A substrate having a glass layer, the glass layer including a first surface and a second surface opposite to the first surface; A first redistribution layer (RDL) adjacent to the first surface, and a second RDL adjacent to the second surface, wherein the first RDL has a thickness of 100 μm or less; At least one glass through-via extending between the first RDL and the second RDL; An integrated circuit (IC) die bonded to a metal feature on the first RDL; and A power supply coupled to the substrate for supplying power to the IC die. A system equipped with these features.

23. The first surface is at least 5,000 mm ２ The system according to claim 22, having an area of ​​the above.

24. The system according to claim 22 or claim 23, wherein the thickness of the glass layer is between 0.2 mm and 1.6 mm.

25. The system according to claim 22 or 23, further comprising an electrical component in the region of the glass layer between the first surface and the second surface.

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