Semiconductor device and method for manufacturing the same

Abstract

The present invention relates to an integrated chip and a method for forming a trench isolation structure having a multilayer film stack forming one or more potential wells configured to trap charge carriers. This invention achieves a reduction in unwanted current and / or improved performance of the integrated chip. [Solution] The present invention relates to an integrated chip in some embodiments. The integrated chip includes a substrate having a device region containing one or more semiconductor devices. The substrate has one or more inner surfaces that form one or more trenches within the substrate along opposing sides of the device region. A multilayer film stack is arranged along one or more inner surfaces of the substrate. A core material is placed in one or more trenches and surrounded by the multilayer film stack. The multilayer film stack includes a plurality of dielectric materials, each having a different electron affinity. The plurality of dielectric materials are arranged to form one or more potential wells within the multilayer film stack.

Description

Background Art

[0002]

[0001] Integrated circuits (ICs) equipped with image sensors are used in a wide range of modern electronic devices such as cameras and mobile phones. In recent years, complementary metal-oxide-semiconductor (CMOS) image sensors have become widely used and have largely replaced charge-coupled device (CCD) image sensors. Compared with CCD image sensors, CMOS image sensors are becoming increasingly popular due to their low power consumption, small size, high-speed data processing, direct data output, and low manufacturing cost. CMOS image sensors include front-side illumination (FSI) image sensors and back-side illumination (BSI) image sensors.

Summary of the Invention

Problems to be Solved by the Invention

[0002] The present invention relates to an integrated chip including / forming a trench isolation structure having a multilayer film stack that forms one or more potential wells configured to capture charge carriers, and a method of forming the same.

Means for Solving the Problems

[0003] According to an embodiment of the present invention, an integrated chip includes a substrate, a multilayer film stack, and a core material. The substrate has a device region including one or more semiconductor devices and has one or more inner surfaces that form one or more trenches in the substrate along opposite sides of the device region. The multilayer film stack is disposed along one or more inner surfaces of the substrate. The core material is disposed within one or more trenches and is surrounded by the multilayer film stack. The multilayer film stack includes a plurality of dielectric materials having different electron affinities, and the plurality of dielectric materials are arranged to form one or more potential wells within the multilayer film stack.

[0004] According to one embodiment of the present invention, an integrated chip includes a substrate and one or more trench isolation structures. The substrate has pixel regions including an image sensor configured to convert radiation into electrical signals. One or more trench isolation structures are arranged in the substrate along opposing sides of the pixel regions. One or more trench isolation structures include a first dielectric material having a first electron affinity, a second dielectric material disposed on the first dielectric material and having a second electron affinity, a third dielectric material disposed on the second dielectric material and having a third electron affinity, a fourth dielectric material disposed on the third dielectric material and having a fourth electron affinity, and a core material disposed on the fourth dielectric material. The second electron affinity is greater than both the first and third electron affinities.

[0005] According to one embodiment of the present invention, a method for forming an integrated chip includes forming a semiconductor device in a substrate having a first surface and a second surface, etching the second surface of the substrate to form one or more trenches in the substrate along the side facing the semiconductor device, and forming a multilayer film stack in one or more trenches and along the second surface of the substrate, wherein the multilayer film stack includes a plurality of dielectric materials having different electron affinities that form one or more potential wells, and forming a core material in one or more trenches and on the multilayer film stack. [Effects of the Invention]

[0006] By reducing unnecessary current (e.g., dark current, leakage current, etc.), the performance of the integrated chip can be improved. [Brief explanation of the drawing]

[0007] The aspects of the present invention will be best understood by reading the following detailed description in conjunction with the accompanying drawings. Note that, in accordance with standard industry practice, various features are not depicted to scale. In fact, the dimensions of various features may be arbitrarily enlarged or reduced for the sake of clarity in the discussion. [Figure 1A]The images show cross-sectional views of several embodiments of an integrated chip that include a trench isolation structure having a multilayer film stack forming a potential well configured to trap charge carriers. [Figure 1B] Figure 1A shows an exemplary energy band diagram related to the disclosed multilayer film stack, cut along line 112. [Figure 2A] Cross-sectional views of several additional embodiments of an integrated chip, including a trench isolation structure having a multilayer film stack forming a potential well configured to trap charge carriers, are shown. [Figure 2B] Figure 2A shows an exemplary energy band diagram related to the disclosed multilayer film stack 108, cut along line 204. [Figure 3A] The following are some additional embodiments of an integrated chip that include a trench isolation structure having a multilayer film stack forming one or more potential wells configured to trap charge carriers. [Figure 3B] An exemplary energy band diagram is shown, cut along line 302 in Figure 3A. [Figure 3C] An exemplary energy band diagram is shown, cut along line 302 in Figure 3A. [Figure 4A] Cross-sectional views of several additional embodiments of an integrated chip including a trench isolation structure having the disclosed multilayer film stack are shown. [Figure 4B] Cross-sectional views of several additional embodiments of an integrated chip including a trench isolation structure having the disclosed multilayer film stack are shown. [Figure 5A] Cross-sectional views of several embodiments of an image sensor integrated chip including a trench isolation structure having a disclosed multilayer film stack are shown. [Figure 5B] Figure 5A shows several embodiments of a top view of an image sensor integrated chip whose structure is disclosed. [Figure 6]Several additional embodiments of an image sensor integrated chip including a trench isolation structure having a disclosed multilayer film stack are shown. [Figure 7A] Several embodiments of an image sensor integrated chip including a trench isolation structure having a disclosed multilayer film stack are shown. [Figure 7B] Figure 7A shows several embodiments of a top view of an image sensor integrated chip whose structure is disclosed. [Figure 8] Cross-sectional views of several embodiments of an image sensor integrated chip including multiple trench isolation structures having a disclosed multilayer film stack are shown. [Figure 9] Cross-sectional views of several embodiments of an image sensor integrated chip including multiple trench isolation structures having a disclosed multilayer film stack are shown. [Figure 10] Cross-sectional views of several embodiments of an image sensor integrated chip including multiple trench isolation structures having a disclosed multilayer film stack are shown. [Figure 11] Cross-sectional views of several embodiments of an image sensor integrated chip including multiple trench isolation structures having a disclosed multilayer film stack are shown. [Figure 12] The images show cross-sectional views of several embodiments of a method for forming an integrated chip, which includes a trench isolation structure having a multilayer film stack that forms a potential well configured to trap charge carriers. [Figure 13] The images show cross-sectional views of several embodiments of a method for forming an integrated chip, which includes a trench isolation structure having a multilayer film stack that forms a potential well configured to trap charge carriers. [Figure 14] The images show cross-sectional views of several embodiments of a method for forming an integrated chip, which includes a trench isolation structure having a multilayer film stack that forms a potential well configured to trap charge carriers. [Figure 15]A cross-sectional view of some embodiments of a method of forming an integrated chip including a trench isolation structure having a multilayer film stack that forms a potential well configured to capture charge carriers is shown. [Figure 16] A cross-sectional view of some embodiments of a method of forming an integrated chip including a trench isolation structure having a multilayer film stack that forms a potential well configured to capture charge carriers is shown. [Figure 17] A cross-sectional view of some embodiments of a method of forming an integrated chip including a trench isolation structure having a multilayer film stack that forms a potential well configured to capture charge carriers is shown. [Figure 18] A cross-sectional view of some embodiments of a method of forming an integrated chip including a trench isolation structure having a multilayer film stack that forms a potential well configured to capture charge carriers is shown. [Figure 19] A cross-sectional view of some embodiments of a method of forming an integrated chip including a trench isolation structure having a multilayer film stack that forms a potential well configured to capture charge carriers is shown. [Figure 20] A cross-sectional view of some embodiments of a method of forming an integrated chip including a trench isolation structure having a multilayer film stack that forms a potential well configured to capture charge carriers is shown. [Figure 21] A cross-sectional view of some embodiments of a method of forming an integrated chip including a trench isolation structure having a multilayer film stack that forms a potential well configured to capture charge carriers is shown. [Figure 22] A cross-sectional view of some embodiments of a method of forming an integrated chip including a trench isolation structure having a multilayer film stack that forms a potential well configured to capture charge carriers is shown. [Figure 23]A cross-sectional view of some embodiments of a method of forming an integrated chip including a trench isolation structure having a multilayer film stack that forms a potential well configured to capture charge carriers is shown. [Figure 24] A cross-sectional view of some embodiments of a method of forming an integrated chip including a trench isolation structure having a multilayer film stack that forms a potential well configured to capture charge carriers is shown. [Figure 25] A cross-sectional view of some embodiments of a method of forming an integrated chip including a trench isolation structure having a multilayer film stack that forms a potential well configured to capture charge carriers is shown. [Figure 26] A cross-sectional view of some embodiments of a method of forming an integrated chip including a trench isolation structure having a multilayer film stack that forms a potential well configured to capture charge carriers is shown. [Figure 27] A flowchart of some embodiments of a method of forming an integrated chip including a trench isolation structure having a multilayer film stack that forms a potential well configured to capture charge carriers is shown. **DETAILED DESCRIPTION OF THE INVENTION**

[0008] The following disclosure provides many different embodiments or examples for carrying out different features of the subject matter provided. For the sake of brevity of the invention, specific examples of components and arrangements are described below. These are, of course, merely examples and are not intended to be limiting. For example, forming a first feature on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature is formed between the first and second features, and the first and second features do not need to be in direct contact. Furthermore, the invention may repeat reference numerals and / or words in various examples. This repetition is for the sake of brevity and clarity and does not in itself define the relationships between the various embodiments and / or configurations discussed.

[0009] Furthermore, spatially relative terms such as “down,” “below,” “underside,” “up,” and “top” may be used in this specification to facilitate the description of the relationship between one element or feature and another, as shown in the figures. These spatially relative terms are intended to encompass different orientations of the device during use or operation, in addition to the orientation shown in the figures. The device may also be oriented in other directions (90-degree rotation or other directions), and the spatially relative descriptions used herein may be interpreted accordingly.

[0010] Many electronic devices (e.g., cameras, mobile phones, computers, etc.) include one or more image sensor integrated chips (ICs) that contain image sensors configured to capture images. An image sensor IC may include a large array of pixel regions, each containing an image sensor, arranged on a semiconductor substrate. The pixel regions are often electrically isolated from each other by trench isolation structures (e.g., deep trench isolation structures). The trench isolation structures may consist of insulating materials placed in trenches within the semiconductor substrate.

[0011] In the fabrication of trench isolation structures, a semiconductor substrate may be etched to form trenches, which are then filled with one or more dielectric materials. The etching process to form the trenches can damage the semiconductor substrate and cause defects (e.g., dangling bonds) along the inner surface of the substrate where the trenches are formed. These defects can trap electrons and cause unwanted leakage currents between adjacent pixel regions, potentially leading to dark current and / or white pixel problems in the image sensor IC.

[0012] Some trench isolation structures may include a high-dielectric-constant dielectric material placed along the inner surface of the semiconductor substrate forming the trench. The high-dielectric-constant dielectric material accumulates charge, and this charge generates an electric field that accumulates holes along the inner surface of the semiconductor substrate. These accumulated holes are configured to deactivate defects, thereby mitigating dark current and / or white pixel problems. However, it is recognized that the electric field provided by such high-dielectric-constant dielectric materials may not be strong enough to achieve a hole density sufficient to effectively deactivate electrons trapped in defects. Therefore, image sensor ICs with high-dielectric-constant dielectric material along the sidewalls of trenches formed during the manufacturing of trench isolation structures may still suffer from performance degradation due to dark current and / or white pixel problems.

[0013] The present invention relates to an integrated chip comprising a trench isolation structure having a multilayer film stack forming a potential well configured to trap charge carriers. In some embodiments, the integrated chip comprises a substrate having a device region comprising one or more semiconductor devices (e.g., one or more image sensors). The substrate has one or more inner surfaces that form one or more trenches within the substrate along opposing sides of the device region. The trench isolation structure is located within one or more trenches. The trench isolation structure comprises a multilayer film stack and a core material. The multilayer film stack is located within one or more trenches and along one or more inner surfaces of the substrate. The multilayer film stack comprises a plurality of dielectric materials, each having a different electron affinity. The plurality of dielectric materials are arranged to form one or more potential wells within the multilayer film stack. The potential wells can trap charge carriers (e.g., electrons). By trapping charge carriers, the multilayer film stack can increase the total charge associated with the isolation structure and generate an electric field that attracts opposing charge carriers (e.g., holes) toward one or more inner surfaces of the substrate. The opposite charge carriers can deactivate defects (e.g., traps) along one or more inner surfaces of the substrate, thereby reducing unwanted currents (e.g., dark current, leakage current, etc.) and improving the performance of the integrated chip.

[0014] Figure 1A shows cross-sectional views of several embodiments of an integrated chip 100 that include a trench isolation structure having a multilayer film stack forming a potential well configured to trap charge carriers.

[0015] The integrated chip 100 includes a substrate 102 having a first surface 102a and a second surface 102b facing the first surface 102a. The substrate 102 includes a device region 106 having a semiconductor device. In some embodiments, the semiconductor device includes and / or may be a transistor device such as a planar FET, a FinFET, a gate-all-around structure, a nanowire structure, or a high-voltage device. In other embodiments, the semiconductor device includes, or may be, an image sensor configured to convert incident light into an electrical signal. In some embodiments, the image sensor may include a photodiode (e.g., a PN photodiode, a PIN photodiode, a Schottky photodiode, an avalanche photodiode, etc.).

[0016] The substrate 102 includes one or more inner surfaces (e.g., sidewalls) that form one or more trenches 104 arranged along opposing sides of the device region 106. The one or more trenches 104 extend from a first surface 102a of the substrate 102 into the substrate 102. The trench isolation structure 111 is located within the one or more trenches 104. The trench isolation structure 111 includes a multilayer film stack 108 and a core material 110. The multilayer film stack 108 is located along one or more inner surfaces of the substrate 102. The multilayer film stack 108 isolates the core material 110 from the substrate 102. In some embodiments, the multilayer film stack 108 extends along sidewalls and bottoms facing the core material 110.

[0017] The multilayer film stack 108 includes a plurality of dielectric materials 108a to 108d stacked on top of each other. In some embodiments, the multilayer film stack 108 may include a first dielectric material 108a, a second dielectric material 108b stacked on the first dielectric material 108a, a third dielectric material 108c stacked on the second dielectric material 108b, and a fourth dielectric material 108d stacked on the third dielectric material 108c. In some additional embodiments, the multilayer film stack 108 may include one or more additional dielectric materials. Two or more of the plurality of dielectric materials 108a to 108d have different electron affinities. The plurality of dielectric materials 108a to 108d are arranged to give the multilayer film stack 108 a conduction energy band with one or more potential wells (e.g., one potential well, two potential wells, three potential wells, etc.). In some embodiments, the conduction energy band of the multilayer film stack 108 is symmetrical. In some embodiments, the conduction energy band of the multilayer film stack 108 is asymmetrical.

[0018] Figure 1B shows an exemplary energy band figure 118 related to the disclosed multilayer film stack 108, cut along line 112 in Figure 1A.

[0019] As can be seen from the energy band diagram 118, the multiple dielectric materials 108a to 108d of the multilayer film stack 108 have different conduction band energies. The different conduction band energies form a potential well 120 within one of the dielectric materials of the multilayer film stack 108. The potential well 120 can trap charge carriers (e.g., electrons 114 or holes) within the multilayer film stack 108. The trapped charge carriers increase the total charge associated with the trench isolation structure (e.g., 111 in Figure 1A), generating an electric field. This electric field attracts opposing charge carriers (e.g., holes 116 or electrons) toward one or more inner surfaces of the substrate 102 forming one or more trenches 104. The opposing charge carriers within the substrate 102 can deactivate defects within the substrate 102 (e.g., traps 122 configured to trap electrons within the substrate), thereby reducing unwanted currents (e.g., dark currents) within the substrate 102 and improving the isolation between the device region 106 and adjacent device regions.

[0020] Figure 2A shows cross-sectional views of several additional embodiments of the integrated chip 200, which include a trench isolation structure having a multilayer film stack forming a potential well configured to trap charge carriers.

[0021] The integrated chip 200 includes a substrate 102. The substrate 102 includes a device region 106 having semiconductor devices (e.g., transistor devices, image sensors, etc.). The substrate 102 further includes one or more inner surfaces (e.g., sidewalls) that form one or more trenches 104 along opposing sides of the device region 106. In some embodiments, the depth 202 of the one or more trenches 104 may be about 100 nanometers (nm) to about 10 micrometers, 200 nm to about 5 micrometers, and / or other similar values.

[0022] The trench isolation structure 111 is located within one or more trenches 104. The trench isolation structure 111 includes a multilayer film stack 108 that laterally surrounds the core material 110. In some embodiments, the core material 110 may include a conductive material such as aluminum, tungsten, or doped polysilicon. In other embodiments, the core material 110 may include a dielectric material such as a high dielectric constant dielectric material or a low dielectric constant dielectric material. For example, the dielectric material may include aluminum oxide, hafnium oxide, silicon oxide, silicon nitride, etc.

[0023] The multilayer film stack 108 includes a plurality of dielectric materials 108a to 108d stacked on top of each other. For example, the multilayer film stack 108 may include a first dielectric material 108a disposed on one or more inner surfaces of the substrate 102, a second dielectric material 108b stacked on the first dielectric material 108a, a third dielectric material 108c stacked on the second dielectric material 108b, and a fourth dielectric material 108d stacked on the third dielectric material 108c. In some embodiments, the multilayer film stack 108, the core material 110, and the substrate 102 may have horizontally extending surfaces that are substantially coplanar (e.g., planes within the tolerance range of the chemical mechanical planarization (CMP) process).

[0024] Figure 2B shows an exemplary energy band diagram 206 related to the disclosed multilayer film stack 108, cut along line 204 in Figure 2A.

[0025] As shown in the energy band diagram 206, the multiple dielectric materials 108a to 108d have different electron affinities 208 to 214 (for example, different energy values ​​between the conduction band energy 207 and the vacuum energy 216 of the relevant dielectric materials). The multiple dielectric materials 108a to 108d are arranged such that the different electron affinities 208 to 214 form a potential well 120 within the multilayer film stack 108. For example, in some embodiments, the first dielectric material 108a may have a first electron affinity 208, the second dielectric material 108b may have a second electron affinity 210, the third dielectric material 108c may have a third electron affinity 212, and the fourth dielectric material 108d may have a fourth electron affinity 214. In some embodiments, the first electron affinity 208 and the third electron affinity 212 are smaller than the second electron affinity 210, so that a potential well 120 is formed at the location corresponding to the second dielectric material 108b. In various embodiments, the first electron affinity 208 may be greater than, less than, or substantially equal to the third electron affinity 212. In various embodiments, the fourth electron affinity 214 may be greater than, less than, or substantially equal to the first electron affinity 208, the second electron affinity 210, and / or the third electron affinity 212.

[0026] In some embodiments, one or more treatments (e.g., heat treatment, electrical treatment, etc.) can be applied to the multilayer film stack 108 during its manufacture. These treatments cause charge carriers (e.g., electrons 114) from within the substrate 102 and / or core material 110 to tunnel through the potential energy barrier formed by the first dielectric material 108a and / or third dielectric material 108c into the potential well 120. The charge carriers are trapped in the potential well 120, increasing the charge of the multilayer film stack 108. This is because, once the charge carriers enter the potential well 120, the different electron affinities of the different dielectric materials form an energy barrier, preventing the charge carriers from leaving the potential well 120. For example, in some embodiments, the first difference 218 between the first electron affinity 208 and the second electron affinity 210, and the second difference 220 between the second electron affinity 210 and the third electron affinity 212, may be greater than about 0.001 electron volts (eV), greater than about 0.01 eV, less than about 1 eV, greater than about 1 eV, or other similar values.

[0027] Referring again to Figure 2A, in some embodiments, the multiple dielectric materials 108a-108d may have a total thickness 205 in the range of about 50 nanometers (nm) to about 100 nm. If the total thickness 205 is less than about 50 nm, the amount of charge in the multilayer film stack 108 is insufficient to provide a passivation effect against defects in the substrate 102. If the total thickness 205 is greater than about 100 nm, the tunneling effect of charge carriers (e.g., electrons) from the substrate 102 to the potential well formed by the second dielectric material 108b is reduced, thereby decreasing the passivation effect against defects in the substrate 102. In some embodiments, the multiple dielectric materials 108a-108d may have different thicknesses T1-T4. In other embodiments, the multiple dielectric materials 108a-108d may have substantially equal thicknesses T1-T4 to each other.

[0028] In some embodiments, two or more of the dielectric materials 108a to 108d may have different oxygen densities. For example, in some embodiments, the first dielectric material 108a may have a first oxygen density, the second dielectric material 108b may have a second oxygen density, the third dielectric material 108c may have a third oxygen density, and the fourth dielectric material 108d may have a fourth oxygen density. The fourth oxygen density is greater than the third oxygen density. The greater fourth oxygen density causes oxygen in the fourth dielectric material 108d to diffuse into the third dielectric material 108c, forming a dipole within the third dielectric material 108c. The oxygen dipole enhances the electric field generated by the charge carriers (e.g., electrons) trapped in the potential well and / or the opposite charge carriers (e.g., holes) accumulated in the substrate 102, along one or more inner surfaces forming one or more trenches 104.

[0029] In some embodiments, the multiple dielectric materials 108a to 108d may each include oxides, nitrides, dielectric materials, high dielectric constant dielectric materials, etc. In some embodiments, the first dielectric material 108a may include one or more of the following: zirconium oxide, hafnium oxide, hafnium silicon oxide, aluminum lanthanum oxide, yttrium oxide, lanthanum oxide, silicon nitride, aluminum oxide, silicon oxide, etc. In some embodiments, the second dielectric material 108b may include one or more of the following: strontium titanium oxide, tantalum oxide, barium zirconium oxide, zirconium oxide, hafnium oxide, hafnium silicon oxide, aluminum lanthanum oxide, yttrium oxide, lanthanum oxide, silicon nitride, etc. In some embodiments, the third dielectric material 108c may include one or more of the following: zirconium oxide, hafnium oxide, hafnium silicon oxide, aluminum lanthanum oxide, yttrium oxide, lanthanum oxide, silicon nitride, aluminum oxide, silicon oxide, etc. In some embodiments, the fourth dielectric material 108d may contain one or more of the following: aluminum oxide, titanium oxide, tantalum oxide, zirconium oxide, hafnium oxide, magnesium oxide, scandium oxide, silicon oxide, etc.

[0030] Figure 3A shows several additional embodiments of the integrated chip 300, which includes a trench isolation structure having a multilayer film stack that forms a potential well configured to trap charge carriers.

[0031] The integrated chip 300 includes a substrate 102 having one or more trenches 104 arranged along opposite sides of a device region 106 containing semiconductor devices (e.g., transistor devices, image sensors, etc.). The trench isolation structure 111 is located within one or more trenches 104. The trench isolation structure 111 includes a multilayer film stack 108 that laterally surrounds the core material 110. In various embodiments, the core material 110 may include a conductive material (e.g., aluminum, tungsten, doped polysilicon, etc.) or a dielectric material (e.g., aluminum oxide, hafnium oxide, silicon oxide, silicon nitride, etc.).

[0032] The multilayer film stack 108 includes a plurality of dielectric materials 108a to 108e stacked on top of each other. For example, the multilayer film stack 108 may include a first dielectric material 108a disposed on one or more inner surfaces of a substrate 102 forming one or more trenches 104, a second dielectric material 108b stacked on the first dielectric material 108a, a third dielectric material 108c stacked on the second dielectric material 108b, a fourth dielectric material 108d stacked on the third dielectric material 108c, and a fifth dielectric material 108e stacked on the fourth dielectric material 108d. In some embodiments, the plurality of dielectric materials 108a to 108e may have a total thickness 205 in the range of about 50 nanometers (nm) to about 100 nanometers (nm). In some embodiments, the multilayer film stack 108 may include one or more additional dielectric materials.

[0033] In some embodiments, the multiple dielectric materials 108a to 108e may each include oxides, nitrides, dielectric materials, high dielectric constant dielectric materials, etc. In some embodiments, the first dielectric material 108a may include one or more of the following: zirconium oxide, hafnium oxide, hafnium silicon oxide, aluminum lanthanum oxide, yttrium oxide, lanthanum oxide, silicon nitride, aluminum oxide, silicon oxide, etc. In some embodiments, the second dielectric material 108b may include one or more of the following: strontium titanium oxide, tantalum oxide, barium zirconium oxide, zirconium oxide, hafnium oxide, hafnium silicon oxide, aluminum lanthanum oxide, yttrium oxide, lanthanum oxide, silicon nitride, etc. In some embodiments, the third dielectric material 108c may include one or more of the following: zirconium oxide, hafnium oxide, hafnium silicon oxide, aluminum lanthanum oxide, yttrium oxide, lanthanum oxide, silicon nitride, aluminum oxide, silicon oxide, etc. In some embodiments, the fourth dielectric material 108d may contain one or more of the following: strontium titanium oxide, tantalum oxide, barium zirconium oxide, zirconium oxide, hafnium oxide, hafnium silicon oxide, aluminum lanthanum oxide, yttrium oxide, lanthanum oxide, silicon nitride, etc. In some embodiments, the fifth dielectric material 108e may contain one or more of the following: zirconium oxide, hafnium oxide, hafnium silicon oxide, aluminum lanthanum oxide, yttrium oxide, lanthanum oxide, silicon nitride, aluminum oxide, silicon oxide, etc.

[0034] Multiple dielectric materials 108a to 108e have different electron affinities (e.g., different energy values ​​between conduction band energy and vacuum energy) and form one or more potential wells within the multilayer film stack 108. Figures 3B and 3C show exemplary energy band diagrams related to the disclosed multilayer film stack 108. It should be understood that the exemplary energy band diagrams shown in Figures 3B and 3C are not limiting examples, and the disclosed multilayer film stack may have energy band diagrams of alternative shapes.

[0035] Figure 3B shows an exemplary energy band, Figure 304, cut along line 302 in Figure 3A.

[0036] As shown in the energy band diagram 304, the first dielectric material 108a has a first electron affinity 208, the second dielectric material 108b has a second electron affinity 210, the third dielectric material 108c has a third electron affinity 212, the fourth dielectric material 108d has a fourth electron affinity 214, and the fifth dielectric material 108e has a fifth electron affinity 306. The first electron affinity 208, the third electron affinity 212, and the fifth electron affinity 306 are smaller than the second electron affinity 210 and the fourth electron affinity 214, thereby forming a first potential well 120a at the location of the second dielectric material 108b and a second potential well 120b at the location of the fourth dielectric material 108d. In various embodiments, the first electron affinity 208 may be greater than, less than, or substantially equal to, the third electron affinity 212 and the fifth electron affinity 306. In various embodiments, the second electron affinity 210 may be greater than, less than, or substantially equal to, the fourth electron affinity 214. In some embodiments, the first potential well 120a and the second potential well 120b may have depths 308 of about 0.001 eV, about 0.01 eV, less than 1 eV, about 1 eV, or other similar values, respectively.

[0037] In some embodiments, during the manufacturing of the multilayer film stack 108, a process (e.g., heat treatment, electrical treatment, etc.) may be applied so that electrons 114 from within the substrate 102 and / or core material 110 tunnel through the potential energy barrier of the first dielectric material 108a and / or fifth dielectric material 108e and enter the first potential well 120a and the second potential well 120b. The electrons 114 are confined in the first potential well 120a and the second potential well 120b, increasing the charge of the multilayer film stack 108.

[0038] Figure 3C shows an exemplary energy band diagram 310, cut along line 302 in Figure 3A.

[0039] As shown in the energy band diagram 310, the first electron affinity 208 and the fifth electron affinity 306 are smaller than the second electron affinity 210 and the fourth electron affinity 214, and smaller than the third electron affinity 212, thus forming a stepped potential well 120 within the multilayer film stack 108. The stepped surface of the potential well 120 allows more electrons 114 to tunnel into the potential well 120, thereby increasing the charge within the multilayer film stack 108 and improving the passivation effect of electrons 114 trapped within the potential well 120. This is because the stepped surface of the potential well 120 thins the energy barrier formed by the first dielectric material 108a and / or the fifth dielectric material 108e, thus increasing the probability of electrons tunneling into the potential well 120. Furthermore, the escape probability (for example, due to external noise) of electrons 108c accumulated in the third dielectric material decreases with the depth of the stepped potential well 120.

[0040] In various embodiments, the first electron affinity 208 may be greater than, less than, or substantially equal to, the fifth electron affinity 306. In various embodiments, the second electron affinity 210 may be greater than, less than, or substantially equal to, the fourth electron affinity 214. In some embodiments, the first difference 312 between the first electron affinity 208 and the second electron affinity 210, the second difference 314 between the second electron affinity 210 and the third electron affinity 212, the third difference 316 between the third electron affinity 212 and the fourth electron affinity 214, and the fourth difference 318 between the fourth electron affinity 214 and the fifth electron affinity 306 may be greater than about 0.001 eV, greater than about 0.01 eV, less than about 1 eV, or other similar values.

[0041] Figure 4A shows cross-sectional views of several additional embodiments of the integrated chip 400, including a trench isolation structure having the disclosed multilayer film stack.

[0042] The integrated chip 400 includes a substrate 102 having one or more trenches 104 arranged along opposite sides of a device region 106. The device region 106 includes a transistor device 402. The transistor device 402 includes a gate electrode 404 isolated from the substrate 102 by a gate dielectric 406. A source / drain region 408 is arranged along opposite sides of the gate electrode 404. A trench isolation structure 111 is located within one or more trenches 104. The trench isolation structure 111 includes a multilayer film stack 108 that laterally surrounds a core material 110.

[0043] The interlayer dielectric (ILD) structure 410 is disposed on the substrate 102. In some embodiments, the ILD structure 410 includes one or more interlayer dielectric (ILD) layers stacked on top of each other. The ILD structure 410 surrounds one or more interconnects 412. In some embodiments, the one or more interconnects 412 may include conductive contacts, middle-end-of-the-line (MEOL) interconnects, interconnect wires, and / or interconnect vias. In some embodiments, the ILD structure 410 may include a contact etching stop layer (CESL) 414 disposed on the substrate 102. In some embodiments, the ILD structure 410 (e.g., CESL 414) can be in contact with the first dielectric material 108a, the second dielectric material 108b, the third dielectric material 108c, the fourth dielectric material 108d, and the outermost surface of the core material 110.

[0044] Figure 4B shows cross-sectional views of several additional embodiments of the integrated chip 416, including a trench isolation structure having the disclosed multilayer film stack.

[0045] The integrated chip 416 includes a substrate 102 having one or more trenches 104 arranged along the opposite side of a device region 106 containing a transistor device 402. The trench isolation structure 111 is located within one or more trenches 104. The trench isolation structure 111 includes a multilayer film stack 108 that laterally surrounds a core material 110. The core material 110 is conductive.

[0046] The ILD structure 410 is placed on a substrate 102. The ILD structure 410 surrounds one or more interconnects 412. One or more interconnects 412 are electrically connected to a core material 110. One or more interconnects 412 are configured to supply a voltage to the core material 110. This voltage can form an electric field between the core material 110 and the substrate 102. This electric field attracts charge carriers (e.g., electrons) toward the core material 110. In some embodiments, the charge carriers can tunnel into one or more potential wells in a multilayer film stack 108. In some embodiments, one or more interconnects 412 can be connected via through-substrate vias (TSVs) to one or more additional interconnects located along opposing sides of the substrate 102.

[0047] Figures 5A-5B show several embodiments of an image sensor integrated chip including a trench isolation structure having the disclosed multilayer film stack.

[0048] Figure 5A shows cross-sectional views 500 of several embodiments of an image sensor integrated chip including a trench isolation structure having the disclosed multilayer film stack.

[0049] As shown in cross-sectional view 500, the image sensor integrated chip includes a substrate 102 having a device region including a plurality of pixel regions 502a to 502b. Each of the plurality of pixel regions 502a to 502b includes an image sensor 504 configured to convert incident light (e.g., photons) into an electrical signal (i.e., generate electron-hole pairs from incident light). In some embodiments, the image sensor 504 may include a photodiode.

[0050] Multiple gate structures 506 are arranged along the first surface 102a of the substrate 102. A dielectric structure 508 is also arranged along the first surface 102a of the substrate 102. The dielectric structure 508 surrounds multiple conductive interconnects 510. In some embodiments, the dielectric structure 508 includes multiple stacked ILD layers, and the multiple conductive interconnects 510 include alternating layers of conductive vias and conductive wires electrically connected to the multiple gate structures 506. In some embodiments, the multiple gate structures 506 may include multiple transfer gates.

[0051] In some embodiments, a second substrate 512 is coupled to a dielectric structure 508. A plurality of transistor devices 514 are arranged on the second substrate 512. In some embodiments, the plurality of transistor devices 514 may include a first type of transistor device 514a (e.g., NMOS transistors) and a second type of transistor device 514b (e.g., PMOS transistors). In some embodiments, the plurality of transistor devices 514 may be isolated by a shallow trench isolation structure 516. In some embodiments, the plurality of transistor devices 514 may include support circuits. For example, the plurality of transistor devices 514 may include one or more of the following: row decoders, pixel support devices, reset drivers, selection drivers, column amplifiers and / or capacitors, column decoders (e.g., multiplexers), analog / digital converters, etc.

[0052] Multiple pixel regions 502a to 502b are isolated by one or more trench isolation structures 111 located in one or more trenches extending from a second surface 102b of the substrate 102 into the substrate 102. The one or more trench isolation structures 111 include a multilayer film stack 108 and a core material 110. In some embodiments, the one or more trench isolation structures 111 extend perpendicularly from a second surface 102b of the substrate 102 to a first surface 102a of the substrate 102. In some additional embodiments (not shown), the one or more trench isolation structures 111 extend perpendicularly from a second surface 102b of the substrate into a dielectric structure 508.

[0053] Figure 5B shows several embodiments of the top view 518 of the image sensor integrated chip whose structure is disclosed in Figure 5A. In some embodiments, the cross-sectional view of Figure 5A is cut along the line A-A' in the top view 518.

[0054] As shown in the top view 518, the multiple pixel regions 502a to 502b are arranged in rows and columns on the substrate. The rows extend in a first direction 520, and the columns extend in a second direction 522 perpendicular to the first direction 520. One or more trench isolation structures 111 are arranged along opposing sides of the multiple pixel regions 502a to 502b. In some embodiments, one or more trench isolation structures 111 surround the multiple pixel regions 502a to 502b along the first direction 520 and the second direction 522. In some embodiments, one or more trench isolation structures 111 continuously enclose multiple sides of each of the multiple pixel regions 502a to 502b, as shown in the top view 518. In some embodiments, one or more trench isolation structures 111 may enclose the multiple pixel regions 502a to 502b in a closed, uninterrupted loop.

[0055] Figure 6 shows cross-sectional views of several embodiments of an image sensor integrated chip 600, which includes a trench isolation structure having a disclosed multilayer film stack that forms a potential well configured to trap charge carriers.

[0056] The image sensor integrated chip 600 includes a plurality of gate structures 506 arranged along a first surface 102a (e.g., the front surface) of the substrate 102. Each of the plurality of gate structures 506 includes a gate dielectric layer 506d arranged along the first surface 102a of the substrate 102 and a gate electrode 506e disposed on the gate dielectric layer 506d. In some embodiments, sidewall spacers 506s are located on the opposite side of the gate electrode 506e. In some embodiments, a gate structure 506 corresponding to a transfer transistor is arranged laterally between the photodiode 602 and the floating diffusion well 604 within the substrate 102. In such embodiments, the photodiode 602 may include a first region 601 having a first doping type (e.g., n-type doping) and an adjacent second region 603 having a second doping type different from the first doping type (e.g., p-type doping). The gate structures 506 are configured to control the transfer of charge from the photodiode 602 to the floating diffusion well 604. If the charge level in the floating diffusion well 604 is sufficiently high, a source follower transistor (not shown) is activated, and the charge is selectively output according to the operation of a row selection transistor (not shown) used for addressing. A reset transistor (not shown) is configured to reset the photodiode 602 during the exposure period.

[0057] A dielectric structure 508 is also arranged along the first surface 102a (e.g., the front surface) of the substrate 102. The dielectric structure 508 may include a plurality of stacked ILD layers. In various embodiments, the plurality of stacked ILD layers may include one or more of the following: oxides (e.g., SiO2, SiCO, etc.), fluorosilicate glass, phosphate glass (e.g., borate silicate glass), etc. The dielectric structure 508 surrounds a plurality of conductive interconnects 510 electrically connected to the gate structure 506. In some embodiments, the plurality of conductive interconnects 510 may include one or more of the following: copper, aluminum, tungsten, carbon nanotubes, etc. In some embodiments, the dielectric structure 508 is bonded to a second substrate 512 (e.g., a carrier substrate). In some embodiments, the second substrate 512 may contain silicon.

[0058] In some embodiments, a plurality of shallow trench isolation (STI) structures 606 are also arranged within a first surface 102a of the substrate 102. The plurality of STI structures 606 include one or more dielectric materials (e.g., SiO2) arranged within trenches in the first surface 102a of the substrate 102. The plurality of trench isolation structures 111 are arranged within one or more trenches in a second surface 102b (e.g., the back surface) of the substrate 102, located above the plurality of STI structures 606. The plurality of trench isolation structures 111 include a multilayer film stack 108 surrounding a core material 110. In some embodiments, each of the plurality of trench isolation structures 111 may have a width smaller than the width of one of the plurality of STI structures 606. In some embodiments, one or more isolation well regions (not shown) may be arranged between the plurality of STI structures 606 and the plurality of trench isolation structures 111. One or more isolation well regions may include doped regions that provide further separation between adjacent regions of multiple pixel regions 502a to 502b by junction separation.

[0059] In some embodiments, the dielectric structure 609 is arranged along the second surface 102b of the substrate 102. The dielectric structure 609 may also include an anti-reflective structure 608 and a dielectric planarization structure 610 having a substantially flat surface facing away from the substrate 102. In some embodiments, the anti-reflective structure 608 may include a high dielectric constant dielectric layer containing hafnium oxide (HfO2), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O3), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), oxides (e.g., silicon oxide), TEOS, etc. In various embodiments, the dielectric planarization structure 610 may contain oxides (e.g., SiO2) and / or nitrides.

[0060] The grid structure 612 is arranged on the dielectric structure 609. The grid structure 612 includes side walls that form openings covering a plurality of pixel regions 502a to 502c. In various embodiments, the grid structure 612 may include a metal (e.g., aluminum, cobalt, copper, silver, gold, tungsten, etc.) and / or a dielectric material (e.g., SiO2, SiN, etc.). The plurality of color filters 614a to 614c are arranged within the openings of the grid structure 612. Each of the plurality of color filters 614a to 614c is configured to transmit a specific wavelength of incident light. For example, the first color filter 614a can transmit radiation having wavelengths in a first range (e.g., corresponding to green light), and the second color filter 614b can transmit radiation having wavelengths in a second range different from the first range (e.g., corresponding to red light). The plurality of microlenses 616 are arranged on the plurality of color filters 614a to 614c. Each of the multiple microlenses 616 is aligned laterally with the multiple color filters 614a to 614c and positioned above the multiple pixel regions 502a to 502c. The multiple microlenses 616 are configured to focus incident light (e.g., light) toward the multiple pixel regions 502a to 502c.

[0061] In some embodiments, one or more conductive routing layers 618 may be located on or within the dielectric structure 609. The one or more conductive routing layers 618 electrically couple the core material 110 to the bias source 620 (for example, via ports located outside the pixel regions 502a to 502c). In some embodiments, the one or more conductive routing layers 618 may be located below the grid structure 612 so as not to obstruct incident light from reaching the multiple pixel regions 502a to 502c.

[0062] Figures 7A and 7B show several embodiments of an image sensor integrated chip that include a trench isolation structure having a disclosed multilayer film stack that forms a potential well configured to trap charge carriers.

[0063] As shown in the cross-sectional view 700 of Figure 7A, the image sensor integrated chip includes a substrate 102 having a device region containing a plurality of pixel regions 502a to 502b. Each of the plurality of pixel regions 502a to 502b contains an image sensor 504 (e.g., a photodiode). In some embodiments, the plurality of pixel regions 502a to 502b may also be part of a dual photodiode pixel region 502 configured to contain a pair of photodiodes. A plurality of gate structures 506 are arranged along the first surface 102a of the substrate 102. A dielectric structure 508 is also arranged along the first surface 102a of the substrate 102. The dielectric structure 508 surrounds a plurality of conductive interconnects 510.

[0064] Multiple pixel regions 502a to 502b are separated by trench isolation structures 111a to 111b located in one or more trenches extending from the second surface 102b of the substrate 102 into the substrate 102. The trench isolation structures 111a to 111b include a multilayer film stack 108 and a core material 110. The trench isolation structures 111a to 111b may include one or more first trench isolation structures 111a and one or more second trench isolation structures 111b. One or more first trench isolation structures 111a extend perpendicularly from the second surface 102b of the substrate 102 to the first surface 102a of the substrate 102. In some embodiments, one or more first trench isolation structures 111a extend perpendicularly from the second surface 102b of the substrate 102 into the dielectric structure 508. One or more second trench isolation structures 111b extend perpendicularly from the second surface 102b of the substrate to a point not at zero distance from the first surface 102a of the substrate 102.

[0065] Figure 7B shows several embodiments of the top view 702 of the image sensor integrated chip whose structure is disclosed in Figure 7A. In some embodiments, the cross-sectional view of Figure 7A is cut along the line A-A' in the top view 702.

[0066] The top view 702 shows that one or more first trench isolation structures 111a are arranged around a plurality of pixel regions 502a to 502b, and one or more second trench isolation structures 111b separate adjacent pixel regions among the plurality of pixel regions 502a to 502b.

[0067] In various embodiments, the disclosed trench isolation structure may be arranged along different sides of a substrate and / or within one or more trenches extending to different depths within the substrate. Figures 8 to 11 show some additional embodiments of an image sensor integrated chip having trench isolation structures with different configurations.

[0068] Figure 8 shows cross-sectional views of several embodiments of an image sensor integrated chip 800, which includes multiple trench isolation structures having the disclosed multilayer film stack.

[0069] The image sensor integrated chip 800 includes a substrate 102 having a plurality of pixel regions 502a to 502b, each containing an image sensor 504. A plurality of gate structures 506 are arranged along a first surface 102a (e.g., the front surface) of the substrate 102. Dielectric structures 508 are arranged on the first surface 102a of the substrate 102 and around the plurality of gate structures 506. A plurality of color filters 614 are arranged on a second surface 102b (e.g., the back surface) of the substrate 102, which is opposite the first surface 102a. A plurality of microlenses 616 are arranged on the plurality of color filters 614.

[0070] Multiple trench isolation structures 111 are arranged along opposing sides of multiple pixel regions 502a to 502b. Each of the multiple trench isolation structures 111 extends through a portion of the substrate 102 (for example, from the second surface 102b of the substrate 102 to a point not at zero distance from the first surface 102a of the substrate 102), rather than the entire substrate 102. In some embodiments, the multiple trench isolation structures 111 narrow towards the first surface 102a of the substrate 102. Each of the multiple trench isolation structures 111 includes a multilayer film stack 108 surrounding the core material 110. In some embodiments, the multilayer film stack 108 extends around the core material 110 and has an open end along the second surface 102b of the substrate 102.

[0071] Figure 9 shows cross-sectional views of several embodiments of an image sensor integrated chip 900, which includes multiple trench isolation structures having the disclosed multilayer film stack.

[0072] The image sensor integrated chip 900 includes a substrate 102 having a plurality of pixel regions 502a to 502b, each containing an image sensor 504. A plurality of gate structures 506 are arranged along a first surface 102a (e.g., the front surface) of the substrate 102. A dielectric structure 508 is arranged on the first surface 102a of the substrate 102 and around the plurality of gate structures 506. A plurality of color filters 614 are arranged on a second surface 102b (e.g., the back surface) of the substrate 102 that faces the first surface 102a. A plurality of microlenses 616 are arranged on the plurality of color filters 614.

[0073] Multiple trench isolation structures 111 are arranged along opposing sides of multiple pixel regions 502a to 502b. Each of the multiple trench isolation structures 111 extends completely through the substrate 102 (for example, from a first surface 102a of the substrate 102 to a second surface 102b of the substrate 102). In some embodiments, the multiple trench isolation structures 111 narrow towards the second surface 102b of the substrate 102. Each of the multiple trench isolation structures 111 includes a multilayer film stack 108 surrounding the core material 110. In some embodiments, the multilayer film stack 108 extends around the core material 110 and has an open end along the first surface 102a of the substrate 102.

[0074] Figure 10 shows cross-sectional views of several embodiments of the image sensor integrated chip 1000, which includes multiple trench isolation structures having the disclosed multilayer film stack.

[0075] The image sensor integrated chip 1000 includes a substrate 102 having a plurality of pixel regions 502a to 502b, each containing an image sensor 504. A plurality of gate structures 506 are arranged along a first surface 102a (e.g., the front surface) of the substrate 102. A dielectric structure 508 is arranged on the first surface 102a of the substrate 102 and around the plurality of gate structures 506. A plurality of color filters 614 are arranged on a second surface 102b (e.g., the back surface) of the substrate 102 that faces the first surface 102a. A plurality of microlenses 616 are arranged on the plurality of color filters 614.

[0076] The multiple trench isolation structures 111 are arranged along opposing sides of multiple pixel regions 502a to 502b. Each of the multiple trench isolation structures 111 includes one or more first trench isolation structures 111a that completely penetrate the substrate 102 (e.g., from the first surface 102a of the substrate 102 to the second surface 102b of the substrate 102), and one or more second trench isolation structures 111b that penetrate only a portion of the substrate 102, rather than the entirety of it (e.g., from the first surface 102a of the substrate 102 to a non-zero distance from the second surface 102b of the substrate 102). In some embodiments, the multiple trench isolation structures 111 narrow towards the second surface 102b of the substrate 102. Each of the multiple trench isolation structures 111 includes a multilayer film stack 108 surrounding the core material 110. In some embodiments, the multilayer film stack 108 extends around the core material 110 and has an open end along the first surface 102a of the substrate 102.

[0077] Figure 11 shows cross-sectional views of several embodiments of an image sensor integrated chip 1100, which includes multiple trench isolation structures having the disclosed multilayer film stack.

[0078] The image sensor integrated chip 1100 includes a substrate 102 having a plurality of pixel regions 502a to 502b, each containing an image sensor 504. A plurality of gate structures 506 are arranged along a first surface 102a (e.g., the front surface) of the substrate 102. A dielectric structure 508 is arranged on the first surface 102a of the substrate 102 and around the plurality of gate structures 506. A plurality of color filters 614 are arranged on a second surface 102b (e.g., the back surface) of the substrate 102 that faces the first surface 102a. A plurality of microlenses 616 are arranged on the plurality of color filters 614.

[0079] Multiple trench isolation structures 111 are arranged along opposing sides of multiple pixel regions 502a to 502b. Each of the multiple trench isolation structures 111 extends through a portion of the substrate 102 (for example, from the first surface 102a of the substrate 102 to a non-zero distance from the second surface 102b of the substrate 102) rather than the entire substrate 102. In some embodiments, the multiple trench isolation structures 111 narrow towards the second surface 102b of the substrate 102. Each of the multiple trench isolation structures 111 includes a multilayer film stack 108 surrounding the core material 110. In some embodiments, the multilayer film stack 108 extends around the core material 110 and has an open end along the first surface 102a of the substrate 102.

[0080] Figures 12–26 show cross-sectional views 1200–2600 of several embodiments of a method for forming an integrated chip, which includes a trench isolation structure having a multilayer film stack forming one or more potential wells configured to trap charge carriers. Although the cross-sectional views 1200–2600 shown in Figures 12–26 are described in relation to the method, it should be understood that the structures disclosed in Figures 12–26 are not limited to the formation method and may exist independently of the method.

[0081] A substrate 102 is provided, as shown in the cross-sectional view 1200 of Figure 12. In various embodiments, the substrate 102 may be any type of substrate (e.g., silicon, SiGe, SOI, etc.), such as a semiconductor wafer, and any other type of semiconductor and / or epitaxial layer associated therewith. The substrate 102 has a first surface 102a and a second surface 102b opposite the first surface 102a. In some embodiments, the substrate 102 can be bonded to a carrier substrate 1202 and then thinned to reduce the thickness of the substrate 102. In some embodiments, an etching process or a mechanical grinding process may be used to thin the substrate 102.

[0082] As shown in the cross-sectional view 1300 of Figure 13, an image sensor 504 is formed within a plurality of pixel regions 502a to 502b in the substrate 102. In some embodiments, the image sensor 504 may include a photodiode formed by injecting one or more dopant species into a first surface 102a of the substrate 102. For example, the image sensor 504 may be formed by selectively performing a first injection process (e.g., depending on a masking layer) to form a first region having a first doping type (e.g., n-type), and then performing a second injection process to form a second region adjacent to the first region having a second doping type (e.g., p-type) different from the first doping type. In some embodiments, either the first or second injection process may be used to form a floating diffusion well (not shown). In some embodiments, one or more shallow trench isolation (STI) structures 606 may be formed within the first surface 102a of the substrate along the opposing sides of the plurality of pixel regions 502a to 502b.

[0083] As shown in the cross-sectional view 1400 of Figure 14, a plurality of gate structures 506 are formed along the first surface 102a of the substrate 102. In some embodiments, the plurality of gate structures 506 may be formed by forming a gate dielectric layer on the first surface 102a of the substrate 102. In some embodiments, the gate dielectric layer may be deposited by a deposition process (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma CVD (PE-CVD), atomic layer deposition (ALD), sputter deposition, etc.). One or more gate electrodes are formed on the gate dielectric layer. In some embodiments, one or more gate electrodes are formed by a patterning process that deposits gate electrode layers on the gate dielectric layer and then selectively etches the gate electrode layer and the gate dielectric layer.

[0084] As shown in the cross-section 1500 of Figure 15, one or more conductive interconnects 510 are formed within a dielectric structure 508 formed along the first surface 102a of the substrate 102. The dielectric structure 508 includes a plurality of stacked ILD layers, and the one or more conductive interconnects 510 include alternating layers of conductive wires and vias. In some embodiments, one or more of the one or more conductive interconnects 510 can be formed using a damascene process (e.g., a single damascene process or a dual damascene process). The damascene process is performed by forming an ILD layer on the first surface 102a of the substrate 102, etching the ILD layer to form holes and / or trenches, and filling the holes and / or trenches with a conductive material. In some embodiments, the ILD layer can be deposited by physical vapor deposition techniques (e.g., PVD, CVD, PE-CVD, ALD, etc.), and the conductive material can be formed using deposition processes and / or plating processes (e.g., electroplating, electroless plating, etc.). In various embodiments, the conductive material may include tungsten, copper, aluminum, or the like.

[0085] In some embodiments (not shown), the carrier substrate 1202 can be removed after the dielectric structure 508 has been formed. In some embodiments, after removing the carrier substrate 1202, the substrate 102 can be thinned to reduce its thickness. In some embodiments, the dielectric structure 508 may be bonded to an additional support substrate before thinning the substrate 102.

[0086] As shown in the cross-sectional view 1600 of Figure 16, a mask 1602 is formed along the second surface 102b (e.g., the back surface) of the substrate 102. The mask 1602 includes side walls that form openings along the second surface 102b of the substrate 102. In some embodiments, the mask 1602 may be formed by depositing a layer of photosensitive material (e.g., positive or negative photoresist) along the second surface 102b of the substrate 102. The layer of photosensitive material is selectively exposed to electromagnetic radiation according to the photomask. The electromagnetic radiation changes the solubility of the exposed areas in the photosensitive material, forming soluble areas. The photosensitive material is then developed to remove the soluble areas, thereby forming openings in the photosensitive material.

[0087] A pattern formation process is performed on the second surface 102b of the substrate 102 according to the mask 1602. The pattern formation process forms one or more trenches 104 within the second surface 102b of the substrate 102. The one or more trenches 104 extend perpendicularly from the second surface 102b of the substrate 102 into the substrate 102 along the opposing sides of a plurality of pixel regions 502a to 502b. In some embodiments, the pattern formation process can selectively expose the substrate 102 to one or more etchants 1604 (e.g., one or more dry etchants) according to the mask 1602. In some embodiments, the one or more etchants 1604 may have etching chemicals including one or more of oxygen (O2), nitrogen (N2), hydrogen (H2), argon (Ar), and / or fluorine species (e.g., CF4, CHF3, C4F8, etc.).

[0088] As shown in the cross-sectional view 1700 of Figure 17, a first dielectric layer 1702 is formed on the second surface 102b of the substrate 102 and in one or more trenches 104. The first dielectric layer 1702 can be formed to conformally back the sidewall of the substrate 102. The first dielectric layer 1702 has a first electron affinity. In some embodiments, the first dielectric layer 1702 may contain one or more of the following: zirconium oxide, hafnium oxide, silicon hafnium oxide, aluminum lanthanum oxide, yttrium oxide, lanthanum oxide, silicon nitride, aluminum oxide, silicon oxide, etc. In various embodiments, the first dielectric layer 1702 may be deposited by a deposition process (e.g., PVD process, CVD process, PE-CVD process, ALD process, sputter deposition process, etc.).

[0089] As shown in the cross-sectional view 1800 of Figure 18, a second dielectric layer 1802 is formed on the first dielectric layer 1702 and in one or more trenches 104. The second dielectric layer 1802 can be formed to conformally back the sidewalls of the first dielectric layer 1702. The second dielectric layer 1802 has a second electron affinity. In some embodiments, the second dielectric layer 1802 may contain one or more of the following: strontium titanium oxide, tantalum oxide, barium zirconium oxide, zirconium oxide, hafnium oxide, hafnium silicon oxide, lanthanum aluminum oxide, yttrium oxide, lanthanum oxide, silicon nitride, etc. In various embodiments, the second dielectric layer 1802 may be deposited by a deposition process (e.g., PVD process, CVD process, PE-CVD process, ALD process, sputter deposition process, etc.).

[0090] As shown in the cross-sectional view 1900 of Figure 19, a third dielectric layer 1902 is formed on the second dielectric layer 1802 and in one or more trenches 104. The third dielectric layer 1902 can be formed to conformally back the sidewalls of the second dielectric layer 1802. The third dielectric layer 1902 has a third electron affinity. In some embodiments, the third dielectric layer 1902 may contain one or more of the following: zirconium oxide, hafnium oxide, silicon hafnium oxide, aluminum lanthanum oxide, yttrium oxide, lanthanum oxide, silicon nitride, aluminum oxide, silicon oxide, etc. In various embodiments, the third dielectric layer 1902 may be deposited by a deposition process (e.g., PVD process, CVD process, PE-CVD process, ALD process, sputter deposition process, etc.).

[0091] As shown in the cross-sectional view 2000 of Figure 20, a fourth dielectric layer 2002 is formed on the third dielectric layer 1902 and in one or more trenches 104, and a multilayer film stack 108 is formed in one or more trenches 104. The fourth dielectric layer 2002 can be formed to conformally back the sidewalls of the third dielectric layer 1902. The fourth dielectric layer 1802 has a fourth electron affinity. In some embodiments, the fourth dielectric layer 2002 may have a higher oxygen density than the third dielectric layer 1902. In some embodiments, the fourth dielectric layer 2002 may contain one or more of the following: aluminum oxide, titanium oxide, tantalum oxide, zirconium oxide, hafnium oxide, magnesium oxide, scandium oxide, silicon oxide, etc. In various embodiments, the fourth dielectric layer 2002 may be deposited by a deposition process (e.g., PVD process, CVD process, PE-CVD process, ALD process, sputter deposition process, etc.).

[0092] In some embodiments (not shown), a multilayer film stack 108 can be formed by forming one or more additional dielectric layers in one or more trenches. For example, in some embodiments, a multilayer film stack 108 can be formed by forming a fifth dielectric layer on a fourth dielectric layer and in one or more trenches 104. The fifth dielectric layer can be formed to conformally back the sidewalls of the fourth dielectric layer 2002. The fifth dielectric layer has a fifth electron affinity. In some embodiments, the fifth dielectric layer may have a higher oxygen density than the fourth dielectric layer 2002. In some embodiments, the fifth dielectric layer may contain one or more of the following: zirconium oxide, hafnium oxide, silicon hafnium oxide, aluminum lanthanum oxide, yttrium oxide, lanthanum oxide, silicon nitride, aluminum oxide, silicon oxide, etc. In various embodiments, the fifth dielectric layer may be deposited by a deposition process (e.g., PVD process, CVD process, PE-CVD process, ALD process, sputter deposition process, etc.).

[0093] As shown in the cross-sectional view 2100 of Figure 21, a core layer 2102 is formed between one or more trenches 104 and the sidewall of the fourth dielectric layer 2002. In some embodiments, the core layer 2102 may contain a conductive material, while in other embodiments, the core layer 2102 may contain a dielectric material. In some embodiments, the core layer 2102 may be formed by a deposition process (e.g., PVD process, CVD process, PE-CVD process, ALD process, sputter deposition process, etc.) and / or a plating process (e.g., electroplating, electroless plating, etc.).

[0094] As shown in the cross-sectional view 2200 of Figure 22, the planarization process is performed (along line 2202) to remove a portion of the multilayer film stack 108. The planarization process can remove portions of the first dielectric layer (e.g., 1702 in Figure 21), the second dielectric layer (e.g., 1802 in Figure 21), the third dielectric layer (e.g., 1902 in Figure 21), the fourth dielectric layer (e.g., 2002 in Figure 21), and the core layer (e.g., 2102 in Figure 21) outside one or more trenches 104. In some embodiments, the planarization process may include a chemical mechanical polishing (CMP) process. In other embodiments, the planarization process may include an etching process, a grinding process, and so on.

[0095] The planarization process forms one or more trench isolation structures 111 within one or more trenches 104 in the substrate 102. The one or more trench isolation structures 111 include a multilayer film stack 108 and a core material 110. The multilayer film stack 108 includes a plurality of dielectric materials 108a to 108d stacked on top of each other. For example, the multilayer film stack 108 may include a first dielectric material 108a, a second dielectric material 108b stacked on the first dielectric material 108a, a third dielectric material 108c stacked on the second dielectric material 108b, and a fourth dielectric material 108d stacked on the third dielectric material 108c.

[0096] Two or more of the multiple dielectric materials 108a to 108d have different electron affinities. The multiple dielectric materials 108a to 108d are arranged to give the multilayer film stack 108 a conduction energy band with one or more potential wells. For example, in some embodiments, the second electron affinity is greater than the first and third electron affinities, so a potential well is formed at the position corresponding to the second dielectric material 108b. In some embodiments, the second and fourth electron affinities are greater than the first, third, and fifth electron affinities, so potential wells are formed at the positions corresponding to the second dielectric material 108b and the fourth dielectric material 108d. In other embodiments, the second and fourth electron affinities are greater than the first and fifth electron affinities and smaller than the third electron affinity, so a stepped potential well is formed.

[0097] The dielectric structure 609 is formed along the second surface 102b of the substrate 102. In some embodiments, the dielectric structure 609 may be in physical contact with the surfaces of the first dielectric material 108a, the second dielectric material 108b, the third dielectric material 108c, the fourth dielectric material 108d, and the core material 110.

[0098] As shown in the cross-sectional view 2300 of Figure 23A, the substrate 102 is subjected to a heat treatment 2302. In some embodiments, the heat treatment 2302 may include a furnace process, a rapid thermal annealing (RTA), etc. The heat treatment 2302 tunnels charge carriers (e.g., electrons) from within the substrate 102 and / or core material 110 into potential wells in the multilayer film stack 108. In some embodiments, the heat treatment 2302 may be performed by exposing the substrate 102 to a high temperature above about 100°C, above about 500°C, in the range of about 100°C to about 1000°C, or other similar values. In some embodiments, the heat treatment 2302 may be performed by exposing the substrate 203 to a high temperature for a time greater than about 1 minute, between about 1 minute and about 2 minutes, between about 1 minute and about 5 minutes, or other similar values.

[0099] In some alternative embodiments shown in the cross-sectional view 2304 of Figure 23B, one or more conductive routing layers 618 may be formed on or within the dielectric structure 609. The one or more conductive routing layers 618 are electrically connected to the core material 110. The one or more conductive routing layers 618 can be used to apply a bias voltage to the core material 110. The voltage bias causes charge carriers (e.g., electrons or holes) from within the substrate 102 and / or the core material 110 to tunnel into the potential wells in the multilayer film stack 108. In some embodiments, the bias voltage may be in the range of about -5 volts to about 5 volts.

[0100] As shown in the cross-sectional view 2400 of Figure 24, a grid structure 612 is formed on the dielectric structure 609. The grid structure 612 may include metal directly formed on one or more trench isolation structures 111. In some embodiments, the grid structure 612 may be formed by a deposition process and / or a plating process followed by an etching process.

[0101] As shown in the cross-sectional view 2500 of Figure 25, a plurality of color filters 614a to 614b are formed between the dielectric structure 609 and the sidewall of the grid structure 612. In some embodiments, the plurality of color filters 614a to 614b are formed by depositing an optical filtering material on the substrate 102 (e.g., by CVD, PVD, ALD, sputtering, spin-on process, etc.). The optical filtering material is a material that transmits radiation (e.g., light) having a specific wavelength range while blocking light of wavelengths outside that range. In some embodiments, a planarization process (e.g., CMP) can then be performed on the plurality of color filters 614a to 614b to planarize the upper surfaces of the plurality of color filters 614a to 614b.

[0102] As shown in the cross-sectional view 2600 of Figure 26, multiple microlenses 616 are formed on multiple color filters 614a to 614b. In some embodiments, the multiple microlenses 616 may be formed by depositing microlens material on the multiple color filters 614a to 614b (e.g., by CVD, PVD, ALD, sputtering, spin-on process, etc.). A microlens template (not shown) having a curved top surface is patterned on the microlens material. In some embodiments, the microlens template may include a photoresist material that has been exposed using distributed exposure (e.g., in the case of a negative photoresist, more light is exposed at the bottom of the curvature and less light is exposed at the top of the curvature), developed, and fired to form a circular shape. The multiple microlenses 616 are then formed by selectively etching the microlens material according to the microlens template.

[0103] Figure 27 shows flowcharts of several embodiments of the method for forming an integrated chip 2700, which includes a trench isolation structure having a multilayer film stack that forms a potential well configured to trap charge carriers.

[0104] Although Method 2700 is illustrated and described herein as a series of actions or events, it should be understood that the order of the illustrated actions or events should not be interpreted in an restrictive sense. For example, some actions may occur in a different order than those illustrated and / or described herein, and / or concurrently with other actions or events. Furthermore, not all illustrated actions are necessary to carry out one or more aspects or embodiments of the description herein. Moreover, one or more actions shown herein may be performed in one or more separate actions and / or phases.

[0105] In operation 2702, one or more semiconductor devices are formed within the device region of the substrate. In some embodiments, the one or more semiconductor devices may include an image sensor (e.g., a photodiode), a transistor device, and the like. Figures 13 and / or 14 show cross-sectional views 1300 and / or 1400 of some embodiments corresponding to operation 2702.

[0106] In operation 2704, one or more trenches are formed within the substrate. Figure 16 shows cross-sectional views 1600 of several embodiments corresponding to operation 2704.

[0107] In operation 2706, a multilayer film stack is formed in one or more trenches. The multilayer film stack comprises multiple films having different electron affinities. The different electron affinities form one or more potential wells within the multilayer film stack. In some embodiments, the multilayer film stack may be formed according to operations 2708-2714.

[0108] In operation 2708, a first dielectric layer having a first electron affinity is formed along the inner surface of the substrate and within one or more trenches. Figure 17 shows cross-sectional views 1700 of several embodiments corresponding to operation 2708.

[0109] In operation 2710, a second dielectric layer having a second electron affinity is formed along the inner surface of the first dielectric layer and within one or more trenches. Figure 18 shows cross-sectional views 1800 of several embodiments corresponding to operation 2710.

[0110] In operation 2712, a third dielectric layer having a third electron affinity is formed along the inner surface of the second dielectric layer and within one or more trenches. Figure 19 shows cross-sectional views 1900 of several embodiments corresponding to operation 2712.

[0111] In operation 2714, a fourth dielectric layer having a fourth electron affinity is formed along the inner surface of the third dielectric layer and within one or more trenches. Figure 20 shows cross-sectional views 2000 of several embodiments corresponding to operation 2714.

[0112] In operation 2716, a core material is formed along the inner surface of the fourth dielectric film and within one or more trenches. Figure 21 shows cross-sectional views 2100 of several embodiments corresponding to operation 2716.

[0113] In operation 2718, a planarization process is performed to remove the core material and a portion of the multilayer film stack. Figure 22 shows cross-sectional views 2200 of several embodiments corresponding to operation 2718.

[0114] In operation 2720, one or more processes are performed to drive charge carriers (e.g., electrons) into one or more potential wells in the multilayer film stack. In some embodiments, the one or more processes may include one or more of the following: heat treatment, application of a bias voltage, etc. Figure 23A shows cross-sectional views 2300 of several embodiments corresponding to operation 2720. Figure 23B shows cross-sectional views 2304 of several alternative embodiments corresponding to operation 2720.

[0115] In operation 2722, multiple color filters and microlenses are formed on the substrate. Figures 24-26 show cross-sectional views 2300-2500 of several embodiments corresponding to operation 2722.

[0116] Accordingly, in some embodiments, the present invention relates to an integrated chip comprising a trench isolation structure having a disclosed multilayer film stack that forms one or more potential wells configured to trap charge carriers (e.g., electrons).

[0117] In some embodiments, the present invention relates to an integrated chip. The integrated chip includes: a substrate having a device region including one or more semiconductor devices, and having one or more inner surfaces forming one or more trenches in the substrate along opposing sides of the device region; a multilayer film stack disposed along one or more inner surfaces of the substrate; a core material disposed in one or more trenches and surrounded by the multilayer film stack; and a multilayer film stack comprising a plurality of dielectric materials, each having a different electron affinity, wherein the plurality of dielectric materials are arranged to form one or more potential wells in the multilayer film stack. In some embodiments, the device region includes an image sensor configured to convert radiation into electrical signals. In some embodiments, the multilayer film stack includes a first dielectric material having a first electron affinity; a second dielectric material having a second electron affinity greater than the first electron affinity; a third dielectric material having a third electron affinity less than the second electron affinity; and a fourth dielectric material having a fourth electron affinity. In some embodiments, the fourth dielectric material has a higher oxygen density than the third dielectric material. In some embodiments, the conduction energy band of the multilayer film stack is symmetrical. In some embodiments, the conduction energy band of the multilayer film stack is asymmetrical. In some embodiments, one or more potential wells include two potential wells. In some embodiments, the thickness of the multilayer film stack is in the range of about 50 nanometers to about 100 nanometers.

[0118] In other embodiments, the present invention relates to an integrated chip. The integrated chip includes a substrate having a pixel region equipped with an image sensor configured to convert radiation into electrical signals, and one or more trench isolation structures disposed within the substrate along opposite sides of the pixel region, each trench isolation structure comprising a first dielectric material having a first electron affinity, a second dielectric material disposed on the first dielectric material and having a second electron affinity, a third dielectric material disposed on the second dielectric material and having a third electron affinity, a fourth dielectric material disposed on the third dielectric material and having a fourth electron affinity, and a core material disposed on the fourth dielectric material, wherein the second electron affinity is greater than both the first and third electron affinities. In some embodiments, the difference between the first and second electron affinities is greater than 0.001 electron volts (eV). In some embodiments, one or more trench isolation structures further comprise a fifth dielectric material disposed on a fourth dielectric material, wherein the fifth dielectric material has a fifth electron affinity smaller than that of the fourth. In some embodiments, the integrated chip is disposed on a substrate and further comprises a dielectric structure in contact with the outermost surface of the first dielectric material, the second dielectric material, the third dielectric material, the fourth dielectric material, and the core material. In some embodiments, the integrated chip further comprises one or more conductive routing layers within the dielectric structure, the one or more conductive routing layers in contact with the core material, the core material being a conductive material.

[0119] In yet another embodiment, the present invention relates to a method for forming an integrated chip. This method includes forming a semiconductor device in a substrate having a first surface and a second surface; etching the second surface of the substrate to form one or more trenches in the substrate along the side facing the semiconductor device; forming a multilayer film stack in one or more trenches and along the second surface of the substrate, wherein the multilayer film stack comprises a plurality of dielectric materials having different electron affinities that form one or more potential wells; and forming a core material in one or more trenches and on the multilayer film stack. In some embodiments, forming the multilayer film stack includes forming a first dielectric layer having a first electron affinity; forming a second dielectric layer having a second electron affinity greater than the first electron affinity; forming a third dielectric layer having a third electron affinity less than the second electron affinity; and forming a fourth dielectric layer having a fourth electron affinity. In some embodiments, the method further includes performing a planarization process to remove a first dielectric layer, a second dielectric layer, a third dielectric layer, a fourth dielectric layer, and a portion of the core material along a second surface of the substrate. In some embodiments, one or more potential wells are located in a position corresponding to the second dielectric layer and are surrounded by energy barriers corresponding to the first and third dielectric layers. In some embodiments, the fourth dielectric layer has a higher oxygen density than the third dielectric layer. In some embodiments, the method further includes performing a heat treatment to allow charge carriers to tunnel through one or more energy barriers into one or more potential wells. In some embodiments, the method further includes applying a bias voltage to the entire multilayer film stack to allow charge carriers to tunnel through one or more energy barriers into one or more potential wells.

[0120] The above outlines some features of embodiments so that those skilled in the art may better understand aspects of the present invention. Those skilled in the art should understand that the present invention can be readily used as a basis for designing or modifying other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent configurations do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the present invention. [Industrial applicability]

[0121] The present invention relates to an integrated chip including / forming a trench isolation structure having a multilayer film stack forming one or more potential wells configured to trap charge carriers, and a method for forming the same. [Explanation of symbols]

[0122] 100, 200, 300, 400, 416: Integrated chips 102: Circuit board 102a: First face 102b: Second side 104: Trench 106: Device area 108: Multilayer film stack 108a: Dielectric material, first dielectric material 108b: Dielectric materials, second dielectric material 10⁸c: Dielectric material, third dielectric material 108d: Dielectric materials, fourth dielectric material 110: Core material 111, 111a, 111b: Trench isolation structure 112, 204, 302, 2202: Line 114:Electronic 116: Hole 118, 206, 304, 310: Energy band diagrams 120: Potential Well 122: Trap 202, 308: Depth 205: Total thickness 207: Conduction band energy 208: Electron affinity, first electron affinity 210: Electron affinity, second electron affinity 212: Electron affinity, the third electron affinity 214: Electron affinity, the fourth electron affinity 216: Vacuum Energy 218, 312: First difference 220, 314: The second difference 306: The fifth electron affinity 316: The third difference 318: The fourth difference 402, 514: Transistor devices 404, 506e: Gate gate 406: Gate stop gate 408: Source / Drain Area 410: Interlayer Dielectric (ILD) Structure 412: Interconnection 414: Contact Etching Stop Layer (CESL) 500, 700, 1200, 1300, 1400, 1500, 1600, 1700, 1800, 1900, 2000, 2100, 2200, 2300, 2304, 2400, 2500, 2600: Cross-sectional view 502: Dual photodiode pixel region 502a, 502b, 502c: Pixel area 504: Image sensor 506: Gate structure 506d: Gate dielectric layer 506s: Side wall spacer 508, 609: Dielectric structure 510: Conductive interconnection 512: Second circuit board 514a: First type of transistor device 514b: Second type of transistor device 516, 606: Shallow trench isolation structure 518, 702: Top view 520: First direction 522: Second direction 601: First Domain 602: Photodiode 603: Second Domain 604: Floating Diffusion Well 608: Anti-reflection structure 610: Dielectric planarization structure 612: Grid structure 614a: Color filter, first color filter 614b: Color filter, second color filter 614c: Color filter 616: Microlens 618: Conductive routing layer 620: Bias source 800, 900, 1000, 1100: Image sensor integrated chip 1202: Carrier board 1602: Mask 1604: Etchanto 1702: First dielectric layer 1802: Second dielectric layer 1902: Third dielectric layer 2002: Fourth dielectric layer 2102: Core Layer 2302: Heat treatment 2700: Method 2702, 2704, 2706, 2708, 2710, 2710, 2714, 2716, 2718, 2720, 2722: Operation

Claims

1. A substrate having a device region including one or more semiconductor devices, wherein the substrate has one or more inner surfaces that form one or more trenches within the substrate along the opposing side of the device region, A multilayer film stack arranged along one or more inner surfaces of the substrate, A core material disposed within one or more trenches and surrounded by the multilayer film stack, Includes, The multilayer film stack comprises a plurality of dielectric materials, each having a different electron affinity, and the plurality of dielectric materials are arranged to form one or more potential wells within the multilayer film stack. Integrated chip.

2. The device region includes an image sensor configured to convert radiation into an electrical signal. The integrated chip according to claim 1.

3. The aforementioned multilayer film stack is A first dielectric material having a first electron affinity, A second dielectric material having a second electron affinity greater than the first electron affinity, A third dielectric material having a third electron affinity smaller than the second electron affinity, A fourth dielectric material having a fourth electron affinity, The integrated chip according to claim 1, including the above.

4. The fourth dielectric material has a higher oxygen density than the third dielectric material. The integrated chip according to claim 3.

5. The conduction energy band of the aforementioned multilayer film stack is symmetrical. The integrated chip according to claim 1.

6. The conduction energy band of the aforementioned multilayer film stack is asymmetric. The integrated chip according to claim 1.

7. The aforementioned one or more potential wells include two potential wells. The integrated chip according to claim 1.

8. The thickness of the aforementioned multilayer film stack is in the range of approximately 50 nanometers to approximately 100 nanometers. The integrated chip according to claim 1.

9. A substrate having a pixel region including an image sensor configured to convert radiation into electrical signals, The substrate includes one or more trench isolation structures arranged along the opposing sides of the pixel region, The one or more trench isolation structures described above are: A first dielectric material having a first electron affinity, A second dielectric material having a second electron affinity is disposed on the first dielectric material, A third dielectric material having a third electron affinity is disposed on the second dielectric material, A fourth dielectric material disposed on the third dielectric material and having a fourth electron affinity, A core material disposed on the fourth dielectric material, Includes, The second electron affinity is greater than both the first electron affinity and the third electron affinity. Integrated chip.

10. The difference between the first electron affinity and the second electron affinity is greater than 0.001 electron volts (eV). The integrated chip according to claim 9.

11. The one or more trench isolation structures described above are: The present invention includes a fifth dielectric material disposed in the fourth dielectric material, wherein the fifth dielectric material has a fifth electron affinity smaller than that of the fourth dielectric material. The integrated chip according to claim 9, further comprising:

12. The integrated chip according to claim 9, further comprising a dielectric structure disposed on the substrate and in contact with the first dielectric material, the second dielectric material, the third dielectric material, the fourth dielectric material, and the outermost surface of the core material.

13. The dielectric structure further includes one or more conductive routing layers, the one or more conductive routing layers are in contact with the core material, and the core material is a conductive material. The integrated chip according to claim 12.

14. Forming a semiconductor device within a substrate having a first surface and a second surface, Etching the second surface of the substrate to form one or more trenches in the substrate along the side facing the semiconductor device, Forming a multilayer film stack in one or more trenches and along the second surface of the substrate, wherein the multilayer film stack comprises a plurality of dielectric materials having different electron affinities that form one or more potential wells. Forming a core material in the one or more trenches and on the multilayer film stack, A method for forming an integrated chip, including the method described above.

15. Forming the aforementioned multilayer film stack is To form a first dielectric layer having a first electron affinity, To form a second dielectric layer having a second electron affinity greater than the first electron affinity, To form a third dielectric layer having a third electron affinity smaller than the second electron affinity, To form a fourth dielectric layer having a fourth electron affinity, The method according to claim 14, including the method described in claim 14.

16. The process further includes performing a planarization process along the second surface of the substrate to remove the first dielectric layer, the second dielectric layer, the third dielectric layer, the fourth dielectric layer, and a portion of the core material. The method according to claim 15.

17. The one or more potential wells include potential wells located at positions corresponding to the second dielectric layer and surrounded by energy barriers corresponding to the first dielectric layer and the third dielectric layer. The method according to claim 15.

18. The fourth dielectric layer has a higher oxygen density than the third dielectric layer. The method according to claim 15.

19. The further includes performing a heat treatment so that charge carriers tunnel through one or more energy barriers into one or more potential wells. The method according to claim 14.

20. The further includes applying a bias voltage to the entire multilayer film stack so that charge carriers tunnel through one or more energy barriers into one or more potential wells. The method according to claim 14.

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