Method for manufacturing a semiconductor device and a semiconductor device.

Abstract

When the chip size is large, there is a concern that unintended phenomena such as solder cracks may occur during temperature cycling tests, leading to an increase in thermal resistance. [Solution] The semiconductor device A10 comprises a support member 21 having a first surface 221a, a semiconductor element 1 having a second surface 112, and a bonding material 3. The first surface 221a has a first recess 215 and a flat portion 216, and the bonding material 3 is filled into the first recess 215, so that the first surface 221a and the second surface 112 are electrically bonded by the bonding material 3.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device.

Background Art

[0002] The chip is mounted on one surface of a lead frame and is electrically connected to the lead frame via a solder layer. The chip is also fixed by this solder layer.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] When the size of the chip is large, there is a concern that unintended phenomena such as solder cracks may occur in the temperature cycle test, resulting in an increase in thermal resistance.

[0005] [[ID=A39]]This disclosure aims to provide a semiconductor device capable of improving reliability against temperature cycles.

Means for Solving the Problems

[0006] The semiconductor device provided by this disclosure includes a support member having a first surface, a semiconductor element having a second surface, and a bonding material. The first surface or the second surface has a concave portion and a flat portion, the bonding material is filled in the concave portion, and the first surface and the second surface are conductively joined by the bonding material.

Effects of the Invention

[0007] According to this disclosure, reliability against temperature cycles can be improved.

[0008] Other features and advantages of this disclosure will become more apparent from the detailed description below, with reference to the accompanying drawings. [Brief explanation of the drawing]

[0009] [Figure 1] This is a perspective view showing a semiconductor device according to the first embodiment of this disclosure. [Figure 2] Figure 1 is a perspective view of the semiconductor device shown, with the sealing resin omitted. [Figure 3] This is a plan view showing a semiconductor device according to the first embodiment of the present disclosure. [Figure 4] This is a cross-sectional view along the line IV-IV in Figure 3. [Figure 5] This is a cross-sectional view along the VV line in Figure 3. [Figure 6] This is a cross-sectional view showing a first modified example of a semiconductor device according to the first embodiment of this disclosure. [Figure 7] This is a plan view showing a second modified example of a semiconductor device according to the first embodiment of the present disclosure. [Figure 8] This is a cross-sectional view along line VIII-VIII in Figure 7 showing a second modified example of the semiconductor device according to the first embodiment of the present disclosure. [Figure 9] This is a plan view showing a third modified example of a semiconductor device according to the first embodiment of this disclosure. [Figure 10] This is a cross-sectional view along line XX in Figure 9 showing a third modified example of the semiconductor device according to the first embodiment of this disclosure. [Figure 11] This is a cross-sectional view showing a semiconductor device according to a second embodiment of the present disclosure. [Figure 12] This is a cross-sectional view showing a semiconductor device according to a third embodiment of the present disclosure. [Modes for carrying out the invention]

[0010] The embodiments of this disclosure will be described in detail below with reference to the drawings.

[0011] Figures 1 to 5 show a semiconductor device A10 according to a first embodiment of the present disclosure. The semiconductor device A10 of the present disclosure is of a type that is surface-mounted on an electrical circuit board, such as in an automobile or electronic device. The semiconductor device A10 comprises a semiconductor element 1, a lead frame 2, a bonding material 3, wires 4, and a sealing resin 5. Here, the wires 4 include a first wire 41 and a second wire 42. The semiconductor device of the present disclosure is not limited to a configuration comprising wires 4, and may also be configured to include conductive members formed from, for example, a metal plate material instead of wires 4.

[0012] Figure 1 is a perspective view of semiconductor device A10. Figure 2 is a perspective view of Figure 1, with the sealing resin 5 omitted. Figure 3 is a plan view of semiconductor device A10. Figure 4 is a cross-sectional view along line IV-IV in Figure 3. Figure 5 is a cross-sectional view along line VV in Figure 3. Note that in Figure 3, the sealing resin 5 is shown as transparent. For ease of understanding, the thickness direction of semiconductor device A10 is defined as the first direction z, the vertical direction of the plan view (Figure 3) perpendicular to the first direction z is defined as the second direction x, and the horizontal direction of the plan view (Figure 3) perpendicular to both the first direction z and the second direction x is defined as the third direction y. Note that the term "up and down" in the following explanation is used for ease of explanation and does not limit the installation orientation of semiconductor device A10 of this disclosure.

[0013] The semiconductor element 1 is a circuit element made of semiconductor material and is a central element in the function of the semiconductor device A10. The specific example of the semiconductor element 1 is not limited in any way and may be, for example, an IGBT (Insulated Gate Bipolar Transistor), a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), a diode, etc. In this embodiment, the semiconductor element 1 is an IGBT (Insulated Gate Bipolar Transistor). As shown in Figure 4, the semiconductor element 1 has a semiconductor element main surface 111 and a semiconductor element back surface 112.

[0014] The main surface 111 of the semiconductor element is the upper surface of the semiconductor element 1. The back surface 112 of the semiconductor element is the lower surface of the semiconductor element 11. Here, the back surface 112 of the semiconductor element corresponds to the "second surface" of the present disclosure. The main surface 111 of the semiconductor element and the back surface 112 of the semiconductor element face opposite sides in the first direction z.

[0015] A part of the main surface 111 of the semiconductor element is the first electrode pad 113 and the second electrode pad 114. The area of the first electrode pad 113 is smaller than the area of the second electrode pad 114. In the present embodiment, the first electrode pad 113 is the gate electrode of the IGBT, and the second electrode pad 114 is the emitter electrode of the IGBT. Also, the main part of the back surface 112 of the semiconductor element is the third electrode pad 115. In the present embodiment, the third electrode pad 115 is the collector electrode of the IGBT.

[0016] The semiconductor element 1 has a rectangular shape when viewed in the thickness direction (viewed in the first direction z). In the present embodiment, the semiconductor element 1 has dimensions of 1 mm to 10 mm square when viewed in the first direction z. Also, the thickness direction dimension of the semiconductor element 1 is 40 μm to 300 μm.

[0017] The lead frame 2 is a conductive member, and by being joined to the circuit board, it constitutes a conduction path between the semiconductor device A10 and the circuit board. The lead frame 2 is made of an alloy mainly composed of Cu. In addition, in consideration of corrosion resistance, conductivity, heat conductivity, or joining property, etc., a part of the surface may be plated. The lead frame 2 has the first lead 21, the second lead 22, and the third lead 23. Here, the first lead 21 corresponds to the "supporting member" of the present disclosure.

[0018] The first lead 21 includes the first pad 211 (die pad), the first terminal 212, and the intermediate connecting portion 213. The material of the first lead 21 includes copper, nickel, iron, etc.

[0019] The first pad 211 has a pad main surface 211a and a pad back surface 211b. The pad main surface 211a is the upper surface of the first pad 211. Here, the pad main surface 211a corresponds to the "first surface" in this disclosure. The pad main surface 211a is the surface on which the semiconductor element 1 is mounted, and as shown in Figure 4, the back surface 112 of the semiconductor element faces the pad main surface 211a. The pad back surface 211b is the lower surface of the first pad 211. Both the pad main surface 211a and the pad back surface 211b are flat and face opposite each other in the first direction z.

[0020] The pad main surface 211a includes a first recess 215 and a first flat portion 216. The first flat portion 216 is a flat area and, in this embodiment, is perpendicular to the first direction z. The first recess 215 is recessed from the first flat portion 216 in the first direction z and is an example of a "recess" in this disclosure. The first recess 215 includes a first recess bottom surface 215a and a first recess circumferential surface 215b. The first recess bottom surface 215a is the innermost surface in the depth direction (first direction z) of the first recess 215. The first recess circumferential surface 215b is located between the first recess bottom surface 215a and the first flat portion 216. The area of ​​the first recess 215 in plan view, that is, the area enclosed by the edges where the first recess circumferential surface 215b and the first flat portion 216 intersect, is smaller than the area of ​​the back surface 112 of the semiconductor element. In a plan view, the first recess 215 is enclosed within the semiconductor element 1. In a plan view, a portion of the first flat portion 216 overlaps with the semiconductor element 1. As can be seen from Figure 3, the bottom surface 215a of the first recess is assumed to be rectangular, but it may also be triangular, polygonal, circular, or other shapes. The angle α formed by the bottom surface 215a of the first recess and the circumferential surface 215b of the first recess is approximately 45 degrees. The depth of the first recess 215 is not particularly limited, but is approximately 10 μm to 650 μm. The thicker the first pad 211, the deeper the first recess 215 can be made.

[0021] Furthermore, the first pad 211 has a pad through-hole 211c that extends from the main pad surface 211a to the back surface 211b. The pad through-hole 211c is spaced apart from the semiconductor element 1 when viewed in the thickness direction. In this embodiment, the pad through-hole 211c is circular when viewed in the thickness direction, but its shape is not limited.

[0022] As shown in Figures 1 to 3, the first terminal 212 extends along the second direction x, and a portion of it is exposed from the sealing resin 5. The first terminal 212 is electrically connected to the third electrode pad 115 via the intermediate connecting portion 213, the first pad 211, and the bonding material 3. As described above, the third electrode pad 115 is a collector electrode, so the first terminal 212 is the collector terminal of the semiconductor device A1.

[0023] As shown in Figures 2 and 3, the intermediate connecting portion 213 is the part that connects the first pad 211 and the first terminal 212. As shown in Figure 5, in the first direction z, the positions of the first pad 211 and the first terminal 212 are different, with the first pad 211 located below the first terminal 212 in Figure 5. Therefore, the intermediate connecting portion 213 is inclined with respect to the first pad 211 and the first terminal 212. The entire intermediate connecting portion 213 is covered with sealing resin 5.

[0024] As shown in Figures 1 to 3, the second lead 22 is positioned spaced apart from the first lead 21 and extends along the second direction x. In the third direction y, the second lead 22 is located on one side of the first terminal 212. The second lead 22 includes the second pad 221 and the second terminal 222.

[0025] As shown in Figure 3, the second pad 221 is a portion whose length in the third direction y is longer than that of the second terminal 222, and whose entirety is covered with the sealing resin 5. As shown in Figures 2 and 3, the first wire 41 is connected to the second pad 221.

[0026] As shown in Figures 1 to 3, the second terminal 222 extends along the second direction x, and a portion of it is exposed from the sealing resin 5. The second terminal 222 is electrically connected to the first electrode pad 113 via the second pad 221 and the first wire 41. In this embodiment, as described above, the first electrode pad 113 is a gate electrode, so the second terminal 222 is the gate terminal of the semiconductor device A1.

[0027] As shown in Figures 1 to 3, the third lead 23 is positioned spaced apart from the first lead 21 and the second lead 22, and extends along the second direction x. In the third direction y, the third lead 23 is located on the opposite side of the second lead 22 from the first terminal 212. The third lead 23 includes a third pad 231 and a third terminal 232.

[0028] As shown in Figure 3, the third pad 231 is a portion whose length in the third direction y is longer than that of the third pad 231, and whose entirety is covered with the sealing resin 5. As shown in Figures 2 and 3, the second wire 42 is connected to the third pad 231.

[0029] As shown in Figures 1 to 3, the third terminal 232 extends along the second direction x, and a portion of it is exposed from the sealing resin 5. The third terminal 232 is electrically connected to the second electrode pad 114 via the third pad 231 and the second wire 42. In this embodiment, as described above, the second electrode pad 114 is the emitter electrode, so the third terminal 232 is the emitter terminal of the semiconductor device A10.

[0030] Furthermore, the portions of the first terminal 212, second terminal 222, and third terminal 232 that are exposed from the sealing resin 5 may be covered with plating. Covering these with plating can improve corrosion resistance.

[0031] As shown in Figures 2 and 4, the bonding material 3 is a conductive material interposed between the semiconductor element 1 and the first pad 211 of the first lead 21. The bonding material 3 includes a thick portion 31 and a thin portion 32. The thick portion 31 fills the first recess 215. The thin portion 32 is interposed between the back surface 112 of the semiconductor element and the first flat portion 216. The thickness of the thick portion 31 is approximately 15 μm to 750 μm, and the thickness of the thin portion 32 is approximately 10 μm to 120 μm. The thickness of the thick portion 31 is the sum of the thickness of the thin portion 32 and the depth of the first recess 215. The bonding material 3 mounts the semiconductor element 1 onto the first pad 211 and ensures electrical conductivity between the third electrode pad 115 of the semiconductor element 1 and the first lead 21. The material of the bonding material 3 can be any conductive material such as solder or silver paste.

[0032] The first wire 41 and the second wire 42 are made of the same metal and are conductive components. In this embodiment, the first wire 41 and the second wire 42 are made of Al (aluminum) or an Al alloy.

[0033] As shown in Figures 2 and 3, one end of the first wire 41 is bonded to the second pad 221, and the other end is bonded to the first electrode pad 113 on the main surface 111 of the semiconductor element. Therefore, the first wire 41 provides electrical conductivity between the second pad 221 and the first electrode pad 113.

[0034] As shown in Figures 2 and 3, one end of the second wire 42 is bonded to the third pad 231, and the other end is bonded to the second electrode pad 114 on the main surface 111 of the semiconductor element. Therefore, the second wire 42 provides electrical conductivity between the third pad 231 and the second electrode pad 114.

[0035] The sealing resin 5 is a component that covers a part of the lead frame 2, the semiconductor element 1, the first wire 41, and the second wire 42. The sealing resin 5 is a thermosetting synthetic resin having electrical insulating properties. In this embodiment, it is a black epoxy resin. The sealing resin 5 has a resin main surface 51, a resin back surface 52, a pair of resin first side surfaces 53, and a pair of resin second side surfaces 54.

[0036] The main resin surface 51 is the upper surface of the sealing resin 5 shown in Figures 4 and 5. The back surface of the resin 52 is the lower surface of the sealing resin 5 shown in Figures 4 and 5. The main resin surface 51 and the back surface of the resin 52 are oriented opposite to each other with respect to the first direction z.

[0037] The pair of first resin sides 53 are surfaces formed spaced apart in the second direction x, as shown in Figure 5. The pair of first resin sides 53 face opposite each other in the second direction x. The upper end of the first resin side 53 shown in Figure 5 is connected to the main resin surface 51, and the lower end of the first resin side 53 shown in Figure 5 is connected to the back surface 52. In this embodiment, a portion of the first lead 21 (first terminal 212) and the second lead 22 (second terminal 222) are exposed from one of the first resin sides 53.

[0038] The pair of second resin surfaces 54 are formed spaced apart in the third direction y, as shown in Figure 4. The pair of second resin surfaces 54 face opposite each other in the third direction y. The upper end of the second resin surface 54 shown in Figure 4 is connected to the main resin surface 51, and the lower end of the second resin surface 54 shown in Figure 4 is connected to the back surface 52.

[0039] The sealing resin 5 has a pair of recesses 55 formed in it, which are recessed into the interior of the sealing resin 5 from the upper part of each of the pair of second resin sides 54 shown in Figure 1. Also, as shown in Figures 1 and 5, in the first direction z, the sealing resin 5 has a resin through-hole 56 that extends from the resin main surface 51 to the resin back surface 52. In this embodiment, the center of the resin through-hole 56 is the same as the center of the pad through-hole 211c. Also, the diameter of the resin through-hole 56 is smaller than the diameter of the pad through-hole 211c. In this embodiment, the entire wall of the pad through-hole 211c is covered by the sealing resin 5.

[0040] Next, we will explain the operation of semiconductor device A10.

[0041] Unlike this embodiment, there was concern that cracks would occur in the bonding material 3 when a semiconductor device without the first recess 215 was subjected to temperature cycling. Therefore, an analysis was performed on a configuration in which the thickness of the bonding material 3 was increased by providing the first recess 215 in the lead frame 2, as in semiconductor device A1 of this embodiment, and then subjected to temperature cycling. As a result, it was found that there was an effect of reducing the stress generated in the bonding material 3 compared to the case without the first recess 215. Therefore, it became clear that the occurrence of solder cracks can be suppressed by providing the first recess 215, and the reliability against temperature cycling can be improved. It was also found that the effect is greater when the volume of the bonding material 3 is larger. Specifically, the greater the depth of the first recess 215 and the area of ​​the bottom surface 215a of the first recess, the greater the stress reduction effect can be expected. The angle α formed by the bottom surface 215a of the first recess and the circumferential surface 215b of the first recess is less than 45 degrees, which was found to be advantageous for stress reduction.

[0042] Figures 6 to 12 show modified examples and other embodiments of the present disclosure. In these figures, elements identical or similar to those in the above embodiments are denoted by the same reference numerals. Furthermore, the configurations of the parts in each modified example and each embodiment can be combined with each other as appropriate, to the extent that no technical inconsistencies arise.

[0043] <First Embodiment, First Modification> Figure 6 shows a first modified example of semiconductor device A10. In this modified example, semiconductor device A11, the shape of the first recess 215 differs from that of semiconductor device A10.

[0044] In this modified example, the angle between the bottom surface 215a of the first recess and the circumferential surface 215b of the first recess is approximately 90 degrees.

[0045] In this modified form as well, the volume of the joining material 3 increases, thus reducing the stress generated in the joining material 3. As can be seen from this modified form, the angle between the bottom surface 215a of the first recess and the circumferential surface 215b of the first recess is arbitrary.

[0046] <First Embodiment, Second Modification> Figures 7 and 8 show a second modified example of semiconductor device A10. In this modified example, semiconductor device A12, the configuration of the first recess 215 differs from that of semiconductor device A10.

[0047] In this modified example, the first recess 215 includes multiple regions 217. Specifically, the multiple regions 217 are separated from each other in a plan view, with a portion of the first flat portion 216 between them. The number of regions 217 is not limited; in the illustrated example, there are four. Correspondingly, the first recess 215 has four first recess bottom surfaces 215a. As can be seen from this modified example, the first recess 215 may be configured to include multiple regions 217 that are separated from each other. In the illustrated example, the shape of the regions 217 is rectangular, but they may be of other shapes. In Figure 7, the four regions 217 are arranged in a 2x2 arrangement, but the arrangement is also arbitrary.

[0048] <First Embodiment, Third Modification> Figures 9 and 10 show a third modified example of semiconductor device A10. In this modified example, semiconductor device A13, the shape of the first recess 215 differs from that of semiconductor device A10.

[0049] In this modified example, the first recess 215 includes region 217 and multiple regions 218. In this modified example, region 217 and multiple regions 218 are connected to each other. In a plan view, region 217 overlaps with and is contained within the back surface 112 of the semiconductor element. The multiple regions 218 are arranged to overlap the four corners of the back surface 112 of the semiconductor element. The multiple regions 218 are connected to the four corners of region 217. In this case, the thickened portion 31 fills regions 217 and 218. That is, in a plan view, a part of region 218 overlaps with the back surface 112 of the semiconductor element, and the other part protrudes from the back surface 112 of the semiconductor element. In Figure 9, in a plan view, region 217 and multiple regions 218 are rectangular, but their shapes are arbitrary.

[0050] Even with this modified configuration, the volume of the bonding material 3 increases, making it possible to reduce the stress on the bonding material 3 beneath the semiconductor element 1. Furthermore, according to the inventors' analysis, significant stress concentration was observed in the portion of the bonding material 3 located directly beneath the four corners of the semiconductor element 1. In this modified configuration, multiple regions 218 exist at the four corners of the semiconductor element 1. Therefore, multiple thickened portions 31 are arranged at the four corners of the semiconductor element 1. This allows for more efficient mitigation of stress concentration in the bonding material 3 at the four corners of the semiconductor element 1. In addition, a first flat portion 216 is provided in the regions other than region 217 and the multiple regions 218. This allows for proper support of the semiconductor element 1.

[0051] <Second Embodiment> Figure 11 shows a semiconductor device according to a second embodiment of the present disclosure. In this embodiment, the semiconductor device A20 has a semiconductor element back surface 112 which includes a second recess 117 and a second flat portion 118. The second flat portion 118 is a flat portion and, in this embodiment, is perpendicular to the first direction z. The second recess 117 is recessed from the second flat portion 118 in the first direction z and is an example of a "recess" in this disclosure. The second recess 117 includes a second recess bottom surface 117a and a second recess circumferential surface 117b. The second recess bottom surface 117a is the innermost surface in the depth direction (first direction z) of the second recess 117. The second recess circumferential surface 117b is located between the second recess bottom surface 117a and the second flat portion 118. The second recess bottom surface 117a is assumed to be rectangular, but it may be triangular, polygonal, circular, or other shapes. The angle between the bottom surface 117a of the second recess and the circumferential surface 117b of the second recess is arbitrary. The depth of the second recess 117 is not particularly limited, but is approximately 1 μm to 230 μm. The thicker the semiconductor element 1, the deeper the second recess 117 can be made. The thick-walled portion 31 is filled into the second recess 117.

[0052] In this embodiment as well, a thickened portion 31 can be formed, so that stress on the joining material 3 can be relieved in the same way as in the first embodiment. Furthermore, as can be understood from this embodiment, the recess in this disclosure may be provided on either the first surface or the second surface of this disclosure.

[0053] <Third Embodiment> Figure 12 shows a semiconductor device according to a third embodiment of the present disclosure. The semiconductor device A30 of this embodiment has a recess 8.

[0054] The recess 8 includes a first region 219 and a second region 119. The main surface of the pad 211a is configured to include a first flat portion 216 and a first region 219. The back surface 112 of the semiconductor element is configured to include a second flat portion 118 and a second region 119. The first region 219 and the second region 119 overlap each other in a plan view. In this embodiment, the thickened portion 31 fills the first region 219 and the second region 119.

[0055] This embodiment also allows for the formation of a thickened portion 31, thus enabling stress relief of the joining material 3, similar to the first embodiment. Furthermore, since the recess 8 includes both a first region 219 and a second region 119, the volume of the thickened portion 31 can be increased, which is preferable for stress relief of the joining material 3.

[0056] The above disclosure includes embodiments relating to the following appendices. [Note 1] A support member having a first surface, A semiconductor device having a second surface, Having a joining material, The first surface and the second surface have at least one of them a recess and a flat portion, The recess is recessed from the flat portion, The bonding material is filled into the recess, The first surface and the second surface are electrically joined by the joining material. Semiconductor equipment. [Note 2] The recess includes a recess bottom surface and a recess circumferential surface located between the recess bottom surface and the flat portion. The semiconductor device described in Appendix 1. [Note 3] The bottom surface of the recess is rectangular in shape when viewed from above. Semiconductor device as described in Appendix 2. [Note 4] The recess includes multiple regions, A semiconductor device as described in any of the appendices 1 to 3. [Note 5] The aforementioned joining material includes a thick-walled portion and a thin-walled portion. The aforementioned thickened portion is filled in the recess. A semiconductor device as described in any of the appendices 1 to 4. [Note 6] The aforementioned joining material is solder. A semiconductor device as described in any of Appendix 1 to 5. [Note 7] The recess on the first surface is contained within the semiconductor element in a plan view. A semiconductor device as described in any of Appendix 1 to 6. [Note 8] The recess on the first surface includes a region that extends beyond the semiconductor element in a plan view. A semiconductor device as described in any of Appendix 1 to 6. [Note 9] The recess includes a first region included in the first surface and a second region included in the second surface. The semiconductor device described in Appendix 1. [Explanation of Symbols]

[0057] A1, A10, A10, A11, A12, A13, A2: Semiconductor equipment 1: Semiconductor element 2: Lead frame 3: Bonding material 4: Wire 5: Sealing resin 8: Recess 11: Semiconductor devices 21: First lead 22: Second lead 23: Third lead 31: Thick wall part 32: Thin-walled section 41: First wire 42: The second wire 51: Resin main surface 52: Resin back 53: Resin, first side 54: Resin second side 55: Recess 56: Resin through hole 111: Main surface of semiconductor device 112: Back surface of semiconductor device 113: First electrode pad 114: Second electrode pad 115: Third electrode pad 117: Second recess 117a: Bottom surface of the second recess 117a: Bottom surface of the second recess 117b: Second recessed circumferential surface 117b: Second recessed circumferential surface 118: 2nd flat part 119:Second area 211: First pad 211a: Pad main surface 211a: Pad main surface 211b: Back of the pad 211c: Pad through hole 212: 1st terminal 213: Intermediate connection section 215: First recess 215a: Bottom surface of the first recess 215a: Bottom surface of the first recess 215b: First recessed circumferential surface 215b: First recessed circumferential surface 216: 1st flat part 217 :Area 218: area 219: 1st area 221: Second pad 222: 2nd terminal 231: Third pad 232: 3rd terminal x :Second direction y: Third direction z: first direction α :Angle

Claims

1. A support member having a first surface, A semiconductor element having a second surface, Having a joining material, The first surface and the second surface have at least one of them a recess and a flat portion, The recess is recessed from the flat portion, The bonding material is filled into the recess, The first surface and the second surface are electrically joined by the joining material. Semiconductor equipment.

2. The recess includes a recess bottom surface and a recess circumferential surface located between the recess bottom surface and the flat portion. The semiconductor device according to claim 1.

3. The bottom surface of the recess is rectangular in shape when viewed from above. The semiconductor device according to claim 2.

4. The recess includes multiple regions, The semiconductor device according to claim 1.

5. The aforementioned joining material includes a thick-walled portion and a thin-walled portion. The aforementioned thickened portion is filled in the recess. A semiconductor device according to any one of claims 1 to 4.

6. The aforementioned joining material is solder. The semiconductor device according to claim 1.

7. The recess on the first surface is contained within the semiconductor element in a plan view. The semiconductor device according to claim 1.

8. The recess on the first surface includes a region that extends beyond the semiconductor element in a plan view. The semiconductor device according to claim 1.

9. The recess includes a first region included in the first surface and a second region included in the second surface. The semiconductor device according to claim 1.

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