Semiconductor device and method for manufacturing a semiconductor device

Abstract

In a semiconductor device equipped with gate electrodes divided vertically within a trench, the objective is to increase the Cgc / Cge ratio and reduce Qg while preventing a decrease in breakdown withstand capability. [Solution] The semiconductor device includes a trench (7) that penetrates the source layer (5) and the base layer (3) to reach the drift layer (2), a first gate electrode (9) positioned in the lower part of the trench (7) with a first gate insulating film (8) formed on its side and bottom surfaces, and a second gate electrode (12) positioned in the upper part of the trench (7) with a second gate insulating film (11) formed on its side surfaces. The thickness (t1) of the portion of the second gate insulating film (11) in contact with the source layer (5) is greater than the thickness (t2) of the portion of the second gate insulating film (11) in contact with the base layer (3), and the portion of the second gate insulating film (11) in contact with the source layer (5) protrudes inward into the trench (7) but not outward.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device having a gate electrode embedded in a trench.

Background Art

[0002] For example, Patent Document 1 discloses a semiconductor device having a gate electrode divided vertically in a trench provided in a semiconductor substrate, and having a structure in which a gate insulating film around the upper gate electrode is thickened near the upper end of the upper gate electrode.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the semiconductor device of Patent Document 1, the gate insulating film around the upper gate electrode is thickened so as to spread toward both the inside (gate electrode side) and the outside (source layer side) of the trench near the upper end of the upper gate electrode. When the gate insulating film is thick near the upper end of the upper gate electrode, the ratio Cgc / Cge of the gate-collector capacitance (Cgc) to the gate-emitter capacitance (Cge) can be increased, and the turn-on loss (Eon) can be reduced. Further, since the area of the upper gate electrode in a cross-sectional view becomes small, an effect of reducing the gate charge amount (Qg), which is the amount of charge required for charging and discharging the gate, can be obtained.

[0005] However, since the gate electrode spreads not only to the inside (gate electrode side) but also to the outside (source layer side) of the trench near the upper end of the upper gate electrode, there is a concern that the hole discharge efficiency at the turn-off of the semiconductor device deteriorates and the breakdown withstand voltage at the turn-off decreases.

[0006] This disclosure is made to solve the above-mentioned problems, and aims to increase the Cgc / Cge ratio and reduce Qg in a semiconductor device having a gate electrode divided vertically within a trench, while preventing a decrease in fracture withstand capability. [Means for solving the problem]

[0007] The semiconductor device according to this disclosure comprises a semiconductor substrate, a drift layer of a first conductivity type formed on the semiconductor substrate, a base layer of a second conductivity type formed on the surface of the semiconductor substrate, a source layer of the first conductivity type selectively formed on the surface of the base layer, a trench formed in the semiconductor substrate so as to penetrate the source layer and the base layer and reach the drift layer, an intermediate insulating film dividing the trench into upper and lower sections, a first gate electrode disposed in the trench below the intermediate insulating film and having a first gate insulating film formed on its side surface and bottom surface, a second gate electrode disposed in the trench above the intermediate insulating film and having a second gate insulating film formed on its side surface, and an emitter electrode formed on the semiconductor substrate and connected to the source layer, wherein the thickness of the portion of the second gate insulating film in contact with the source layer is greater than the thickness of the portion of the second gate insulating film in contact with the base layer, and the portion of the second gate insulating film in contact with the source layer protrudes inward into the trench but not outward from the trench. [Effects of the Invention]

[0008] According to this disclosure, in a semiconductor device having a gate electrode divided vertically within a trench, it is possible to increase the Cgc / Cge ratio and reduce Qg while preventing a decrease in breakdown withstand capability. [Brief explanation of the drawing]

[0009] [Figure 1] This is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 1. [Figure 2] This is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 2. [Figure 3]This is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 3. [Figure 4] This is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 4. [Figure 5] This is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 5. [Figure 6] This is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 6. [Figure 7] This is an explanatory diagram of the method for manufacturing a semiconductor device according to Embodiment 7. [Figure 8] This is an explanatory diagram of the method for manufacturing a semiconductor device according to Embodiment 7. [Figure 9] This is an explanatory diagram of the method for manufacturing a semiconductor device according to Embodiment 7. [Figure 10] This is an explanatory diagram of the method for manufacturing a semiconductor device according to Embodiment 7. [Figure 11] This is an explanatory diagram of the method for manufacturing a semiconductor device according to Embodiment 7. [Figure 12] This is an explanatory diagram of the method for manufacturing a semiconductor device according to Embodiment 7. [Figure 13] This is an explanatory diagram of the method for manufacturing a semiconductor device according to Embodiment 7. [Figure 14] This is an explanatory diagram of the method for manufacturing a semiconductor device according to Embodiment 7. [Figure 15] This is an explanatory diagram of the method for manufacturing a semiconductor device according to Embodiment 7. [Figure 16] This is an explanatory diagram of the method for manufacturing a semiconductor device according to Embodiment 7. [Figure 17] This is an explanatory diagram of the method for manufacturing a semiconductor device according to Embodiment 7. [Figure 18] This is an explanatory diagram of the method for manufacturing a semiconductor device according to Embodiment 7. [Figure 19] This is an explanatory diagram of the method for manufacturing a semiconductor device according to Embodiment 7. [Figure 20] This is an explanatory diagram of the method for manufacturing a semiconductor device according to Embodiment 7. [Figure 21] This is an explanatory diagram of the method for manufacturing a semiconductor device according to Embodiment 7. [Figure 22] It is an explanatory diagram of a method for manufacturing a semiconductor device according to Embodiment 7.

Embodiments for Carrying Out the Invention

[0010] Embodiments of the technology according to the present disclosure will be described. In the following description, N-type and P-type indicate the conductivity type of a semiconductor. In each embodiment, the first conductivity type is described as N-type and the second conductivity type as P-type, but conversely, the first conductivity type may be P-type and the second conductivity type may be N-type. Also, the height of the impurity concentration in each region is defined by the peak concentration. That is, a region with a high (or low) impurity concentration means a region with a high (or low) peak concentration of impurities.

[0011] Also, in the drawings shown below, the same or corresponding elements are denoted by the same reference numerals. Therefore, the description of elements denoted by the same reference numerals as those described above will be omitted as appropriate.

[0012] <Embodiment 1> FIG. 1 is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 1. Here, the semiconductor element included in the semiconductor device will be described as an IGBT (Insulated Gate Bipolar Transistor). However, the semiconductor element may be any trench-type insulated gate semiconductor element, for example, something other than an IGBT such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

[0013] As shown in Figure 1, the semiconductor device according to Embodiment 1 is formed using a semiconductor substrate 1 on which an N-type drift layer 2 is formed. A P-type base layer 3 is formed on the upper surface of the semiconductor substrate 1. Between the drift layer 2 and the base layer 3, an N-type carrier storage layer 4 with a higher impurity concentration than the drift layer 2 is formed. However, the carrier storage layer 4 may be omitted (i.e., the portion of the carrier storage layer 4 in Figure 1 may also be the drift layer 2). By providing the carrier storage layer 4, the current loss of the IGBT can be reduced.

[0014] A source layer 5 of type N and a contact layer 6 of type P with a higher impurity concentration than the base layer 3 are selectively formed on the surface of the base layer 3. The contact layer 6 may be omitted (i.e., the base layer 3 may extend up to the portion of the contact layer 6 shown in Figure 1). By providing the contact layer 6, the connection resistance between the emitter electrode 14 and the base layer 3, which will be described later, can be reduced.

[0015] A trench 7 is formed on the upper surface of the semiconductor substrate 1, penetrating the source layer 5, the base layer 3, and the carrier storage layer 4, and reaching the drift layer 2 below the carrier storage layer 4. The trench 7 is divided vertically by an intermediate insulating film 10. Below the intermediate insulating film 10 is a first gate electrode 9 with a first gate insulating film 8 formed on its sides and bottom, and above the intermediate insulating film 10 is a second gate electrode 12 with a second gate insulating film 11 formed on its sides.

[0016] An interlayer insulating film 13 is formed on the semiconductor substrate 1 so as to cover the second gate electrode 12, and an emitter electrode 14 is formed on the interlayer insulating film 13. Contact holes are formed in the interlayer insulating film 13 that reach the source layer 5 and the contact layer 6, and the emitter electrode 14 is connected to the source layer 5 and the contact layer 6 through these contact holes.

[0017] In the semiconductor device according to Embodiment 1, the thickness t1 of the portion of the second gate insulating film 11 provided on the side surface of the second gate electrode 12 that is in contact with the source layer 5 is greater than the thickness t2 of the portion that is in contact with the base layer 3. However, the thickness of the portion of the second gate insulating film 11 that is in contact with the source layer 5 extends only to the inside of the trench 7 (the second gate electrode 12 side) and does not extend to the outside of the trench 7 (the source layer 5 side). In other words, as shown in Figure 1, in a cross-sectional view, the portion of the second gate insulating film 11 that is in contact with the source layer 5 protrudes to the inside of the trench 7, but does not protrude to the outside of the trench 7.

[0018] In the semiconductor device according to Embodiment 1, the gate-emitter capacitance (Cge) is reduced because the thickness of the portion of the second gate insulating film 11 that is in contact with the source layer 5 is large. Therefore, the ratio of Cge to gate-collector capacitance (Cgc), which is Cgc / Cge, becomes large, and the turn-on loss (Eon) of the semiconductor device can be reduced.

[0019] Furthermore, in the semiconductor device according to Embodiment 1, the second gate electrode 12 becomes smaller by the amount by which the portion of the second gate insulating film 11 that contacts the source layer 5 protrudes inward from the trench 7 (towards the second gate electrode 12). Since the gate charge amount (Qg), which is the amount of charge required to charge and discharge the gate, is proportional to the volume or cross-sectional area of ​​the second gate electrode 12, Qg becomes smaller, and the effect is obtained that the semiconductor device can be turned on with a smaller amount of charge. Here, since the portion of the second gate insulating film 11 that contacts the source layer 5 does not protrude outward from the trench 7 (towards the source layer 5), the hole discharge efficiency during turn-off of the semiconductor device does not deteriorate, and there is no decrease in the breakdown resistance during turn-off.

[0020] <Embodiment 2> In Figure 1, the thickness t1 of the portion of the second gate insulating film 11 in contact with the source layer 5 is uniform, but the shape of this portion is not limited to this. In other words, the portion of the second gate insulating film 11 in contact with the source layer 5 can have any shape as long as its thickness t1 is greater than the thickness t2 of the portion in contact with the base layer 3 and it does not protrude outside the trench 7.

[0021] Figure 2 is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 2. As shown in Figure 2, in the semiconductor device according to Embodiment 2, the portion of the second gate insulating film 11 that contacts the source layer 5 has a shape that gradually widens upwards. In other words, the thickness of the portion of the second gate insulating film 11 that contacts the source layer 5 increases as it approaches the upper end of the trench 7. However, the portion of the second gate insulating film 11 that contacts the source layer 5 does not extend outside the trench 7.

[0022] The semiconductor device according to Embodiment 2 also provides the same effects as in Embodiment 1.

[0023] <Embodiment 3> Figure 3 is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 3. As shown in Figure 3, in the semiconductor device according to Embodiment 3, a recess 12a is provided on the upper surface of the second gate electrode 12. A portion of the interlayer insulating film 13 is embedded in the recess 12a.

[0024] In the semiconductor device according to Embodiment 3, in addition to the portion of the second gate insulating film 11 that contacts the source layer 5 protruding inward from the trench 7 (towards the second gate electrode 12), the presence of a recess 12a on the upper surface of the second gate electrode 12 further reduces the volume or cross-sectional area of ​​the second gate electrode 12. Therefore, Embodiment 3 provides the effect of further reducing the Qg of the semiconductor device.

[0025] <Embodiment 4> Figure 4 is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 4. As shown in Figure 4, in the semiconductor device according to Embodiment 4, the thick portion of the second gate insulating film 11 extends to a position deeper than the source layer 5. The second gate insulating film 11 is thickened not only in the portion that contacts the source layer 5, but also in the upper part of the portion that contacts the base layer 3 (near the boundary between the base layer 3 and the source layer 5), protruding inward into the trench 7. In other words, the second gate insulating film 11 is thickened in the region extending from the upper part that contacts the base layer 3 to the portion that contacts the source layer 5, protruding inward into the trench 7.

[0026] In the example shown in Figure 4, the thickness of the second gate insulating film 11 increases as it approaches the upper end of the trench 7 in the region extending from the upper part of the second gate insulating film 11 that contacts the base layer 3 to the part that contacts the source layer 5. However, the shape of the second gate insulating film 11 is not limited to this; for example, the thickness of the thicker part of the second gate insulating film 11 may be uniform.

[0027] According to the semiconductor device of Embodiment 4, in addition to the portion of the second gate insulating film 11 that is in contact with the source layer 5, the upper part of the portion of the second gate insulating film 11 that is in contact with the base layer 3 (near the boundary between the base layer 3 and the source layer 5) is also thicker, which allows for a further increase in Cgc / Cge and a further decrease in Qg.

[0028] <Embodiment 5> Figure 5 is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 5. As shown in Figure 5, in the semiconductor device according to Embodiment 5, an opening 12b is formed in the second gate electrode 12, extending from the top surface to the bottom surface of the second gate electrode 12. In Figure 5, the opening 12b reaches the intermediate insulating film 10 at the bottom of the second gate electrode 12, dividing the second gate electrode 12 into two parts. A portion of the interlayer insulating film 13 is embedded within the opening 12b.

[0029] Since the opening 12b of the second gate electrode 12 is formed deeper than the opening 12b shown in Embodiment 3, the volume or cross-sectional area of ​​the second gate electrode 12 can be further reduced. Therefore, the semiconductor device according to Embodiment 5 has the effect of further reducing the Qg of the semiconductor device.

[0030] Furthermore, the opening 12b does not necessarily have to divide the second gate electrode 12. In other words, the second gate electrodes 12 on the left and right sides of the opening 12b in Figure 5 may be connected to each other. For example, the opening 12b may be island-shaped in plan view, and the opening 12b does not have to reach the intermediate insulating film 10.

[0031] <Embodiment 6> Figure 6 is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 6. As shown in Figure 6, the semiconductor device according to Embodiment 6 has a dummy trench 7d added to the configuration of Embodiment 2 (Figure 2). In other words, the semiconductor device according to Embodiment 6 is the same as the semiconductor device of Embodiment 2, but with a portion of the trenches 7 replaced by dummy trenches 7d. For the sake of explanation, in this embodiment, the trenches 7 are referred to as "active trenches 7".

[0032] The dummy trench 7d is not in contact with the source layer 5, but penetrates the contact layer 6, the base layer 3, and the carrier storage layer 4, reaching the drift layer 2 below the carrier storage layer 4. The structure within the dummy trench 7d is similar to that within the active trench 7. Specifically, the dummy trench 7d is divided vertically by a dummy intermediate insulating film 10d. Below the dummy intermediate insulating film 10d, a first dummy gate electrode 9d with a first dummy gate insulating film 8d on its side is formed, and above the dummy intermediate insulating film 10d, a second dummy gate electrode 12d with a second dummy gate insulating film 11d on its side is formed. However, the first dummy gate electrode 9d is supplied with a gate potential similar to the first gate electrode 9, while the second dummy gate electrode 12d is supplied with an emitter potential. That is, the second dummy gate electrode 12d is electrically connected to the emitter electrode 14.

[0033] Furthermore, the second dummy gate insulating film 11d in the dummy trench 7d has the same shape as the second gate insulating film 11 in the active trench 7. In other words, the upper part of the second dummy gate insulating film 11d (the part that contacts the contact layer 6 in Figure 6) is thicker than other parts. However, the thickness of the upper part of the second dummy gate insulating film 11d extends only to the inside of the dummy trench 7d (towards the second dummy gate electrode 12d) and does not extend to the outside of the dummy trench 7d (towards the source layer 5). In other words, in a cross-sectional view, the upper part of the second dummy gate insulating film 11d protrudes into the inside of the dummy trench 7d, but does not protrude to the outside of the dummy trench 7d.

[0034] Narrowing the spacing of the active trenches 7 can improve the breakdown voltage of the semiconductor device, but this increases the density of the second gate electrode 12, raising concerns about an increase in the gate charge amount (Qg). As in this embodiment, the increase in Qg can be suppressed by replacing a portion of the active trenches 7 with dummy trenches 7d.

[0035] Furthermore, the increased thickness of the upper part of the second dummy gate insulating film 11d reduces the capacitance between the second gate electrode 12 in the active trench 7, to which the gate potential is supplied, and the second dummy gate electrode 12d in the dummy trench 7d, to which the emitter potential is supplied. As a result, Cgc becomes smaller, and the Cgc / Cge ratio increases.

[0036] <Embodiment 7> Embodiment 7 describes a method for manufacturing a semiconductor device according to this disclosure. Here, a typical method for manufacturing a semiconductor device according to Embodiment 2 (Figure 2) is shown.

[0037] First, prepare an N-type semiconductor substrate 1 as shown in Figure 7. Here, the semiconductor substrate 1 is assumed to be made of silicon (Si). The semiconductor substrate 1 may also be made of silicon carbide (SiC), which is known as a wide-bandgap semiconductor.

[0038] Next, a base layer 3 and a carrier storage layer 4 are formed on the surface of the semiconductor substrate 1 by selective ion implantation using photolithography technology, as shown in Figure 8. At this time, the N-type region that remains without the formation of the base layer 3 and carrier storage layer 4 becomes the drift layer 2.

[0039] Next, a trench 7 is formed in the semiconductor substrate 1 by selective etching using photogravure technology, as shown in Figure 9. Then, as shown in Figure 10, a first insulating film 21, which is the material for the first gate insulating film 8, is formed on the upper surface of the semiconductor substrate 1, including the inner surface of the trench 7. The first insulating film 21 is, for example, a silicon oxide film. Furthermore, as shown in Figure 11, a first conductive film 22, which is the material for the first gate electrode 9, is formed on the first insulating film 21, thereby embedding the first conductive film 22 in the trench 7. The first conductive film 22 is, for example, polysilicon.

[0040] Then, etching of the first conductive film 22 removes the first conductive film 22 from the upper surface of the semiconductor substrate 1 and the upper part of the trench 7, as shown in Figure 12. At this time, the first conductive film 22 remaining in the lower part of the trench 7 becomes the first gate electrode 9. Also, etching of the first insulating film 21 removes the first insulating film 21 from the upper surface of the semiconductor substrate 1 and the upper part of the trench 7, as shown in Figure 13. At this time, the first insulating film 21 remaining in the lower part of the trench 7 becomes the first gate insulating film 8.

[0041] Next, as shown in Figure 14, a second insulating film 23, which is the material for the second gate insulating film 11, is formed on the upper surface of the semiconductor substrate 1, including the inner surface of the trench 7. The second insulating film 23 is, for example, a silicon oxide film. At this time, the portion of the second insulating film 23 formed to cover the upper surface of the first gate electrode 9 becomes the intermediate insulating film 10. Furthermore, as shown in Figure 15, the second conductive film 24, which is the material for the second gate electrode 12, is formed on the second insulating film 23, thereby embedding the second conductive film 24 in the trench 7. The second conductive film 24 is, for example, polysilicon.

[0042] Then, by etching the second conductive film 24, the second conductive film 24 on the upper surface of the semiconductor substrate 1 is removed, as shown in Figure 16. At this time, the second conductive film 24 remaining in the trench 7 becomes the second gate electrode 12. Also, by etching the second insulating film 23, the second insulating film 23 on the upper surface of the semiconductor substrate 1 is removed, as shown in Figure 17. At this time, the second insulating film 23 remaining in the trench 7 becomes the second gate insulating film 11.

[0043] Next, by selective etching using photogravure technology, source layers 5 and 5 are formed on the surface of the base layer 3, as shown in Figure 18.

[0044] Subsequently, an interlayer insulating film 13 made of silicon oxide is formed on the semiconductor substrate 1 by CVD (Chemical Vapor Deposition), as shown in Figure 19. Then, the interlayer insulating film 13 is annealed in an oxygen atmosphere. As a result, oxygen diffuses into the oxide film constituting the interlayer insulating film 13, and oxidation of the second gate electrode 12 and the semiconductor substrate 1 progresses near the top of the second gate insulating film 11, increasing the thickness of the second gate insulating film 11. However, the oxidation rate of the silicon semiconductor substrate 1 is extremely slow compared to the oxidation rate of the polysilicon second gate electrode 12, so the oxidation of the semiconductor substrate 1 is negligible. Therefore, as shown in Figure 20, the second gate insulating film 11 spreads only inside the trench 7 (on the second gate electrode 12 side) and does not spread outside the trench 7 (on the contact layer 6 side).

[0045] As a result, in cross-sectional view, the portion of the second gate insulating film 11 in contact with the source layer 5 protrudes inward into the trench 7 but does not protrude outward from the trench 7. Furthermore, the thickness t1 of the portion of the second gate insulating film 11 in contact with the source layer 5 is greater than the thickness t2 of the portion of the second gate insulating film 11 in contact with the base layer 3. Also, since the oxidation of the second gate electrode 12 proceeds from the upper side in contact with the interlayer insulating film 13, the thickness of the portion of the second gate insulating film 11 in contact with the source layer 5 increases as it approaches the upper end of the trench 7. Therefore, the shape of the second gate insulating film 11 is as shown in Embodiment 2 (Figure 2).

[0046] Subsequently, selective etching of the interlayer insulating film 13 using photolithography technology is performed to form contact holes in the interlayer insulating film 13 that reach the source layer 5 and the contact layer 6, as shown in Figure 21. Then, as shown in Figure 22, an emitter electrode 14 made of, for example, a metal material is formed on the interlayer insulating film 13. At this time, the emitter electrode 14 is connected to the source layer 5 and the contact layer 6 through the contact holes.

[0047] As a result, the semiconductor device according to Embodiment 2 (Figure 2) is formed.

[0048] As in Embodiment 3 (Figure 3), if a recess 12a is provided on the upper surface of the second gate electrode 12, the thickness of the deposited second conductive film 24 can be reduced in the process of forming the second conductive film 24, which is the material of the second gate electrode 12 (Figure 15).

[0049] As in Embodiment 4 (Figure 4), when extending the thick portion of the second gate insulating film 11 to a position deeper than the contact layer 6, the annealing time or annealing temperature can be increased in the annealing process in an oxygen atmosphere (Figure 20).

[0050] As in Embodiment 5 (Figure 5), when an opening 12b is provided on the upper surface of the second gate electrode 12, it is necessary to add a step to form the opening 12b in the second gate electrode 12 by selective etching after the formation step of the second gate electrode 12 (Figure 18).

[0051] Furthermore, it is possible to freely combine each embodiment, or to modify or omit each embodiment as appropriate.

[0052] <Note> The various aspects of this disclosure are summarized below as an appendix.

[0053] (Note 1) Semiconductor substrate and A first conductivity type drift layer formed on the semiconductor substrate, A second conductivity type base layer formed on the surface of the semiconductor substrate, The first conductive source layer is selectively formed on the surface of the base layer, A trench is formed in the semiconductor substrate so as to penetrate the source layer and the base layer and reach the drift layer, The trench is divided into upper and lower sections by an intermediate insulating film, A first gate electrode is disposed in the trench beneath the intermediate insulating film, and a first gate insulating film is formed on its side and bottom surfaces, A second gate electrode is disposed in the trench on the intermediate insulating film and has a second gate insulating film formed on its side surface, An emitter electrode formed on the semiconductor substrate and connected to the source layer, Equipped with, The thickness of the portion of the second gate insulating film that is in contact with the source layer is greater than the thickness of the portion of the second gate insulating film that is in contact with the base layer. The portion of the second gate insulating film that contacts the source layer protrudes inward from the trench and does not protrude outward from the trench. Semiconductor equipment.

[0054] (Note 2) The thickness of the portion of the second gate insulating film that is in contact with the source layer increases as it approaches the upper end of the trench. The semiconductor device described in Appendix 1.

[0055] (Note 3) The second gate insulating film protrudes inward from the trench in a region extending from the upper part of the portion in contact with the base layer to the portion in contact with the source layer. A semiconductor device as described in Appendix 1 or Appendix 2.

[0056] (Note 4) The second gate electrode has a recess on its upper surface, A semiconductor device described in any one of the appendices 1 through 3.

[0057] (Note 5) The second gate electrode has an opening that extends from the top surface to the bottom surface of the second gate electrode. A semiconductor device described in any one of the appendices 1 through 3.

[0058] (Note 6) The opening reaches the bottom of the second gate electrode. Semiconductor device as described in Appendix 5.

[0059] (Note 7) A dummy trench is formed in the semiconductor substrate so as not to be in contact with the source layer, but to penetrate the base layer and reach the drift layer, A dummy intermediate insulating film divides the dummy trench into upper and lower sections, A first dummy gate electrode is disposed in the dummy trench beneath the dummy intermediate insulating film, and has a first dummy gate insulating film formed on its side and bottom surfaces, A second dummy gate electrode is disposed within the dummy trench on the dummy intermediate insulating film, and a second dummy gate insulating film is formed on its side surface, Furthermore, The second dummy gate electrode is electrically connected to the emitter electrode, The thickness of the portion of the second dummy gate insulating film that is in contact with the source layer is greater than the thickness of the portion of the second dummy gate insulating film that is in contact with the base layer. The portion of the second dummy gate insulating film that contacts the source layer protrudes inward from the dummy trench and does not protrude outward from the dummy trench. A semiconductor device as described in any one of the appendices 1 through 6.

[0060] (Note 8) A process for preparing a semiconductor substrate of the first conductivity type, The process of forming a second conductivity type base layer on the surface layer of the semiconductor substrate, The steps include forming a trench in the semiconductor substrate that reaches below the base layer, A step of forming a first insulating film on the upper surface of the semiconductor substrate including the inner surface of the trench, The process involves forming a first conductive film on the first insulating film, thereby embedding the first conductive film in the trench, The steps include removing the first insulating film and the first conductive film from the upper surface of the semiconductor substrate and the upper part of the trench to form a first gate insulating film made of the first insulating film and a first gate electrode made of the first conductive film in the lower part of the trench, The process involves forming the first gate insulating film and the first gate electrode, followed by forming a second insulating film on the upper surface of the semiconductor substrate including the inner surface of the trench, The process involves forming a second conductive film on the second insulating film, thereby embedding the second conductive film in the trench, The steps include removing the second insulating film and the second conductive film from the upper surface of the semiconductor substrate to form a second gate insulating film made of the second insulating film and a second gate electrode made of the second conductive film in the upper part of the trench, The process involves forming the first conductive source layer on the surface of the base layer, A step of forming an interlayer insulating film made of an oxide film so as to cover the second gate insulating film and the second gate electrode, The interlayer insulating film is subjected to a step of annealing in an oxygen atmosphere, A method for manufacturing a semiconductor device comprising the same equipment. [Explanation of Symbols]

[0061] 1 Semiconductor substrate, 2 Drift layer, 3 Base layer, 4 Carrier storage layer, 5 Source layer, 6 Contact layer, 7 Trench, 8 First gate insulating film, 9 First gate electrode, 10 Intermediate insulating film, 11 Second gate insulating film, 12 Second gate electrode, 12a Recess, 12b Aperture, 13 Interlayer insulating film, 14 Emitter electrode, 7d Dummy trench, 8d First dummy gate insulating film, 9d First dummy gate electrode, 10d Dummy intermediate insulating film, 11d Second dummy gate insulating film, 12d Second dummy gate electrode, 21 First insulating film, 22 First conductive film, 23 Second insulating film, 24 Second conductive film.

Claims

1. Semiconductor substrate and A first conductivity type drift layer formed on the semiconductor substrate, A second conductivity type base layer formed on the surface of the semiconductor substrate, A first conductive source layer selectively formed on the surface of the base layer, A trench is formed in the semiconductor substrate so as to penetrate the source layer and the base layer and reach the drift layer, The trench is divided into upper and lower sections by an intermediate insulating film, A first gate electrode is disposed in the trench beneath the intermediate insulating film, and a first gate insulating film is formed on its side and bottom surfaces, A second gate electrode is disposed in the trench on the intermediate insulating film and has a second gate insulating film formed on its side surface, An emitter electrode formed on the semiconductor substrate and connected to the source layer, Equipped with, The thickness of the portion of the second gate insulating film that is in contact with the source layer is greater than the thickness of the portion of the second gate insulating film that is in contact with the base layer. The portion of the second gate insulating film that contacts the source layer protrudes inward from the trench and does not protrude outward from the trench. Semiconductor equipment.

2. The thickness of the portion of the second gate insulating film that is in contact with the source layer increases as it approaches the upper end of the trench. The semiconductor device according to claim 1.

3. The second gate insulating film protrudes inward from the trench in a region extending from the upper part of the portion in contact with the base layer to the portion in contact with the source layer. The semiconductor device according to claim 1 or claim 2.

4. The second international airport has a recess on its upper surface, The semiconductor device according to claim 1 or claim 2.

5. The second gate electrode has an opening that extends from the top surface to the bottom surface of the second gate electrode. The semiconductor device according to claim 1 or claim 2.

6. The opening reaches the bottom of the second gate electrode. The semiconductor device according to claim 5.

7. A dummy trench is formed in the semiconductor substrate so as not to be in contact with the source layer, but to penetrate the base layer and reach the drift layer, A dummy intermediate insulating film divides the dummy trench into upper and lower sections, A first dummy gate electrode is disposed in the dummy trench beneath the dummy intermediate insulating film, and has a first dummy gate insulating film formed on its side and bottom surfaces, A second dummy gate electrode is disposed in the dummy trench above the dummy intermediate insulating film, and a second dummy gate insulating film is formed on its side surface, Furthermore, The second dummy gate electrode is electrically connected to the emitter electrode, The thickness of the portion of the second dummy gate insulating film that is in contact with the source layer is greater than the thickness of the portion of the second dummy gate insulating film that is in contact with the base layer. The portion of the second dummy gate insulating film that is in contact with the source layer protrudes inward from the dummy trench and does not protrude outward from the dummy trench. The semiconductor device according to claim 1 or claim 2.

8. A process for preparing a semiconductor substrate of the first conductivity type, The process of forming a second conductivity type base layer on the surface layer of the semiconductor substrate, The steps include forming a trench in the semiconductor substrate that reaches below the base layer, A step of forming a first insulating film on the upper surface of the semiconductor substrate including the inner surface of the trench, The process involves forming a first conductive film on the first insulating film, thereby embedding the first conductive film in the trench, The steps include removing the first insulating film and the first conductive film from the upper surface of the semiconductor substrate and the upper part of the trench to form a first gate insulating film made of the first insulating film and a first gate electrode made of the first conductive film in the lower part of the trench, The process involves forming the first gate insulating film and the first gate electrode, followed by forming a second insulating film on the upper surface of the semiconductor substrate including the inner surface of the trench, The process involves forming a second conductive film on the second insulating film, thereby embedding the second conductive film in the trench, The steps include removing the second insulating film and the second conductive film from the upper surface of the semiconductor substrate to form a second gate insulating film made of the second insulating film and a second gate electrode made of the second conductive film in the upper part of the trench, The process involves forming the first conductive source layer on the surface of the base layer, A step of forming an interlayer insulating film made of an oxide film so as to cover the second gate insulating film and the second gate electrode, The interlayer insulating film is subjected to a step of annealing in an oxygen atmosphere, A method for manufacturing a semiconductor device comprising the same equipment.

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