Switching element

Abstract

It suppresses leakage current in switching elements. [Solution] A switching element having at least one of a first lower p layer that contacts the gate insulating film from below and the drift layer from above, and a second lower p layer that contacts the body layer from below and the drift layer from above. The lower p layer has a high-concentration layer having a p-type impurity concentration of more than half of the maximum value of the p-type impurity concentration in the lower p layer, and a low-concentration layer having a p-type impurity concentration of less than half of the maximum value. The low-concentration layer has a lower low-concentration layer disposed between the high-concentration layer and the drift layer in the thickness direction of the semiconductor substrate. The thickness x0 of the portion of the lower low-concentration layer having a p-type impurity concentration higher than the average value A of the p-type impurity concentration of the low-concentration layer is greater than the smaller of the thicknesses x1 and x2 obtained by a predetermined formula.

Description

[Technical Field]

[0001] The technology disclosed herein relates to switching elements.

[0002] As described in Patent Document 1, when cosmic rays enter the inside of a switching element, electron-hole pairs are generated inside the semiconductor substrate, reducing the breakdown voltage of the switching element. The technology in Patent Document 1 suppresses the breakdown voltage reduction caused by cosmic rays by adjusting the n-type impurity concentration distribution in the drift layer. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2003-338624 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] In switching elements having a semiconductor substrate made of silicon carbide, a technique is known in which a p-layer (hereinafter referred to as the lower p-layer) is provided within the drift layer. By providing the lower p-layer, the electric field applied to the gate insulating film can be relaxed. When the lower p-layer is provided, a depletion layer extends from the boundary between the drift layer and the lower p-layer into the lower p-layer when the switching element is off. Since there are many crystal defects in the lower p-layer, if the depletion layer extends widely into the lower p-layer, the leakage current of the switching element increases. This specification proposes a technique for suppressing leakage current in a switching element having a lower p-layer. [Means for solving the problem]

[0005] The switching element disclosed herein comprises a semiconductor substrate made of silicon carbide and a gate electrode facing the semiconductor substrate via a gate insulating film. The semiconductor substrate comprises an n-type source layer in contact with the gate insulating film, a p-type body layer in contact with the gate insulating film and the source layer, an n-type drift layer in contact with the gate insulating film and the body layer and separated from the source layer by the body layer, and at least one of a first lower p-layer in contact with the gate insulating film from below and with the drift layer from above, and a second lower p-layer in contact with the body layer from below and with the drift layer from above. The first and second lower p-layers comprise a high-concentration layer having a p-type impurity concentration of half or more of the maximum value of the p-type impurity concentration in the first and second lower p-layers, and a low-concentration layer having a p-type impurity concentration of less than half of the maximum value. The low-concentration layer comprises a lower low-concentration layer disposed between the high-concentration layer and the drift layer in the thickness direction of the semiconductor substrate. The thickness x0 of the portion of the lower low-concentration layer having a p-type impurity concentration higher than the average value A of the p-type impurity concentration in the low-concentration layer is greater than the smaller of the thicknesses x1 and x2 obtained by the following formulas (1) and (2).

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[0006] In addition, in the above formula 2, the maximum rated voltage V BV This value represents the direction in which the drain side has a higher potential, with the positive side being represented as positive.

[0007] The above thickness x1 is the width of the depletion layer extending into the low-concentration layer when the drift layer below the lower p layer is depleted throughout the thickness direction. Also, the above thickness x2 is the width of the depletion layer extending into the low-concentration layer when the maximum rated voltage V BV is applied. When the switching element is a punch-through type, since the drift layer is depleted when the drain-source voltage is lower than the maximum rated voltage V BV , the thickness x1 becomes smaller than the thickness x2. When the switching element is a non-punch-through type, the thickness x2 becomes smaller than the thickness x1. Therefore, the smaller value of the thicknesses x1 and x2 indicates the maximum width of the depletion layer extending into the low-concentration layer in the operating environment of the switching element. In this switching element, the thickness x0 of the portion having a p-type impurity concentration higher than the average value A of the p-type impurity concentration of the low-concentration layer in the lower low-concentration layer is larger than the maximum width of the depletion layer extending into the low-concentration layer. For this reason, the depletion layer does not reach the high-concentration layer. Since the depletion layer does not reach the high-concentration layer where crystal defects exist at a high density, leakage current is unlikely to occur in this switching element.

Brief Description of the Drawings

[0008] [Figure 1] Cross-sectional view of the switching element of Example 1. [Figure 2] Graph showing the impurity concentration distribution of the lower p layer of Example 1. [Figure 3] Cross-sectional view of the switching element of the first modification of Example 1. [Figure 4] Graph showing the impurity concentration distribution of the lower p layer of the first modification of Example 1. [Figure 5] Cross-sectional view of the switching element of the second modification of Example 1. [Figure 6] Cross-sectional view of the switching element of the third modification of Example 1. [Figure 7] Cross-sectional view of the switching element of Example 2. [Figure 8] Cross-sectional view of the switching element of the first modification of Example 2. [Figure 9]Cross-sectional view of the switching element according to the second modification of Example 2.

Mode for Carrying Out the Invention

[0009] In a switching element of an example disclosed in this specification, a trench may be provided on the upper surface of the semiconductor substrate. The gate insulating film and the gate electrode may be disposed in the trench. The first lower p-layer that contacts the gate insulating film at the bottom surface of the trench may be provided.

[0010] In a switching element of an example disclosed in this specification, the second lower p-layer that contacts the body layer from below may be provided.

Examples

[0011] The switching element 10 of Example 1 shown in FIG. 1 is a trench gate type MOSFET (metal - oxide - semiconductor field effect transistor). The switching element 10 is designed to be used in the stratosphere or at a higher altitude (for example, outer space) and has a structure capable of suppressing the influence of cosmic rays. The switching element 10 includes a semiconductor substrate 12, a gate electrode 22, a gate insulating film 20, a source electrode 26, and a drain electrode 28.

[0012] The semiconductor substrate 12 is made of silicon carbide (that is, SiC). Hereinafter, the position direction parallel to the upper surface 12a of the semiconductor substrate 12 is referred to as the x direction, the direction parallel to the upper surface 12a and orthogonal to the x direction is referred to as the y direction, and the thickness direction of the semiconductor substrate 12 is referred to as the z direction. A plurality of trenches 14 are provided on the upper surface 12a of the semiconductor substrate 12. Each trench 14 extends linearly in the y direction on the upper surface 12a. The plurality of trenches 14 are arranged at intervals in the x direction.

[0013] The gate insulating film 20 covers the inner surface of each trench 14. The gate electrode 22 is located within each trench 14. The gate electrode 22 is insulated from the semiconductor substrate 12 by the gate insulating film 20. The upper surface of the gate electrode 22 is covered by the interlayer insulating film 24.

[0014] The source electrode 26 covers the upper surface 12a of the semiconductor substrate 12. The source electrode 26 is insulated from the gate electrode 22 by the interlayer insulating film 24. The drain electrode 28 covers the lower surface 12b of the semiconductor substrate 12.

[0015] The semiconductor substrate 12 has a plurality of source layers 32, a plurality of contact layers 34, a body layer 36, a drift layer 38, a buffer layer 40, a drain layer 42, a plurality of first lower p layers 51, and a plurality of second lower p layers 52.

[0016] Each source layer 32 is an n-type layer having a high n-type impurity concentration. Each source layer 32 is in ohmic contact with the source electrode 26 at its upper surface 12a. Each source layer 32 is in contact with the gate insulating film 20 at the upper end of the side surface of the corresponding trench 14.

[0017] Each contact layer 34 is a p-type layer having a high concentration of p-type impurities. Each contact layer 34 is in ohmic contact with the source electrode 26 on its upper surface 12a.

[0018] The body layer 36 is a p-type layer having a lower p-type impurity concentration than the contact layer 34. The body layer 36 is located below the source layer 32 and the contact layer 34. The body layer 36 is in contact with the source layer 32 and the contact layer 34 from below. The body layer 36 is in contact with the gate insulating film 20 on the side surface of the trench 14 below the source layer 32.

[0019] The drift layer 38 is an n-type layer having a lower n-type impurity concentration than the source layer 32. The n-type impurity concentration of the drift layer 38 is 9 × 10⁻⁶. 17 cm -3The following is the case. The drift layer 38 is disposed below the body layer 36. The drift layer 38 contacts the body layer 36 from below. The drift layer 38 is separated from the source layer 32 by the body layer 36. The drift layer 38 contacts the gate insulating film 20 on the side surface of the trench 14 below the body layer 36. The drift layer 38 extends from the position where it contacts the body layer 36 to below the lower end of each trench 14.

[0020] The buffer layer 40 is an n-type layer having an n-type impurity concentration higher than that of the drift layer 38. The n-type impurity concentration of the buffer layer 40 is higher than 9×10 17 cm -3 . The buffer layer 40 contacts the drift layer 38 from below.

[0021] The drain layer 42 is an n-type layer having an n-type impurity concentration higher than that of the buffer layer 40. The drain layer 42 contacts the buffer layer 40 from below. The drain layer 42 makes an ohmic contact with the drain electrode 28 on the lower surface 12b of the semiconductor substrate 12.

[0022] Each first lower p-layer 51 is disposed below the corresponding trench 14. Each first lower p-layer 51 contacts the gate insulating film 20 on the bottom surface of the corresponding trench 14. That is, each first lower p-layer 51 contacts the gate insulating film 20 from below. Each first lower p-layer 51 contacts the drift layer 38 from above. The lower surface and side surface of each first lower p-layer 51 contact the drift layer 38. Each first lower p-layer 51 is connected to the body layer 36 by a p-type layer not shown. Therefore, the potential of each first lower p-layer 51 is substantially equal to the potential of the body layer 36.

[0023] Each second lower p-layer 52 is disposed below the body layer 36. Each second lower p-layer 52 extends long in the y direction parallel to the trench 14. Each second lower p-layer 52 contacts the body layer 36 from below. Each second lower p-layer 52 contacts the drift layer 38 from above. The lower surface and side surface of each second lower p-layer 52 contact the drift layer 38.

[0024] Figure 2 shows the distribution of p-type impurity concentration at the position of line II-II in Figure 1 (i.e., the distribution of p-type impurity concentration in the z direction of the lower p layer). The maximum value N shown in Figure 2. Amax The value N is the maximum value of the p-type impurity concentration in the first lower p-layer 51, and the value C is the average value of the n-type impurity concentration in the drift layer 38 below the first lower p-layer 51. The region with a p-type impurity concentration higher than the value C is the first lower p-layer 51. The first lower p-layer 51 has a maximum value N Amax A high-concentration layer 51a having a p-type impurity concentration of more than half, and a maximum value N Amax It has a low-concentration layer 51b (i.e., a p-type layer including an upper low-concentration layer 51bU and a lower low-concentration layer 51bL) having a p-type impurity concentration of less than half of the above. In this embodiment, the maximum value N Amax is 5 x 10 19 cm -3 This concludes the explanation. As shown in Figure 1, the high-concentration layer 51a is located approximately in the center of the first lower p-layer 51, and the low-concentration layer 51b is located around the high-concentration layer 51a. The low-concentration layer 51b has an upper low-concentration layer 51bU and a lower low-concentration layer 51bL. The upper low-concentration layer 51bU is located above the high-concentration layer 51a, and the lower low-concentration layer 51bL is located below the high-concentration layer 51a. The lower low-concentration layer 51bL is located between the high-concentration layer 51a and the drift layer 38 in the z direction. Also, the average value A shown in Figure 2 is the average value of the p-type impurity concentration in the low-concentration layer 51b. The lower low-concentration layer 51bL has a region 51c that has a higher p-type impurity concentration than the average value A. Region 51c is in contact with the high-concentration layer 51a from below.

[0025] The thickness x0 of region 51c is greater than the smaller of the thicknesses x1 and x2 obtained by the following equations (1) and (2).

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[0026] Within the second lower p-layer 52, the p-type impurity concentration is distributed in approximately the same way as in the first lower p-layer 51 (i.e., Figure 2). The second lower p-layer 52 has a high-concentration layer 52a and a low-concentration layer 52b (i.e., a p-type layer including an upper low-concentration layer 52bU and a lower low-concentration layer 52bL). The high-concentration layer 52a is the maximum value N of the p-type impurity concentration in the second lower p-layer 52. Amax It has a p-type impurity concentration of more than half, and the low-concentration layer 52b has a maximum value of N Amax It has a p-type impurity concentration of less than half of the above. As shown in Figure 1, the high-concentration layer 52a is located approximately in the center of the second lower p-layer 52, and the low-concentration layer 52b is located around the high-concentration layer 52a. The low-concentration layer 52b has an upper low-concentration layer 52bU and a lower low-concentration layer 52bL. The upper low-concentration layer 52bU is located above the high-concentration layer 52a, and the lower low-concentration layer 52bL is located below the high-concentration layer 52a. The lower low-concentration layer 52bL has a region 52c having a p-type impurity concentration higher than the average value A of the p-type impurity concentration in the low-concentration layer 52b. Region 52c is in contact with the high-concentration layer 52a from below. When the above formulas (1) and (2) are applied to the drift layer 38 below the second lower p-layer 52, the thickness x0 of region 52c of the second lower p-layer 52 is greater than the smaller of the thicknesses x1 and x2.

[0027] Next, the operation of the switching element 10 will be described. When the switching element 10 is in use, a higher potential is applied to the drain electrode 28 than to the source electrode 26. When a potential greater than or equal to the gate threshold is applied to the gate electrode 22, a channel is formed in the body layer 36 within the range adjacent to the gate insulating film 20. Then, the source layer 32 and the drift layer 38 are connected by the channel. As a result, electrons flow from the source layer 32 to the drain layer 42 via the channel, the drift layer 38, and the buffer layer 40. That is, the switching element 10 turns on. When the potential of the gate electrode 22 is reduced to a potential less than the gate threshold, the channel disappears, and the switching element 10 turns off.

[0028] When the switching element 10 is turned off, a reverse voltage is applied to the interface (i.e., the pn junction) between the p-type layer, which is composed of the body layer 36, the first lower p-layer 51, and the second lower p-layer 52, and the drift layer 38. As a result, a depletion layer extends from the pn junction into the p-type layer and into the drift layer 38.

[0029] When the switching element 10 is a punch-through type, the entire drift layer 38 is depleted when the drain-source voltage of the switching element 10 is lower than the maximum rated voltage. Therefore, in the punch-through type, the maximum width of the depletion layer extending into the drift layer 38 is equal to the thickness T of the drift layer 38. In this case, the width of the depletion layer extending into the first lower p layer 51 from the bottom surface (i.e., the pn junction) is the thickness x1 obtained by the above formula 1. Similarly, the width of the depletion layer extending into the second lower p layer 52 from the bottom surface (i.e., the pn junction) is also x1 obtained by the above formula 1.

[0030] When the switching element 10 is a non-punch-through type, when the maximum rated voltage is applied between the drain and source of the switching element 10, a depletion layer with a width corresponding to the maximum rated voltage is formed in the drift layer 38. In this case, the width of the depletion layer extending from the lower surface (i.e., the pn junction) of the first lower p layer 51 into the first lower p layer 51 is the thickness x 2 obtained by the above formula 2. Similarly, the width of the depletion layer extending from the lower surface (i.e., the pn junction) of the second lower p layer 52 into the second lower p layer 52 is also the thickness x 2 obtained by the above formula 2.

[0031] Thus, the smaller of the thicknesses x1 and x2 represents the maximum width of the depletion layer extending within the first lower p layer 51 and the second lower p layer 52. In Example 1, the thickness x0 of region 51c, which is part of the lower low-concentration layer 51bL located below the high-concentration layer 51a, is greater than the smaller of the thicknesses x1 and x2. Also, the thickness x0 of region 52c, which is part of the lower low-concentration layer 52bL located below the high-concentration layer 52a, is greater than the smaller of the thicknesses x1 and x2. Therefore, when the switching element 10 is turned off, the depletion layer does not reach the high-concentration layers 51a and 52a. Because the p-type impurity concentration in the high-concentration layers 51a and 52a is high, crystal defects exist at high density within the high-concentration layers 51a and 52a. When the depletion layer reaches the high-concentration layers 51a and 52a, which have a high crystal defect density, a high leakage current is generated. In contrast, in this embodiment, the depletion layer does not reach the high-concentration layers 51a and 52a, so leakage current is less likely to occur.

[0032] Furthermore, when cosmic rays are incident on the lower p-layer 51 while the switching element 10 is off, electron-hole pairs are generated within the lower p-layer 51. When holes generated within the lower p-layer 51 are accelerated by an electric field and injected into the gate insulating film 20, the insulating properties of the gate insulating film 20 deteriorate. In contrast, in Example 1, the maximum value N of the p-type impurity concentration in the lower p-layer 51 Amax 5 x 10 19 cm -3As described above, the space charge in the lower p-layer 51 is significantly negative. Therefore, even if holes are generated in the lower p-layer 51 due to the incidence of cosmic rays, an electric field directed toward the gate insulating film 20 is unlikely to be generated in the lower p-layer 51, and the injection of holes into the gate insulating film 20 is suppressed. As a result, the degradation of the gate insulating film 20 is suppressed. Similarly, if cosmic rays are incident in the lower p-layer 52, the injection of holes into the gate oxide film 20 is suppressed, and the degradation of the gate oxide film 20 is suppressed.

[0033] As described above, in the switching element 10 of Example 1, the first lower p layer 51 and the second lower p layer 52 can suppress the injection of holes generated by cosmic rays into the gate insulating film 20, thereby suppressing the degradation of the gate insulating film 20. Furthermore, leakage current caused by the first lower p layer 51 and the second lower p layer 52 can be suppressed.

[0034] In Example 1, an upper low-concentration layer 51bU was provided above the high-concentration layer 51a, but as shown in Figures 3 and 4, the upper low-concentration layer 51bU may not be provided, and the high-concentration layer 51a may be in direct contact with the gate insulating film 20. Also, in Example 1, an upper low-concentration layer 52bU was provided above the high-concentration layer 52a, but as shown in Figures 3 and 4, the upper low-concentration layer 52bU may not be provided, and the high-concentration layer 52a may be in direct contact with the body layer 36. In this configuration as well, since the lower low-concentration layers 51bL and 52bL exist below the high-concentration layers 51a and 52a, the depletion layer does not reach the high-concentration layers 51a and 52a, similar to Example 1. Therefore, leakage current can be suppressed. Note that in Figure 4, the maximum value N Amax 5 x 10 19 cm -3 The above is also acceptable. Furthermore, if the upper low-concentration layers 51bU and 52bU are not provided, low-concentration layers 51b and 52b may be provided on the sides and below the high-concentration layers 51a and 52a, as shown in Figure 5.

[0035] Furthermore, in Example 1, the second lower p layer 52 extended along the y-direction, but as shown in Figure 6, the second lower p layer 52 may extend along the x-direction (i.e., the direction intersecting the trench 14). In this structure, the first lower p layer 51 and the second lower p layer 52 are connected to each other at their intersection.

[0036] Furthermore, in Example 1, a buffer layer 40 was provided between the drift layer 38 and the drain layer 42, but the buffer layer 40 may be absent, and the drift layer 38 may be in contact with the drain layer 42.

[0037] Furthermore, in Example 1, both the first lower p layer 51 and the second lower p layer 52 were provided on the semiconductor substrate 12, but either the first lower p layer 51 or the second lower p layer 52 may be provided. [Examples]

[0038] The switching element 100 of Embodiment 2 shown in Figure 7 is a planar type MOSFET. The switching element 100 is designed for use in the stratosphere or higher altitudes (e.g., outer space) and has a structure that can suppress the effects of cosmic rays. In the following description, the same reference numerals as in Embodiment 1 will be used to indicate the parts of the switching element 100 of Embodiment 2. The switching element 100 has a semiconductor substrate 12, a gate electrode 22, a gate insulating film 20, a source electrode 26, and a drain electrode 28.

[0039] The semiconductor substrate 12 is made of silicon carbide (i.e., SiC). The gate insulating film 20 covers a portion of the upper surface 12a of the semiconductor substrate 12. The gate electrode 22 is positioned on the gate insulating film 20. The gate electrode 22 is insulated from the semiconductor substrate 12 by the gate insulating film 20. The upper and side surfaces of the gate electrode 22 are covered by the interlayer insulating film 24. The source electrode 26 covers the upper surface 12a of the semiconductor substrate 12. The source electrode 26 is insulated from the gate electrode 22 by the interlayer insulating film 24. The drain electrode 28 covers the lower surface 12b of the semiconductor substrate 12.

[0040] The semiconductor substrate 12 has a plurality of source layers 32, a plurality of contact layers 34, a plurality of body layers 36, a drift layer 38, a buffer layer 40, a drain layer 42, and a plurality of lower p layers 52.

[0041] Each source layer 32 is an n-type layer having a high n-type impurity concentration. Each source layer 32 is in ohmic contact with the source electrode 26 at its upper surface 12a. Each source layer 32 is in contact with the gate insulating film 20 at its upper surface 12a.

[0042] Each contact layer 34 is a p-type layer having a high concentration of p-type impurities. Each contact layer 34 is in ohmic contact with the source electrode 26 on its upper surface 12a.

[0043] Each body layer 36 is a p-type layer having a lower p-type impurity concentration than the contact layer 34. Multiple body layers 36 are arranged with spacing in the x-direction. Each body layer 36 is positioned around the source layer 32 and the contact layer 34. Each body layer 36 is in contact with the source layer 32 and the contact layer 34 from below. Each body layer 36 is distributed to the side of the source layer 32 and is in contact with the side surface of the source layer 32. Each body layer 36 is in contact with the gate insulating film 20 at a position adjacent to the source layer 32.

[0044] The drift layer 38 is an n-type layer having a lower n-type impurity concentration than the source layer 32. The n-type impurity concentration of the drift layer 38 is 9 × 10⁻⁶. 17 cm -3 The following applies: The drift layer 38 is located beneath each body layer 36. The drift layer 38 is distributed up to the top surface 12a between the two body layers 36 and is in contact with the side surfaces of each body layer 36. The drift layer 38 is in contact with the gate insulating film 20 at a position adjacent to the body layer 36. The drift layer 38 is separated from the source layer 32 by the body layer 36.

[0045] The buffer layer 40 is an n-type layer having a higher n-type impurity concentration than the drift layer 38. The n-type impurity concentration of the buffer layer 40 is 9 × 10⁻⁶.17 cm -3 It is higher. The buffer layer 40 is in contact with the drift layer 38 from below.

[0046] The drain layer 42 is an n-type layer having a higher n-type impurity concentration than the buffer layer 40. The drain layer 42 is in contact with the buffer layer 40 from below. The drain layer 42 is in ohmic contact with the drain electrode 28 on the lower surface 12b of the semiconductor substrate 12.

[0047] Each lower p layer 52 is positioned below the corresponding body layer 36. Each lower p layer 52 is in contact with the corresponding body layer 36 from below. The bottom surface and sides of each lower p layer 52 are in contact with the drift layer 38.

[0048] The p-type impurity concentration distribution within each lower p-layer 52 is equal to the p-type impurity concentration within the lower p-layer 52 of Example 1 (i.e., Figure 2). That is, each lower p-layer 52 has a high-concentration layer 52a and a low-concentration layer 52b. An upper low-concentration layer 52bU is provided above the high-concentration layer 52a, and a lower low-concentration layer 52bL is provided below the high-concentration layer 52a. The lower low-concentration layer 52bL has a region 52c having a p-type impurity concentration higher than the average value A of the p-type impurity concentration of the low-concentration layer 52b. The thickness x0 of region 52c is greater than the smaller of the thicknesses x1 and x2 obtained by the above formulas (1) and (2). Therefore, when the switching element 100 of Example 2 is off, the depletion layer extending from the lower surface (i.e., the pn junction) of each lower p-layer 52 into the interior of each lower p-layer 52 does not reach the high-concentration layer 52a. Therefore, leakage current is suppressed in the switching element of Example 2 as well. Furthermore, in the switching element of Example 2, the injection of holes into the gate insulating film 20 is suppressed by each lower p layer 52.

[0049] In Example 2, an upper low-concentration layer 52bU was provided above the high-concentration layer 52a. However, as shown in Figure 8, the upper low-concentration layer 52bU may not be provided, and the high-concentration layer 52a may be in direct contact with the body layer 36. In this configuration as well, since a lower low-concentration layer 52bL exists below the high-concentration layer 52a, the depletion layer does not reach the high-concentration layer 52a. Therefore, leakage current can be suppressed. Furthermore, if the upper low-concentration layer 52bU is not provided, a low-concentration layer 52b may be provided on the side and below the high-concentration layer 52a, as shown in Figure 9.

[0050] Furthermore, in Example 2, a buffer layer 40 was provided between the drift layer 38 and the drain layer 42, but the buffer layer 40 is not required. In each of the above examples, the concentrations of the drift layer 38 and the buffer layer 40 may be adjusted during epitaxial growth, or they may be adjusted by ion implantation after epitaxial growth.

[0051] Although embodiments have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technologies illustrated in this specification or drawings achieve multiple objectives simultaneously, and achieving even one of these objectives constitutes technical usefulness. [Explanation of Symbols]

[0052] 10: Switching element, 20: Gate insulating film, 22: Gate electrode, 32: Source layer, 36: Body layer, 38: Drift layer, 51: First lower p-layer, 51a: High-density layer, 51b: Low-density layer, 52: Second lower p-layer, 52a: High-density layer, 52b: Low-density layer

Claims

1. A switching element, A semiconductor substrate made of silicon carbide, A gate electrode facing the semiconductor substrate via a gate insulating film, It has, The aforementioned semiconductor substrate An n-type source layer in contact with the gate insulating film, The gate insulating film and the p-type body layer in contact with the source layer, The gate insulating film and the body layer are in contact with an n-type drift layer which is separated from the source layer by the body layer, At least one of the following: a first lower p layer that contacts the gate insulating film from below and the drift layer from above, and a second lower p layer that contacts the body layer from below and the drift layer from above. It has, The first and second lower p layers are A high-concentration layer having a p-type impurity concentration of more than half of the maximum value of the p-type impurity concentration in the first and second lower p-layers, A low-concentration layer having a p-type impurity concentration less than half of the aforementioned maximum value, It has, The low-concentration layer has a lower low-concentration layer disposed between the high-concentration layer and the drift layer in the thickness direction of the semiconductor substrate. The thickness x0 of the portion of the lower low-concentration layer having a p-type impurity concentration higher than the average value A of the p-type impurity concentration in the low-concentration layer is greater than the smaller of the thicknesses x1 and x2 obtained by the following formulas (1) and (2). [Math 1] Here, the symbol C is the average value of the n-type impurity concentration in the drift layer below the first and second lower p layers, the symbol T is the thickness of the drift layer below the first and second lower p layers, the symbol ε is the dielectric constant of silicon carbide, the symbol q is the elementary charge, and the symbol V ｂｉ V is the built-in potential at the interface between the low-concentration layer and the drift layer. ＢＶ k is the maximum rated voltage that can be applied between the drain and source of the switching element, k is the Boltzmann constant, and n ｉ This is the intrinsic carrier density of silicon carbide.

2. A trench is provided on the upper surface of the semiconductor substrate, The gate insulating film and the gate electrode are arranged in the trench. The trench has a first lower p layer in contact with the gate insulating film at its bottom surface, The switching element according to claim 1.

3. The switching element according to claim 1, further comprising the second lower p layer that contacts the body layer from below.

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