Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device and a method for manufacturing the same. [Solution] The semiconductor device 100 includes a substrate 102 which is an n+-doped silicon carbide substrate, an n-doped silicon carbide substrate, or a p-doped silicon carbide substrate; a buffer layer 104 provided above the substrate and containing doped gallium nitride and having a breakdown field of 80 V / μm or more; an active region M provided above the buffer layer and including a channel layer 106 containing undoped or intentionally undoped gallium nitride and a barrier layer 108 provided above the channel layer and containing undoped or intentionally undoped aluminum gallium nitride; and a source S, gate G, and drain D provided above the active region, the gate being provided between the source and the drain.

Description

[Technical Field]

[0001] The present invention provides semiconductor devices and methods for manufacturing the same, and more particularly, semiconductor devices used as power elements and methods for manufacturing the same. However, the present invention is not limited thereto. [Background technology]

[0002] With the rapid development and proliferation of wireless communication systems and mobile devices, the industrial demand for power elements is gradually increasing. In particular, in the application market for 5G infrastructure, superior power elements will play an increasingly important role in achieving objectives such as cost reduction, efficiency improvement, and bandwidth expansion.

[0003] Specifically, high electron mobility transistors (HEMTs) using aluminum gallium nitride (AlGaN) / gallium nitride (GaN) are considered a noteworthy technological option for power devices due to their advantages such as low on-resistance, high current density, and high breakdown voltage. These excellent characteristics mainly stem from the superior material properties of GaN, such as its wide bandgap, high critical electric field, and high electron saturation velocity. Furthermore, due to the unique polarization effect of GaN, AlGaN / GaN heterostructures can induce two-dimensional electron gases (2DEGs) in the interface block without doping, allowing AlGaN / GaN HEMTs to operate with high current output while maintaining extremely low on-resistance.

[0004] Many of the above semiconductor devices include a substrate that supports the epitaxial and overall device structure and provides a heat dissipation channel. Generally, when preparing a substrate, in addition to considering its thermal conductivity and compatibility with other layers, further properties such as its crystal orientation, surface defects, and electrical properties are also considered. [Overview of the Initiative]

[0005] The inventors of the present invention have discovered that, in the prior art, semiconductor devices, in response to the need to increase the breakdown voltage of the entire device, either use expensive semi-insulating substrates or, in pursuit of ideal electrical characteristics, may overlook the crystal orientation and surface defects of the substrate. Therefore, the inventors have proposed a technique in which the breakdown voltage of the device is controlled by the epitaxial structure, and low-cost n+-doped silicon carbide substrates, n-doped silicon carbide substrates, or p-doped silicon carbide substrates are used. In other words, in the present invention, a specific buffer layer is provided above the substrate of the semiconductor device, thereby controlling the breakdown voltage of the entire device. As a result, the present invention can ensure the crystal orientation and surface quality of the substrate, and achieve an ideal device breakdown voltage at a low cost. Furthermore, since the breakdown voltage is controlled by the epitaxial structure, the present invention can meet various needs and further improve the design flexibility of the device by adjusting the parameters of the buffer layer.

[0006] Specifically, one aspect of the present invention provides a semiconductor device comprising: a substrate which is an n+-doped silicon carbide substrate, an n-doped silicon carbide substrate, or a p-doped silicon carbide substrate; an active region provided above the substrate which includes a buffer layer containing doped gallium nitride and having a breakdown electric field of 80 V / μm or more; an active region provided above the buffer layer which includes a channel layer containing undoped or intentionally undoped gallium nitride; and an active region provided above the channel layer which includes an undoped or intentionally undoped aluminum gallium nitride; and a source, gate, and drain provided above the active region, wherein the gate is provided between the source and the drain.

[0007] According to some embodiments of the present invention, the thickness of the buffer layer is 1 μm or more.

[0008] According to some embodiments of the present invention, the thickness of the buffer layer is 1 to 15 μm.

[0009] According to some embodiments of the present invention, the semiconductor device further includes a nucleating layer provided between the conductive substrate and the buffer layer, wherein the nucleating layer comprises undoped or intentionally undoped aluminum nitride.

[0010] According to some embodiments of the present invention, the thickness of the nucleating layer is less than 100 nm.

[0011] According to some embodiments of the present invention, the semiconductor device further includes a first dielectric layer covering a portion of the active region, a gate metal field plate covering the gate and a portion of the first dielectric layer, a second dielectric layer covering the gate metal field plate and a portion of the first dielectric layer, and a source metal field plate covering a portion of the source and the second dielectric layer.

[0012] According to some embodiments of the present invention, the materials of the first dielectric layer and the second dielectric layer are nitrides or oxides.

[0013] According to some embodiments of the present invention, the substrate is a 4H-SiC substrate.

[0014] According to some embodiments of the present invention, the active region further includes a surface layer (Cap layer) provided above the barrier layer, the thickness of which is 1.5 to 2.0 nm.

[0015] Another aspect of the present invention provides a method for manufacturing a semiconductor device, comprising the steps of: (a) preparing a substrate which is an n+-doped silicon carbide substrate, an n-doped silicon carbide substrate, or a p-doped silicon carbide substrate; (b) forming a buffer layer on the substrate which contains doped gallium nitride and has a breakdown electric field of 80 V / μm or more; (c) forming an active region on the buffer layer which includes forming a channel layer and then forming a barrier layer on the channel layer, wherein the channel layer contains undoped or intentionally undoped gallium nitride and the barrier layer contains undoped or intentionally undoped aluminum gallium nitride; and (d) forming a source, gate, and drain on the active region which the gate is located between the source and the drain.

[0016] According to some embodiments of the present invention, the thickness of the buffer layer is 1 μm or more.

[0017] According to some embodiments of the present invention, the thickness of the buffer layer is 1 to 15 μm.

[0018] According to some embodiments of the present invention, the manufacturing method further includes step (a-1) between step (a) and step (b) forming a nucleation layer on the substrate comprising undoped or intentionally undoped aluminum nitride.

[0019] According to some embodiments of the present invention, the thickness of the nucleating layer is less than 100 nm.

[0020] According to some embodiments of the present invention, the manufacturing method further includes: (e) forming a first dielectric layer above the active region so as to cover a part of the active region; (f) forming a gate metal field plate so as to cover the gate and a part of the first dielectric layer; (g) forming a second dielectric layer so as to cover the gate metal field plate and a part of the first dielectric layer; and (h) forming a source metal field plate so as to cover a part of the source and the second dielectric layer.

[0021] According to some embodiments of the present invention, the materials of the first dielectric layer and the second dielectric layer are nitrides or oxides.

[0022] According to some embodiments of the present invention, the substrate is a 4H-SiC substrate.

[0023] According to some embodiments of the present invention, step (c) further includes forming a surface layer above the barrier layer, and the thickness of the surface layer is 1.5 - 2.0 nm.

[0024] As described above, the semiconductor device and its manufacturing method provided by the present invention can ensure the crystal orientation and surface quality of the substrate, and achieve an ideal element breakdown voltage at a low cost. Further, since the breakdown voltage is dominated by the epitaxial structure, in the present invention, by adjusting the parameters of the buffer layer, various needs can be satisfied, and the design freedom of the element can be further improved.

Brief Description of the Drawings

[0025] For a clearer understanding of the above and other objects, features, advantages and embodiments of the present invention, the description of the accompanying drawings is as follows.

[0026] [Figure 1] It is a step flowchart of a manufacturing method of a semiconductor device according to an embodiment of the present invention. [Figure 2]This is a step flowchart of a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 3] This is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.

[0027] Based on standard working procedures, the various features and elements in the figures are not drawn according to actual proportions, but rather the method of drawing is intended to show the specific features and elements related to the present invention in the most optimal way. Furthermore, identical or similar reference numerals between different drawings refer to similar elements and components. [Modes for carrying out the invention]

[0028] To provide a more detailed and complete description of the present invention, embodiments and specific examples of the present invention are described below, but these are not the only ways of carrying out or operating specific embodiments of the present invention. In this specification and the appended claims, "one" and "the" may be interpreted as plural unless otherwise specified in the context. Also, in this specification and the appended claims, "provided on an article" can be considered to be in direct or indirect contact with the surface of an article by attachment or other means unless otherwise specified, and the definition of the surface should be determined based on the context of the preceding and following paragraphs of the specification and ordinary knowledge in the art to which the present invention pertains.

[0029] All numerical ranges and parameters used to limit the present invention are approximate; however, the relevant numerical values ​​in the specific examples are shown as accurately as possible. However, it is unavoidable that any numerical value inherently includes a standard deviation due to the individual test method. Here, "approximately" usually means that the actual value is within plus or minus 10%, 5%, 1%, or 0.5% of a particular value or range. Alternatively, the term "approximately" indicates that the actual numerical value is within the acceptable standard error of the mean value considered by a person of ordinary skill in the art to which the present invention pertains. Therefore, unless otherwise specified, all numerical parameters disclosed herein and in the appended claims are approximate and may be modified as necessary. At a minimum, these numerical parameters should be understood as values ​​obtained using the indicated number of significant figures and common carry methods.

[0030] term As used herein, the term “semiconductor material” may include chemical compounds of multiple elements, the chemical compounds of which may include pairs composed of elements from Group 13 (i.e., the group consisting of boron (B), aluminum (Al), gallium (Ga), indium (In), and thallium (Tl)) and elements from Group 15 (i.e., the group consisting of nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi)), or pairs composed of elements from Group 14 (i.e., the group consisting of elements such as carbon (C), silicon (Si), germanium (Ge), and tin (Sn)), for example, silicon carbide (SiC) or silicon germanium alloys. The groups 13 to 15 may be called Group III, IV, and V, respectively.

[0031] As used herein, the term “semiconductor device” refers to an active or passive device made of semiconductor material, and includes, but is not limited to, transistors, diodes, resistors / capacitors / sensors, sensing elements, and their arrays, matching circuits, power modules, and packages. The transistor is, for example, a high electron mobility transistor (HEMT), which may have a naturally normally-on structure and a negative threshold voltage, or may be converted to a normally-off structure and have a positive threshold voltage.

[0032] As used herein, “method for manufacturing a semiconductor device” refers to any set of steps for manufacturing a semiconductor device, including, but not limited to, surface pretreatment, nucleation and epitaxial growth / deposition processes, patterning (including exposure / development), etching processes, stripping processes, ion implantation / doping, annealing, alloying, passivation, packaging, and testing. Unless otherwise stated, the order, number of repetitions, and conditions of each step can be adjusted according to the product design and are not limited to the present invention.

[0033] As used herein, the term “epitaxial growth or deposition process” includes, but is not limited to, chemical vapor deposition (CVD), low-pressure CVD (LPCVD), atmospheric pressure CVD (APCVD), ultra-high vacuum CVD (UHVCVD), atomic layer deposition (ALD), molecular layer deposition (MLD), plasma-enhanced CVD (PECVD), metal-organic CVD (MOCVD), molecular beam epitaxy (MBE), sputtering, and other methods or combinations thereof.

[0034] As used herein, the term "etching process" includes, but is not limited to, dry etching and wet etching. Of these, dry etching includes physical impact methods such as reactive ion etching (RIE) and inductively coupled plasma etching (ICP), while wet etching refers to well-known chemical solution etching methods in the art to which this invention pertains.

[0035] The following description of the present invention contains the necessary technical information to be easily understood by a person ordinary in the art, and other embodiments of the present invention also fall within the scope of the claims of the present invention if various modifications and modifications are made to the present invention to adapt it to different uses and circumstances without violating its spirit and scope.

[0036] Examples Here, some embodiments of the semiconductor device and its manufacturing method according to the present invention are illustratively shown in this specification. Specifically, FIGS. 1 and 2 show the step flow of the manufacturing method of the semiconductor device, and FIG. 3 shows the cross-sectional structure of the semiconductor device manufactured by the above method.

[0037] First, refer to FIG. 1. The manufacturing method of the semiconductor device provided by the present invention generally includes the following steps. In step S100, a substrate is prepared. In step S102, a buffer layer is formed above the substrate. In step S104, an active region is formed above the buffer layer. In step S106, a source, a gate, and a drain are formed above the active region.

[0038] In step S100, the substrate includes a doped silicon carbide material, and although not limited by a specific theory, the substrate made of the silicon carbide material not only has favorable heat dissipation performance but also has good lattice matching with the gallium nitride material. Specifically, the substrate is an n+-type doped silicon carbide substrate, an n-type doped silicon carbide substrate, or a p-type doped silicon carbide substrate, and its doping type can be selected and set according to the requirements of the device. Preferably, the substrate is an n+-type doped silicon carbide substrate or a p-type doped silicon carbide substrate. On the other hand, the doping concentration of the substrate is 1×10 17 ~5×10 19 cm -3 , for example, 1×10 17 、5×10 17 、1×10 18 、5×10 18 、1×10 19 、5×10 19 cm -3 or within the range between any two of the above values. According to a preferred embodiment of the present invention, the substrate is a 4H-SiC substrate, which has ideal crystal orientation (0 degrees, that is, a tilt angle close to zero / zero) and few surface defects, so it is more suitable for application to semiconductor devices.

[0039] In step S102, the buffer layer comprises a doped III-V material. Specifically, the buffer layer comprises doped gallium nitride and has a breakdown field of 80 V / μm or more, for example, 80, 90, 100, 110, 120, 130, 140, 150, 160, 170, 180, 190, 200, 210, 220, 230, 240, 250, 260, 270, 280, 290, 300, 310, 320, 330, 340, 350 V / μm or in the range of any two of the above values. Preferably, the breakdown field is 200-300 V / μm, which allows the device to reach a constant breakdown voltage within a suitable set thickness. On the other hand, the buffer layer is formed by a suitable epitaxial growth or deposition process, and the process method specifically employed is not limited to the present invention.

[0040] According to some embodiments of the present invention, between step S100 and step S102, a nucleation layer is further formed above the substrate, thereby further compensating for lattice mismatch between the substrate and the buffer layer. Specifically, the nucleation layer comprises undoped or intentionally undoped aluminum nitride and is formed by a suitable epitaxial growth or deposition process.

[0041] In step S104, forming the active region includes forming a channel layer and then forming a barrier layer thereon. Specifically, the channel layer is produced by a suitable epitaxial growth or deposition process using undoped or intentionally undoped gallium nitride as the forming material. The barrier layer is made of undoped or intentionally undoped aluminum gallium nitride (Al x Ga 1-x The forming material is N), where x is in the range of approximately 0.1 to approximately 1. In one embodiment, x is 0.15 to 1, and in another embodiment, x is 0.20 to 0.25. The barrier layer is also formed by an appropriate epitaxial growth or deposition process.

[0042] According to some embodiments of the present invention, step S104 further includes forming a surface layer (Cap layer) above the barrier layer, thereby achieving synergistic effects of surface passivation, edge leakage reduction, and electric field redistribution. Specifically, the surface layer may be made of a semiconductor material or a dielectric material and can be formed by a suitable epitaxial growth or deposition process.

[0043] According to some embodiments of the present invention, prior to step S106, preparatory steps such as mesa isolation, which further include an etching process, may be included. The etching process may be dry etching or wet etching, and preferably employs a dry etching method, such as reactive ion etching or inductively coupled plasma etching, which is a physical impact method.

[0044] In step S106, forming the source, gate, and drain includes forming source openings, gate openings, and drain openings at predetermined positions using a suitable etching process, and further forming source electrodes, gate electrodes, and drain electrodes with metal layers, respectively. Here, the material used for the source electrodes and drain electrodes is any suitable conductive material capable of forming ohmic contacts or other conductive junctions, preferably titanium (Ti) / aluminum (Al) / nickel (Ni) / tantalum (Ta) / molybdenum (Mo) / gold (Au), and the material used for the gate electrode is any conductive material that enables biasing or control of the semiconductor device, but preferably nickel (Ni) / gold (Au) or zirconium (Zr) / gold (Au) can be used to create a larger valence band energy gap with the semiconductor material used in the present invention. On the other hand, the source opening and drain opening are etched downward to a barrier layer or channel layer, and specifically the metal layer formed within the opening needs to be alloyed by an alloying process, and then the source electrodes and drain electrodes are formed, respectively, to generate ohmic contact in the semiconductor device.

[0045] Next, refer to Figure 2. The method for manufacturing a semiconductor device of the present invention further includes the following steps: In step S108, a first dielectric layer is formed above the active region so as to cover a portion of the active region. In step S110, a gate metal field plate is formed so as to cover the gate and a portion of the first dielectric layer. In step S112, a second dielectric layer is formed so as to cover the gate metal field plate and a portion of the first dielectric layer. In step S114, a source metal field plate is formed so as to cover a portion of the source and the second dielectric layer.

[0046] In step S108, the first dielectric layer is formed by a suitable epitaxial growth or deposition process, the material of which is a nitride or oxide. Specifically, the material of the first dielectric layer is silicon oxide (SiO2) or silicon oxynitride (SiON). x , or silicon nitride (SiN) xIt is at least one of the following (x is approximately 0.1 to 1). This allows for adjustment of the electric field distribution to make it more uniform if it covers part of the active region, further improving the breakdown voltage of the element, reducing leakage current, and further ensuring that the breakdown voltage of the entire element is dominated by the epitaxial structure.

[0047] In step S110, the material of the gate metal field plate is a metal or a conductive / semiconductor thin film. Specifically, the material of the gate metal field plate may be, but is not limited to, aluminum, copper, titanium / aluminum laminates, nickel / gold laminates, tungsten, and molybdenum.

[0048] In step S112, the second dielectric layer is formed by a suitable epitaxial growth or deposition process, the material of which is a nitride or oxide. Specifically, the material of the second dielectric layer is silicon oxide (SiO2) or silicon oxynitride (SiON). x , or silicon nitride (SiN) x It is at least one of the following (x is approximately 0.1 to 1). This allows for the adjustment of the electric field distribution to make it more uniform if it covers part of the gate metal field plate and the first dielectric layer, further improving the breakdown voltage of the device and reducing leakage current, and also ensuring that the breakdown voltage of the entire device is dominated by the epitaxial structure.

[0049] In step S114, the source metal field plate is a metal or a conductive / semiconductor thin film. Specifically, the material of the source metal field plate may be, but is not limited to, aluminum, copper, titanium / aluminum laminates, nickel / gold laminates, tungsten, and molybdenum. According to some other embodiments of the present invention, in step S114, a second gate metal field plate may be formed above the second dielectric layer instead of the source metal field plate.

[0050] Figure 3 shows the cross-sectional structure of the semiconductor device 100 of the present invention; please refer to Figures 1-3 as well. According to some embodiments of the present invention, the semiconductor device 100 is a structure based on a high electron mobility transistor of aluminum gallium nitride (AlGaN) / gallium nitride (GaN), and is an epitaxial growth layer. However, according to some other embodiments, the semiconductor device 100 of the present invention may be an element based on other materials.

[0051] Specifically, the layer structure of the semiconductor device 100 consists of a substrate 102, a nucleation layer 103, a buffer layer 104, and an active region M, arranged from bottom to top. The active region M includes a channel layer 106 and a barrier layer 108. Furthermore, a source S, a gate G, and a drain D are provided above the barrier layer, and the gate G is located between the source S and the drain D.

[0052] According to some embodiments of the present invention, the semiconductor device 100 further includes a first dielectric layer 110 covering a portion of the active region M, a gate metal field plate PG covering the gate G and a portion of the first dielectric layer 110, a second dielectric layer 112 covering the gate metal field plate PG and a portion of the first dielectric layer 110, and a source metal field plate PS covering a portion of the source S and the second dielectric layer 112.

[0053] According to some embodiments of the present invention, the substrate 102 is an n+-doped silicon carbide substrate, an n-doped silicon carbide substrate, or a p-doped silicon carbide substrate. Preferably, the substrate 102 is an n+-doped silicon carbide substrate or a p-doped silicon carbide substrate. On the other hand, according to a preferred embodiment of the present invention, the substrate 102 is a 4H-SiC substrate, which has the characteristics of ideal crystal orientation (0 degrees, i.e., a tilt angle close to zero / zero) and few surface defects, making it more suitable for application in semiconductor devices.

[0054] According to some embodiments of the present invention, the buffer layer 104 contains doped gallium nitride and has a breakdown electric field of 80 V / μm or more. Preferably, the breakdown electric field is 200 to 300 V / μm, which allows the element to reach a constant breakdown voltage within an appropriate set thickness. Also, according to some preferred embodiments of the present invention, the thickness of the buffer layer 104 is 1 μm or more. Preferably, the thickness of the buffer layer 104 is 1 to 15 μm, for example, 1.0, 1.5, 2.0, 2.5, 3.0, 3.5, 4.0, 4.5, 5.0, 5.5, 6.0, 6.5, 7.0, 7.5, 8.0, 8.5, 9.0, 9.5, 10.0, 10.5, 11.0, 11.5, 12.0, 12.5, 13.0, 13.5, 14.0, 14.5, 15.0 μm or a range between any two of the above values. Although not limited by any particular theory, based on the idea that the breakdown voltage of the element is governed by the epitaxial structure, the numerical value of the breakdown voltage approximates the product of the material's breakdown electric field and its effective epitaxial thickness. This makes it advantageous to provide a buffer layer having a breakdown electric field within a specific range and limiting its thickness range to obtain a desired element breakdown voltage at a low cost. More specifically, if the thickness of the buffer layer 104 is made too thin, a sufficiently high device breakdown voltage may not be obtained, but if the thickness of the buffer layer 104 is made too thick, it may lead to adverse effects such as increased costs and process complexity.

[0055] According to some embodiments of the present invention, a dissimilar material interface exists between the channel layer 106 and the barrier layer 108, so a two-dimensional electron gas region is formed in the channel layer 106 near the interface. This two-dimensional electron gas region can form a conduction channel for free electrons when biased, and can further achieve the objective of electrically coupling, for example, a source S and a drain D. Furthermore, the material of the channel layer 106 is undoped or unintentionally doped GaN, with a thickness of 50 to 1000 nm, for example, in the range of 50, 100, 150, 200, 250, 300, 350, 400, 450, 500, 550, 600, 650, 700, 750, 800, 850, 900, 950, 1000 nm or between any two of the above values, preferably 200 to 600 nm. The material of the barrier layer 108 is undoped or unintentionally doped Al x Ga 1-x N is the value of x in the formula, where x is in the range of approximately 0.1 to approximately 1. The thickness of the barrier layer 108 is 10 to 40 nm, for example, in the range of 10, 15, 20, 25, 30, 35, 40 nm or any two of the above values, preferably 10 to 20 nm.

[0056] According to a preferred embodiment of the present invention, the nucleation layer 103 comprises undoped or intentionally undoped aluminum nitride and can be used to compensate for lattice mismatch between the substrate 102 and the buffer layer 104. Specifically, the thickness of the nucleation layer 103 is less than 100 nm, and is, for example, in the range of 10, 20, 30, 40, 50, 60, 70, 80, 90, 99 or any two of the above values.

[0057] According to a preferred embodiment of the present invention, the barrier layer 108 may further include a surface layer (not shown) having a thickness of 1.5 to 2.0 nm, for example, 1.5, 1.6, 1.7, 1.8, 1.9, 2.0 nm, or a range between any two of the above values.

[0058] According to some embodiments of the present invention, the gate G is provided above the barrier layer 108, and the source S and drain D are provided on either side of the gate G. Specifically, the electrode material of the gate G may be any conductive material that enables biasing or control of the semiconductor device 100, but considering the semiconductor material used in this embodiment and the generation of a larger valence band energy gap, nickel (Ni) / gold (Au) or zirconium (Zr) / gold (Au) may be preferred. The electrode material of the source S and drain D may be any suitable conductive material that can form an ohmic contact or other conductive junction with the two-dimensional electron gas region, and may be titanium (Ti) / aluminum (Al) / nickel (Ni) / tantalum (Ta) / molybdenum (Mo) / gold (Au).

[0059] According to some embodiments of the present invention, a first dielectric layer 110 is formed above and covering a portion of the barrier layer 108, a gate metal field plate PG is formed above the gate G and a portion of the first dielectric layer 110, a second dielectric layer 112 is formed above the gate metal field plate PG and a portion of the first dielectric layer 110, and a source metal field plate PS is formed above a portion of the source S and the second dielectric layer 112. However, the specific size of the covered area is not limited by the present invention. More specifically, the first dielectric layer 110 and the second dielectric layer 112 may be formed of the same or different materials, and the gate metal field plate PG and the source metal field plate PS may be formed of the same or different materials. In addition, according to some other embodiments of the present invention, the source metal field plate PS can be replaced by a second gate metal field plate (not shown). Specifically, the second gate metal field plate is provided above the second dielectric layer 112.

[0060] As described above, the semiconductor device and its manufacturing method provided in the present invention ensure the crystal orientation and surface quality of the substrate, and can achieve an ideal device breakdown voltage at a low cost. Furthermore, since the breakdown voltage is governed by the epitaxial structure, the present invention can meet various needs and further improve the design flexibility of the device by adjusting the parameters of the buffer layer.

[0061] Although the present invention has been described in detail above, these are merely preferred embodiments of the present invention and are not intended to limit the scope of the invention. That is, equivalent modifications and alterations that can be made by a person with ordinary skill in the art without departing from the spirit and scope of the invention still fall within the scope of the invention. [Explanation of Symbols]

[0062] 100 Semiconductor Equipment 102 circuit boards 103 Nucleation layer 104 Buffer Layer 106 channel layer 108 Barrier layer 110 First Dielectric Layer 112 Second Dielectric Layer D Drain G Gate M Active Area PG Gate Metal Field Plate PS Source Metal Field Plate S Sauce S100~S114 Step

Claims

1. A substrate which is an n+-doped silicon carbide substrate, an n-doped silicon carbide substrate, or a p-doped silicon carbide substrate, A buffer layer provided above the substrate, containing doped gallium nitride and having a breakdown electric field of 80 V / μm or more, An active region provided above the buffer layer, comprising a channel layer containing undoped or intentionally undoped gallium nitride, and a barrier layer provided above the channel layer, containing undoped or intentionally undoped aluminum gallium nitride, The system includes a source, a gate, and a drain located above the active region, wherein the gate is located between the source and the drain. Semiconductor equipment.

2. The semiconductor device according to claim 1, wherein the thickness of the buffer layer is 1 μm or more.

3. The semiconductor device according to claim 2, wherein the thickness of the buffer layer is 1 to 15 μm.

4. The semiconductor device according to claim 1, further comprising a nucleating layer provided between the substrate and the buffer layer, wherein the nucleating layer comprises undoped or unintentionally undoped aluminum nitride.

5. The semiconductor device according to claim 4, wherein the thickness of the nucleation layer is less than 100 nm.

6. A first dielectric layer covering a portion of the active region, A gate metal field plate covering the gate and a portion of the first dielectric layer, The gate metal field plate and a second dielectric layer covering a portion of the first dielectric layer, The source further includes a part of the source and a source metal field plate covering the second dielectric layer, The semiconductor device according to claim 1.

7. The semiconductor device according to claim 6, wherein the material of the first dielectric layer and the second dielectric layer is a nitride or an oxide.

8. The semiconductor device according to claim 1, wherein the substrate is a 4H-SiC substrate.

9. The semiconductor device according to claim 1, wherein the active region further includes a surface layer (Cap layer) provided above the barrier layer, and the thickness of the surface layer is 1.5 to 2.0 nm.

10. (a) A step of preparing a substrate which is an n+-doped silicon carbide substrate, an n-doped silicon carbide substrate, or a p-doped silicon carbide substrate, (b) A step of forming a buffer layer on the substrate containing doped gallium nitride and having a breakdown field of 80 V / μm or more, (c) A step of forming an active region above the buffer layer, comprising forming a channel layer and then forming a barrier layer above the channel layer, wherein the channel layer comprises undoped or unintentionally doped gallium nitride and the barrier layer comprises undoped or unintentionally doped aluminum gallium nitride, (d) A step of forming a source, gate and drain above the active region, wherein the gate is located between the source and the drain, A method for manufacturing a semiconductor device.

11. The manufacturing method according to claim 10, wherein the thickness of the buffer layer is 1 μm or more.

12. The manufacturing method according to claim 10, wherein the thickness of the buffer layer is 1 to 15 μm.

13. The manufacturing method according to claim 10, further comprising step (a-1) between step (a) and step (b) of forming a nucleation layer on the substrate that is not doped or intentionally not doped aluminum nitride.

14. The manufacturing method according to claim 13, wherein the thickness of the nucleation layer is less than 100 nm.

15. (e) The step of forming a first dielectric layer above the active region so as to cover a part of the active region, (f) A step of forming a gate metal field plate so as to cover the gate and a part of the first dielectric layer, (g) The step of forming a second dielectric layer so as to cover the gate metal field plate and a portion of the first dielectric layer, (h) The step of forming a source metal field plate so as to cover a portion of the source and the second dielectric layer, The manufacturing method according to claim 10.

16. The manufacturing method according to claim 15, wherein the material of the first dielectric layer and the second dielectric layer is a nitride or an oxide.

17. The manufacturing method according to claim 10, wherein the substrate is a 4H-SiC substrate.

18. The manufacturing method according to claim 10, wherein step (c) further comprises forming a surface layer above the barrier layer, the thickness of the surface layer being 1.5 to 2.0 nm.

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