Image sensor

Abstract

The present invention provides an image sensor that accurately detects signals based on charge transferred to a floating diffusion. [Solution] In the image sensor, the readout unit 30 of the pixel 10 includes a photoelectric conversion unit 12 that converts light into electric charge, a storage unit 19 that stores the electric charge converted by the photoelectric conversion unit, a discharge unit 14 that discharges the charge from the storage unit and has a transistor M4 to which a first control signal output based on the amount of charge in the storage unit is applied, and a control unit that, when the charge from the storage unit is being discharged by the discharge unit, raises the potential of the charge transfer path that electrically connects the photoelectric conversion unit and the storage unit to a higher level than the potential of the storage unit.

Description

Technical Field

[0001] The present invention relates to an imaging device.

Background Art

[0002] An imaging device such as a CMOS sensor that outputs a signal based on the charge transferred from a photoelectric conversion unit such as a photodiode to a floating diffusion is known. Conventionally, it has been required to accurately detect a signal based on the charge transferred to the floating diffusion.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

[0004] An imaging device according to a first aspect of the invention includes a first photoelectric conversion unit that converts light into charge, an accumulation unit that accumulates the charge converted by the first photoelectric conversion unit, a first transistor to which a first control signal output based on the charge amount of the accumulation unit is applied, a discharge unit that discharges the charge of the accumulation unit, and a control unit that raises the potential of a charge transfer path that electrically connects the first photoelectric conversion unit and the accumulation unit higher than the potential of the accumulation unit when the charge of the accumulation unit is being discharged by the discharge unit.

Brief Description of the Drawings

[0005] [Figure 1] It is a block diagram illustrating the configuration of an imaging device according to an embodiment. [Figure 2] It is a diagram illustrating a cross-sectional structure of an imaging device. [Figure 3] It is a circuit diagram illustrating the configuration of a pixel of an imaging device. [Figure 4] FIGS. 4(a) to 4(d) are schematic diagrams for explaining the potential of a charge transfer path in a pixel. [Figure 5] Figures 5(a) and 5(b) are schematic diagrams illustrating the potential of the charge transfer path in a pixel. [Figure 6] This is a circuit diagram illustrating the configuration of an A / D conversion circuit. [Figure 7] This figure illustrates a timing chart showing the main signal waveforms in the state shown in Figure 4(d). [Modes for carrying out the invention]

[0006] The following describes embodiments for carrying out the invention with reference to the drawings. <Configuration of the imaging device> Figure 1 is a block diagram illustrating the configuration of an imaging device equipped with an image sensor according to an embodiment. The imaging device 1 comprises an imaging optical system 2, an image sensor 3, and a control unit 4. The imaging device 1 is, for example, a camera. The imaging optical system 2 forms an image of a subject on the image sensor 3. The image sensor 3 captures the image of the subject formed by the imaging optical system 2 and generates an image signal. The image sensor 3 is, for example, a CMOS image sensor. The control unit 4 outputs control signals to the image sensor 3 to control its operation. The control unit 4 also functions as an image generation unit that performs various image processing on the image signal output from the image sensor 3 to generate image data. The imaging optical system 2 may be configured to be detachable from the imaging device 1.

[0007] <Cross-sectional structure of the image sensor> Figure 2 is a diagram illustrating the cross-sectional structure of the image sensor 3 shown in Figure 1. The image sensor 3 shown in Figure 2 is a back-illuminated image sensor. The image sensor 3 comprises a first substrate 111, a second substrate 112, a third substrate 113, and a fourth substrate 114. The first substrate 111, second substrate 112, third substrate 113, and fourth substrate 114 are each made of a semiconductor substrate or the like. The first substrate 111 is laminated onto the second substrate 112 via wiring layers 140 and 141. The second substrate 112 is laminated onto the third substrate 113 via wiring layers 142 and 143. The third substrate 113 is laminated onto the fourth substrate 114 via wiring layers 144 and 145.

[0008] The incident light L, indicated by the white arrow, is incident in the positive Z-axis direction. Also, as shown in the coordinate axes, the direction to the right of the paper perpendicular to the Z-axis is the positive X-axis direction, and the direction towards the front of the paper perpendicular to both the Z-axis and X-axis is the positive Y-axis direction. The image sensor 3 has the first substrate 111, the second substrate 112, the third substrate 113, and the fourth substrate 114 stacked in the direction from which the incident light L is incident.

[0009] The image sensor 3 further includes a microlens layer 101, a color filter layer 102, and a passivation layer 103. These passivation layer 103, color filter layer 102, and microlens layer 101 are sequentially stacked on the first substrate 111. The microlens layer 101 has multiple microlenses ML. The microlenses ML focus the incident light onto the photoelectric conversion unit 12, which will be described later. The color filter layer 102 has multiple color filters F. The passivation layer 103 is composed of a nitride film and an oxide film.

[0010] The first substrate 111, the second substrate 112, the third substrate 113, and the fourth substrate 114 each have a first surface 105a, 106a, 107a, and 108a on which gate electrodes and gate insulating films are provided, and a second surface 105b, 106b, 107b, and 108b that is different from the first surface. Various elements such as transistors are provided on the first surface 105a, 106a, 107a, and 108a, respectively. Wiring layers 140, 141, 144, and 145 are laminated on the first surface 105a of the first substrate 111, the first surface 106a of the second substrate 112, the first surface 107a of the third substrate 113, and the first surface 108a of the fourth substrate 114, respectively. Furthermore, wiring layers (inter-substrate connection layers) 142 and 143 are laminated on the second surface 106b of the second substrate 112 and the second surface 107b of the third substrate 113, respectively. Wiring layers 140 to 145 are layers containing a conductive film (metal film) and an insulating film, and each has multiple wirings and vias arranged on it.

[0011] The elements on the first surface 105a of the first substrate 111 and the elements on the first surface 106a of the second substrate 112 are electrically connected via wiring layers 140 and 141 by connection parts 109 such as bumps and electrodes. Similarly, the elements on the first surface 107a of the third substrate 113 and the elements on the first surface 108a of the fourth substrate 114 are electrically connected via wiring layers 144 and 145 by connection parts 109 such as bumps and electrodes. In addition, the second substrate 112 and the third substrate 113 have multiple through electrodes 110. The through electrodes 110 of the second substrate 112 connect the circuits provided on the first surface 106a and the second surface 106b of the second substrate 112 to each other, and the through electrodes 110 of the third substrate 113 connect the circuits provided on the first surface 107a and the second surface 107b of the third substrate 113 to each other. The circuits provided on the second surface 106b of the second substrate 112 and the circuits provided on the second surface 107b of the third substrate 113 are electrically connected via inter-substrate connecting layers 142 and 143 by connection parts 109 such as bumps and electrodes. In this embodiment, the example shows a case where the first substrate 111, the second substrate 112, the third substrate 113, and the fourth substrate 114 are stacked, but the number of stacked substrates may be more or less than that in this embodiment. Furthermore, the first substrate 111, the second substrate 112, the third substrate 113, and the fourth substrate 114 may be referred to as the first layer, the second layer, the third layer, and the fourth layer, respectively.

[0012] <Pixel configuration> Figure 3 is a circuit diagram illustrating the configuration of pixels in the image sensor 3. Each pixel 10 includes, for example, a photoelectric conversion unit 12 such as a photodiode (PD), and a readout unit 30 that reads out a signal based on the charge generated by the photoelectric conversion unit 12. Pixel 10 is configured in the first layer. The reading unit 30 may be configured in one of the second, third, and fourth layers, or it may be configured in multiple layers from the first to fourth layers.

[0013] The photoelectric conversion unit 12 has the function of converting incident light into electric charge and accumulating the photoelectrically converted charge. The reading unit 30 includes a transfer unit 13, an output unit 14, a first floating diffusion (FD1) 15, a second floating diffusion (FD2) 19, a control switch unit 20, an amplification unit 16, and a current source 17.

[0014] The transfer unit 13 is controlled by the signal φTX. The signal φTX is generated, for example, by a pixel control unit (not shown). The charge photoelectrically converted in the photoelectric conversion unit 12 is transferred to the second floating diffusion 19 or the first floating diffusion 15 via the transfer unit 13. The transfer unit 13 forms a charge transfer path between the photoelectric conversion unit 12 and the second floating diffusion 19 and the first floating diffusion 15. Furthermore, the transfer unit 13 is configured to allow the excess charge from the photoelectric conversion unit 12 to pass through even when it is turned off by the signal φTX.

[0015] The control switch unit 20 is controlled by the signal φOF. The signal φOF is generated based on, for example, the output signal φOF- from the second control circuit 210 which will be described later with reference to FIG. 6. The control switch unit 20 switches between holding the charge from the photoelectric conversion unit 12 in the first floating diffusion 15 or not holding the charge from the photoelectric conversion unit 12 in the first floating diffusion 15. In the embodiment, holding the charge in the first floating diffusion 15 corresponds to not sending the charge to the second floating diffusion 19, and not holding the charge from the photoelectric conversion unit 12 in the first floating diffusion 15 corresponds to sending the charge to the second floating diffusion 19 via the control switch unit 20.

[0016] The second floating diffusion 19 holds (accumulates) the charge sent from the photoelectric conversion unit 12 in a state where the discharge unit 14 which will be described later is turned off by the signal φRES. The first floating diffusion 15 temporarily holds (accumulates) the excessive charge from the photoelectric conversion unit 12 in a state where the control switch unit 20 is turned off by the signal φOF. The amplification unit 16 amplifies the signal due to the charge accumulated in the second floating diffusion 19 and outputs it to the signal line 18. In the example shown in FIG. 3, the amplification unit 16 is composed of a transistor M3 whose drain terminal, gate terminal, and source terminal are connected to the power supply VDD, the second floating diffusion 19, and the current source 17 respectively.

[0017] The discharge unit (reset unit) 14 is controlled by the signal φRES. The signal φRES is generated, for example, in the second control circuit 210 which will be described later with reference to FIG. 6. The discharge unit 14 discharges the charge accumulated in the second floating diffusion 19 and resets the potential of the second floating diffusion 19 to the potential of the power supply VDD (referred to as the reset potential). Also, if necessary, the control switch unit 20 is also used in combination, and as will be described later with reference to FIG. 4(a), the charge of the first floating diffusion 15 is also discharged. The transfer unit 13, the control switch unit 20, and the discharge unit 14 are each composed of a transistor M1, a transistor M4, and a transistor M2. With the reading unit 30 described above, a signal (photoelectric conversion signal) corresponding to the charge generated in the photoelectric conversion unit 12 is sent to an A / D conversion circuit, which will be described later, via the signal line 18.

[0018] <Potential diagram of charge transfer path> The potential of the charge transfer path in the pixel 10 will be described with reference to FIGS. 4(a) to 4(d), FIGS. 5(a) and 5(b). In the embodiment, the potential is represented based on the reset potential. FIGS. 4(a) to 4(d), FIGS. 5(a) and 5(b) are schematic diagrams for explaining the potential of the charge transfer path in the pixel 10. These figures show the high and low of the potential of the charge transfer path along the dashed line A - B in FIG. 3. The horizontal axis represents the charge transfer path from position A to position B, and the vertical axis represents the high and low of the potential. In the embodiment, the potential of the photoelectric conversion unit 12 is the highest (in other words, the depletion potential of the photoelectric conversion unit 12 is the lowest), and the potential of the second floating diffusion 19 at the time of reset is the lowest (in other words, the reset potential is the highest).

[0019] Also, as will be described later with reference to FIG. 4(d), the potential of the first floating diffusion 15 is lower than that of the photoelectric conversion unit 12 (in other words, the potential of the first floating diffusion 15 is higher than the depletion potential of the photoelectric conversion unit), and becomes higher than the potential of the second floating diffusion 19 immediately before reset (in other words, the potential of the first floating diffusion 15 is lower than the potential of the second floating diffusion 19 immediately before reset). Such potential levels can be set, for example, by changing the concentration of impurity ions injected into the semiconductor substrates constituting the photoelectric conversion unit 12, the second floating diffusion 19, and the first floating diffusion 15.

[0020] Figure 4(a) shows the state in which, in addition to resetting the second floating diffusion 19, charge is also discharged from the photoelectric conversion unit 12 and the first floating diffusion 15. The above signals φTX, φOF, and φRES turn on transistors M1, M4, and M2 of each pixel. The charge accumulated in the photoelectric conversion unit 12 and the first floating diffusion 15 moves to the second floating diffusion 19, which has the lowest potential. Additionally, the reset operation discharges the charge from the second floating diffusion 19, resetting its potential to the reset potential.

[0021] Figure 4(b) shows the state when exposure to the photoelectric conversion unit 12 has started, in other words, the state when the accumulation of charge generated by photoelectric conversion has started. The signals φTX, φOF, and φRES above turn off, on, and off the transistors M1, M4, and M2 of each pixel, respectively.

[0022] Figure 4(c) shows a state where the charge accumulated in the photoelectric conversion unit 12 exceeds the storage capacity of the photoelectric conversion unit 12 and overflows. Transistors M1, M4, and M2 are switched off, on, and off, respectively, as in Figure 4(b). The charge that overflows from the photoelectric conversion unit 12 to the first floating diffusion 15 moves via transistor M4 to the second floating diffusion 19, which has a lower potential than the first floating diffusion 15, and is accumulated there. As a result, the potential of the second floating diffusion 19 begins to decrease.

[0023] Figure 4(d) shows the state where the amount of charge accumulated in the second floating diffusion 19 has reached a predetermined amount, and the potential of the second floating diffusion 19 has dropped to the threshold potential. Transistors M1, M4, and M2 are switched off, on, and off, respectively, as in Figures 4(b) and 4(c). When the potential of the second floating diffusion 19 drops to the threshold potential, this change in potential is amplified by transistor M3 and read out as a pixel signal. The second control circuit 210, described later, generates a signal φRES to reset the second floating diffusion 19 based on the signal level of the read-out pixel signal. Therefore, the threshold potential corresponds to the potential of the second floating diffusion 19 immediately before the reset.

[0024] Figure 5(a) shows the state in which the second floating diffusion 19 is reset while retaining the charge of the photoelectric conversion unit 12 and the first floating diffusion 15. The signals φTX, φOF, and φRES above turn off, off, and on the transistors M1, M4, and M2 of each pixel, respectively. In Figure 4(d), the charge held in the second floating diffusion 19 is discharged through transistor M2, and the potential of the second floating diffusion 19 is reset to the reset potential.

[0025] The charge flowing into the first floating diffusion 15 during the reset of the second floating diffusion 19 is held in the first floating diffusion 15 because transistor M4 is turned off. That is, it is temporarily accumulated in the first floating diffusion 15.

[0026] Figure 5(b) shows the state in which charge accumulation has resumed in the second floating diffusion 19 after the reset. The signals φTX, φOF, and φRES above turn the transistors M1, M4, and M2 of each pixel off, on, and off, respectively. The charge that was accumulated in the first floating diffusion 15 in Figure 5(a) moves to the second floating diffusion 19, which has a lower potential than the first floating diffusion 15, via transistor M4 and is accumulated there. In other words, the charge that moved from the photoelectric conversion unit 12 to the first floating diffusion 15 and accumulated there during the reset operation of the second floating diffusion 19 is accumulated in the second floating diffusion 19 without disappearing. From the state shown in Figure 5(b) onward, the on / off states of transistors M1, M4, and M2 of each pixel are controlled to repeat the states shown in Figures 4(c), 4(d), 5(a), and 5(b) until the exposure time set in the imaging device 1 is completed.

[0027] In this embodiment, during the exposure time set in the imaging device 1, a predetermined amount of charge is accumulated in the second floating diffusion 19, and the second floating diffusion 19 is repeatedly reset. Therefore, the amount of charge generated per pixel during the exposure time can be expressed as the product of the amount of charge when the threshold potential is reached (as explained with reference to Figure 4(d)) and the number of times the second floating diffusion 19 is reset. This method of determining the amount of charge using A / D conversion is called pulse counting A / D conversion because it generates a pulse signal each time the potential of the second floating diffusion 19 reaches the threshold potential, and the number of generated pulse signals is counted. An example circuit for counting the number of resets of the second floating diffusion 19 per pixel will be explained with reference to Figure 6.

[0028] ​Figure 6 is a circuit diagram illustrating the configuration of the A / D conversion circuit 250 according to the embodiment. As described above, the signal based on the charge held in the second floating diffusion 19 is amplified by the amplification unit 16 and read out as a pixel signal via the signal line 18. The pixel signal is input to terminal 41 of the comparator 40, which acts as a comparison unit. The first control circuit 200 generates a reference signal of a predetermined voltage level based, for example, on instructions from a pixel control unit (not shown). The reference signal corresponds to the voltage level of the pixel signal generated when the potential of the second floating diffusion 19 has dropped to a threshold potential, as described with reference to Figure 4(d). The reference signal generated by the first control circuit 200 is input to terminal 42 of the comparator 40.

[0029] The comparator 40 compares the pixel signal from the pixel 10 with the reference signal, and when the level of the pixel signal from the pixel 10 is approximately equal to the level of the reference signal, it causes the potential of the output signal 40_Out to change. In this embodiment, when the potential of the second floating diffusion 19 drops to a threshold potential (as shown in Figure 4(d)), the output signal 40_Out of the comparator 40 is configured to invert from a high level to a low level. The output signal 40_Out is input to the inverter circuit 44.

[0030] The inverter circuit 44 has multiple inverters connected to it, and the outputs are sequentially inverted and transmitted. By connecting multiple inverters in stages, the output signal of the inverter circuit 44 is inverted to a low level at a delayed timing compared to the output signal 40_Out of the comparator 40. Including such a delay circuit can stabilize the circuit operation. Note that the number of inverter stages can be changed as appropriate.

[0031] The output signal of the inverter circuit 44 is input to the second control circuit 210. Based on the fact that the output signal of the inverter circuit 44 has been inverted from a high level to a low level, the second control circuit 210 generates a pulsed count signal 210_Out, a signal φRES, and a signal φOF-, respectively.

[0032] The count signal 210_Out is supplied to the counter circuit 220. The counter circuit 220 counts the number of count signals 210_Out that are input to it, in other words, the number of resets of the second floating diffusion 19 per pixel.

[0033] The signal φRES is a signal that controls the transistor M2 that constitutes the output unit 14, and is supplied to the output unit 14. The second control circuit 210 generates a signal φRES with a wider pulse half-width than the count signal 210_Out, based on instructions from, for example, a pixel control unit (not shown), and outputs the signal φRES at a timing delayed compared to the signal φOF- described later. The pulse half-width of the signal φRES is, for example, 50 nsec or less.

[0034] The signal φOF- is the source signal for the signal φOF that controls the transistor M4 constituting the control switch unit 20. In this embodiment, the signal obtained by inverting the logic level of the signal φOF- using the inverter circuit 46 is called the signal φOF. The second control circuit 210 generates a φOF- with a pulse half-width wider than that of the count signal 210_Out, for example, based on instructions from a pixel control unit (not shown). The pulse half-width of the signal φOF- is, for example, 60 nsec.

[0035] The count value of the counter circuit 220 is output to the data bus 300 via the selector circuit 230. The counter circuit 220 is reset after the count value is read out when the exposure time set on the imaging device 1 is completed. In other words, the counter circuit 220 counts the number of count signals 210_Out input after the exposure time has started, and the count value is reset when the exposure time is completed.

[0036] <Explanation of the timing chart> Figure 7 is a timing chart illustrating the main signal waveforms in the state where the potential of the second floating diffusion 19 drops to the threshold potential, as explained with reference to Figure 4(d). From top to bottom, the waveforms are shown for signal φOF, signal Sig_FD2 indicating the potential of the second floating diffusion 19, the output signal 40_Out of the comparator 40, the count signal 210_Out, and signal φRES.

[0037] If time t1 is defined as the time when the potential of the second floating diffusion 19 drops to the threshold potential, the comparator 40 inverts the output signal 40_Out from a high level to a low level. Based on the fact that the input signal has been inverted from a high level to a low level, the second control circuit 210 outputs a pulsed count signal 210_Out, as well as a signal φOF- with a wider pulse half-width. The signal φOF shown in Figure 7 is the signal obtained by inverting the logic level of the signal φOF- using the inverter circuit 46. The second control circuit 210 further outputs a signal φRES with a narrower pulse half-width than the signal φOF- at time t2, which is a predetermined time (e.g., 5 nsec) later than time t1.

[0038] With this configuration, the signal φRES is output after the signal φOF, which is the source of the signal φOF-, is output. Therefore, as illustrated in Figure 5(a), the transistor M4 constituting the control switch section 20 can be turned off, and then the transistor M2 constituting the discharge section 14 can be turned on to start the reset operation of the second floating diffusion 19. When the reset operation of the second floating diffusion 19 begins, the level of the signal Sig_FD2, which indicates the potential of the second floating diffusion 19, rises and is reset to the reset potential.

[0039] At time t3, the reset operation of the second floating diffusion 19 based on the signal φRES is completed. At time t3, the transistor M4 constituting the switch unit 20 is turned off by the control signal φOF. After the reset operation is completed, the transistor M4 constituting the switch unit 20 is turned on by the control signal φOF, and charge accumulation for the second floating diffusion 19 is resumed. With this configuration, the charge flowing into the first floating diffusion 15 during the reset operation of the second floating diffusion 19 is held in the first floating diffusion 15 because transistor M4 is turned off (Figure 5(a)). In other words, discharge due to the reset operation can be avoided. Furthermore, the charge accumulated in the first floating diffusion 15 during the reset operation will move to the second floating diffusion 19 when charge accumulation in the second floating diffusion 19 resumes (Figure 5(b)).

[0040] According to the embodiment described above, the following effects can be obtained: (1) The image sensor 3 mounted on the imaging device 1 includes a first floating diffusion 15 having a first potential to which photoelectrically converted charge is transferred, a second floating diffusion 19 having a second potential lower than the first potential, a control switch unit 20 that controls the connection between the first floating diffusion 15 and the second floating diffusion 19, an A / D conversion circuit 250 that generates a control signal according to the amount of charge accumulated in the second floating diffusion 19, and an discharge unit 14 that resets the potential of the second floating diffusion 19. With this configuration, it becomes possible to detect a signal based on the charge generated during the reset operation of the second floating diffusion 19. For example, during the reset of the second floating diffusion 19, the control switch unit 20 controls the system to prevent charge from moving from the first floating diffusion 15 to the second floating diffusion 19, thereby preventing the charge that has moved from the first floating diffusion 15 to the second floating diffusion 19 from being discharged by the discharge unit 14 without being detected. Furthermore, after the reset of the second floating diffusion 19 is complete, the control switch unit 20 controls the movement of charge from the first floating diffusion 15 to the second floating diffusion 19. This allows the charge temporarily held in the first floating diffusion 15 to be moved to the second floating diffusion 19, making it possible to detect a signal based on the moved charge.

[0041] (2) The control switch unit 20 prevents the transfer of charge from the first floating diffusion 15 to the second floating diffusion 19 based on the signal φOF as a control signal. With this configuration, the A / D conversion circuit 250 generates a signal φOF at the appropriate timing based on the amount of charge accumulated in the second floating diffusion 19. As a result, the control switch unit 20 can block the transfer of charge from the first floating diffusion 15 to the second floating diffusion 19 at the appropriate timing.

[0042] (3) The discharge unit 14, acting as a reset unit, resets the potential of the second floating diffusion 19 while the transfer of charge from the first floating diffusion 15 to the second floating diffusion 19 is prevented by the control switch unit 20. With this configuration, it is possible to effectively prevent the charge that has moved from the first floating diffusion 15 to the second floating diffusion 19 from being discharged without being detected.

[0043] (4) The control switch unit 20 controls the potential between the first floating diffusion 15 and the second floating diffusion 19 (transistor M4) to be higher than the first potential, thereby preventing the transfer of charge from the first floating diffusion 15 to the second floating diffusion 19. With this configuration, it is possible to effectively prevent the transfer of charge from the first floating diffusion 15 to the second floating diffusion 19.

[0044] (5) The control switch unit 20 controls the potential between the first floating diffusion 15 and the second floating diffusion 19 (transistor M4) to be lower than the first potential, thereby transferring charge from the first floating diffusion 15 to the second floating diffusion 19. With this configuration, it is possible to appropriately transfer the charge from the first floating diffusion 15 to the second floating diffusion 19.

[0045] (6) The first potential is higher than the third potential, which corresponds to the threshold potential of the second floating diffusion 19 immediately before it is reset by the discharge unit 14. With this configuration, charge can be appropriately transferred from the first floating diffusion 15 to the second floating diffusion 19 until the potential of the second floating diffusion 19 drops to the threshold potential.

[0046] (7) The image sensor 3 further has a photoelectric conversion unit 12 that converts light into electric charge, and the first potential is lower than the fourth potential which corresponds to the depletion potential of the photoelectric conversion unit 12. With this configuration, the charge can be appropriately transferred from the photoelectric conversion unit 12 to the first floating diffusion 15.

[0047] (8) During the set exposure time, the image sensor 3 repeatedly accumulates charge through the second floating diffusion 19 and resets the potential of the second floating diffusion 19 through the discharge unit 14. With this configuration, the accumulation and reset of charge in pulse-count type A / D conversion can be appropriately repeated.

[0048] (Modification 1) In the above-described embodiment, an example was given in which the image sensor 3 is a back-illuminated type. Alternatively, the image sensor 3 may be configured as a front-illuminated type with the wiring layer 140 on the incident surface side into which light enters.

[0049] (Modification 2) In the above-described embodiment, an example was given in which a photodiode is used as the photoelectric conversion unit 12. However, a photoelectric conversion film may also be used as the photoelectric conversion unit 12.

[0050] (Modification 3) The image sensor 3 may be used in cameras, smartphones, tablets, cameras built into PCs, in-vehicle cameras, etc.

[0051] (Modification 4) In the description of the embodiment, an example of A / D conversion using a pulse counting method was described. In Modification 4 of the embodiment, the pulse counting method may be used in combination with another A / D conversion method different from the pulse counting method. The other A / D conversion method can be, for example, a single-slope A / D conversion method. The single-slope method compares the pixel signal from pixel 10 with a reference signal called a ramp signal using a comparator circuit. The level of the ramp signal is changed in synchronization with the clock signal of the counter for the single-slope method, and is correlated with the count value of the counter for the single-slope method. The comparator 40 compares the pixel signal from pixel 10 with the ramp signal, and when the level of the pixel signal from pixel 10 approximately matches the level of the ramp signal, it shifts the potential of the output signal. In the single-slope method, the level of the pixel signal is detected based on the count value of the counter for the single-slope method at the point when the levels of the pixel signal and the ramp signal match.

[0052] Although various embodiments and modifications have been described above, the present invention is not limited to these. Combinations of the configurations shown in the embodiments and modifications are also included within the scope of the present invention. Other embodiments conceivable within the technical concept of the present invention are also included within the scope of the present invention. [Explanation of symbols]

[0053] 1…Imaging device, 3…Image sensor, 4…Control unit, 10…Pixel, 12…Photoelectric conversion unit, 13…Transfer unit, 14…Ejection unit, 15…First floating diffusion, 16…Amplification unit, 18…Signal line, 19…Second floating diffusion, 20…Control switch unit, M1, M2, M4…Transistors, 40…Comparator, 44, 46…Inverter circuit, 200…First control circuit, 210…Second control circuit, 220…Counter circuit, 250…A / D conversion circuit

Claims

[Claim 1] A first photoelectric conversion unit that converts light into electric charge, A storage unit for storing the charge converted by the first photoelectric conversion unit, A discharge unit has a first transistor to which a first control signal output based on the amount of charge in the storage unit is applied, and a discharge unit that discharges the charge from the storage unit, When the charge of the storage unit is being discharged by the discharge unit, a control unit raises the potential of the charge transfer path electrically connecting the first photoelectric conversion unit and the storage unit to be higher than the potential of the storage unit. An image sensor equipped with the following features.

Images