Image sensor and imaging device
The stacked semiconductor structure in the imaging device addresses power consumption issues by optimizing signal processing through overlapping pixel and processing circuit arrangements, achieving reduced power consumption and efficient parallel operations.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- NIKON CORP
- Filing Date
- 2026-01-15
- Publication Date
- 2026-04-10
AI Technical Summary
Conventional imaging devices face issues with increased power consumption due to the design of signal output lines for each pixel, which is a challenge in existing imaging technologies.
The imaging device employs a stacked semiconductor structure with multiple photoelectric conversion units and processing blocks, including junctions between substrates to optimize signal processing and reduce power consumption by overlapping pixel and processing circuit arrangements.
This configuration reduces power consumption by allowing for efficient parallel processing and overlapping operations, thereby minimizing the need for multiple signal outputs and enhancing power efficiency.
Smart Images
Figure 2026063198000001_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to an imaging device and an imaging apparatus.
Background Art
[0002] An imaging device having signal output lines for each cell formed by combining a plurality of pixels is known (for example, Patent Document 1). Conventionally, an increase in power consumption has been a problem. [Patent Document] Patent Document 1: JP-A-2006-49361
Summary of the Invention
[0003] In a first embodiment of the present invention, an image sensor comprises a first semiconductor section having a pixel section that includes a first pixel block in which a first photoelectric conversion unit for converting light into electric charge and a second photoelectric conversion unit for converting light into electric charge are arranged, and a second pixel block in which a third photoelectric conversion unit for converting light into electric charge and a fourth photoelectric conversion unit for converting light into electric charge are arranged; a semiconductor section stacked together with the first semiconductor section, comprising a first conversion unit for converting a first signal based on the electric charge converted by the first photoelectric conversion unit into a digital signal, a second conversion unit for converting a second signal based on the electric charge converted by the second photoelectric conversion unit into a digital signal, a first processing block including a first correction processing unit for correcting the first digital signal converted from the first signal into a digital signal by the first conversion unit and a second correction processing unit for correcting the second digital signal converted from the second signal into a digital signal by the second conversion unit; a third conversion unit for converting a third signal based on the electric charge converted by the third photoelectric conversion unit into a digital signal, and a fourth photoelectric conversion unit for converting The semiconductor device includes a second semiconductor unit having a processing circuit unit that includes a second processing block which includes a fourth conversion unit that converts a fourth signal based on converted charge into a digital signal, a third correction process that corrects the third digital signal converted from the third signal to a digital signal by the third conversion unit, and a second correction processing unit that corrects the fourth digital signal converted from the fourth signal to a digital signal by the fourth conversion unit. The semiconductor device also includes a first junction that joins the first semiconductor unit and the second semiconductor unit and outputs a first signal, a second junction that joins the first semiconductor unit and the second semiconductor unit and outputs a second signal, a third junction that joins the first semiconductor unit and the second semiconductor unit and outputs a third signal, and a fourth junction that joins the first semiconductor unit and the second semiconductor unit and outputs a fourth signal, wherein the first junction, the second junction, the third junction and the fourth junction are arranged between the pixel unit and the processing circuit unit in the stacking direction in which the first semiconductor unit and the second semiconductor unit are stacked.
[0004] In a second embodiment of the present invention, the imaging device comprises the image sensor described above.
[0005] It should be noted that the above summary of the invention does not enumerate all of its features. Furthermore, subcombinations of these features may also constitute an invention. [Brief explanation of the drawing]
[0006] [Figure 1] This diagram shows an overview of the image sensor 400 according to this embodiment. [Figure 2] An example of the specific configuration of the pixel section 110 is shown. [Figure 3] An example of the circuit configuration for pixel 112 is shown. [Figure 4] A more specific example of the configuration of the processing circuit section 210 is shown below. [Figure 5] This is a schematic diagram illustrating the ADC 42, memory unit 44, and signal output unit 50 of the processing block 220. [Figure 6] This chart shows the timing of processing in processing block 220. [Figure 7] This is a schematic diagram illustrating the other processing block 222. [Figure 8] This chart shows the timing of processing in processing block 222. [Figure 9] This is a block diagram showing an example configuration of the imaging device 500 according to the embodiment. [Modes for carrying out the invention]
[0007] The present invention will be described below through embodiments, but these embodiments are not intended to limit the scope of the claims. Furthermore, not all combinations of features described in the embodiments are necessarily essential to the solution of the invention.
[0008] In this specification, the X and Y axes are orthogonal to each other, and the Z axis is orthogonal to the XY plane. The XYZ axes form a right-handed system. The direction parallel to the Z axis may be referred to as the stacking direction of the image sensor 400. In this specification, the terms "up" and "down" are not limited to the up and down directions in the direction of gravity. These terms merely refer to relative directions in the Z axis direction. In this specification, the arrangement in the X axis direction is described as a "row," and the arrangement in the Y axis direction is described as a "column," but the matrix direction is not limited to these. Also, the Z axis direction is the optical axis direction from which light from the subject is incident.
[0009] Figure 1 is a diagram illustrating the overview of the image sensor 400 according to this embodiment. The image sensor 400 captures an image of a subject. The image sensor 400 generates image data of the captured subject. The image sensor 400 comprises a first substrate 100 and a second substrate 200. As shown in Figure 1, the first substrate 100 is stacked on the second substrate 200.
[0010] The first substrate 100 has a pixel section 110. The pixel section 110 outputs a pixel signal based on incident light. The first substrate 100 is sometimes referred to as a pixel chip.
[0011] The second substrate 200 has a processing circuit section 210 and a peripheral circuit section 230. The second substrate 200 is sometimes referred to as a signal processing chip.
[0012] The processing circuit 210 receives the pixel signal output from the first substrate 100. The processing circuit 210 processes the input pixel signal. For example, the processing circuit 210 performs a process to convert an analog signal into a digital signal. Specifically, the processing circuit 210 performs a process to convert the input pixel signal into a digital signal. The processing circuit 210 may also perform other signal processing.
[0013] In this example, the processing circuit unit 210 is positioned on the second substrate 200 opposite the pixel unit 110. That is, the processing circuit unit 210 is positioned so as to partially overlap the pixel unit 110 in the optical axis direction. The processing circuit unit 210 may output control signals to the pixel unit 110 to control the driving of the pixel unit 110.
[0014] The peripheral circuit section 230 controls the driving of the processing circuit section 210. The peripheral circuit section 230 is located around the processing circuit section 210 on the second substrate 200. The peripheral circuit section 230 may also be electrically connected to the first substrate 100 and control the driving of the pixel section 110.
[0015] The image sensor 400 may have a third substrate stacked on the second substrate 200, in addition to the first substrate 100 and the second substrate 200. For example, the third substrate is a memory chip that performs image processing according to the signal output by the second substrate 200. Furthermore, the structure of the image sensor 400 may be back-illuminated or front-illuminated. The following explanation will use a back-illuminated example.
[0016] Figure 2 shows an example of the specific configuration of the pixel section 110. In this example, the pixel section 110 and an enlarged view of the pixel block 120 provided in the pixel section 110 are shown.
[0017] The pixel section 110 has a plurality of pixel blocks 120 arranged in a row and column direction. In this example, the pixel section 110 has M × N pixels (where M and N are natural numbers) of pixel blocks 120. In this example, the case where M is equal to N is illustrated, but M and N may be different.
[0018] The pixel block 120 has at least one pixel 112. The pixel block 120 in this example has m×n pixels 112 (m and n are natural numbers). For example, the pixel block 120 has 16×16 pixels 112. The number of pixels 112 corresponding to the pixel block 120 is not limited to this. In this example, the case where m is equal to n is illustrated, but m may be different from n. The pixel block 120 has a plurality of pixels 112 connected to a common control line in the row direction. For example, each pixel 112 of the pixel block 120 is connected to a common control line so as to be set to the same exposure time. In one example, n pixels 112 arranged in the row direction are connected by a common control line.
[0019] On the other hand, among the plurality of pixel blocks 120, different exposure times may be set for each. That is, each pixel 112 of the pixel block 120 has the same exposure time, but different exposure times may be set for other pixel blocks 120. For example, when the pixels 112 of the pixel block 120 are connected by a common control line in the row direction, the pixels 112 of other pixel blocks 120 are commonly connected by different control lines.
[0020] The pixel block 120 is arranged corresponding to the processing block 220 described later. In the present embodiment, one pixel block 120 is arranged for one processing block 220.
[0021] The pixel 112 has a photoelectric conversion function of converting light into electric charges. The pixel 112 accumulates the photoelectrically converted electric charges. m pixels 112 are arranged side by side along the column direction and are connected to a common signal line 122. And the m pixels 112 are arranged in n columns in the row direction in the pixel block 120.
[0022] In other words, the pixel block 120 is an aggregation of a plurality of pixels 112 connected by a common control line and / or a signal line. Also, it can be said that the pixel block 120 is the minimum unit of a circuit of a plurality of pixels 112 for which the same exposure time is set.
[0023] Figure 3 shows an example of the circuit configuration of pixel 112. Pixel 112 comprises a photoelectric conversion unit 104, a transfer unit 123, an output unit 124, a reset unit 126, and a pixel output unit 127. The pixel output unit 127 includes an amplification unit 128 and a selection unit 129. In this example, the transfer unit 123, output unit 124, reset unit 126, amplification unit 128, and selection unit 129 are described as N-channel FETs, but the type of transistor is not limited to this.
[0024] The photoelectric conversion unit 104 has a photoelectric conversion function that converts light into electric charge. The photoelectric conversion unit 104 stores the photoelectrically converted charge. The photoelectric conversion unit 104 is, for example, a photodiode.
[0025] The transfer unit 123 transfers the charge stored in the photoelectric conversion unit 104 to the storage unit 125. The transfer unit 123 is an example of a transfer gate that transfers charge from the photoelectric conversion unit 104. In other words, the transfer unit 123 acts as the gate, the photoelectric conversion unit 104 as the source, and the storage unit 125 as the drain, and these together constitute a so-called transfer transistor. The gate terminal of the transfer unit 123 is connected to a local transfer control line for each pixel block 120 for inputting the control signal φTX1.
[0026] The discharge unit 124 discharges the charge accumulated in the photoelectric conversion unit 104 to the power supply wiring supplied with the power supply voltage VDD. The gate terminal of the discharge unit 124 is connected to a local discharge control line for each pixel block 120 for inputting the discharge control signal φTX2. In this example, the discharge unit 124 is described as discharging the charge of the photoelectric conversion unit 104 to the power supply wiring supplied with the power supply voltage VDD, but it may also discharge to power supply wiring supplied with a power supply voltage different from the power supply voltage VDD.
[0027] The storage unit 125 receives charge from the photoelectric conversion unit 104 via the transfer unit 123. The storage unit 125 is an example of floating diffusion (FD).
[0028] The reset unit 126 discharges the charge from the storage unit 125 to a power supply wiring to which a predetermined power supply voltage VDD is supplied. The gate terminal of the reset unit 126 is connected to a global reset control line spanning multiple pixel blocks 120 for inputting a reset control signal φRST.
[0029] The pixel output unit 127 outputs a signal based on the potential of the storage unit 125 to the signal line 122. The pixel output unit 127 includes an amplification unit 128 and a selection unit 129. The gate terminal of the amplification unit 128 is connected to the storage unit 125, the drain terminal is connected to the power supply wiring to which the power supply voltage VDD is supplied, and the source terminal is connected to the drain terminal of the selection unit 129.
[0030] The selection unit 129 controls the electrical connection between the pixel 112 and the signal line 122. When the selection unit 129 electrically connects the pixel 112 and the signal line 122, a pixel signal is output from the pixel 112 to the signal line 122. The gate terminal of the selection unit 129 is connected to a global selection control line spanning multiple pixel blocks 120 for inputting the selection control signal φSEL. The source terminal of the selection unit 129 is connected to the load current source 121.
[0031] The load current source 121 supplies current to the signal line 122. The load current source 121 may be provided on the first substrate 100 or on the second substrate 200.
[0032] Hereafter, the charge stored in the photoelectric conversion unit 104, the charge transferred to the storage unit 125, and the signal based on the potential of the storage unit 125, or these collectively, may be referred to as the pixel signal.
[0033] In addition, each pixel 112 includes at least one photoelectric conversion unit 104 and a pixel output unit 127, etc., which acts as a readout unit for reading the image signal from the at least one photoelectric conversion unit 104 to the signal line 122. The pixel 112 can also be said to be the smallest unit of the circuit that outputs the pixel signals constituting the image to the signal line 122.
[0034] Figure 4 shows a more specific example of the configuration of the processing circuit unit 210. In this example, the processing circuit unit 210 and an enlarged view of the processing block 220 provided in the processing circuit unit 210 are shown.
[0035] The processing circuit unit 210 has processing blocks 220 arranged in a row and column direction. In this example, the processing circuit unit 210 has M × N processing blocks 220.
[0036] In this embodiment, the processing block 220 and the pixel block 120 are arranged in positions that overlap when viewed from the optical axis direction. In this case, the areas of the processing block 220 and the pixel block 120 may be substantially the same, including the margins between adjacent blocks.
[0037] The processing block 220 controls the driving of the electrically connected pixel block 120. The fact that the processing block 220 and the pixel block 120 are electrically connected is sometimes referred to as "corresponding." In this embodiment, the processing block 220 and the pixel block 120 are connected at positions that overlap each other. However, instead of the processing block 220 and the pixel block 120 being connected at positions that overlap each other, the processing block 220 and the pixel block 120 may be connected at positions that do not overlap each other.
[0038] For example, the processing block 220 controls the exposure time of the corresponding pixel block 120. The processing block 220 also has a processing circuit such as an ADC and processes the signal output by the corresponding pixel block 120. In one example, the processing block 220 converts the analog pixel signal output from the corresponding pixel block 120 into a digital signal. The processing block 220 in this example includes an exposure control unit 10, a pixel driving unit 20, a fusion unit 30, a signal conversion unit 40, and a signal output unit 50.
[0039] The exposure control unit 10 controls the exposure of multiple pixels 112. The exposure control unit 10 generates signals to control the exposure time of the pixels 112. In one example, the exposure control unit 10 controls the exposure time for each pixel block 120 by adjusting at least one of the start timing or end timing of the exposure.
[0040] The pixel drive unit 20 is electrically connected to a plurality of pixels 112. Based on a signal from the exposure control unit 10, the pixel drive unit 20 selects and drives any pixel 112 from the plurality of pixels 112. The image sensor 400 can expand its dynamic range because the exposure time can be set for each pixel block 120 according to the intensity of the incident light.
[0041] The joint 30 joins the first substrate 100 and the second substrate 200. The joint 30 inputs the pixel signal received from the first substrate 100 to the signal conversion unit 40. The joint 30 is provided in accordance with n pixels 112 arranged in the row direction, and inputs the pixel signal to the signal conversion unit 40 column by column.
[0042] The signal conversion unit 40 converts the analog signal output by the pixel unit 110 into a digital signal. In this example, the signal conversion unit 40 converts the analog pixel signal into a digital signal. The signal conversion unit 40 sequentially converts the analog signals from m pixels 112 arranged in the column direction into digital signals. The signal conversion unit 40 has n ADCs 42 arranged in the row direction and a storage unit 44. Each ADC 42 converts the analog signal from the corresponding pixel 112 of the corresponding column of the corresponding pixel block 120 into a digital signal in parallel. This can also be described as a so-called column ADC system for one pixel block 120. The storage unit 44 will be described later.
[0043] The signal output unit 50 receives a digital signal from the signal conversion unit 40. In one example, the signal output unit 50 temporarily stores the digital signal. The signal output unit 50 may have a latch circuit for storing the digital signal.
[0044] Alternatively, instead of providing one processing block 220 for each pixel block 120, one processing block 220 may be provided for N pixel blocks 120 (where N is a natural number greater than or equal to 2). N pixel blocks 120 corresponding to one processing block are sometimes referred to as a pixel block group. For example, two pixel blocks 120 arranged side-by-side in the column direction may be treated as one pixel block group, and one processing block 220 may be provided for each of these groups. In this case, the processing block 220 may control the exposure time for each pixel block 120.
[0045] Furthermore, the processing block 220 is electrically connected to at least one pixel block 120 and can be described as the smallest unit of circuitry that processes the pixel signals of that at least one pixel block 120. Also, the processing circuit section 210 can be described as being composed of a group of processing blocks 220.
[0046] Figure 5 is a schematic diagram illustrating the ADC 42, memory unit 44, and signal output unit 50 of the processing block 220. Note that, for simplification, signal lines corresponding to the number of bits in Figure 5 are represented by a single line, and the presence of multiple lines corresponding to the number of bits is indicated by a thick diagonal line on that line.
[0047] As shown in Figure 5, each ADC42 is connected to a signal line 122 to which pixels 112 are connected in the column direction of the corresponding pixel block 120. Therefore, each ADC42 digitally converts the pixel signals that flow sequentially from the pixels 112 connected in the column direction to the signal line 122. The ADC42 includes a latch circuit that temporarily holds the digitally converted values.
[0048] In this embodiment, the storage unit 44 has a first storage unit 440 and a second storage unit 442 connected to the output side of each ADC 42. The first storage unit 440 and the second storage unit 442 may be SRAMs or other storage elements, respectively.
[0049] The first storage unit 440 stores a signal obtained by digitally converting the pixel signal corresponding to the reset of the pixel 112 by the ADC 42. The second storage unit 442 stores a signal obtained by digitally converting the pixel signal corresponding to the exposure of the pixel 112 by the ADC 42.
[0050] Each of the first storage units 440 is connected via a selector 451 to a local signal line 450 within the processing block 220. Each of the second storage units 442 is connected via a selector 453 to a local signal line 452 within the processing block 220.
[0051] The signal output unit 50 includes a CDS circuit 550, a precharge circuit 552, and a readout circuit 554. In addition, in this embodiment, there is one CDS circuit 550 and one precharge circuit 552 within each processing block 220. The CDS circuit 550 is a circuit that performs CDS (correlated double sampling) processing as an example of noise reduction processing, and in this embodiment, it performs digital CDS processing.
[0052] The CDS circuit 550 and the precharge circuit 552 are connected to signal lines 450 and 452. As a result, for a given pixel 112, the pixel signal corresponding to reset stored in the first storage unit 440 and the pixel signal corresponding to exposure stored in the second storage unit 442 are precharged and processed using CDS, and the digital pixel signal corresponding to the difference is output to the readout circuit 554. The readout circuit 554 outputs the pixel signal to a global signal line 556, which is shared among the processing blocks 220, at a predetermined timing.
[0053] Figure 6 is a chart showing the timing of processing in processing block 220. The dashed lines indicate operations that occur simultaneously and synchronously in all columns of pixel block 120. For simplicity of explanation, Figure 6 uses a pixel 112 in the first column and a pixel 112 in the second column, located in the same row, as examples.
[0054] First, a pixel signal corresponding to reset (referred to as pixel signal RST) is input from pixel 112 of pixel block 120 to the corresponding ADC42. The ADC42 performs AD conversion on the pixel signal RST and stores it in a latch for primary storage.
[0055] The ADC42 writes the pixel signal RST, which was initially stored in the latch, to the first storage unit 440. This frees up the latch, and the pixel signals corresponding to exposure (represented as the pixel signal SGNL) from all the pixels 112 in all columns of the pixel block 120 are input to the corresponding ADC42. The ADC42 performs AD conversion on the pixel signal SGNL and stores it initially in the latch.
[0056] ADC42 writes the pixel signal SGNL, which was initially stored in the latch, to the second storage unit 442. At this time, the selector 451 corresponding to the first storage unit 440, which corresponds to the first column ADC42, is turned on, and the pixel signal RST may be read out to the signal line 450. In other words, the writing of the pixel signal SGNL to the second storage unit 442 and the reading of the first column's pixel signal RST to the signal line may overlap in time.
[0057] The pixel signal RST, read to signal line 450, is input to the CDS circuit. Furthermore, the selector 453 corresponding to the second storage unit 442, which corresponds to the first column's ADC 42, is turned on, and the pixel signal SGNL is read to signal line 452 and input to the CDS circuit. As a result, the CDS circuit 550 performs CDS processing, and the pixel signal corresponding to the difference between them (referred to as the pixel signal DS) is output. Furthermore, the pixel signal DS is output to signal line 556 by the readout circuit 554.
[0058] When the pixel signal DS of the first column is output to signal line 556, the pixel signal RST of the second column is read out to signal line 450. In other words, these operations may overlap in time. Subsequently, the pixel 112 of the second column is processed in the same way as the pixel 112 of the first column, and its pixel signal DS is output to signal line 556. This allows for further image processing in a later stage to generate a single image data.
[0059] For the next row's pixel 112, the AD conversion process can be started as soon as the ADC42 latch becomes available. Therefore, the CDS processing for one row's pixel 112 and the operation of the ADC42 for the next row's pixel 112 can be performed with at least partial overlap.
[0060] As described above, after AD conversion by ADC42, operations are performed sequentially for each column. In this case, each ADC42 is connected to its own first storage unit 440 and second storage unit 442. Therefore, the pixel signals RST and SGNL can be held until the timing for reading to signal lines 450 and 452 arrives. For example, the pixel signals RST and SGNL of the pixel 112 of the second column can be held in the first storage unit 440 and the second storage unit 442 until the pixel 112 of the first column is processed using CDS.
[0061] Furthermore, each of the processing blocks 220 undergoes CDS processing, and the processed pixel signal DS is output to the global signal line 556. Therefore, compared to outputting the pixel signals RST and SGNL to the global signal line and performing CDS processing in a later stage, only one signal output is required for each pixel 112, thus reducing power consumption.
[0062] Figure 7 is a schematic diagram illustrating another processing block 222. In Figure 7, components identical to those in Figure 5 are given the same reference numerals and their explanations are omitted.
[0063] The memory unit 46 in Figure 7 is the same as in Figure 5 in that the first memory unit 440 is connected to the output side of each ADC 42. On the other hand, the memory unit 46 has one second memory unit 444 that is shared by the processing block 222. The second memory unit 444 may also be an SRAM or another memory element. The second memory unit 444 is connected to signal lines 450 and 452 via a selector 454.
[0064] A selector 455 is provided between the signal line 450 and the CDS circuit 550. This allows the signal from the first storage unit 440 corresponding to selector 451 to be transferred to the second storage unit 444 by turning on selector 454 and either selector 451 with selector 455 turned off. Alternatively, by turning on selector 454 with selector 455 and either selector 451 turned off, the signal stored in the second storage unit 444 can be input to the CDS circuit 550. On the other hand, by turning off selector 454 and turning on selector 455 and either selector 451, the signal from the first storage unit 440 corresponding to selector 454 can be input to the CDS circuit 550.
[0065] Figure 8 is a chart showing the timing of processing in processing block 222. The symbols and other terms used are the same as in Figure 6.
[0066] As in Figure 6, the operation of the ADC42 is performed simultaneously for all columns in a given row. Each ADC42 writes the pixel signal RST, which was temporarily stored in its latch, to its respective first storage unit 440. This frees up the latch, allowing the pixel signals SGNL from all pixels 112 in all columns of the pixel block 120 to be input to the corresponding ADC42. The ADC42 performs A / D conversion on the pixel signals SGNL and temporarily stores them in its latch.
[0067] Furthermore, when the selector 451 and selector 454 corresponding to the first storage unit 440 corresponding to the first column's ADC 42 are turned on, the pixel signal RST of the first column is transferred to the second storage unit 444 via the signal line 450.
[0068] When selector 454 is turned on, the pixel signal RST of the first column, which was stored in the second memory unit 444, is input to the CDS circuit 550 via signal line 452. Furthermore, when selectors 451 and 455, which correspond to the first memory unit 440 of the first column, are turned on, the pixel signal SGNL of the first column, which was stored in the first memory unit 440, is input to the CDS circuit via signal line 450. As a result, the CDS circuit 550 performs CDS processing and outputs the pixel signal DS. Furthermore, the pixel signal DS is output to signal line 556 by the readout circuit 554.
[0069] When the pixel signal DS of the first column is output to signal line 556, the pixel signal RST of the second column is read out to signal line 450. In other words, these operations may overlap in time. Subsequently, the pixel 112 of the second column is processed in the same way as the pixel 112 of the first column, and the pixel signal DS is output to signal line 556. This can also be described as the second storage unit 444, which is shared by the processing block 220, sequentially storing the pixel signals RST from each of the first storage units 440 and sequentially outputting them to the CDS circuit 550.
[0070] As described above, after AD conversion by ADC42, operations are performed sequentially for each column. In this case, each ADC42 has its own first storage unit 440, and a second storage unit 442 is provided that is shared by multiple ADC42s. Therefore, by temporarily holding the pixel signal RST of the pixel 112 to be processed next in CDS in the second storage unit 444, the first storage unit 440 can be used to hold the pixel signal SGNL.
[0071] Furthermore, each of the processing blocks 220 undergoes CDS processing, and the processed pixel signal DS is output to the global signal line 556. Therefore, in the processing block 222 of Figure 7, compared to outputting the pixel signal RST and the pixel signal SGNL to the global signal line and performing CDS processing in a later stage, only one signal output is required for each pixel 112, thus reducing power consumption. Note that the second memory unit 444 shared by the processing block 220 is not limited to one, but may be two or more and up to n-1 units.
[0072] In any of the above embodiments, the storage unit 125 and the pixel output unit 127 may be shared with other pixels. Furthermore, the pixel 112 may be composed of multiple photoelectric conversion units 104 and transfer units 123. Also, the pixel 112 may be configured as a so-called 4-transistor type without providing the output unit 124.
[0073] Furthermore, in any of the above embodiments, the exposure control unit 10 and the pixel driving unit 20 may not be provided in the processing block 220, and reading may be performed mainly for each processing block 220 and conversion may be performed by the signal conversion unit 40. In this case, the exposure time of the pixels 112 is controlled for the entire pixel unit 110, rather than for each pixel block 120.
[0074] Figure 9 is a block diagram showing an example configuration of an imaging device 500 according to an embodiment. The imaging device 500 comprises an image sensor 400, a system control unit 501, a drive unit 502, a photometer 503, a work memory 504, a recording unit 505, a display unit 506, a drive unit 514, and a photographic lens 520.
[0075] The imaging lens 520 guides the subject light beam incident along the optical axis OA to the image sensor 400. The imaging lens 520 is composed of multiple optical lens groups and forms an image of the subject light beam from the scene near its focal plane. The imaging lens 520 may be an interchangeable lens that can be attached to and detached from the imaging device 500. In Figure 9, the imaging lens 520 is represented by a single virtual lens positioned near the pupil.
[0076] The drive unit 514 drives the photographic lens 520. In one example, the drive unit 514 moves the optical lens group of the photographic lens 520 to change the focus position. The drive unit 514 may also drive the iris diaphragm within the photographic lens 520 to control the amount of light beam incident on the image sensor 400.
[0077] The drive unit 502 has a control circuit that performs charge accumulation control such as timing control and area control of the image sensor 400 according to instructions from the system control unit 501. The operation unit 508 receives instructions from the imager via a release button or the like.
[0078] The image sensor 400 passes pixel signals to the image processing unit 511 of the system control unit 501. The image processing unit 511 uses the work memory 504 as a workspace to generate image data after performing various image processing steps. For example, when generating image data in JPEG file format, it generates a color video signal from the signal obtained by the Bayer array and then performs compression processing. The generated image data is recorded in the recording unit 505 and converted into a display signal, which is then displayed in the display unit 506 for a preset time.
[0079] Prior to the series of shooting sequences that generate image data, the photometering unit 503 detects the brightness distribution of the scene. The photometering unit 503 includes, for example, an AE sensor with about 1 million pixels. The calculation unit 512 of the system control unit 501 receives the output of the photometering unit 503 and calculates the brightness of each region of the scene.
[0080] The calculation unit 512 determines the shutter speed, aperture value, and ISO sensitivity according to the calculated brightness distribution. The photometering unit 503 may also be integrated into the image sensor 400. The calculation unit 512 also performs various calculations for operating the imaging device 500. The drive unit 502 may be partially or entirely mounted on the image sensor 400. Part of the system control unit 501 may also be mounted on the image sensor 400.
[0081] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. It will be clear from the claims that such modified or improved forms may also be included in the technical scope of the present invention.
[0082] It should be noted that the execution order of operations, procedures, steps, and stages in the apparatus, systems, programs, and methods shown in the claims, specifications, and drawings is not explicitly stated as "before," "prior to," etc., and that these can be implemented in any order unless the output of a previous process is used in a later process. Even if the operation flow in the claims, specifications, and drawings is described using phrases such as "first," "next," etc. for convenience, it does not mean that it is essential to perform the operations in that order. [Explanation of symbols]
[0083] 10 Exposure control unit, 20 Pixel drive unit, 30 Bonding unit, 40 Signal conversion unit, 42 ADC, 44 Memory unit, 50 Signal output unit, 100 First substrate, 104 Photoelectric conversion unit, 110 Pixel unit, 112 Pixel, 120 Pixel block, 121 Load current source, 122 Signal line, 123 Transfer unit, 124 Discharge unit, 125 Storage unit, 126 Reset unit, 127 Pixel output unit, 128 Amplification unit, 129 Selection unit, 200 Second substrate, 210 Processing circuit unit, 220, 222 Processing block, 230 Peripheral circuit unit, 400 Image sensor, 440 First memory unit, 442, 444 Second memory unit, 450, 452 Signal line, 451, 453, 454 Selector, 500 Imaging device, 501 System control unit, 502 drive unit, 503 photometer unit, 504 work memory, 505 recording unit, 506 display unit, 508 operation unit, 511 image processing unit, 512 calculation unit, 514 drive unit, 520 photographic lens, 550 CDS circuit, 552 precharge circuit, 554 read circuit, 556 signal line
Claims
1. A first semiconductor unit having a pixel section including a first pixel block in which a first photoelectric conversion unit that converts light into electric charge and a second photoelectric conversion unit that converts light into electric charge are arranged, and a second pixel block in which a third photoelectric conversion unit that converts light into electric charge and a fourth photoelectric conversion unit that converts light into electric charge are arranged, A second semiconductor section having a processing circuit section, which is laminated together with the first semiconductor section, and includes a first processing block that includes a first conversion section that converts a first signal based on the charge converted by the first photoelectric conversion section into a digital signal, a second conversion section that converts a second signal based on the charge converted by the second photoelectric conversion section into a digital signal, and a first correction processing section that performs a first correction process to correct the first digital signal converted from the first signal to a digital signal by the first conversion section, and a second correction processing to correct the second digital signal converted from the second signal to a digital signal by the second conversion section, and a second correction processing section that performs a third conversion section that converts a third signal based on the charge converted by the third photoelectric conversion section into a digital signal, a fourth conversion section that converts a fourth signal based on the charge converted by the fourth photoelectric conversion section into a digital signal, and a second correction processing section that performs a third correction process to correct the third digital signal converted from the third signal to a digital signal by the third conversion section, and a fourth correction processing to correct the fourth digital signal converted from the fourth signal to a digital signal by the fourth conversion section, A junction that joins the first semiconductor part and the second semiconductor part, and the first junction that outputs the first signal, A junction that joins the first semiconductor part and the second semiconductor part, and a second junction that outputs the second signal, A junction that joins the first semiconductor part and the second semiconductor part, and a third junction that outputs the third signal, A junction that joins the first semiconductor part and the second semiconductor part, and a fourth junction that outputs the fourth signal. Equipped with, The first junction, the second junction, the third junction, and the fourth junction are arranged between the pixel portion and the processing circuit portion in the stacking direction in which the first semiconductor portion and the second semiconductor portion are stacked. Image sensor.
2. In the image sensor according to claim 1, A first signal line is electrically connected to the first junction and outputs the first signal read from the first pixel block, A second signal line is electrically connected to the second junction and outputs the second signal read from the first pixel block, A third signal line is electrically connected to the third junction and outputs the third signal read from the second pixel block, A fourth signal line is electrically connected to the fourth junction and outputs the fourth signal read from the second pixel block. An image sensor equipped with the following features.
3. In the image sensor according to claim 1 or claim 2, The first processing block includes a first storage unit that stores a first correction signal, which is a signal converted from an analog signal to a digital signal and used in the first correction processing, and a second storage unit that stores a second correction signal, which is a signal converted from an analog signal to a digital signal and used in the second correction processing. The second processing block includes a third storage unit that stores a third correction signal, which is a signal converted from an analog signal to a digital signal and used in the third correction processing, and a fourth storage unit that stores a fourth correction signal, which is a signal converted from an analog signal to a digital signal and used in the fourth correction processing. Image sensor.
4. In the image sensor according to claim 3, The first correction processing unit performs the first correction processing using the first correction signal read from the first storage unit. The second correction processing unit performs the third correction processing using the third correction signal read from the third storage unit. Image sensor.
5. In the image sensor according to claim 4, The first correction processing unit performs the second correction processing using the second correction signal read from the second storage unit. The second correction processing unit performs the fourth correction processing using the fourth correction signal read from the fourth storage unit. Image sensor.
6. In the image sensor according to claim 5, The first correction processing unit performs the first correction process and the second correction process at different timings. The second correction processing unit performs the third correction process and the fourth correction process at different timings. Image sensor.
7. In the image sensor according to claim 1 or claim 2, The first processing block includes a first storage unit that stores the first digital signal, a second storage unit that stores a first correction signal which is a signal converted from an analog signal to a digital signal and used in the first correction processing, a third storage unit that stores the second digital signal, and a fourth storage unit that stores a second correction signal which is a signal converted from an analog signal to a digital signal and used in the second correction processing. The second processing block includes a fifth storage unit in which the third digital signal is stored, a sixth storage unit in which a third correction signal, which is a signal converted from an analog signal to a digital signal and used in the third correction processing, a seventh storage unit in which the fourth digital signal is stored, and an eighth storage unit in which a fourth correction signal, which is a signal converted from an analog signal to a digital signal and used in the fourth correction processing, Image sensor.
8. In the image sensor according to claim 7, The first correction processing unit performs the first correction processing using the first digital signal read from the first storage unit and the first correction signal read from the second storage unit. The second correction processing unit performs the third correction processing using the third digital signal read from the fifth storage unit and the third correction signal read from the sixth storage unit. Image sensor.
9. In the image sensor according to claim 8, The first correction processing unit performs the second correction processing using the second digital signal read from the third storage unit and the second correction signal read from the fourth storage unit. The second correction processing unit performs the fourth correction processing using the third digital signal read from the seventh storage unit and the fourth correction signal read from the eighth storage unit. Image sensor.
10. In the image sensor according to claim 9, The first correction processing unit performs the first correction process and the second correction process at different timings. The second correction processing unit performs the third correction process and the fourth correction process at different timings. Image sensor.
11. In the image sensor according to any one of claims 1 to 10, The first processing block includes a first exposure control unit that controls the storage time for storing the charge converted by the first photoelectric conversion unit and the storage time for storing the charge converted by the second photoelectric conversion unit. The second processing block includes a second exposure control unit that controls the storage time for storing the charge converted by the third photoelectric conversion unit and the storage time for storing the charge converted by the fourth photoelectric conversion unit. Image sensor.
12. In the image sensor according to claim 11, The first exposure control unit controls the storage time for accumulating the charge converted by the first photoelectric conversion unit and the storage time for accumulating the charge converted by the second photoelectric conversion unit so that the total storage time is the first storage time. The second exposure control unit controls the storage time for accumulating the charge converted by the third photoelectric conversion unit and the storage time for accumulating the charge converted by the fourth photoelectric conversion unit to be a second storage time that is different from the first storage time. Image sensor.
13. In the image sensor according to claim 11 or claim 12, The first pixel block includes a first transfer unit that transfers the charge converted by the first photoelectric conversion unit, and a second transfer unit that transfers the charge converted by the second photoelectric conversion unit. The second pixel block includes a third transfer unit that transfers the charge converted by the third photoelectric conversion unit, and a fourth transfer unit that transfers the charge converted by the fourth photoelectric conversion unit. The first exposure control unit controls the timing at which charge is transferred from the first photoelectric conversion unit by the first transfer unit and the timing at which charge is transferred from the second photoelectric conversion unit by the second transfer unit. The second exposure control unit controls the timing at which charge is transferred from the third photoelectric conversion unit by the third transfer unit and the timing at which charge is transferred from the fourth photoelectric conversion unit by the fourth transfer unit. Image sensor.
14. In the image sensor according to any one of claims 11 to 13, The first pixel block includes a first discharge unit for discharging the charge of the first photoelectric conversion unit and a second discharge unit for discharging the charge of the second photoelectric conversion unit. The second pixel block includes a third discharge unit for discharging the charge from the third photoelectric conversion unit and a fourth discharge unit for discharging the charge from the fourth photoelectric conversion unit. The first exposure control unit controls the timing at which charge is discharged from the first photoelectric conversion unit by the first discharge unit and the timing at which charge is discharged from the second photoelectric conversion unit by the second discharge unit. The second exposure control unit controls the timing at which charge is discharged from the third photoelectric conversion unit by the third discharge unit and the timing at which charge is discharged from the fourth photoelectric conversion unit by the fourth discharge unit. Image sensor.
15. In the image sensor according to any one of claims 1 to 14, The second pixel block is arranged in the row direction alongside the first pixel block. Image sensor.
16. In the image sensor according to claim 15, The second photoelectric conversion unit is arranged in the row direction alongside the first photoelectric conversion unit, The fourth photoelectric conversion unit is arranged in the row direction alongside the third photoelectric conversion unit. Image sensor.
17. In the image sensor according to any one of claims 1 to 14, The second pixel block is arranged in the column direction alongside the first pixel block. Image sensor.
18. In the image sensor according to claim 17, The second photoelectric conversion unit is arranged in the row direction alongside the first photoelectric conversion unit, The fourth photoelectric conversion unit is arranged in the row direction alongside the third photoelectric conversion unit. Image sensor.
19. An imaging device comprising an image sensor according to any one of claims 1 to 18.
20. In the imaging device according to claim 19, An imaging device comprising a drive unit that drives a photographic lens that emits light to the image sensor.