Semiconductor equipment

Abstract

To provide transistors with good electrical characteristics. [Solution] A semiconductor, a first insulator in contact with the semiconductor, and a first insulator in contact with the first insulator A first conductor overlapping with the semiconductor via a rim, and a second conductor and a third conductor in contact with the semiconductor. A conductor and a conductor, one or more of the first to third conductors being tungsten and silicon One or more elements selected from condensate, carbon, germanium, tin, aluminum, or nickel. A semiconductor device having a region containing an element.

Description

[Technical Field]

[0001] This invention relates, for example, to transistors and semiconductor devices, as well as to methods for manufacturing them. Alternatively, the present invention may be used, for example, as a display device, light-emitting device, lighting device, energy storage device, memory device, or camera. Related to imaging devices, processors, and electronic equipment. Or, display devices, liquid crystal display devices, light-emitting devices. This relates to a method for manufacturing memory devices, imaging devices, and electronic devices. Or, semiconductor devices, display devices, and liquids. This invention relates to a method for driving crystal display devices, light-emitting devices, memory devices, and electronic devices.

[0002] Furthermore, one aspect of the present invention is not limited to the above-mentioned technical field. One aspect of the technical field relates to a product, method, or method of manufacture. Or, the present invention. One aspect of this is a process, machine, manufacture, or composition. It concerns matter.

[0003] In this specification, a semiconductor device refers to a device that can function by utilizing semiconductor properties. This refers to the general category of display devices, light-emitting devices, lighting devices, electro-optical devices, semiconductor circuits, and electronic equipment. It may have a semiconductor device. [Background technology]

[0004] In recent years, transistors using oxide semiconductors have attracted attention. Lampistors are known to have extremely low leakage current when they are not conducting. For example, low power consumption is achieved by taking advantage of the low leakage current characteristic of transistors using oxide semiconductors. Power-based CPUs and the like are disclosed (see Patent Document 1). [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2012-257187 [Overview of the Initiative] [Problems that the invention aims to solve]

[0006] In transistors using oxide semiconductors, in order to reduce impurities such as water and hydrogen Therefore, the gate electrode and socket used in the transistor may undergo high-temperature heat treatment. The drain electrode or drain electrode shall be formed from a material that has heat resistance and oxidation resistance. It is preferable.

[0007] Therefore, one aspect of the present invention relates to a transistor using a conductor having heat resistance and oxidation resistance. One of the objectives is to provide [this].

[0008] Another objective is to provide a transistor with stable electrical characteristics. One of the objectives is to provide a transistor with low leakage current when not conducting. One of the objectives is to provide a transistor with high frequency characteristics. One of the objectives is to provide a transistor with Marie-off electrical characteristics. One of the objectives is to provide a transistor with a small subthreshold swing value. Alternatively, one of the objectives is to provide highly reliable transistors.

[0009] Alternatively, one of the objectives is to provide a semiconductor device having the transistor. One of the objectives is to provide a module having the semiconductor device. One of the objectives is to provide an electronic device that has such a module, or a new One of the objectives is to provide standard semiconductor devices, or to provide novel modules. One of the objectives is to achieve this. Alternatively, one of the objectives is to provide novel electronic devices.

[0010] Furthermore, the description of these problems does not preclude the existence of other problems. The approach does not need to solve all of these problems. This will become clear from the description in the specification, drawings, claims, etc., and the specification, drawings It is possible to extract other issues from the descriptions in the surfaces, claims, etc. [Means for solving the problem]

[0011] One aspect of the present invention comprises a semiconductor, a first insulator in contact with the semiconductor, and a third insulator in contact with the first insulator. A first conductor overlapping with a semiconductor via an insulator, and a second conductor in contact with the semiconductor. It has a third conductor and one or more of the first to third conductors is tungsten ( W) and silicon (Si), carbon (C), germanium (Ge), tin (Sn), aluminum A region having one or more elements selected from nium (Al) or nickel (Ni) It is a semiconductor device.

[0012] One aspect of the present invention is that one or more of the first to third conductors are Rutherford backscattering Analysis(RBS: Rutherford Backscattering Spectrom The silicon concentration obtained by the etry is between 5 atomic% and 70 atomic%. The above-mentioned semiconductor device has a region that is...

[0013] One aspect of the present invention is that one or more of the first to third conductors have silicon and acid on their surface. The above semiconductor having a region containing an element, the thickness of which the region is 0.2 nm or more and 20 nm or less. It is a device.

[0014] One aspect of the present invention is a second insulator in contact with a semiconductor, and a second insulator in contact with the second insulator. It has a fourth conductor that overlaps with the semiconductor via a sieve, and the fourth conductor is made of tungsten and One or more selected from ricon, carbon, germanium, tin, aluminum, or nickel. The above-mentioned semiconductor device has a region containing an element.

[0015] One aspect of the present invention is a fourth conductor, which is silicon obtained by Rutherford backscatter analysis. The above semiconductor device having a region with a concentration of 5 atomic% or more and 70 atomic% or less It is placed there.

[0016] One aspect of the present invention is that the fourth conductor has a region on its surface having silicon and oxygen, The above-mentioned semiconductor device has a region thickness of 0.2 nm or more and 20 nm or less.

[0017] One aspect of the present invention is a semiconductor device having an oxide semiconductor. [Effects of the Invention]

[0018] According to one aspect of the present invention, a transistor using a conductor having heat resistance and oxidation resistance is provided. It can be provided.

[0019] Furthermore, it is possible to provide a transistor with stable electrical characteristics. Or, non-conductive It can provide transistors with low leakage current at high frequencies. A transistor having the following characteristics can be provided: or a transistor having normally-off electrical characteristics. It is possible to provide a transistor that does this. Or, a transistor with a small subthreshold swing value. We can provide transistors. Or, we can provide highly reliable transistors. It is possible.

[0020] Alternatively, a semiconductor device having the transistor can be provided. A module having a device can be provided. Or, the semiconductor device, or the module We can provide electronic equipment having a sphere. Or, we can provide a novel semiconductor device. It is possible to provide a novel module. Or, a novel electronic We can provide the equipment.

[0021] Furthermore, the description of these effects does not preclude the existence of other effects. The embodiment does not need to have all of these effects. Other effects are described in the specification. This will become clear from the descriptions in the drawings and claims, and the specification, drawings, and claims will be clear from the description, drawings, and claims. It is possible to extract other effects from any of these descriptions. [Brief explanation of the drawing]

[0022] [Figure 1] A top view and a cross-sectional view illustrating a transistor according to one aspect of the present invention. [Figure 2] Figures illustrating the XRD structural analysis of CAAC-OS and single-crystal oxide semiconductors, as well as a figure showing the limited-field electron diffraction pattern of CAAC-OS. [Figure 3] Cross-sectional TEM images of CAAC-OS, as well as planar TEM images and their image analysis results. [Figure 4] Figure showing the electron diffraction pattern of nc-OS, and a cross-sectional TEM image of nc-OS. [Figure 5] Cross-sectional TEM image of an a-like OS. [Figure 6] A diagram showing the changes in the crystalline structure of In-Ga-Zn oxide due to electron irradiation. [Figure 7] A cross-sectional view illustrating a transistor according to one aspect of the present invention. [Figure 8] A cross-sectional view illustrating a transistor according to one aspect of the present invention. [Figure 9] A cross-sectional view illustrating a transistor according to one aspect of the present invention. [Figure 10] A cross-sectional view illustrating a transistor according to one aspect of the present invention. [Figure 11] A cross-sectional view illustrating a transistor according to one aspect of the present invention. [Figure 12] A cross-sectional view illustrating a transistor according to one aspect of the present invention. [Figure 13] A cross-sectional view illustrating a method for manufacturing a transistor according to one aspect of the present invention. [Figure 14] A cross-sectional view illustrating a method for manufacturing a transistor according to one aspect of the present invention. [Figure 15] A cross-sectional view illustrating a method for manufacturing a transistor according to one aspect of the present invention. [Figure 16] Schematic and cross-sectional diagrams illustrating the film deposition apparatus. [Figure 17] A cross-sectional view illustrating a method for manufacturing a transistor according to one aspect of the present invention. [Figure 18] A cross-sectional view illustrating a method for manufacturing a transistor according to one aspect of the present invention. [Figure 19] A cross-sectional view illustrating a method for manufacturing a transistor according to one aspect of the present invention. [Figure 20] A top view showing a manufacturing apparatus according to one aspect of the present invention. [Figure 21] A cross-sectional view showing a chamber according to one aspect of the present invention. [Figure 22] A cross-sectional view showing a chamber according to one aspect of the present invention. [Figure 23] Circuit diagram showing a semiconductor device according to one aspect of the present invention. [Figure 24] A cross-sectional view showing a semiconductor device according to one aspect of the present invention. [Figure 25]A cross-sectional view showing a semiconductor device according to one aspect of the present invention. [Figure 26] A cross-sectional view showing a semiconductor device according to one aspect of the present invention. [Figure 27] Circuit diagram showing a storage device according to one aspect of the present invention. [Figure 28] A cross-sectional view showing a semiconductor device according to one aspect of the present invention. [Figure 29] A cross-sectional view showing a semiconductor device according to one aspect of the present invention. [Figure 30] A cross-sectional view showing a semiconductor device according to one aspect of the present invention. [Figure 31] Circuit diagram showing a semiconductor device according to one aspect of the present invention. [Figure 32] A cross-sectional view showing a semiconductor device according to one aspect of the present invention. [Figure 33] A cross-sectional view showing a semiconductor device according to one aspect of the present invention. [Figure 34] A cross-sectional view showing a semiconductor device according to one aspect of the present invention. [Figure 35] A top view showing a semiconductor device according to one aspect of the present invention. [Figure 36] Block diagram showing a semiconductor device according to one aspect of the present invention. [Figure 37] A cross-sectional view showing a semiconductor device according to one aspect of the present invention. [Figure 38] A cross-sectional view showing a semiconductor device according to one aspect of the present invention. [Figure 39] A perspective view and a cross-sectional view showing a semiconductor device according to one aspect of the present invention. [Figure 40] Block diagram showing a semiconductor device according to one aspect of the present invention. [Figure 41] Circuit diagram showing a semiconductor device according to one aspect of the present invention. [Figure 42] A circuit diagram, a top view, and a cross-sectional view showing a semiconductor device according to one aspect of the present invention. [Figure 43] A circuit diagram and a cross-sectional view showing a semiconductor device according to one aspect of the present invention. [Figure 44] A perspective view showing an electronic device according to one aspect of the present invention. [Figure 45] A diagram illustrating the XPS results of the sample. [Figure 46] A diagram illustrating the STEM results of the sample. [Modes for carrying out the invention]

[0023] Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is described below. It is not limited to the above, and its form and details can be easily changed in various ways, as can be easily seen by those skilled in the art. It is understood that the present invention is to be interpreted as being limited to the embodiments described below. No. Furthermore, when explaining the structure of the invention using drawings, the same reference numerals may refer to different things. It is used consistently across drawings. Furthermore, when referring to similar items, the hatch pattern is the same. Furthermore, sometimes no symbol is assigned.

[0024] The configurations shown in the following embodiments can be appropriately applied to and combined with other configurations shown in the embodiments. By combining or substituting, one aspect of the present invention can be obtained.

[0025] Note that in the diagram, the size, thickness of the film (layer), or area has been exaggerated for clarity. They may exist.

[0026] In this specification, the terms "membrane" and "layer" are interchangeable. It is possible to do so.

[0027] Furthermore, voltage is defined by a certain potential and a reference potential (e.g., ground potential (GND) or source potential). It often refers to the potential difference between two points. Therefore, it is possible to rephrase voltage as potential. Generally, electric potential (voltage) is relative, and its magnitude is relative to a reference potential. Therefore, it is determined by this. Consequently, even if it is written as "ground potential," The potential is not necessarily 0V. For example, the lowest potential in a circuit may be the "ground potential". There are also cases where the potential in the middle of the circuit becomes the "ground potential." Based on that potential, positive and negative potentials are defined.

[0028] The ordinal numbers "1st" and "2nd" are used for convenience only and do not necessarily indicate the order of processes or layering. It does not indicate order. Therefore, for example, "the first" could be "the second" or "the third." It can be explained by substituting it as appropriate. Also, ordinal numbers as described in this specification, etc. The ordinal numbers used to specify one aspect of the present invention may not always coincide.

[0029] Impurities in semiconductors refer to components other than the main components that make up the semiconductor. For example, an impurity with a concentration of 0. Elements present in amounts less than 1 atom (also called atomic percent) are considered impurities. This can lead to, for example, the formation of a Density of State (DOS) in a semiconductor. In some cases, this can lead to a decrease in carrier mobility or a decrease in crystallinity. If the semiconductor is an oxide semiconductor, impurities that change the properties of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and elements other than the main component. These include transition metals, and in particular, for example, hydrogen (also found in water), lithium, sodium, Examples include silicon, boron, phosphorus, carbon, and nitrogen. In the case of oxide semiconductors, for example, hydrogen. The inclusion of impurities can sometimes form oxygen vacancies. Also, if the semiconductor is a silicon layer In this case, impurities that alter the properties of semiconductors include, for example, Group 1 elements other than oxygen and hydrogen. These include elements from Group 2, Group 13, Group 15, and so on.

[0030] Note that channel length refers to, for example, the length of the semiconductor (or transistor) in a top view of a transistor. When the zista is in the ON state, the part of the semiconductor through which current flows and the gate electrode overlap each other. In the region where the channel is formed, the source (source region or source power) This refers to the distance between the electrode and the drain (drain region or drain electrode). In transistors, the channel length is not necessarily the same across all regions. That is, The channel length of a transistor may not be fixed to a single value. Therefore, this specification In the book, the channel length is any one value, the maximum value, in the region where the channel is formed. Use the minimum or average value.

[0031] Channel width refers to, for example, the channel width of a semiconductor (or transistor) when it is in the ON state. The region where the current-carrying part and the gate electrode overlap, or the region where a channel is formed. This refers to the length of the portion in the region where the source and drain face each other. In a transistor, the channel width is not necessarily the same across all regions. That is, The channel width of a transistor may not be fixed to a single value. Therefore, this specification In the book, the channel width is any one value, the maximum value, in the region where the channel is formed. Use the minimum or average value.

[0032] Furthermore, depending on the transistor structure, the channel may actually be formed in the region where the channel is formed. The channel width (hereinafter referred to as the effective channel width) and the top view of the transistor are shown. The channel width (hereinafter referred to as the apparent channel width) may differ from the actual channel width. For example, In transistors with a three-dimensional structure, the effective channel width is shown in the top view of the transistor. The apparent channel width shown in [the relevant section] becomes larger, and its effect can no longer be ignored. There are cases where this occurs. For example, in transistors with a fine and three-dimensional structure, the sides of the semiconductor In some cases, the proportion of the formed channel region may be large. In such cases, it is shown in the top view. The effective channel width in which the channel is actually formed is greater than the apparent channel width. The side becomes larger.

[0033] By the way, in transistors with a three-dimensional structure, the effective channel width is measured Estimation can be difficult in some cases. For example, estimating the effective channel width from the design value. In order to do this, it is necessary to assume that the shape of the semiconductor is known. If this information is not precisely known, it is difficult to accurately measure the effective channel width.

[0034] Therefore, in this specification, in the top view of a transistor, the semiconductor and the gate electrode are relative to each other. The apparent length of the portion where the source and drain face each other in the overlapping region. The channel width is called the "Surrounded Channel Width (SCW)". It is sometimes referred to as "L Width." Also, in this specification, it is sometimes simply referred to as "channel width." In some cases, it may refer to the enclosed channel width or the apparent channel width. Or, In this specification, when simply referred to as "channel width," it may refer to the effective channel width. Furthermore, channel length, channel width, effective channel width, apparent channel width, enclosure The channel width and other parameters can be determined by acquiring cross-sectional TEM images and analyzing those images. This allows us to determine the value.

[0035] Furthermore, the field-effect mobility of the transistor and the current value per channel width are calculated to determine this. In some cases, the calculation may be performed using the enclosed channel width. In that case, the effective channel The values ​​may differ from those obtained when calculating using the channel width.

[0036] In this specification, when A is described as having a shape that protrudes from B, the top view is shown. Alternatively, in a cross-sectional view, at least one end of A is located outside at least one end of B. It may be indicated that A has a shape that protrudes from B. If this is the case, for example, in the top view, one end of A is outside the one end of B. It can be reinterpreted as "possessing."

[0037] In this specification, when the term "semiconductor" is used, it may be replaced with various types of semiconductors. This can sometimes be done. For example, with Group 14 semiconductors such as silicon and germanium, and oxide semiconductors. Conductors, silicon carbide, germanium silicide, gallium arsenide, indium phosphide, selenide It can be replaced with compound semiconductors such as zinc and cadmium sulfide, as well as organic semiconductors. .

[0038] In this specification, "parallel" means that two straight lines are positioned at an angle of -10° or more and 10° or less. This refers to a state where the temperature is in a certain condition. Therefore, it also includes cases where the temperature is between -5° and 5°. A "row" refers to a state where two straight lines are positioned at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are positioned at an angle of 80° to 100°. Therefore, it also includes cases where the angle is between 85° and 95°. Also, "approximately perpendicular" means two This refers to a state in which two straight lines are arranged at an angle between 60° and 120°.

[0039] Furthermore, in this specification, if a crystal is trigonal or rhombohedral, it will be represented as a hexagonal crystal system. .

[0040] (Embodiment 1) In this embodiment, the configuration of a semiconductor device according to one aspect of the present invention is shown in Figures 1 to 12. I will use it to explain.

[0041] <Transistor Configuration> The following describes the configuration of a transistor as an example of a semiconductor device according to one aspect of the present invention. I will reveal it.

[0042] The configuration of transistor 10 will be explained using Figures 1(A) to 1(C). Figure 1(B) is a top view of transistor 10. Figure 1(B) is a top view of the same transistor as shown by the dashed line A1-A2 in Figure 1(A). These are corresponding cross-sectional views, and Figure 1(C) is a cross-sectional view corresponding to the dashed line A3-A4 in Figure 1(A). In addition, in the region indicated by the dashed line A1-A2, the channel length direction of transistor 10 is The structure is shown, and in the region indicated by the dashed line A3-A4, the transistor 10 This shows the structure in the channel width direction. Note that the channel length direction of a transistor is... Source region or source electrode and drain region or drain electrode ) refers to the direction in which the carrier moves, and the channel width direction is the plane horizontal to the substrate. In this context, it refers to the direction perpendicular to the channel length direction. Also, in Figure 1(A), The edge material 106a, semiconductor 106b, and insulator 106c are similar to the conductors 108a, 108b, etc. They can be installed so that they overlap, but this becomes difficult to see in the top view, so insulator 106a, The semiconductor 106b and the insulator 106c are represented by thin dashed lines, slightly offset from each other.

[0043] Transistor 10 is located on substrate 100, consisting of insulator 101, conductor 102, insulator 105, and an insulating layer. Body 103 and insulator 104, and insulator 106a and semiconductor 106b on insulator 104 The insulator 106c, the conductors 108a and 108b on the semiconductor 106b, and the insulation An insulator 112 on body 106c, a conductor 114 on insulator 112, and an insulating layer on conductor 114 It comprises a rim 116, an insulator 118, a conductor 120a, and a conductor 120b.

[0044] Here, insulator 101, insulator 103, insulator 104, insulator 105, insulator 106a, Insulators 106c, 112, 116, and 118 are insulating films or insulating films. It can also be called a layer. Also, conductor 102, conductor 108a, conductor 108b, conductor 114. Conductors 120a and 120b can also be called conductive films or conductive layers. Furthermore, semiconductor 106b can also be called a semiconductor film or semiconductor layer.

[0045] Furthermore, a configuration without insulator 106a and / or insulator 106c is also possible.

[0046] Furthermore, the configuration includes one or more of the insulators 105, 103, and 104. It is also possible to have a single-layer structure consisting only of insulator 104, or an insulator 103 and an insulating layer. A laminated structure consisting of two layers of edge body 104 may also be used.

[0047] Furthermore, as will be explained in more detail later, when insulators 106a and 106c are used individually, Sometimes materials that can function as conductors or semiconductors are used. However, semiconductors When a transistor is formed by stacking with conductor 106b, the carriers are semiconductor 106b, and semiconductor Near the interface between conductor 106b and insulator 106a, and at the interface between semiconductor 106b and insulator 106c The current flows near the surface, and insulators 106a and 106c form the channel of the transistor. It has regions that do not function. For this reason, in this specification, etc., insulator 106a and Insulator 106c shall be described as an insulator, not as a conductor or semiconductor.

[0048] A conductor 102 is formed on an insulator 101 formed on a substrate 100. At least a portion of 2 overlaps with the insulator 106a, semiconductor 106b and insulator 106c. Furthermore, the insulator 105 is in contact with the conductor 102 and covers the conductor 102. An insulator 103 is formed on top of the insulator 105, and an insulating layer is formed on top of the insulator 103. Body 104 is formed.

[0049] An insulator 106a is formed on the insulator 104, and a semiconductor 1 is in contact with the upper surface of the insulator 106a. 06b is formed. In Figure 1(B), the edges of the insulator 106a and semiconductor 106b are shown. The insulator 106a and semiconductor 106b are formed so that the parts roughly coincide, but in reality The configuration of the semiconductor device shown in the embodiment is not limited to this.

[0050] Conductors 108a and 108b are formed in contact with semiconductor 106b. Conductors 108a and 108b are formed spaced apart, and the source of transistor 10 It can function as both an electrode and a drain electrode.

[0051] An insulator 106c is formed in contact with the semiconductor 106b. The insulator 106c is connected to the conductor 108 It is preferable that the region sandwiched between a and the conductor 108b is in contact with the semiconductor 106b. In 1(B), the insulator 106c roughly covers the upper surfaces of the conductors 108a and 108b. Although it is formed to cover, the configuration of the semiconductor device shown in this embodiment is not limited to this. .

[0052] An insulator 112 is formed on top of the insulator 106c. A conductor 114 is placed on top of the insulator 112. Formed. In Figure 1(B), the ends of insulator 112 and insulator 106c are roughly coincided. As shown, the insulator 112 and the insulator 106c are formed, but the half shown in this embodiment The configuration of the conductor device is not limited to this. Note that the conductor 114 is the gate voltage of transistor 10. It can function as a pole.

[0053] An insulator 116 is formed on the conductor 114 and the insulator 112, and an insulating layer is formed on the insulator 116. A border 118 is formed. Conductors 120a and 120b are formed on the insulator 118. Conductors 120a and 120b are insulators 106c and 112 Through the openings formed in the insulators 116 and 118, the conductor 108a and the conductor It is connected to the power unit 108b.

[0054] Furthermore, any one of conductors 102, 114, 108a, and 108b The above are tungsten and silicon, carbon, germanium, tin, aluminum or nickel. Preferably, the region has one or more elements selected from the genotype.

[0055] In particular, the conductor in the above embodiment has a region having tungsten and silicon. It is preferable to use a conductor that is obtained by RBS. It is preferable that the region has a concentration of 5 atomic% or more and 70 atomic% or less.

[0056] Furthermore, for example, when tungsten is deposited by sputtering, a crystalline conductor is obtained. This can sometimes happen. As a result, the surface flatness of the conductor may deteriorate. However, this development By using a conductor as clearly shown, it is possible to form an amorphous conductor. This makes it possible to form a conductor with good surface flatness.

[0057] Furthermore, the conductor has a region on its surface that contains silicon and oxygen, and this region The thickness is preferably 0.2 nm to 20 nm. This region has a high concentration of silicon and oxygen. It can be a region that contains such a substance, and in that case, the region can function as an insulator. Furthermore, the entire conductor is oxidized as this region functions as an oxygen barrier layer. It can suppress this.

[0058] Conductors 102, 114, 108a, and 108b are provided as described above. By using a conductive material, for example, in the process of manufacturing the transistor 10, Even when exposed to harsh or oxidizing atmospheres, the entire conductor is prevented from oxidizing. It can be controlled. This suppresses the increase in the resistance of the conductor, thus improving performance. Transistors with specific electrical characteristics (such as on-current) can be fabricated.

[0059] <Semiconductors> The following describes the detailed configuration of semiconductor 106b.

[0060] Furthermore, the detailed configuration of the insulators 106a and 106c, along with the semiconductor 106b, will also be described. explain.

[0061] Semiconductor 106b is, for example, an oxide semiconductor containing indium. Semiconductor 106b is, For example, the presence of indium increases the carrier mobility (electron mobility). 106b preferably contains element M. Element M is preferably Ti, Ga, Y, Zr. Let it represent La, Ce, Nd, Sn, or Hf. However, as element M, let it be one of the aforementioned elements. In some cases, multiple combinations are acceptable. For example, element M has a bond energy with oxygen. It is a high-energy element. For example, its bond energy with oxygen is higher than that of indium. Alternatively, element M may have the function of increasing the energy gap of an oxide semiconductor, for example. It is an element. Furthermore, semiconductor 106b preferably contains zinc. Oxide semiconductors contain zinc. The presence of certain substances can sometimes make crystallization more likely.

[0062] However, semiconductor 106b is not limited to indium-containing oxide semiconductors. 6b is, for example, zinc tin oxide, gallium tin oxide, etc., which do not contain indium, sub These include lead-containing oxide semiconductors, gallium-containing oxide semiconductors, tin-containing oxide semiconductors, etc. That's fine.

[0063] For example, insulators 106a and 106c are composed of oxygen other than that which constitutes semiconductor 106b. It is an oxide semiconductor composed of one or more elements, or two or more elements. One or more elements other than oxygen make up insulators 106a and 106 Since c is formed, the interface between the insulator 106a and the semiconductor 106b, and the semiconductor 106b Defect levels are less likely to form at the interface between the insulator 106c and the insulator 106c.

[0064] The insulator 106a, semiconductor 106b, and insulator 106c contain at least indium. This is preferable. Furthermore, when the insulator 106a is In-M-Zn oxide, the sum of In and M is When set to 100 atomic%, preferably In is less than 50 atomic and M is 50 Higher than atomic%, and more preferably less than 25 atomic% of In and 75% of M. It is assumed to be higher than tomic%. Also, when semiconductor 106b is In-M-Zn oxide, When the sum of n and M is taken as 100 atomic%, preferably In is 25 atomic. Higher than %, M is less than 75 atomic%, and more preferably In is 34 atomic% The ratio should be higher, and M should be less than 66 atomic%. Also, the insulator 106c should be In-M-Zn. When it is an oxide, if the sum of In and M is 100 atomic%, preferably In is Less than 50 atomic%, M is higher than 50 atomic%, and more preferably In is 2 Less than 5 atomic%, M should be higher than 75 atomic%. Note that insulator 106c You may use an oxide of the same type as insulator 106a. However, insulator 106a or / And the insulator 106c may not need to contain indium. For example, the insulator 106a and / or insulator 106c may be gallium oxide. The number of atoms of each element contained in material 106a, semiconductor 106b, and insulator 106c is simple The ratio does not need to be an integer. Furthermore, the above composition can be measured, for example, by RBS. stomach.

[0065] For example, when forming a film using the sputtering method, insulator 106a or insulator 106c A typical example of the atomic ratio of metal elements in the target used is In:M:Zn=1:2: 4, In:M:Zn=1:3:2, In:M:Zn=1:3:4, In:M:Zn=1: 3:6, In:M:Zn=1:3:8, In:M:Zn=1:4:3, In:M:Zn= 1:4:4, In:M:Zn=1:4:5, In:M:Zn=1:4:6, In:M:Z n=1:6:3, In:M:Zn=1:6:4, In:M:Zn=1:6:5, In:M :Zn=1:6:6, In:M:Zn=1:6:7, In:M:Zn=1:6:8, In Examples include :M:Zn=1:6:9.

[0066] Furthermore, for example, when depositing a film using the sputtering method, the target used for semiconductor 106b Typical examples of the atomic ratio of metal elements in a net include In:M:Zn=1:1:1, In:M: Zn=1:1:1.2, In:M:Zn=2:1:1.5, In:M:Zn=2:1:2 .3, In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4 Examples include :2:4.1 and In:M:Zn=5:1:7. In particular, sputtering targets When using an atomic ratio of In:Ga:Zn=4:2:4.1, the semiconductor film to be deposited The atomic ratio of 10⁶b can be close to In:Ga:Zn = 4:2:3.

[0067] Furthermore, indium gallium oxide has low electron affinity and high oxygen blocking properties. Therefore, it is preferable that the insulator 106c contains indium gallium oxide. The ratio of particles [Ga / (In+Ga)] is, for example, 70% or more, preferably 80% or more, and further Preferably, it should be 90% or more.

[0068] For semiconductor 106b, for example, an oxide with a large energy gap is used. Semiconductor 106 The energy gap of b is, for example, 2.5 eV to 4.2 eV, preferably 2.8 eV. The voltage should be between eV and 3.8eV, and more preferably between 3eV and 3.5eV. Here, The energy gap of the insulator 106a is larger than the energy gap of the semiconductor 106b. Furthermore, the energy gap of the insulator 106c is the same as the energy gap of the semiconductor 106b. It's bigger than P.

[0069] Semiconductor 106b is an oxide with a higher electron affinity than insulator 106a or insulator 106c. Materials are used. For example, as semiconductor 106b, from insulator 106a and insulator 106c The electron affinity is 0.07 eV to 1.3 eV, preferably 0.1 eV to 0.7 eV. Furthermore, it is more preferable to use an oxide with a voltage of 0.15 eV or more and 0.4 eV or less. Electron affinity is the energy difference between the vacuum level and the lower edge of the conduction band. In other words, an insulator... The energy level at the lower end of the conduction band of 106a or insulator 106c is the same as the conduction of semiconductor 106b. It is closer to the vacuum level than the energy level at the bottom of the belt.

[0070] When a gate voltage is applied at this time, the insulator 106a, semiconductor 106b and insulator 10 Of the 6c elements, channels are formed in semiconductor 106b, which has a high electron affinity. When a voltage is applied, the vicinity of the interface between the insulator 106a and the semiconductor 106b, and the insulator 1 Current may also flow near the interface between the 06c semiconductor and the 106b semiconductor.

[0071] As described above, when insulators 106a and 106c are used individually, they act as conductors and semiconductors. It consists of a material that can function as a body or an insulator. However, semiconductor 10 When 6b is stacked to form a transistor, electrons are located in semiconductor 106b, semiconductor 106b Flows near the interface between semiconductor 106b and insulator 106a, and near the interface between semiconductor 106b and insulator 106c. Insulators 106a and 106c do not function as channels of the transistor. It has a region. For this reason, in this specification and the like, insulator 106a and insulator 106 c shall be described as an insulator, not a semiconductor. Note that insulator 106a and insulation Describing body 106c as an insulator is based solely on its comparison with semiconductor 106b in the transistor. Because it has a function similar to that of an insulator, it is designated as insulator 106a or insulator 106c. In some cases, materials that can be used in semiconductor 106b are also used.

[0072] Here, between the insulator 106a and the semiconductor 106b, It may have a mixed region with . Also, between semiconductor 106b and insulator 106c, It may have a mixed region of semiconductor 106b and insulator 106c. The mixed region is a defect zone. The density of the insulator 106a, semiconductor 106b, and insulator 106c becomes lower. In a laminate, the energy changes continuously near each interface (also known as continuous bonding). This is the band diagram. Note that the insulator 106a and semiconductor 106b, or insulator 106 In some cases, the interfaces between c and semiconductor 106b may not be clearly distinguishable.

[0073] At this time, the electrons are not in the insulator 106a and insulator 106c, but in semiconductor 106b. It mainly moves through the inside. As mentioned above, at the interface between the insulator 106a and the semiconductor 106b The defect level density, and the defect level density at the interface between semiconductor 106b and insulator 106c. By lowering the degree, the movement of electrons in semiconductor 106b is less inhibited. This allows for an increase in the on-current of the transistor.

[0074] Furthermore, the on-current of a transistor should be increased as the factors that hinder electron movement are reduced. For example, if there are no factors hindering electron movement, electrons can move efficiently. It is presumed that electron movement occurs, for example, when the physical irregularities of the channel-forming region are large. This is also inhibited.

[0075] To increase the on-current of the transistor, for example, the top or bottom surface of semiconductor 106b (The surface to be formed, in this case the upper surface of the insulator 106a) in a 1 μm × 1 μm area square The root mean square (RMS) roughness is less than 1 nm, preferably. Less than 0.6 nm, more preferably less than 0.5 nm, and more preferably less than 0.4 nm. It is sufficient if the average surface roughness (also called Ra) in a 1 μm × 1 μm area is 1 nm. Less than, preferably less than 0.6 nm, more preferably less than 0.5 nm, more preferably 0 It should be less than 0.4 nm. Also, the maximum height difference (PV and Also called.) is less than 10 nm, preferably less than 9 nm, more preferably less than 8 nm, Preferably, it should be less than 7 nm. RMS roughness, Ra, and PV are SII. Using the Nanotechnology Co., Ltd. scanning probe microscope system SPA-500, etc. It can be measured.

[0076] Furthermore, in order to increase the on-current of the transistor, the thickness of the insulator 106c should be as small as possible. It is preferable. The thickness of the insulator 106c is smaller than the thickness of the insulator 106a and smaller than the thickness of the semiconductor 106b is preferably. For example, it may be an insulator 106c having a region of less than 10 nm, preferably 5 nm or less, and more preferably 3 nm or less. On the other hand, the insulator 10 6c has a function of blocking the entry of elements other than oxygen (such as hydrogen and silicon) that constitute the adjacent insulator into the semiconductor 106b where the channel is formed. Therefore, the insulator 106c preferably has a certain thickness. For example, it may be an insulator 106 c having a region with a thickness of 0.3 nm or more, preferably 1 nm or more, and more preferably 2 nm or more. In addition, in order to improve reliability, the insulator 106a is preferably thick. For example, it may be an insulator 106a having a region with a thickness of 10 nm or more, preferably 20 nm or more, more preferably 40 nm or more, and even more preferably 6 0 nm or more. By increasing the thickness of the insulator 106a, the distance from the interface between the adjacent insulator and the insulator 106a to the semiconductor 106b where the channel is formed can be increased. However, since the productivity of the semiconductor device may decrease, for example, it may be an insulator 106a having a region with a thickness of 200 nm or less, preferably 120 nm or less, and more preferably

[0077] 80 nm or less. Silicon in the oxide semiconductor may become a carrier trap or a carrier generation source. Therefore, the lower the silicon concentration of the semiconductor 106b, the better. For example, between the semiconductor 106b and the insulator 106a, for example, in secondary ion mass spectrometry (SIMS), 1× 10 atoms / cm There may be cases where the productivity of the semiconductor device decreases. Therefore, for example, it may be an insulator 106a having a region with a thickness of 200 nm or less, preferably 120 nm or less, and more preferably 80 nm or less.

[0078] Silicon in the oxide semiconductor may become a carrier trap or a carrier generation source. Therefore, the lower the silicon concentration of the semiconductor 106b, the better. For example, between the semiconductor 106b and the insulator 106a, for example, in secondary ion mass spectrometry (SIMS), 1× 10 10 16 atoms / cm3 above 1×10 19 atoms / cm 3 below, preferably 1× 10 16 atoms / cm 3 above 5×10 18 atoms / cm 3 below, more preferably is 1×10 16 atoms / cm 3 above 2×10 18 atoms / cm 3 below of silicon has a concentration region. Also, between the semiconductor 106b and the insulator 106c, in SIMS where, 1×10 16 atoms / cm 3 above 1×10 19 atoms / cm 3 below, preferably is 1×10 16 atoms / cm 3 above 5×10 18 atoms / cm 3 below, further more preferably 1×10 16 atoms / cm 3 above 2×10 18 atoms / cm 3 below has a silicon concentration region.

[0079] Also, in order to reduce the hydrogen concentration of the semiconductor 106b, it is preferable to reduce the hydrogen concentrations of the insulator 106a and the insulator 106 c. The insulator 106a and the insulator 106c are, in SIMS where, 1×10 16 atoms / cm 3 above 2×10 20 atoms / cm 3 below, preferably 1×10 16 atoms / cm 3 above 5×10 19 atoms / cm 3 below, more preferably 1×1016 atoms / cm 3 The above 1 x 10 19 atoms / cm 3 Below Below, more preferably 1 × 10 16 atoms / cm 3 The above 5 x 10 18 ate / c m 3 It has a region with the following hydrogen concentrations. Also, to reduce the nitrogen concentration of semiconductor 106b Therefore, it is preferable to reduce the nitrogen concentration of insulators 106a and 106c. Insulator 1 06a and insulator 106c are 1 × 10 in SIMS. 15 atoms / cm 3 Below Top 5×10 19 atoms / cm 3 The following is preferably 1 × 10 15 atoms / cm 3 Below Top 5×10 18 atoms / cm 3 More preferably 1 × 10 15 atoms / cm 3 The above 1 x 10 18 atoms / cm 3 More preferably 1 × 10 15 atoms / cm 3 The above 5 x 10 17 atoms / cm 3 It has a region with the following nitrogen concentrations.

[0080] The insulator 106a, semiconductor 106b, and insulator 106c shown in this embodiment, particularly the semiconductor 106b is an oxide semiconductor with a low impurity concentration and low defect level density (few oxygen vacancies). It can be called a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. Oxide semiconductors that are highly intrinsic or substantially high-purity intrinsic have few carrier sources, The carrier density can be lowered. Therefore, a channel region is formed in the oxide semiconductor. Transistors exhibit an electrical characteristic where the threshold voltage is negative (also known as normally-on). It rarely becomes . Also, oxide semiconductors that are high-purity intrinsic or substantially high-purity intrinsic Because the body has a low defect level density, the trap level density may also be low. Intrinsic or substantially high-purity intrinsic oxide semiconductors have remarkably low off-currents and channels The width W is 1 x 10 6 Even with a device with a channel length L of 10 μm in μm, the source electrode and drain When the voltage between the in-electrode (drain voltage) is in the range of 1V to 10V, the off-current is semiconductor Below the measurement limit of the body parameter analyzer, i.e., 1 × 10⁻⁶ -13 It acquires the characteristic of being A or less. It is possible.

[0081] Therefore, the above-mentioned high-purity intrinsic, or substantially high-purity intrinsic oxide semiconductor has a channel region Transistors formed in this manner exhibit small fluctuations in electrical characteristics and are highly reliable transistors. This is possible. Furthermore, charges trapped in the trap levels of an oxide semiconductor will remain trapped until they disappear. The time required is long, and it can behave as if it were a fixed charge. Therefore, Transistors in which a channel region is formed in an oxide semiconductor with a high level density have electrical properties Instability may occur. Impurities that form trap levels in oxide semiconductors include water. These include elements such as nitrogen, alkali metals, or alkaline earth metals.

[0082] The hydrogen contained in insulator 106a, semiconductor 106b, and insulator 106c bonds with metal atoms. It reacts with oxygen to form water, and the lattice (or the part from which oxygen has been removed) also reacts with the oxygen to form water. An oxygen deficiency is formed in (0). When hydrogen enters this oxygen deficiency, carriers, i.e., electrons, may be generated. Also, a part of the hydrogen may combine with oxygen that binds to metal atoms to generate carriers, i.e., electrons. In particular, hydrogen trapped by the oxygen deficiency may form shallow donor levels with respect to the band structure of the semiconductor. Therefore, a transistor using a hydrogen-containing oxide semiconductor tends to have normally-on characteristics. For this reason, it is preferable that the insulator 106a, the semiconductor 106b, and the insulator 106c have as little hydrogen as possible. Specifically, in the insulator 106a, the semiconductor 106b, and the insulator 106c, the hydrogen concentration obtained by SIMS is 2×10 atoms / cm or less, preferably 5 ×10 atoms / cm or less, more preferably 1×10 atoms / cm or less, 5×10 20 atoms / cm 3 or less, preferably 1×10 ×10 19 atoms / cm 3 or less, more preferably 5×10 19 atoms / cm 3 or less, preferably 1×10 ×10 18 atoms / cm 3 or less, more preferably 5×10 18 atoms / cm 3 or less, more preferably 1×l0 17 atoms / cm 3 or less, still more preferably 1×10 16 atoms / cm 3 or less.

[0083] If silicon or carbon, which is one of the Group 14 elements, is contained in the insulator 106a, the semiconductor 106b, and the insulator 106c, the oxygen deficiency increases in the insulator 106a, the semiconductor 106b, and the insulator 106 c, resulting in n-type conversion. For this reason, the concentration of silicon or carbon in the insulator 106a, the semiconductor 106b, and the insulator 106c, and the insulator 106a, the semiconductor 106b and the insulator 106 c Concentrations of silicon and carbon near the interface between 106b and the insulator 106c (obtained by SIMS) (The concentration that can be achieved) 2 × 10 18 atoms / cm 3 The following is preferably 2 × 10 17 ato ms / cm 3 The following applies:

[0084] Furthermore, in the insulator 106a, semiconductor 106b, and insulator 106c, SIMS The resulting alkali metal or alkaline earth metal concentration is 1 × 10⁻⁶ 18 atoms / cm 3 The following is preferably 2 × 10 16 atoms / cm 3 The following applies: Alkali metals and Lucali earth metals can generate carriers when they bond with oxide semiconductors, and transients The off-current of the sta may increase. For this reason, the insulator 106a and semiconductor 106 The concentration of alkali metals or alkaline earth metals in b and insulator 106c can be reduced. preferable.

[0085] Furthermore, if nitrogen is present in the insulator 106a, semiconductor 106b, and insulator 106c, Electrons, which act as carriers, are generated, increasing the carrier density and making it easier to become n-type. As a result, nitrogen Transistors using oxide semiconductor films containing these materials tend to exhibit normally-on characteristics. Therefore, it is preferable that nitrogen is reduced as much as possible in the oxide semiconductor film. For example, the nitrogen concentration obtained by SIMS is 5 × 10⁻⁶ 18 atoms / cm 3 Below It is preferable to do so.

[0086] Here, Figure 1(D) shows an enlarged cross-sectional view of the vicinity of the center of the insulator 106a and semiconductor 106b. As shown in Figures 1(B) and 1(D), the conductor 108a and of semiconductor 106b A low-resistance region is formed in the area in contact with the conductor 108b (shown as a dotted line in Figures 1(B) and 1(D)). Region 109a and low-resistance region 109b may be formed. The low-resistance region 109b is the conductor 108a or conductor 108b that the semiconductor 106b is in contact with. The conductive material from which oxygen is extracted, or which is contained in conductor 108a or conductor 108b This can be formed by bonding with elements in semiconductor 106b. The formation of the resistance region 109a and the low resistance region 109b results in the conductor 108a and This makes it possible to reduce the contact resistance between the conductor 108b and the semiconductor 106b, so The on-current of Zistor 10 can be increased.

[0087] Also, although not shown in the diagram, the insulator 106c and the conductor 108a or conductor 108b Low-resistance regions may also be formed in the contact areas. Furthermore, in the following drawings... Similar dotted lines indicate low-resistance regions.

[0088] Furthermore, as shown in Figure 1(D), semiconductor 106b is composed of conductor 108a and conductor 108b There is a region in between that has a thinner film thickness than the region overlapping with conductors 108a and 108b. This is because when forming the conductor 108a and conductor 108b, the semiconductor 106 It is formed by removing a portion of the upper surface of b. The upper surface of semiconductor 106b has a conductor 1 When a conductive film is formed to form 08a and conductor 108b, the low-resistance region 109a and 1 A region with low resistance similar to 09b may be formed. In this way, semiconductor 106b By removing the region located between the upper conductive material 108a and conductive material 108b, the semiconductor This prevents channels from forming in low-resistance regions on the upper surface of body 106b. Furthermore, in subsequent drawings, even if areas with thin film thickness are not shown in enlarged views, the same film thickness will be used. A thin area may be formed.

[0089] Note that the three-layer structure of insulator 106a, semiconductor 106b, and insulator 106c described above is just one example. Yes, there is. For example, a two-layer structure without either insulator 106a or insulator 106c. This may also be done. Furthermore, a single-layer structure without both insulator 106a or insulator 106c may be provided. Alternatively, they may be exemplified as insulator 106a, semiconductor 106b, or insulator 106c. An n-layer structure (where n is an integer of 4 or more) having either an insulator, semiconductor, or conductor. That's fine.

[0090] <Oxide semiconductor structure> The structure of oxide semiconductors will be described below.

[0091] Oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (c-axis-aligned (crystalline oxide semiconductor), polycrystalline oxide Semiconductors, nc-OS (nanocrystalline oxide semiconductor) uctor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous-l Examples include oxide semiconductors and amorphous oxide semiconductors. ru.

[0092] From another perspective, oxide semiconductors include amorphous oxide semiconductors and other crystalline oxide semiconductors. It can be divided into conductors and crystalline oxide semiconductors. As for crystalline oxide semiconductors, there are single-crystal oxide semiconductors, CAAC- Examples include OS, polycrystalline oxide semiconductors, and nc-OS.

[0093] Amorphous structures are generally isotropic and lack heterogeneous structures, representing a metastable state of atomic arrangement. It is not fixed, the bonding angle is flexible, and it has short-range order but not long-range order. It is said that...

[0094] In other words, a stable oxide semiconductor is completely amorphous. ) It cannot be called an oxide semiconductor. Also, it is not isotropic (for example, periodic structure in a minute region). Oxide semiconductors (which have a structure) cannot be called perfectly amorphous oxide semiconductors. On the other hand, a-li ke OS is an unstable structure that is not isotropic but contains voids (also called porous structures). In terms of instability, a-like OSs are physically similar to amorphous oxide semiconductors. .

[0095] <caac-os> First, let me explain CAAC-OS.

[0096] CAAC-OS is an oxide semiconductor having multiple c-axis oriented crystalline portions (also called pellets). It is a type of conductor.

[0097] CAAC-OS can be analyzed by X-ray diffraction (XRD). Let's explain the case of analysis. For example, InGaZnO4, which is classified as space group R-3m Structural analysis of crystalline CAAC-OS is performed using the out-of-plane method. As shown in Figure 2(A), a peak appears near 31° at the diffraction angle (2θ). Since it is attributed to the (009) plane of the InGaZnO4 crystal, CAAC-OS The crystal has c-axis orientation, and the c-axis is the surface that forms the CAAC-OS film (also called the surface to be formed). It can be confirmed that it is facing in a direction approximately perpendicular to the top surface. Note that 2θ is close to 31°. In addition to the nearby peak, a peak may also appear near 2θ = 36°. The peak is due to a crystal structure classified as space group Fd-3m. Therefore, CAAC- It is preferable that the OS does not show this peak.

[0098] On the other hand, in CAAC-OS, X-rays are incident from a direction parallel to the surface being formed. Structural analysis using the ne method reveals a peak near 2θ = 56°. This peak corresponds to I It is attributed to the (110) plane of the nGaZnO4 crystal. Then, 2θ is fixed near 56°. The analysis (φ-scan) is performed while rotating the sample around the normal vector of the sample surface as the axis (φ-axis). Even when this is done, no clear peak appears, as shown in Figure 2(B). On the other hand, single crystal InGaZn When φ scanning is performed with O4 while fixing 2θ to approximately 56°, as shown in Figure 2(C) Six peaks are observed that belong to a crystal plane equivalent to the (110) plane. Therefore, XRD Structural analysis using this method revealed that the orientation of the a-axis and b-axis of CAAC-OS is irregular. It can be confirmed.

[0099] Next, we will explain CAAC-OS analyzed by electron diffraction. For example, InGaZ For CAAC-OS having nO4 crystals, a probe is applied parallel to the surface of the CAAC-OS being formed. When an electron beam with a diameter of 300 nm is incident, a diffraction pattern like the one shown in Figure 2(D) (limitation) is observed. This is also called a field-of-view electron diffraction pattern. Sometimes, this diffraction pattern may appear. The spots include those originating from the (009) plane of the aZnO4 crystal. Therefore, electron diffraction Furthermore, the pellets contained in CAAC-OS have c-axis orientation, and the c-axis is aligned with the surface to be formed. It can be seen that it is oriented in a direction that is approximately perpendicular to the upper surface. On the other hand, for the same sample, perpendicular to the sample surface Figure 2(E) shows the diffraction pattern when an electron beam with a probe diameter of 300 nm is directly incident on the probe. Figure 2(E) shows a ring-shaped diffraction pattern. Therefore, the probe diameter is Electron diffraction using a 300 nm electron beam also revealed the pellets contained in CAAC-OS. It can be seen that the a-axis and b-axis do not have orientation. Note that the first ring in Figure 2(E) This is thought to be due to the (010) and (100) planes of the InGaZnO4 crystal. Furthermore, the second ring in Figure 2(E) is thought to be caused by the (110) plane, etc. .

[0100] Furthermore, a transmission electron microscope (TEM) A composite image of the bright-field image and diffraction pattern of CAAC-OS obtained by (croscope) analysis. When observing a high-resolution TEM image (also known as a TEM image), multiple pellets can be identified. On the other hand, even in high-resolution TEM images, the boundaries between pellets, i.e., grain boundaries, are not visible. Also called "Nandaly." ) There are cases where it is not possible to clearly confirm this. Therefore, CAAC -OS can be said to be less prone to the decrease in electron mobility caused by grain boundaries.

[0101] Figure 3(A) shows a high-resolution TE of the cross-section of CAAC-OS observed from a direction approximately parallel to the sample surface. The M image is shown. For observing high-resolution TEM images, spherical aberration correction (Spherical Abe) is used. The (Aberration Corrector) function was used. High resolution using spherical aberration correction function. High-resolution TEM images are specifically called Cs-corrected high-resolution TEM images. For example, using an atomic resolution analytical electron microscope such as the JEM-ARM200F manufactured by JEOL Ltd. It can be observed.

[0102] From Figure 3(A), we can see the pellet, which is a region in which metal atoms are arranged in layers. It can be done. It has been found that the size of a single pellet can be 1 nm or larger, or 3 nm or larger. Therefore, pellets can also be called nanocrystals (nc). Yes, it is possible. Also, CAAC-OS can be used with CANC (C-Axis Aligned nano It can also be called an oxide semiconductor having crystals. The pellet is CAAC- It reflects the unevenness of the surface or top surface of the OS, and the surface or top surface of the CAAC-OS It will be parallel to this.

[0103] Furthermore, Figures 3(B) and 3(C) show CAAC-O observed from a direction approximately perpendicular to the sample surface. Figures 3(D) and 3(E) show Cs-corrected high-resolution TEM images of the plane of S. These are images obtained by image processing from Figures 3(B) and 3(C). The image processing method is described below. Let me explain. First, Figure 3(B) shows the Fast Fourier Transform (FFT). The FFT image is obtained by performing a Transform operation on the obtained FFT image. With the origin as the reference point, 2.8nm -1 from 5.0nm -1 Masking process leaves the area between them intact. Next, the masked FFT image is subjected to the inverse Fast Fourier Transform (IFFT). The image processed by applying Fast Fourier Transform (FFT) is obtained. This is advantageous. The image obtained in this way is called an FFT filtered image. FFT filtered image This image is an image obtained by extracting the periodic component from a Cs-corrected high-resolution TEM image, and shows the grid arrangement. ru.

[0104] In Figure 3(D), areas where the grid arrangement is disordered are indicated by dashed lines. The area enclosed by the dashed lines is one These are two pellets. The dotted lines indicate the connections between the pellets. The dashed line indicates a hexagonal shape, showing that the pellet is hexagonal. The shape of the toe is not necessarily a regular hexagon; it is often a non-regular hexagon.

[0105] In Figure 3(E), a dotted line is drawn between a region with a aligned grid arrangement and another region with a aligned grid arrangement. This indicates that even near the dotted line, a clear grain boundary cannot be confirmed. Connecting the surrounding grid points to the center of a grid point results in a distorted hexagon, or a pentagon and / or heptagon. These can be formed. In other words, the formation of grain boundaries is suppressed by distorting the lattice arrangement. This can be seen. This is because CAAC-OS has a non-dense atomic arrangement in the ab-plane direction. Due to factors such as the substitution of metal elements, which changes the bond distance between atoms, strain occurs. This is thought to be because it allows for tolerance.

[0106] As described above, CAAC-OS has c-axis orientation and multiple properties in the ab-plane direction. A number of pellets (nanocrystals) are linked together, forming a distorted crystalline structure. Therefore, CA AC-OS, CAA crystal(c-axis-aligned ab-pl It can also be called an oxide semiconductor having an anchored crystal. ru.

[0107] CAAC-OS is a highly crystalline oxide semiconductor. The crystallinity of oxide semiconductors depends on the presence of impurities. CAAC-OS may decrease due to impurities and defects ( It can be described as an oxide semiconductor with few oxygen vacancies, etc.

[0108] Impurities are elements other than the main components of oxide semiconductors, such as hydrogen, carbon, silicon, and transition metals. There are elements, for example. For instance, oxygen is more abundant than the metallic elements that make up oxide semiconductors such as silicon. Elements with strong bonding forces can alter the atomic arrangement of oxide semiconductors by removing oxygen from them. It disrupts the crystallinity and causes a decrease in its properties. Also, heavy metals such as iron and nickel, argon, and nickel... Because carbon oxides and other elements have a large atomic radius (or molecular radius), they affect the atomic arrangement of oxide semiconductors. This disrupts the crystallinity and reduces its properties.

[0109] When the oxide semiconductor has impurities or defects, its characteristics may vary due to light, heat, etc. For example, impurities contained in the oxide semiconductor may become carrier traps or carrier generation sources. For example, oxygen deficiencies in the oxide semiconductor may become carrier traps or may become carrier generation sources by capturing hydrogen.

[0110] CAAC-OS with few impurities and oxygen deficiencies is an oxide semiconductor with a low carrier density. Specifically, it is less than 8×10 11 / cm 3 , preferably less than 1×10 11 / cm 3 and more preferably less than 1×10 / cm 10 / cm 3 and can be an oxide semiconductor with a carrier -9 density of 1×10 3 / cm or higher. Such an oxide semiconductor is called a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. CAAC-OS has a low impurity concentration and a low defect level density. That is, it can be said that it is an oxide semiconductor having stable characteristics.

[0111] <nc-os> Next, I will explain nc-OS.

[0112] This section describes the case of analyzing nc-OS using XRD. For example, for nc-OS When structural analysis is performed using the out-of-plane method, no peaks indicating orientation appear. In other words, nc-OS crystals do not have orientation.

[0113] Furthermore, for example, nc-OS having an InGaZnO4 crystal is thinned to a thickness of 34 nm. When an electron beam with a probe diameter of 50 nm is incident on the region parallel to the surface to be formed, Figure 4( A ring-shaped diffraction pattern (nanobeam electron diffraction pattern) as shown in A) is observed. Furthermore, the diffraction pattern (nano) when an electron beam with a probe diameter of 1 nm is incident on the same sample. The beam electron diffraction pattern is shown in Figure 4(B). From Figure 4(B), multiple electrons are observed within the ring-shaped region. A number of spots are observed. Therefore, nc-OS is an electron beam with a probe diameter of 50 nm. Order is not observed when an electron beam with a probe diameter of 1 nm is incident. This confirms order.

[0114] Furthermore, when an electron beam with a probe diameter of 1 nm is incident on a region with a thickness of less than 10 nm, As shown in Figure 4(C), an electron diffraction pattern was observed in which the spots were arranged in a roughly regular hexagonal shape. In some cases, this may occur. Therefore, in the range of thickness less than 10 nm, nc-OS is ordered. It can be seen that there is a region with high density, i.e., that it has crystals. Note that the crystals are oriented in various directions. However, there are also regions where a regular electron diffraction pattern is not observed.

[0115] Figure 4(D) shows the Cs-corrected high-resolution cross-section of nc-OS observed from a direction approximately parallel to the surface being formed. The image shows a high-resolution TEM image. nc-OS is used in high-resolution TEM images, such as the areas indicated by the auxiliary lines. Regions where the crystalline structure can be observed, and regions where the crystalline structure cannot be clearly observed. It has a region and a crystal portion contained in nc-OS, which is between 1 nm and 10 nm in size. Furthermore, they are often between 1 nm and 3 nm in size. Oxide semiconductors with a wavelength greater than nm but less than 100 nm are called microcrystalline oxide semiconductors (micro It is sometimes called a crystalline oxide semiconductor. nc-OS may, for example, make it difficult to clearly identify grain boundaries in high-resolution TEM images. Yes. Furthermore, the nanocrystals may share the same origin as the pellets in CAAC-OS. Yes, it exists. Therefore, in the following, the crystalline portion of nc-OS may be referred to as a pellet.

[0116] Thus, nc-OS is suitable for minute regions (for example, regions between 1 nm and 10 nm, particularly The atomic arrangement has periodicity in the region between 1 nm and 3 nm. Furthermore, nc-OS is Furthermore, no regularity is observed in the crystal orientation between different pellets. Therefore, orientation is not observed throughout the entire film. Therefore, nc-OS can be analyzed using methods that produce a-like OS or amorphous OS. It can sometimes be indistinguishable from oxide semiconductors.

[0117] Furthermore, since there is no regularity in the crystal orientation between pellets (nanocrystals), nc-OS is used. Oxides containing RANC (Random Aligned nanocrystals) semiconductors, or containing NANC (Non-Aligned nanocrystals) It can also be called an oxide semiconductor.

[0118] nc-OS is an oxide semiconductor with higher orderliness than amorphous oxide semiconductors. Therefore, nc-OS has a lower defect level density than a-like OS and amorphous oxide semiconductors. However, nc-OS does not show any regularity in crystal orientation between different pellets. nc-OS has a higher defect level density compared to CAAC-OS.

[0119] <a-like OS> a-like OS is an oxide semiconductor having a structure between nc-OS and amorphous oxide semiconductors. It is a conductor.

[0120] Figure 5 shows a high-resolution cross-sectional TEM image of an a-like OS. Here, Figure 5(A) shows electron This is a high-resolution cross-sectional TEM image of a-like OS at the start of irradiation. Figure 5(B) is 4 0.3×10 8 e - / nm 2 electrons (e - ) High resolution of a-like OS after irradiation These are cross-sectional TEM images. From Figures 5(A) and 5(B), it can be seen that a-like OS is electron-irradiated. From the start, it can be seen that striped light regions extending in the vertical direction are observed. Also, the light regions are It can be seen that the shape changes after electron irradiation. Note that the bright areas are presumed to be porous or low-density areas. It is measured.

[0121] Because it has porosity, a-like OS has an unstable structure. Below, a-like To demonstrate that the OS has a less stable structure compared to CAAC-OS and nc-OS. This shows the structural changes caused by electron irradiation.

[0122] As samples, prepare a-like OS, nc-OS, and CAAC-OS. The sample is also an In-Ga-Zn oxide.

[0123] First, obtain high-resolution cross-sectional TEM images of each sample. From the high-resolution cross-sectional TEM images, each sample has a crystalline part.

[0124] Note that the unit cell of the InGaZnO4 crystal has three In-O layers and six Ga-Zn- O layers, and it is known to have a structure in which a total of nine layers overlap in the c-axis direction in a layered manner. The distance between these adjacent layers is approximately the same as the lattice plane spacing of the (009) plane (also referred to as the d value). From crystal structure analysis, the value is determined to be 0.29 nm. Therefore, hereinafter, a portion where the lattice fringe spacing is between 0.28 nm and 0.30 nm is regarded as the crystalline part of InGaZn O4. Note that the lattice fringes correspond to the a-b plane of the InGaZnO4 crystal. O4.

[0125] Figure 6 shows an example of investigating the average size of the crystalline parts (22 to 30 locations) of each sample. Note that the length of the above-described lattice fringes is regarded as the size of the crystalline part. From Figure 6, it can be seen that for a-like O S, the crystalline part grows as the cumulative irradiation dose of electrons related to the acquisition of the TEM image and the like increases. From Figure 6, it can be seen that at the initial stage of observation by TEM, the crystalline part (also referred to as the initial nucleus), which was about 1.2 nm in size, grows to about 1.9 nm in size when the cumulative irradiation dose of electrons (e - ) reaches 4.2×10 8 e - / nm 2 . On the other hand, for nc-OS and CAAC-OS, it can be seen that there is no change in the size of the crystalline part within the range where the cumulative irradiation dose of electrons reaches 4.2×10 8 e - / nm 2 from the start of electron irradiation. From Figure 6, electrons​​ Regardless of the cumulative irradiation dose, the size of the crystal portion of nc-OS and CAAC-OS is, It can be seen that the wavelengths are approximately 1.3 nm and 1.8 nm. Furthermore, electron beam irradiation and TE (electron beam irradiation) were performed. Observation of M was performed using a Hitachi transmission electron microscope H-9000NAR. The electron beam irradiation conditions were accelerated. Voltage 300kV, current density 6.7 × 10 5 e - / (nm 2 ·s), the diameter of the irradiation area The wavelength was set to 230nm.

[0126] Thus, in a-like OS, crystalline growth can sometimes be observed upon electron irradiation. On the other hand, nc-OS and CAAC-OS show almost no crystal growth due to electron irradiation. It cannot be seen. In other words, a-like OS is different from nc-OS and CAAC-OS. It is clear that the structure is unstable.

[0127] Furthermore, because it has porosity, a-like OS is superior to nc-OS and CAAC-OS. It has a low-density structure. Specifically, the density of a-like OS is the same as that of a single crystal of the same composition. The density is between 78.6% and 92.3%. Also, the density of nc-OS and CAAC - The density of OS is between 92.3% and 100% of the density of a single crystal of the same composition. Oxide semiconductors with a density of less than 78% are inherently difficult to deposit.

[0128] For example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio], The density of single-crystal InGaZnO4 with a faceted crystal structure is 6.357 g / cm³. 3 That's right. For example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio] The density of a-like OS is 5.0 g / cm³. 3 More than 5.9g / cm 3 It is less than. For example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio], The density of nc-OS and CAAC-OS is 5.9 g / cm³. 3 More than 6.3g / cm 3 It is less than.

[0129] If single crystals with the same composition do not exist, single crystals with different compositions can be combined in any proportion. By doing so, the density equivalent to a single crystal at the desired composition can be estimated. The density corresponding to a single crystal of the desired composition is, with respect to the ratio of single crystals with different compositions combined, The density can be estimated using a weighted average. However, the density should be calculated using as few types of single crystals as possible. It is preferable to estimate by combining the costs.

[0130] As described above, oxide semiconductors can take on various structures, each possessing a variety of properties. Oxide semiconductors include, for example, amorphous oxide semiconductors, a-like OS, nc-OS, The multilayer film may have two or more types of CAAC-OS.

[0131] <Substrates, insulators, conductors> The following provides a detailed explanation of each component of transistor 10 other than the semiconductor.

[0132] The substrate 100 may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of substrates include glass substrates, quartz substrates, sapphire substrates, and stabilized zirconia groups. These include plates (such as yttria-stabilized zirconia substrates) and resin substrates. Also, semiconductor substrates and For example, single semiconductor substrates such as silicon and germanium, or silicon carbide, Silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, etc. These include semiconductor substrates. Furthermore, there are semiconductors that have an insulating region inside the aforementioned semiconductor substrate. There are substrates, such as SOI (Silicon On Insulator) substrates. Examples of electrolytic substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. These include substrates containing metallic nitrides and substrates containing metallic oxides. Furthermore, insulators A substrate on which a conductor or semiconductor is provided, a semiconductor substrate on which a conductor or insulator is provided These include substrates, conductive substrates, and substrates on which semiconductors or insulators are provided. A substrate on which elements are provided may also be used. The elements provided on the substrate may include capacitance Examples include elements, resistive elements, switch elements, light-emitting elements, and memory elements.

[0133] Furthermore, the substrate 100 is a flexible substrate that can withstand the heat treatment during transistor fabrication. This may also be done. Furthermore, as a method for mounting transistors on a flexible substrate, a non-flexible substrate may be used. After fabricating the transistor on the board, the transistor is removed from the flexible substrate 10 Another method is to transpose it to 0. In that case, a delamination layer is formed between the non-flexible substrate and the transistor. It is advisable to provide this. The substrate 100 may be a sheet, film, or foil with woven fibers. The following may be used. Furthermore, the substrate 100 may be stretchable. Also, the substrate 100 may be It may have the property of returning to its original shape when the bending or pulling is stopped. It may have the property of not returning to its original state. The thickness of the substrate 100 is, for example, 5 μm to 700 μm. Preferably, 10 μm to 500 μm, and more preferably 15 μm to 300 μm The thickness should be less than or equal to m. Making the substrate 100 thinner allows for a lighter semiconductor device. Also, By making the substrate 100 thinner, it may have elasticity even when using glass or other materials, or it may be foldable. It may have the property of returning to its original shape when bending or pulling is stopped. Therefore, when it falls... This makes it possible to mitigate shocks and other impacts applied to the semiconductor device on the substrate 100. This allows us to provide robust semiconductor devices.

[0134] The flexible substrate 100 can be, for example, a metal, alloy, resin, or glass. Alternatively, those fibers can be used. The substrate 100, which is a flexible substrate, undergoes linear expansion. A lower ratio is preferable as it suppresses deformation due to the environment. The substrate 100 is a flexible substrate. For example, the coefficient of thermal expansion is 1 × 10⁻⁶. -3 / K or less, 5×10 -5 / K or less, or 1×1 0 -5 Any material with a K value of 0.5 or less should be used. Examples of resins include polyester and poly Olefins, polyamides (nylon, aramid, etc.), polyimides, polycarbonates, Examples include acrylic. In particular, aramid has a low coefficient of thermal expansion, making it suitable for flexible substrates. A value of 100 is preferable.

[0135] The insulator 101 uses an insulator that has the function of blocking hydrogen or water. 6a, semiconductor 106b, hydrogen and water in the insulator located near the insulator 106c, 106a, semiconductor 106b, and insulator 106c are among the factors that generate carriers. This may reduce the reliability of transistor 10, especially substrate 10. When using a substrate on which silicon-based semiconductor elements such as switch elements are provided as 0, the semiconductor Hydrogen is used to terminate the dangling bonds of the body element, and this hydrogen is used in the transistor. It may diffuse up to 10. It has the function to block hydrogen or water in response to this. By providing the insulator 101, hydrogen or water diffuses from the lower layer of the transistor 10. This suppresses the noise and improves the reliability of the transistor 10. The insulator 101 is an insulating material. It is preferable that the body 105 or the insulator 104 is less permeable to hydrogen or water.

[0136] Furthermore, it is preferable that the insulator 101 also has the function of blocking oxygen. By blocking the oxygen diffusing from the insulator 104, for example, from the insulator 104 It is possible to effectively supply oxygen to the insulator 106a, semiconductor 106b, and insulator 106c. ru.

[0137] Examples of insulators 101 include aluminum oxide, aluminum oxide and nitride, and gallium oxide. M, gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafnium oxide, acid Hafnium nitride and the like can be used. By using these as insulator 101, It can function as an insulating film that blocks the diffusion of oxygen, hydrogen, or water. It can be done. Also, as the insulator 101, for example, silicon nitride, silicon oxide nitride, etc. can be used. This can be done. By using these as insulators 101, the diffusion of hydrogen and water can be blocked. It can function as an insulating film that exhibits a locking effect.

[0138] The conductor 102 is in a region where at least a portion is sandwiched between the conductors 108a and 108b. It is preferable that it overlaps with semiconductor 106b. Conductor 102 is the battery of transistor 10 It functions as a gate. By providing such a conductor 102, transistor 1 It is possible to control the threshold voltage to 0. It is also used for injecting charge into the insulator 103. It is possible to control the threshold voltage of transistor 10's gate. When the voltage applied to (conductor 114) is low, for example, when the applied voltage is 0V or less, This prevents transistor 10 from becoming conductive. This makes it easier to shift the electrical characteristics towards a more normally-off state.

[0139] The conductor 102 includes tungsten, silicon, carbon, germanium, tin, and aluminum. Using a conductor having a region containing one or more elements selected from nium or nickel This is sufficient. In particular, a conductor having tungsten and silicon is preferred. Furthermore, R The silicon concentration obtained by BS is between 5 atomic% and 70 atomic%. Preferably, it has a region, and the silicon concentration is 10 atomic% or more and 60 atomic% or less. It is even more preferable if it has a region below. The conductor 102 is, for example, an alloy or a compound. It may be formed as a single layer or in layers.

[0140] Furthermore, the conductor 102 has a region on its surface that contains silicon and oxygen. The thickness of the region is preferably 0.2 nm or more and 20 nm or less. The region is composed of silicon and acid. It can be a region containing many elements, in which case the region functions as an insulator. This can be achieved. Furthermore, the entire conductor is oxidized as this region functions as a barrier layer. It can suppress this.

[0141] Furthermore, the conductor 102 can be deposited by sputtering. Alternatively, metal CVD ( By the MCVD (Metal Chemical Vapor Deposition) method You just need to deposit the film.

[0142] The insulator 105 is provided so as to cover the conductor 102. The insulator 105 is an insulator described later. An insulator similar to 104 or insulator 112 can be used.

[0143] The insulator 103 is provided so as to cover the insulator 105. The insulator 103 blocks oxygen. It is preferable that it has the function of providing such an insulator 103. This prevents the conductor 102 from extracting oxygen from 04. To effectively supply oxygen from 04 to insulator 106a, semiconductor 106b, and insulator 106c. It is possible.

[0144] Insulator 103 can be boron, aluminum, silicon, scandium, titanium, or gallium. Indium, yttrium, zirconium, indium, lanthanum, cerium, neodymium, HAF It may have an oxide or nitride containing nium or thallium. Preferably, acid Hafnium oxide or aluminum oxide is used.

[0145] Furthermore, in insulators 105, 103, and 104, insulator 103 captures electrons. It is preferable to have a capture region. The insulators 105 and 104 suppress electron emission. When it has the ability, electrons captured by the insulator 103 behave like negative fixed charges. be.

[0146] Insulator 104 preferably contains a small amount of water or hydrogen in the film. 104 is preferably an insulator having excess oxygen. For example, as insulator 104 For example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon Phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, or An insulator containing tan, neodymium, hafnium, or tantalum is used in a single layer or in a multilayer structure. For example, as the insulator 104, aluminum oxide, magnesium oxide, and oxide Silicon, silicon oxide nitride, silicon nitride, silicon nitride, gallium oxide, gallium oxide Lumanium, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, oxide Hafnium or tantalum oxide may be used. Preferably, silicon oxide or nitrogen oxide. Use silicon dioxide.

[0147] The amount of water or hydrogen contained in the insulator 104 is preferably small. For example, the insulator 104 is Thermal Desorption Sperm Analysis (TDS). (ctroscopy) 100°C to 700°C or 100°C to 500°C Within the surface temperature range, the amount of water molecules removed is 1.0 × 10⁻⁶. 13 molecule / cm 2 The above 1.4 × 10 16 molecule / cm 2 Below, 1.0 × 10 13 molecule / cm 2 The above 4.0 × 10 15 molecule / cm 2 Below, 1.0 × 10 13 molecule / cm 2 The above 2.0 × 10 15 molecule / cm 2 The following is preferable. Also, in TDS, 100°C to 700°C or 100 In the surface temperature range of ℃ to 500℃, the amount of hydrogen molecules removed is 1.0 × 10⁻⁶. 13 molecule / c m 2 The above 1.2 × 10 15 molecule / cm 2 Below, 1.0 × 10 13 molecule / cm 2 That's all. 9.0×10 14 molecule / cm 2 The following is preferable. Note that the molecule using TDS Details on the method for measuring the amount of emissions will be described later.

[0148] Impurities such as water and hydrogen affect insulator 106a, semiconductor 106b, and insulator 106c, in particular. In semiconductor 106b, a defect level is formed, which is a factor that causes the electrical characteristics of the transistor to change. Therefore, it is provided below the insulator 106a, semiconductor 106b, and insulator 106c. By reducing the amount of water or hydrogen in the insulator 104, water is removed from the insulator 104. This reduces the amount of elements supplied to semiconductors such as 106b that can form defect levels. By using oxide semiconductors with reduced defect level density, stable electrical properties can be achieved. A transistor can be provided.

[0149] The insulator 104 is deposited using plasma CVD (PECVD), which allows for the formation of high-quality films at relatively low temperatures. It is preferable to deposit the film using the Plasma Enhanced CVD method. However, For example, when depositing silicon oxide films using the PECVD method, silicon is used as the raw material gas. Hydrogen hydrides are often used, and hydrogen, water, etc. are introduced into the insulator 104 during film formation. Therefore, the film formation of the insulator 104 shown in this embodiment is performed using a halo as the raw material gas. It is preferable to use silicon halogens. Here, examples of silicon halogens include For example, SiF4 (silicon tetrafluoride), SiCl4 (silicon tetrachloride), SiHCl3 ( Silicon trichloride, SiH2Cl2 (dichlorosilane), or SiBr4 (silicone tetrabromide) Materials such as (n) can be used, and in particular, the use of SiF4 (silicon tetrafluoride) is preferred. stomach.

[0150] Furthermore, when silicon halide is used as a raw material gas for forming the insulator 104, In addition to silicon hydride, silicon hydride may also be added. This allows silicon hydride When only hydrogen and water are used as raw material gases, the hydrogen and water content in the insulator 104 is reduced, and halogen This method allows for an improvement in the film deposition rate compared to using silicon dioxide alone as the raw material gas. The insulator 104 can be formed using SiF4 and SiH4 as raw material gases. The ratio of the flow rates of 4 and SiH4 is determined considering the water and hydrogen content in the insulator 104 and the film deposition rate. You can set it as appropriate.

[0151] Furthermore, it is preferable that the insulator 104 is an insulator having excess oxygen. By providing 104, the insulator 104 is separated from the insulator 106a, semiconductor 106b, and insulator Oxygen can be supplied to 10⁶C. With this oxygen, the oxide semiconductor insulator 1 This can reduce oxygen vacancies that become defects in 06a, semiconductor 106b, and insulator 106c. This results in a low defect level density for insulator 106a, semiconductor 106b, and insulator 106c. This allows for the creation of an oxide semiconductor with stable properties.

[0152] In this specification, etc., excess oxygen refers, for example, to oxygen present in amounts exceeding the stoichiometric composition. This refers to oxygen. Alternatively, excess oxygen refers to, for example, a membrane containing excess oxygen when heated. Alternatively, it refers to oxygen released from a layer. Excess oxygen, for example, moves within a membrane or layer. This is possible. The movement of excess oxygen can occur when it moves between atoms in a membrane or layer, or when it moves between atoms that make up the membrane or layer. In some cases, they may move in a chain reaction, replacing one another as they are replaced.

[0153] Insulator 104 having excess oxygen is measured by TDS at a temperature of 100°C to 700°C or 100°C. In the surface temperature range of ℃ to 500℃, the amount of oxygen molecules removed is 1.0 × 10⁻⁶. 14 molecule / c m 2 The above 1.0 × 10 16 molecule / cm 2 Below, more comfortable, 1.0 × 10 15 molecule / cm 2 The above 5.0 x 10 15 molecule / cm 2 The results are as follows:

[0154] The following explains how to measure the amount of molecular release using TDS, using oxygen release as an example. do.

[0155] The total amount of gas released when a sample is analyzed by TDS is the integral of the ionic intensity of the released gas. It is proportional to the value. And by comparing it with a standard sample, the total amount of gas released can be calculated. .

[0156] For example, TDS results and measurements of a silicon substrate containing hydrogen at a predetermined density, which is a standard sample. From the TDS results of the sample, the amount of oxygen molecules released from the measured sample (N O2 ) can be calculated using the formula shown below. This is possible. Here, the gas detected at a mass-to-charge ratio of 32 obtained by TDS analysis Let's assume everything originates from oxygen molecules. The mass-to-charge ratio of CH3OH is 32, but it is possible that it exists. Acids with low acidity will not be considered here. Also, acids with a mass number of 17, which are isotopes of the oxygen atom. Regarding elementary atoms and oxygen molecules, including oxygen atoms with a mass number of 18, the abundance ratio in nature It is not considered because the amount is extremely small.

[0157] N O2 =N H2 / S H2 ×S O2 ×α

[0158] N H2 This value represents the density of hydrogen molecules detached from the standard sample. H2 The standard test This is the integrated value of the ionic intensity when the material is analyzed by TDS. Here, the reference value of the standard sample is used. N H2 / S H2 Let's assume that. S O2 This is the ionic strength when the measurement sample is analyzed by TDS. This is the integral value in degrees. α is a coefficient that affects the ionic intensity in TDS. The equation shown above For further details, please refer to Japanese Patent Publication No. 6-275697. The amount of oxygen released is as follows: Using the EMD-WA1000S / W temperature-controlled desorption analyzer manufactured by Denshi Kagaku Co., Ltd., standard samples The measurement is performed using a silicon substrate containing a certain amount of hydrogen atoms.

[0159] Furthermore, in TDS, some of the oxygen is detected as oxygen atoms. The ratio can be calculated from the ionization rate of oxygen molecules. Note that α above is the oxygen molecule Since it includes the ionization rate, by evaluating the amount of oxygen molecules released, the amount of oxygen atoms released can be determined. It can also be estimated.

[0160] Note N O2 This is the amount of oxygen molecules released. The amount released when converted to oxygen atoms is the amount of oxygen molecules. This will be twice the amount released.

[0161] Alternatively, insulators that release oxygen through heat treatment may contain peroxide radicals. Specifically, the spin density caused by peroxide radicals is 5 × 10⁻⁶ 17 spins / cm 3 The above is what is meant. Furthermore, insulators containing peroxide radicals are analyzed by electron spin resonance (ES). In R: Electron Spin Resonance, the g value is near 2.01. They may also have symmetrical signals.

[0162] Furthermore, the insulator 104 may also have a function to prevent the diffusion of impurities from the substrate 100.

[0163] Furthermore, as mentioned above, it is preferable that the upper or lower surface of the semiconductor 106b has high flatness. Therefore, the upper surface of the insulator 104 is subjected to chemical mechanical polishing (CMP). Planarization treatments such as cal polishing are performed to improve flatness. That's good too.

[0164] Conductors 108a and 108b are the source electrodes or of transistor 10, respectively. It can function as one of the drain electrodes.

[0165] Conductors 108a and 108b may be formed in the same manner as conductor 102.

[0166] Furthermore, in regions where conductors 108a and 108b do not overlap with conductor 114 Preferably, at least a portion of it overlaps with the insulator 112 via the insulator 106c. As shown in Figure 1(B), most of the upper surfaces of the conductors 108a and 108b are isolated. The configuration should be such that the conductor 108 is covered by the edge 106c. On the upper surfaces of a and conductor 108b, the extraction of oxygen from the insulator 112 is suppressed. This allows the insulator 112 to be separated from the insulator 106a, semiconductor 106b and insulator 10 It can effectively supply oxygen to 6°C.

[0167] The insulator 112 can function as a gate insulating film of the transistor 10. 112 may be an insulator having excess oxygen, similar to insulator 104. By providing the body 112, the insulator 112 separates the insulator 106a, the semiconductor 106b and Oxygen can be supplied to the insulator 106.

[0168] Examples of insulators 112 include boron, carbon, nitrogen, oxygen, fluorine, magnesium, and Aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium An insulator containing zirconium, lanthanum, neodymium, hafnium, or tantalum, in a single layer Alternatively, they can be used in a laminated configuration. For example, as the insulator 112, aluminum oxide, acid Magnesium oxide, silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, Gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide Neodymium oxide, hafnium oxide, or tantalum oxide may be used.

[0169] Conductor 114 can function as the gate electrode of transistor 10. Conductor 11 For component 4, it can be formed in the same manner as the conductor 102.

[0170] Here, as shown in Figure 1(C), the electric field formed by conductors 102 and 114 , the semiconductor 106b can be electrically surrounded (Note that this is due to the electric field generated from the conductor) The structure of a transistor, which electrically surrounds a semiconductor, is called a surrounded chan This is called a nel (s-channel) structure. Therefore, the entire semiconductor 106b (top surface) Channels are formed on the bottom and sides. In an s-channel structure, the transient A large current can flow between the source and drain of the device, and the current when conducting (on current) It can be increased.

[0171] Furthermore, because a high on-current can be obtained, the s-channel structure is suitable for miniaturized transients. It can be said to be a suitable structure for transistors. Because transistors can be miniaturized, the transistor has Semiconductor devices can be made highly integrated and high-density. The transistor preferably has a channel length of 40 nm or less, and more preferably 30 nm. More preferably, the region has a range of 20 nm or less, and the transistor has a channel width Preferably 40 nm or less, more preferably 30 nm or less, and more preferably 20 nm or less. It has the domain of.

[0172] The insulator 116 can function as a protective insulating film for the transistor 10. The thickness of the edge body 116 can be, for example, 1 nm or more, or 20 nm or more. Furthermore, at least a portion of the insulator 116 is in contact with the upper surface of the insulator 104 or the insulator 112. It is preferable that it be formed in this way.

[0173] Examples of insulators 116 include carbon, nitrogen, oxygen, fluorine, magnesium, and aluminum. Gluten, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium An insulator containing nium, lanthanum, neodymium, hafnium, or tantalum, in a single layer, It can be used in a laminated configuration. Insulator 116 is oxygen, hydrogen, water, alkali metals, alkaline earth metals It is preferable that the insulator has the effect of blocking elements such as [specific elements]. Examples of such insulators include: A nitride insulating film can be used. Examples of the nitride insulating film include silicon nitride and silicon nitride. Examples include silicon, aluminum nitride, and aluminum nitride oxide. Note that these are substitutes for nitride insulating films. Alternatively, an oxide insulating film having a blocking effect on oxygen, hydrogen, water, etc. may be provided. Examples of oxide insulating films include aluminum oxide, aluminum oxide nitride, gallium oxide, and nitrile oxide. Gallium oxide, yttrium oxide, yttrium oxide and nitride, hafnium oxide, hafnium oxide and nitride It includes things like nium.

[0174] Here, the deposition of the insulator 116 is preferably carried out using a sputtering method, and oxygen is included. It is more preferable to perform the process using the sputtering method under an ambient atmosphere. By forming a film on the edge 116, the insulator 104 or insulator 112 is formed simultaneously with the film formation. The surface (after the insulator 116 is formed, the interface between insulator 104 or insulator 112 and insulator 116) Oxygen is added nearby.

[0175] Insulator 116 is an insulator that is less permeable to oxygen than insulators 104 and 112. It is preferable that the insulator 116 has the effect of blocking oxygen. As a result, the insulator 104 and insulator 112 are converted to insulator 106a, semiconductor 106b and When supplying oxygen to the insulator 106c, the oxygen is released to the outside above the insulator 116. This can prevent that from happening.

[0176] Furthermore, aluminum oxide allows the film to penetrate both hydrogen, water and other impurities, as well as oxygen. Because it has a high barrier effect that prevents leakage, it is preferable to apply it to the insulator 116.

[0177] Furthermore, the insulator 116 can be used as the insulator 106a or insulator 106c as described above. It is also possible to use oxides that can be produced relatively easily. These oxides can be produced using the sputtering method. Because it can be easily formed into a film, oxygen can be effectively added to the insulator 104 and the insulator 112. This can be done. For such an insulator 116, it is preferable to use an oxide insulator containing In. For example, In-Al oxide, In-Ga oxide, and In-Ga-Zn oxide can be used. In oxide insulators containing In produce particles when the film is deposited by sputtering. Because of its small quantity, it is suitable for use as insulator 116.

[0178] The insulator 118 functions as an interlayer insulating film. Examples of insulators include insulator 105. It can be formed in the same manner as before.

[0179] Conductors 120a and 120b are the source electrode or drain of transistor 10. It functions as wiring electrically connected to the electrodes. Conductors 120a and 120b Therefore, conductors that can be used as conductor 108a and conductor 108b are used. Yes, that's fine. This allows it to function as wiring with heat resistance and oxidation resistance.

[0180] By adopting the above configuration, a conductor with heat resistance and oxidation resistance can be used. We can provide transistors. We can provide transistors with stable electrical characteristics. This is possible. Alternatively, it is possible to provide a transistor with low leakage current when not conducting. Alternatively, it is possible to provide a transistor with high frequency characteristics. Alternatively, - A transistor having off-electrical characteristics can be provided. Or, subs It is possible to provide transistors with small threshold swing values. Or, reliability It can provide high-performance transistors.

[0181] <Transistor variation> Below, modified examples of transistor 10 will be described using Figures 7 to 12. Figures 12 and 12 show the transistor in the channel length direction, similar to Figures 1(B) and 1(C). This shows a cross-sectional view and a cross-sectional view of the transistor in the channel width direction.

[0182] The transistor 12 shown in Figures 7(A) and 7(B) has a silicon ion on the surface of the conductor 108a. It has a region 108c having silicon and oxygen, and on the surface of the conductor 108b, silicon and It differs from transistor 10 in that it has a region 108d containing oxygen. Figure 7(C) shows a magnified view of the area enclosed by the dashed line in 7(A).

[0183] Regions 108c and 108d are oxygen regions on the surface of conductors 108a and 108b. When supplied, silicon in conductors 108a and 108b segregates to the surface and reacts with oxygen. It is formed by bonding. In addition, regions 108c and 108d are insulators and In some cases, it can function in this way. For example, as shown in Figure 7(C), conductive A region 108c that functions as an insulator is provided between the body 114 and the conductor 108a. This reduces the parasitic capacitance between conductor 114 and conductor 108a. Therefore, by providing region 108d, between conductor 114 and conductor 108b, Parasitic capacitance is also reduced. The reduction in parasitic capacitance improves the electrical characteristics of transistor 12. It can improve.

[0184] Furthermore, by providing regions 108c and 108d that function as insulators, Furthermore, the leakage current between conductor 114 and conductor 108a or conductor 108b is also reduced. It can be done.

[0185] Furthermore, if the thickness of regions 108c and 108d is too thin, they will not function adequately as insulators. If it cannot be contained, and if it is too thick, the areas of conductors 108a and 108b become small. As a result, the electrical resistance values ​​of conductors 108a and 108b increase. Therefore, the thickness of regions 108c and 108d is preferably between 0.2 nm and 20 nm. It's nice.

[0186] Regions 108c and 108d can also form spontaneously simply by exposure to the atmosphere. Yes, it exists. It can also be formed intentionally. One way to form it intentionally is, for example... Alternatively, heat treatment can be performed in an oxidizing atmosphere. It is also acceptable. Plasma processing is performed using, for example, a high-density plasma using a power supply with a frequency of 2.45 GHz. It is preferable to use Zuma treatment. In addition, oxygen should be added to semiconductor 106b during this process. The oxygen vacancy in semiconductor 106b may be compensated for by this method.

[0187] The transistor 16 shown in Figures 8(A) and 8(B) consists of a conductor 102, an insulator 101, It differs from transistor 10 in that an insulator 105 is not formed.

[0188] The transistor 18 shown in Figures 8(C) and 8(D) has a conductor 114 and an insulator 112 Openings formed in insulator 106c, insulator 104, insulator 103, insulator 105, etc. It differs from the transistor 10 in that it is connected to the conductor 102 via a conductor.

[0189] The transistor 20 shown in Figures 9(A) and 9(B) has an insulator 107 on top of insulator 101. It is provided therein, and the conductor 102 is embedded in an opening provided in the insulator 107. In this respect, it differs from transistor 10. Here, the insulator 107 is insulator 105 Any insulator that can be used as such may be used. Also, insulator 107 and conductor 10 The upper surface of 2 should preferably be planarized using methods such as CMP to improve its flatness. i. As a result, even if a conductor 102 that functions as a back gate is provided, semiconductor 106b Because the flatness of the surface forming the transistor is not impaired, the carrier mobility is improved, The on-current of 20 can be increased. Also, the insulator due to the shape of the conductor 102 104 The step on the surface is eliminated, which reduces the drag of conductor 108a or conductor 108b. A component that functions as a conductor, the conductor 102, and the insulator 104 generate a signal between them via the stepped portion. This reduces the leakage current. This reduces the off-current of transistor 20. It is possible.

[0190] The transistor 22 shown in Figures 10(A) and 10(B) consists of conductor 108a and conductor 1 An insulator 117 is provided on 08b and insulator 104, and semiconductor 106 An opening reaching b is provided. An insulator 106c, an insulator 112, and a conductive material are provided in the opening. It differs from the transistor 10 in that the body 114 is provided in a way that allows it to be embedded. Furthermore, the opening separates the conductor 108a and the conductor 108b. It exists. Transistor 22 has a conductor 114 that can function as a gate electrode, To fill the opening provided in the edge 117, in a self-aligning manner. Therefore, TGSA s-channel FET (Trench Gate S It can also be called an elf (Align s-channel FET).

[0191] Here, if the insulator 117 is formed using an insulator that can be used for the insulator 104 That's good. Also, the upper surface of the insulator 117 may be flattened by methods such as CMP.

[0192] In transistor 22, an insulator 117 and an insulator 10 are placed between the conductor 108a and the conductor 114. 6c and insulator 112 are provided. In addition, insulation is provided between conductor 108b and conductor 114. Body 117, insulator 106c and insulator 112 are provided. Therefore, the conductor 108a The distance between the top surface and the bottom surface of the conductor 114, and the distance between the top surface of the conductor 108b and the bottom surface of the conductor 114 The distance between the surfaces can be increased by the thickness of the insulator 117. This allows the conductor To reduce parasitic capacitance that occurs in the region where 114 and conductors 108a and 108b overlap. This can be achieved by reducing parasitic capacitance, thereby improving the switching speed of the transistor. This allows for an improvement in frequency characteristics, making it possible to provide transistors with high frequency performance. ru.

[0193] The transistor 24 shown in Figures 10(C) and 10(D) is insulator 117, insulator 10 6c, the upper surfaces of the insulator 112 and the conductor 114 are roughly coincide and are provided flat. In this respect, it differs from transistor 22. To form it in this way, insulator 117, The upper surfaces of insulator 106c, insulator 112, and conductor 114 were flattened by methods such as CMP. That's all you need to do.

[0194] By using this structure, the conductor 114, conductor 108a, and conductor 108b Since the region where they overlap is almost completely eliminated, the gate-source junction of transistor 24, and This can reduce the parasitic capacity that occurs between the gate and the drain. This allows for an improvement in the switching speed of the transistor, thus enabling high frequencies. A transistor with numerical characteristics can be provided.

[0195] The transistor 29 shown in Figures 11(A) and 11(B) has an insulator 107 and an insulator 10 It is provided on 1, and the conductor 102 is embedded in the opening in the insulator 107. In this respect, it differs from transistor 24. Also, insulator 106c is different from insulator 106a and semiconductor Another difference from transistor 24 is that it covers the conductor 106b. Transistor 29 is an insulator. An insulator 106c is not provided on the side of the opening of the body 117. Therefore, the opening of the insulator 117 The length of the conductor 114 in the channel length direction at the opening is made longer than that of the transistor 24, etc. It is possible.

[0196] Furthermore, in transistor 29, silicon and oxygen are present on the surface of the conductor 108a. Region 1 has region 108c, and the surface of the conductor 108b has region 1 having silicon and oxygen. It also differs from transistor 24 in that it has region 08d. Regions 108c and 108d are It can be formed in the same manner as transistor 12 shown in Figure 7.

[0197] However, regions 108c and 108d are the fields of transistors 12 and 29. It is not limited to just this. For example, other transistors can access regions 108c and 108d. It's okay to have it.

[0198] The transistor 26 shown in Figures 12(A) and 12(B) is composed of a conductor 108a and a conductive The fact that body 108b is not provided, and the side edges of the conductor 114 and the insulator 112 It differs from transistor 10 in that it is provided in roughly the same manner.

[0199] In transistor 26, the low-resistance region 109a and the low-resistance region 109b are insulator 1 At least one of the elements contained in 16 may be included. Also, the low resistance region 109a In the low-resistance region 10⁹b, various elements may be added to lower the electrical resistance. stomach.

[0200] Examples of elements added to the low-resistance region 109a and low-resistance region 109b include boron. Element, phosphorus, nitrogen, argon, helium, magnesium, aluminum, silicon, titanium Vanadium, chromium, nickel, cobalt, germanium, yttrium, zirconium Molybdenum, niobium, molybdenum, indium, tin, lanthanum, cerium, neodymium, hafnium Materials such as luminous, tantalum, or tungsten are preferred. For example, the low resistance region 109a and low The above elements are present in the resistive region 10⁹b for 1 × 10⁻⁶ 14 / cm 2 The above 2 x 10 16 / cm 2 Included below It is preferable that the low resistance region 109a and low resistance region in the insulator 106c are also included. The resistance region 109b is in the low-resistance region 109a and low-resistance region 109b of the insulator 106c. The concentration of the above-mentioned elements is higher in areas where there are no elements (for example, in the area where the insulator 106c overlaps with the conductor 114). The degree is high.

[0201] Furthermore, in transistor 26, semiconductor 106b is connected to insulator 106a and insulator 106c. Therefore, it is provided so as to be enclosed. Therefore, the side edges of semiconductor 106b, especially the The side edges in the channel width direction are provided in contact with the insulators 106a and 106c. As a result, near the side edge of semiconductor 106b, the insulator 106a or insulating A continuous bond is formed between body 106c and the material, reducing the defect level density. Therefore, a low-resistance region is formed. Even if the ON current flows more easily by providing region 109a and low-resistance region 109b The side edges of semiconductor 106b in the channel width direction do not become parasitic channels, and stable electrical characteristics are maintained. This property can be obtained. Note that this is a configuration without insulator 106a and / or insulator 106c. That is also acceptable.

[0202] The transistor 28 shown in Figures 12(C) and 12(D) consists of an insulator 112 and a conductor. It differs from transistor 10 in that 114 is not provided. The Ta28 is a so-called bottom-gate type transistor.

[0203] In this embodiment, the gate electrode, source electrode or drain electrode of the transistor, etc. In addition, tungsten, silicon, carbon, germanium, tin, aluminum, or nickel This describes a configuration using a conductor having a region containing one or more elements selected from the group. However, this is not the only example. For example, MIM (Metal-Insulator-Meta l) In capacitive elements such as the electrodes, tungsten, silicon, carbon, germanium, Having a region containing one or more elements selected from tin, aluminum, or nickel. A conductor may be used. In that case, a region having silicon and oxygen on the surface of the conductor may be used. A configuration in which the region having and capable of functioning as an insulator is used as the dielectric of a capacitive element. That is also acceptable.

[0204] This embodiment provides a transistor using a conductor having heat resistance and oxidation resistance. It is possible.

[0205] The configurations and methods shown in this embodiment can be appropriately combined with the configurations and methods shown in other embodiments. They can be used together.

[0206] (Embodiment 2) In this embodiment, a method for manufacturing a semiconductor device according to one aspect of the present invention is shown in Figures 13 to 13. I will explain using 19.

[0207] <Transistor Fabrication Method 1> The method for fabricating transistor 10 will be explained below with reference to Figures 13 to 15.

[0208] First, prepare circuit board 100. The circuit board used for circuit board 100 is the one described above. good.

[0209] Next, the insulator 101 is deposited. The insulator described above can be used as the insulator 101.

[0210] The insulator 101 was deposited using sputtering and chemical vapor deposition (CVD). Vapor Deposition (VAP) method, Molecular Beam Epitaxy (MBE) (ar beam epitaxy) or pulsed laser deposition (PLD) Laser Deposition) method, Atomic Layer Deposition (ALD) method This can be done using methods such as the (r Deposition) method.

[0211] Next, a conductive film to become conductor 102 is formed. The conductive material to become conductor 102 is as described above. Conductors can be used. The conductive film can be deposited by sputtering, CVD, or MBE. This can be done using methods such as the PLD method or ALD method.

[0212] Next, a resist or the like is formed on the conductive material, and the conductive material 102 is processed using the resist or the like. This forms a resist (see Figures 13(A) and 13(B)). This also includes cases where an anti-reflective layer is formed beneath the resist.

[0213] The resist is removed after the object has been processed by etching or other methods. This involves plasma treatment and / or wet etching. Therefore, plasma ashing is preferable. If the removal of resist, etc. is insufficient, 0.00 Hydrofluoric acid and / or ozone in a concentration of 1 volume or more and 1 volume or less You may remove any remaining resist or other residue with water or other means.

[0214] Next, the insulator 105 is deposited. The insulator described above can be used as the insulator 105. The film deposition of the edge body 105 is performed by sputtering, CVD, MBE, PLD, or ALD. This can be done using methods such as the above. In addition, the amount of water or hydrogen contained in the insulator 105 can be reduced. To achieve this, the film deposition may be carried out while heating the substrate. For example, below transistor 10 When a semiconductor element layer is provided, a relatively low temperature range (for example, 350°C or more, 445°C or more) It may be heated in a temperature range of approximately °C or below.

[0215] Furthermore, by forming a film using the PECVD method in the same manner as the insulator 104 described later, The amount of water or hydrogen contained in the insulator 105 may be reduced.

[0216] Next, the insulator 103 is deposited. The insulator described above can be used as the insulator 103. The film deposition of the edge body 103 is performed by sputtering, CVD, MBE, PLD, or ALD. This can be done using methods such as the above. In addition, the amount of water or hydrogen contained in the insulator 103 can be reduced. To achieve this, the film deposition may be carried out while heating the substrate. For example, below transistor 10 When a semiconductor element layer is provided, a relatively low temperature range (for example, 350°C or more, 445°C or more) It may be heated in a temperature range of approximately °C or below.

[0217] Furthermore, the CVD method is a plasma CVD (PECVD) method that utilizes plasma. Processed CVD (CVD), thermal CVD (TCVD) which utilizes heat. Method D) can be classified into methods such as photoCVD (Photo-CVD), which utilizes light. Depending on the source gas, the process can be performed using metal CVD (MCVD) or organometallic CVD. It can be divided into MOCVD (Metal Organic CVD) methods.

[0218] The PECVD method yields high-quality films at relatively low temperatures. The TCVD method, on the other hand, uses plasma... Because it does not use plasma, this film deposition method can minimize plasma damage to the workpiece. For example, wiring, electrodes, and elements (transistors, capacitive elements, etc.) included in semiconductor devices. It can charge up by receiving charge from the plasma. At this time, storage The resulting electric charge can sometimes destroy wiring, electrodes, and other components contained within semiconductor devices. On the other hand, in the case of TCVD, which does not use plasma, such plasma damage does not occur. Therefore, the yield of semiconductor devices can be increased. In addition, in the TCVD method, during film deposition Because plasma damage does not occur, a film with fewer defects can be obtained.

[0219] Furthermore, the ALD method is a film deposition method that can minimize plasma damage to the workpiece. Yes. Also, the ALD method does not cause plasma damage during film deposition, so it produces films with fewer defects. It can be obtained.

[0220] CVD and ALD are film deposition methods in which particles emitted from a target or other source are deposited. In contrast, this is a film formation method in which a film is formed by a reaction on the surface of the object being treated. This film formation method is less affected by the shape of the workpiece and has good step-level coverage. The ALD method has excellent step coverage and excellent thickness uniformity, so the aspect ratio This is suitable for coating the surface of high openings, etc. Furthermore, this allows for pinning of the deposited film. Holes and other defects are less likely to form. However, the ALD method has a relatively slow film deposition rate, so It may be preferable to use this method in combination with other film deposition methods, such as high-speed CVD. .

[0221] The CVD and ALD methods allow control of the composition of the resulting film by adjusting the flow rate ratio of the source gas. This is possible. For example, in the CVD method and ALD method, the flow rate ratio of the raw material gas can be adjusted to any A film of a certain composition can be formed. Also, for example, in the CVD method and ALD method, the film is formed. By changing the flow rate ratio of the raw material gas, a film with a continuously changing composition is formed. This is possible. When forming a film while changing the flow rate ratio of the raw material gas, multiple deposition chambers can be used. Compared to the method used for film deposition, the time required for film deposition is reduced by eliminating the time spent on transport and pressure adjustment. This is possible. Therefore, it may be possible to increase the productivity of semiconductor devices.

[0222] Conventional CVD-based film deposition equipment uses one or more raw material gases for the reaction during film deposition. Several types are supplied to the chamber simultaneously. The film deposition apparatus using the ALD method is designed for the reaction A precursor gas and a reactant gas are used. The gases are introduced into the chamber alternately, and the film deposition is carried out by repeating the introduction of these gases. Switching the incoming gas involves, for example, using each switching valve (also called a high-speed valve) It can be done by switching between modes.

[0223] For example, the film deposition is carried out using the following procedure: First, the precursor is introduced into the chamber, and the substrate The precursor is adsorbed onto the surface (Step 1). Here, the precursor is adsorbed onto the substrate surface. As a result, the self-termination mechanism of the surface chemical reaction is activated, and on the precursor layer on the substrate Furthermore, the precursor will not be adsorbed. Note that the self-termination mechanism of the surface chemical reaction is at work. The optimal temperature range for the substrate is also called the ALD Window. It is determined by the temperature characteristics, vapor pressure, decomposition temperature, etc. Next, the inert gas (argon, Alternatively, nitrogen or other substances can be introduced into the chamber to remove excess precursors and reaction products. Discharge from the vacuum (second step). Alternatively, instead of introducing an inert gas, use a vacuum exhaust. Therefore, excess precursors and reaction products may be discharged from the chamber. Next, An actant (e.g., an oxidizing agent (H2O, O3, etc.)) is introduced into the chamber, and the substrate surface is absorbed. The attached precursor reacts with the film's constituent molecules, which remain adsorbed onto the substrate, while a portion of the precursor is also adsorbed. Remove (third step). Next, remove excess by introducing an inert gas or by vacuum evacuation. The reactant and reaction products are discharged from the chamber (step 4).

[0224] Furthermore, the introduction of the reactant in the third step and the inert gas in the fourth step The introduction can be repeated multiple times. That is, after the first and second steps, the third step may be performed. Step, Step 4, Step 3, Step 4... and Step 3 and Step 4 You may repeat the process.

[0225] For example, in the third step, O3 is introduced as an oxidizing agent, and in the fourth step, N2 purging is performed. This process may be repeated multiple times.

[0226] Furthermore, when repeating steps 3 and 4, it is not necessarily the case that the same type of reactant is used. There is no need to repeat the introduction. For example, if you use H2O as the oxidizing agent in the third step of the first introduction In the third step, from the second time onward, O3 may be used as the oxidizing agent.

[0227] In this way, the oxidizer is introduced and the inert gas (or vacuum evacuation) is performed within the chamber. By repeating the process multiple times in a short period of time, excess hydrogen atoms are removed from the precursor adsorbed on the substrate surface. This allows for more reliable removal of contaminants and their expulsion from the chamber. Furthermore, the type of oxidizing agent... By increasing the number of types to two, excess hydrogen atoms etc. can be extracted from the precursor adsorbed on the substrate surface. This allows for the removal of more hydrogen atoms. In this way, hydrogen atoms are incorporated into the film during film formation. By doing so, the amount of water, hydrogen, etc. contained in the formed insulator 103 is reduced. It is possible.

[0228] In this way, a first single layer can be formed on the substrate surface, and the first to fourth steps By repeating this process, a second single layer can be stacked on top of the first single layer. The fourth step is repeated multiple times, while controlling the gas introduction, until the film reaches the desired thickness. This allows for the formation of a thin film with excellent step coverage. The thickness of the thin film depends on the number of repetitions. Because it can be adjusted, precise film thickness control is possible, and miniature transistors can be created. It is suitable for manufacturing.

[0229] The ALD method is a film deposition method that uses thermal energy to react with a precursor. In the above reactant reaction, plasma is used to convert the reactant into a radical state. The ALD method that performs processing in this way is sometimes called the plasma ALD method. In contrast to this, pre The ALD method, in which the reaction between cassa and reactant is carried out using thermal energy, is called the thermal ALD method. There is.

[0230] The ALD method can deposit extremely thin films with uniform thickness. Furthermore, it can be used on surfaces with uneven surfaces. It also has a high surface coverage rate.

[0231] Furthermore, by using the plasma ALD method for film deposition, film deposition can be performed at even lower temperatures compared to the thermal ALD method. This becomes possible. For example, the plasma ALD method does not reduce the film deposition rate even at temperatures below 100 degrees Celsius. It is possible to deposit films. In addition, in the plasma ALD method, not only oxidizing agents but also nitrogen gas, etc. Since many reactants can be used, not only oxides, but also nitrides, fluorides, It can deposit many types of films, including metals.

[0232] Furthermore, when performing plasma ALD, ICP (Inductively Coupling) is used. It is also possible to generate plasma while it is separated from the substrate, such as with ed Plasma. It is possible. By generating plasma in this way, plasma damage can be suppressed. Cut.

[0233] Here, as an example of an apparatus capable of forming films using the ALD method, the film deposition apparatus 1000 The configuration will be explained using Figures 16(A) and 16(B). Figure 16(A) shows the Ma Figure 16(B) is a schematic diagram of a multichamber type film deposition apparatus 1000. This is a cross-sectional view of an ALD device that can be used in 0.

[0234] <Example of a film deposition apparatus configuration> The film deposition apparatus 1000 includes an input chamber 1002, an output chamber 1004, a transport chamber 1006, and a film deposition chamber. It includes 1008, a film deposition chamber 1009, a film deposition chamber 1010, and a transport arm 1014. Here, the loading room 1002, the unloading room 1004, and the film deposition rooms 1008 to 1010 are transport rooms 10 It is connected to 06. This prevents exposure to the atmosphere in deposition chambers 1008 to 1010. This allows for continuous film deposition and prevents impurities from being incorporated into the film.

[0235] Furthermore, the loading room 1002, unloading room 1004, transport room 1006, and film deposition rooms 1008 to 1010 To prevent moisture from adhering, etc., the container is filled with an inert gas (such as nitrogen gas) with a controlled dew point. It is preferably left as it is, and it is desirable to maintain reduced pressure.

[0236] In addition, an ALD apparatus can be used in the film formation chambers 1008 to 1010. Further, it may be configured to use a film formation apparatus other than the ALD apparatus in any of the film formation chambers 1008 to 1010. Examples of the film formation apparatus used in the film formation chambers 1008 to 1010 include a sputtering apparatus, a PECVD apparatus, a TCVD apparatus, a MOCVD apparatus, and the like.

[0237] For example, by configuring the film formation chambers 1008 to 1010 to be provided with an ALD apparatus and a PECVD apparatus, the insulator 105 made of silicon oxide of the transistor 10 shown in FIGS. 1(B) and (C) can be formed by PECVD, the insulator 103 made of hafnium oxide can be formed by ALD, and the insulator 104 made of silicon oxide containing halogen can be formed by PECVD. Since a series of film formation is continuously performed without exposing the film to the atmosphere, film formation can be performed without impurities being mixed into the film.

[0238] In addition, the film formation apparatus 1000 has a load lock chamber 1002, an unload lock chamber 1004, and film formation chambers 1008 to 1010, but the present invention is not limited thereto. The film formation chambers of the film formation apparatus 1000 may be configured to have four or more, or a processing chamber for performing heat treatment or plasma treatment may be added. Further, the film formation apparatus 1000 may be a single wafer type, or may be a batch type for simultaneously forming films on a plurality of substrates.

[0239] <ALD apparatus> Next, the configuration of the ALD apparatus that can be used in the film formation apparatus 1000 will be described. AL Apparatus D consists of a film deposition chamber (chamber 1020), raw material supply units 1021a and 1021b, and flow The high-speed valves 1022a and 1022b, which are volume controllers, and the raw material inlets 1023a and 1023 It has a raw material discharge port 1024 and an exhaust device 1025. It is installed inside the chamber 1020. The raw material inlets 1023a and 1023b are connected to the raw material supply section 1021 via supply pipes and valves. a and 1021b are connected respectively, and the raw material discharge port 1024 is connected to a discharge pipe, valve and pressure It is connected to the exhaust system 1025 via a power regulator.

[0240] Furthermore, as shown in Figure 16(B), the plasma generator 1028 is connected to the chamber 1020. This allows for film deposition using plasma ALD in addition to thermal ALD. The rasma ALD method allows for film deposition even at low temperatures without reducing the deposition rate, thus reducing the deposition efficiency. It is best used with a single-wafer film deposition apparatus.

[0241] Inside the chamber is a substrate holder 1026 equipped with a heater, and this substrate holder 1026 A substrate 1030 to be coated is placed on top of it.

[0242] In the raw material supply units 1021a and 1021b, solid raw materials and liquid raw materials are supplied by vaporizers, heating means, etc. The raw material gas is formed from the raw materials of the body. Alternatively, the raw material supply units 1021a and 1021b are gases. The system may also be configured to supply the raw material gas.

[0243] Furthermore, while an example is shown in which two raw material supply units 1021a and 1021b are provided, this does not particularly limit the possibilities. It is not necessary to provide three or more. Also, the high-speed valves 1022a and 1022b are precisely controlled by time. It can be controlled and is configured to supply either a source gas or an inert gas. The high-speed valves 1022a and 1022b are flow controllers for the raw material gas, and also for inert gas It could also be called a flow control device.

[0244] In the film deposition apparatus shown in Figure 16(B), the substrate 1030 is loaded onto the substrate holder 1026, and After sealing the module 1020, the substrate 103 is heated by the heater of the substrate holder 1026. Set 0 to the desired temperature (for example, 80°C or higher, 100°C or higher, or 150°C or higher), and the raw material gas The supply of gas, exhaust by exhaust device 1025, supply of inert gas, and exhaust device 1025 A thin film is formed on the substrate surface by repeatedly exhausting air.

[0245] In the film deposition apparatus shown in Figure 16(B), the raw materials used in the raw material supply units 1021a and 1021b (volatile By appropriately selecting (such as bio-active organometallic compounds), hafnium, aluminum, tan Oxides (including complex oxides) containing one or more elements selected from tal, zirconium, etc. An insulating layer can be formed by including the following. Specifically, it contains hafnium oxide. An insulating layer composed of, an insulating layer containing aluminum oxide, hafnium silicate An insulating layer comprising a t, or an insulating layer comprising an aluminum silicate. The following can be formed into films. Also, the raw materials used in the raw material supply units 1021a and 1021b ( By appropriately selecting volatile organometallic compounds (such as volatile organometallic compounds), a tungsten layer, a titanium layer, etc. can be created. It is also possible to deposit thin films such as metal layers or nitride layers, including titanium nitride layers.

[0246] For example, when forming a hafnium oxide layer using an ALD apparatus, a solvent and a hafnium precursor are used. Liquids containing compound (such as hafnium alkoxide or tetrakisdimethylamide hafnium) The raw material gas is a vaporized hafnium amide (such as TDMAH), and ozone is used as the oxidizing agent. Two types of gases (O3) are used. In this case, the first gas supplied from the raw material supply unit 1021a The raw material gas is TDMAH, and the second raw material gas supplied from the raw material supply unit 1021b is oz The chemical formula for tetrakisdimethylamidehafnium is Hf[N(CH3)2 ]4. Other material liquids include tetrakis(ethylmethylamide)hafnium. These are some examples.

[0247] When forming an aluminum oxide layer using an ALD apparatus, the solvent and aluminum precursor are used. A raw material gas obtained by vaporizing a liquid containing a compound (such as TMA: trimethylaluminum), and oxidation Two types of gas, H2O, are used as the agent. In this case, they are supplied from the raw material supply unit 1021a. The first raw material gas is TMA, and the second raw material gas supplied from the raw material supply unit 1021b is H It becomes 2O. The chemical formula for trimethylaluminum is Al(CH3)3. Also, Other material liquids include tris(dimethylamide)aluminum and triisobutylaluminum. Aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedione) Examples include (T).

[0248] When depositing a tungsten layer using an ALD apparatus, WF6 gas and B2H6 gas are used. The initial tungsten layer is formed by sequentially and repeatedly introducing the following: WF6 gas and H2 gas are then introduced. A tungsten layer is formed using this method. Note that SiH4 gas can be used instead of B2H6 gas. Good. These gases may also be controlled by a mass flow controller. .

[0249] Next, the insulator 104 is deposited (see Figures 13(C) and 13(D)). Insulator 104 The above-mentioned insulator can be used for this purpose. The insulator 104 is deposited by sputtering, CV This can be performed using methods such as the D method, MBE method, PLD method, or ALD method.

[0250] The deposition of the insulator 104 is preferably carried out using the CVD method, and more preferably using the PECVD method. It is preferable to do so.

[0251] When depositing an insulator 104 using the PECVD method, the raw material gas should not contain hydrogen or It is preferable to use a substance with a low hydrogen content, for example, a halide. This is preferable. For example, silicon oxide or silicon oxide nitride is used as the insulator 104. In such cases, silicon halogens are preferably used as the raw material gas, for example, SiF4 (Silicon tetrafluoride), SiCl4 (silicon tetrachloride), SiHCl3 (silicon trichloride) Using, SiH2Cl2 (dichlorosilane) or SiBr4 (silicon tetrabromide), etc. It is possible.

[0252] When depositing insulator 104 using the PECVD method, an oxidizing gas (e.g., N2O) is introduced. The film is formed. Since the above silicon halide has lower reactivity compared to SiH4, it is oxidizing. The gas readily acts on the insulator 103. This causes water or water contained in the insulator 103 to be released. The element is removed by the oxidizing gas, reducing the amount of water and hydrogen contained in the insulator 103. It may be possible.

[0253] Furthermore, when silicon halide is used as a raw material gas for forming the insulator 104, In addition to silicon hydride, silicon hydride may also be added. This allows silicon hydride When only hydrogen and water are used as raw material gases, the hydrogen and water content in the insulator 104 is reduced, and halogen This method allows for an improvement in the film deposition rate compared to using silicon dioxide alone as the raw material gas. The insulator 104 can be formed using SiF4 and SiH4 as source gases. For example, Si The flow rate of H4 should be greater than 1 sccm but less than 10 sccm, more preferably 2 sccm or more. By keeping it below 4 sccm, both the water and hydrogen content in the insulator 104 and the film formation rate can be controlled. This can be obtained relatively well. However, the ratio of SiF4 and SiH4 flow rates is extremely low. The water and hydrogen content in the edge body 104 and the film deposition rate can be appropriately set.

[0254] Furthermore, in order to reduce the amount of water or hydrogen contained in the insulator 104, the substrate is heated while... It is preferable to perform the film formation.

[0255] Furthermore, it is preferable that the upper or lower surface of the semiconductor 106b, which is formed later, has high flatness. Therefore, planarization treatments such as CMP treatment are performed on the upper surface of the insulator 104 to improve its flatness. That's fine.

[0256] Next, it is preferable to perform a heat treatment. By performing the heat treatment, the insulator 105 and insulator 1 The amount of water or hydrogen in 03 and the insulator 104 can be further reduced. It may be possible to introduce excess oxygen into the edge body 104. Heat treatment is performed at 250°C or higher. 650°C or lower, preferably 450°C to 600°C, more preferably 520°C or higher The process should be carried out at temperatures below 70°C. The heat treatment should be performed in an inert gas atmosphere or with 10 pp of oxidizing gas. The procedure should be carried out in an atmosphere containing m or more, 1% or more, or 10% or more. Heat treatment can also be performed under reduced pressure. Good. Alternatively, the heat treatment can be performed by heating in an inert gas atmosphere and then replenishing the desorbed oxygen. Therefore, heat treatment is performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. It may be done. Heat treatment enhances the crystallinity of the insulator 126a and semiconductor 126b. It can remove impurities such as hydrogen and water. Heat treatment is done using lamp heating. It is also possible to use an RTA (Rapid Thermal Annealing) device. Yes, it is possible. Heat treatment using an RTA device can be completed in a shorter time compared to a furnace, thus increasing productivity. It is effective for [purpose].

[0257] Furthermore, if a semiconductor element layer is provided below the transistor 10, a relatively low temperature range It can be heated in a range (for example, a temperature range of approximately 350°C to 445°C). If, any of the substrate heating temperatures during film formation of insulator 105, insulator 103, and insulator 104. It is preferable to set the heating temperature below the highest of the above.

[0258] Next, an insulator 126a is formed. The insulator 126a is the same as the insulator 106a mentioned above. Any suitable insulator or semiconductor can be used. The deposition of the insulator 126a is performed as follows: This can be done using methods such as sputtering, CVD, MBE, PLD, or ALD. It is possible.

[0259] Next, semiconductor 126b is deposited. As semiconductor 126b, the above semiconductor 106b is used. Any suitable semiconductor can be used. The semiconductor 126b is deposited by sputtering. This can be done using methods such as CVD, MBE, PLD, or ALD. The deposition of the insulator 126a and the deposition of the semiconductor 126b are carried out continuously without exposure to the atmosphere. This reduces the inclusion of impurities in the film and at the interface.

[0260] Next, it is preferable to perform a heat treatment. By performing the heat treatment, the insulator 126a and the semiconductor In some cases, the hydrogen concentration of 176b can be reduced. Also, insulator 126a and In some cases, oxygen deficiency in semiconductor 126b can be reduced. The heat treatment is performed at 250°C. Above 650°C or below, preferably 450°C to 600°C, and more preferably 520°C or below. The process should be carried out at temperatures below 570°C. The heat treatment should be performed in an inert gas atmosphere or with an oxidizing gas for 10 minutes. The process should be carried out in an atmosphere containing ppm or more, 1% or more, or 10% or more. The heat treatment should be performed under reduced pressure. Alternatively, the heat treatment may be performed by heating in an inert gas atmosphere and then removing the desorbed oxygen. To compensate, heating treatment is performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. A heat treatment may be performed to change the crystallinity of the insulator 126a and semiconductor 126b. It can be used to enhance the properties of the substance and remove impurities such as hydrogen and water. Heat treatment is performed using a lamp. A heating-based RTA device can also be used. Heat treatment using an RTA device is more efficient than using a furnace. Because it can be done in a short time, it is effective in increasing productivity. Insulator 126a and semiconductor 12 When using CAAC-OS as 6b, the peak intensity increases after heat treatment. The full width at half maximum decreases. In other words, the crystallinity of CAAC-OS increases with heat treatment.

[0261] Furthermore, if a semiconductor element layer is provided below the transistor 10, a relatively low temperature range It can be heated in a range (for example, a temperature range of approximately 350°C to 445°C). For example, the substrate heating temperature during film formation of insulators 105, 103, and 104, or the insulating The heating temperature must be less than or equal to the highest of the following: the temperature of the heat treatment after film formation of the edge body 104. Preferably, by forming the insulator 104 using the method described above, the water in the insulator 104 Since hydrogen and other elements have been sufficiently removed, water or water is used to insulator 126a and semiconductor 126b. The amount of raw material supplied can be significantly reduced.

[0262] This heat treatment introduces oxygen from the insulator 104 to the insulator 126a and the semiconductor 126b. It can be supplied. By heat-treating the insulator 104, it can be done very easily. Oxygen can be supplied to the insulator 126a and the semiconductor 126b.

[0263] Here, the insulator 103 functions as a barrier film that blocks oxygen. Because it is located beneath the insulator 104, oxygen diffused into the insulator 104 This prevents diffusion to layers below 104.

[0264] In this way, oxygen is supplied to the insulator 126a and semiconductor 126b, reducing oxygen deficiency. This results in high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors with a low defect level density. It can be done this way.

[0265] Furthermore, high-density plasma treatment may be performed. High-density plasma is produced using microwaves. It is sufficient to generate it. In high-density plasma processing, for example, oxidizing gases such as oxygen and nitrous oxide are used. You can use this. Alternatively, a mixture of an oxidizing gas and a noble gas such as He, Ar, Kr, or Xe. A mixed gas may be used. A bias may be applied to the substrate during high-density plasma processing. This allows oxygen ions and other elements in the plasma to be drawn towards the substrate. The rasmer treatment may be performed while heating the substrate. For example, instead of the above heating treatment, high density When performing plasma treatment, the same effect can be obtained at a lower temperature than the heat treatment described above. The high-density plasma treatment may be performed before the deposition of the insulator 126a, or as described later. This can be done before the deposition of film 26a, or after the deposition of insulator 112, or insulator 11 This can be done after the deposition of film 6, for example.

[0266] Next, the conductive material 128 is deposited (see Figures 13(E) and 13(F)). Conductive material 12 8 is a conductor that can be used as the conductor 108a and conductor 108b described above. The conductor 128 can be deposited using sputtering, CVD, MBE, or This can be done using methods such as the PLD method and ALD method.

[0267] Next, a resist or the like is formed on the conductive material 128, and the conductive material is processed using the resist or the like. Forms 108a and the conductor 108b.

[0268] Next, a resist or the like is formed on the semiconductor 126b, and the resist or the like, conductor 108a and The conductive material 108b is used to process and form the insulator 106a and semiconductor 106b (Figure See Figures 13(G) and 13(H).

[0269] Furthermore, in the region of semiconductor 106b that is in contact with conductor 108a and conductor 108b, As a result, low-resistance regions 109a and 109b may be formed. Also, half Conductor 106b is between conductor 108a and conductor 108b It may have a region with a thinner film thickness than the region overlapping with 08b. This is due to conductor 108a And when forming the conductor 108b, by removing a portion of the upper surface of the semiconductor 106b It is formed.

[0270] Furthermore, after forming the conductor 128, the insulator 126a, semiconductor 126b, and conductor 128 are combined. The insulator 106a, the semiconductor 106b, and the overlapping shape of the semiconductor 106b are processed together. A conductive material in the shape of a semiconductor 106b is formed, and the conductive material in the shape that overlaps with the semiconductor 106b is further processed to form a conductive material. 108a and conductive 108b may be formed.

[0271] Next, the insulator 126c is deposited. The insulator 126c is the same as the insulator 106c mentioned above. Any suitable insulator or semiconductor can be used. The deposition of the insulator 126c is as follows: This can be done using methods such as sputtering, CVD, MBE, PLD, or ALD. This can be done. Before forming the insulator 126c, semiconductor 106b, conductor 108a and conductor The surface of 108b can be etched. For example, using a plasma containing a noble gas... It can be adjusted. After that, the insulator 126c can be continuously formed without exposure to the atmosphere. By forming a film, semiconductor 106b, conductor 108a and conductor 108b, and insulator 1 This reduces the incorporation of impurities into the interface between 06c and other materials. The impurities that enter the film may diffuse more easily than the impurities already present. Therefore, the contamination of the film with these impurities may be a concern. By reducing this, stable electrical characteristics can be imparted to the transistor.

[0272] Next, an insulator 132 is formed. The insulator 132 is the same as the insulator 112 described above. Any insulator that can perform this function should be used. The insulator 132 can be deposited by sputtering or CVD. This can be done using methods such as the MBE method, PLD method, or ALD method. By performing the deposition of film 26c and the deposition of insulator 132 in a continuous manner without exposure to the atmosphere, This reduces the inclusion of impurities in the film and at the interface.

[0273] Next, the conductive film 134 is deposited (see Figures 14(A) and 14(B)). Conductive film 13 For 4, any conductor that can be used as the conductor 114 described above may be used. The film deposition of body 134 is performed by sputtering, CVD, MBE, PLD, ALD, etc. This can be done using the following: The deposition of the insulator 132 and the deposition of the conductor 134 are performed using the following: Performing the process continuously without exposure to the atmosphere reduces the incorporation of impurities into the film and its interface. It is possible.

[0274] Next, a resist or the like is formed on the conductive material 134, and the conductive material is processed using the resist or the like. Forms 114.

[0275] Next, a resist or the like is formed on the conductor 114 and the insulator 132, and the resist or the like is used The material is then processed to form the insulator 106c and the insulator 112 (Figures 14(C) and 14 (See D).) Note that at this time, the conductors 120a and 120b that will be formed later are The insulator 106c and the region in contact with the conductors 108a and 108b are exposed. An insulator 112 may be formed.

[0276] Next, the insulator 116 is deposited (see Figures 14(E) and 14(F)). Insulator 11 For 6, the above-mentioned insulator can be used. The insulator 116 is deposited by sputtering, C This can be performed using methods such as the VD method, MBE method, PLD method, or ALD method.

[0277] Here, as the insulator 116, aluminum oxide or other blocking agent for oxygen, hydrogen, water, etc. It is preferable to provide an oxide insulating film that has the desired effect.

[0278] The deposition of the insulator 116 is preferably carried out using plasma, and the sputtering method is used. It is more preferable to carry out the process using a sputtering method in an oxygen-containing atmosphere. That is even more preferable.

[0279] As for the sputtering method, a DC power supply is used for the sputtering power supply (DC C (Urrent) Sputtering method, and pulsed DC sputtering where a pulsed bias is applied. The sputtering method uses a high-frequency power supply (RF) to power the sputtering process. A puttering method may also be used. Alternatively, a magnetron equipped with a magnetic mechanism inside the chamber may be used. Sputtering method, bias sputtering method which applies voltage to the substrate during film deposition, reactive gas Reactive sputtering methods performed in a saturating atmosphere may also be used. The flow rate of the primary gas and the film deposition power should be determined appropriately according to the amount of oxygen added, etc.

[0280] By depositing the insulator 116 using the sputtering method, the insulator 10 is deposited simultaneously with the film formation. 4 or the surface of insulator 112 (after the film of insulator 116 is formed, insulator 104 or insulator 112 and Oxygen is added near the interface of the insulator 116. Here, the oxygen is, for example, an oxygen radical. It is added to insulator 104 or insulator 112 as such, but the state when oxygen is added is This is not limited to this. Oxygen acts as an insulator in the form of oxygen atoms or oxygen ions. Alternatively, it may be added to the insulator 112. Note that with the addition of oxygen, the insulator 104 or the insulator may also be affected. In some cases, the oxygen content in the surrounding material 112 may exceed the stoichiometric composition, and in this case, the oxygen content may exceed It can also be called excess oxygen.

[0281] Next, it is preferable to perform a heat treatment (see Figures 15(A) and 15(B)). By performing this process, the oxygen added to the insulator 104 or insulator 112 is diffused, and insulation It can be supplied to body 106a, semiconductor 106b, and insulator 106c. The heat treatment is 2 The heat treatment should be carried out at a temperature between 50°C and 650°C, preferably between 350°C and 450°C. This refers to an inert gas atmosphere, or an oxidizing gas at a concentration of 10 ppm or more, 1% or more, or 10% or less. The process is carried out in an atmosphere including the above. The heat treatment may also be carried out under reduced pressure. The heat treatment is carried out by lamp heating. An RTA device can also be used.

[0282] Furthermore, the heat treatment is preferably performed at a lower temperature than the heat treatment performed after the deposition of semiconductor 126b. The temperature difference between the heat treatment after film formation of conductor 126b and the heat treatment is 20°C to 150°C, preferably 40°C. The temperature should be between ℃ and 100℃. This will prevent excess oxygen (oxygen) from being released from the insulator 104, etc. This can suppress the release of [unclear]. Furthermore, the heat treatment after the deposition of the insulator 118 is equivalent. When the heat treatment can be combined with the heating during film formation of each layer (for example, insulator 118) If equivalent heating is performed during film deposition, it may not be necessary.

[0283] This heat treatment causes the insulator 116 to form a film, thereby forming insulators 104 and 112 The oxygen added inside (hereinafter referred to as oxygen 186) is absorbed into the insulator 104 or insulator 112 Diffuse (see Figures 15(A) and 15(B)). Insulator 116 extends to insulator 104. Alternatively, it is an insulator that is less permeable to oxygen than insulator 112, and acts as a barrier film that blocks oxygen. It functions as such. Such an insulator 116 is formed on the insulator 104 or insulator 112. Therefore, oxygen 186 diffusing in insulator 104 or insulator 112 Alternatively, it does not diffuse upwards on the insulator 112, but mainly laterally on the insulator 104 or insulator 112. It spreads downwards.

[0284] Oxygen 186 diffusing in insulator 104 or insulator 112, as indicated by the arrow, insulator It is supplied to 106a, the insulator 106c, and the semiconductor 106b. At this time, oxygen is blocked. Because the insulating material 103, which has the function of insulating, is provided below the insulating material 104, This prevents the oxygen 186 diffused in body 104 from diffusing to the layer below the insulator 104. Cut.

[0285] In this way, the insulator 106a, the insulator 106c and the semiconductor 106b, in particular the semiconductor 1 This allows for effective supply of oxygen 186 to the region where the channel is formed at 06b. In this way, oxygen is supplied to the insulator 106a, the insulator 106c, and the semiconductor 106b, and oxygen deficiency is eliminated. By reducing the defect level density, high-purity intrinsic or substantially high-purity intrinsic materials are produced. It can be made into an oxide semiconductor.

[0286] Furthermore, the heat treatment after the formation of the insulator 116 can be performed at any time after the formation of the insulator 116. For example, this may be done after the formation of the insulator 118, or after the formation of the conductors 120a and 120b. You can go later.

[0287] Next, the insulator 118 is deposited. The insulator described above can be used as the insulator 118. The edge body 118 is deposited using sputtering, CVD, MBE, PLD, or ALD. This can be done using methods such as [mention specific methods].

[0288] Next, a resist or the like is formed on the insulator 118, insulator 118, insulator 116, insulator 1 Openings are formed in 12 and insulator 106c. Then, conductor 120a and conductor 1 A conductive film that will become 20b is formed. Conductors that will become conductor 120a and conductor 120b are formed. The above-mentioned conductors can be used. The conductors can be deposited by sputtering, CVD, etc. This can be done using methods such as the MBE method, PLD method, or ALD method.

[0289] Next, a resist or the like is formed on the conductive material, and the conductive material 120 is processed using the resist or the like. a and the conductor 120b are formed (see Figures 15(C) and 15(D)).

[0290] By following the above steps, a transistor 10 according to one aspect of the present invention can be manufactured.

[0291] <Transistor Fabrication Method 2> The method for fabricating transistor 29 will be explained below using Figures 17 to 19. Regarding the method for fabricating transistor 29, the above-described method for fabricating transistors should be taken into consideration as appropriate. It is possible.

[0292] First, prepare circuit board 100. The circuit board used for circuit board 100 is the one described above. good.

[0293] Next, the insulator 101 is deposited. The insulator described above can be used as the insulator 101.

[0294] Next, an insulating film, which will become the insulator 107, is formed. The insulator described above can be used as the insulating film. The deposition of insulating films can be done by sputtering, CVD, MBE, PLD, or ALD. This can be done using methods such as [mention specific methods].

[0295] Next, a resist or the like is formed on an insulator, and the resist or the like is used for processing to create an opening. An insulator 107 is formed.

[0296] Next, a conductive film to become conductor 102 is formed. The conductive material to become conductor 102 is as described above. Conductors can be used. The conductive film can be deposited by sputtering, CVD, or MBE. This can be done using methods such as the PLD method or ALD method.

[0297] Next, the conductor is polished until the insulator 107 is exposed, forming the conductor 102 (Figure 17( See A) and Figure 17(B). Polishing can be performed by CMP treatment, etc.

[0298] Next, the insulator 105 is deposited. The insulator described above can be used as the insulator 105. The film deposition of the edge body 105 is performed by sputtering, CVD, MBE, PLD, or ALD. This can be done using methods such as the above. In addition, the amount of water or hydrogen contained in the insulator 105 can be reduced. To achieve this, the film deposition may be carried out while heating the substrate. For example, below transistor 29 When a semiconductor element layer is provided, a relatively low temperature range (for example, 350°C or more, 445°C or more) It may be heated in a temperature range of approximately °C or below.

[0299] Furthermore, by forming a film using the PECVD method in the same manner as the insulator 104 described above, The amount of water or hydrogen contained in the insulator 103 may be reduced.

[0300] Next, the insulator 103 is deposited. The insulator described above can be used as the insulator 103. The film deposition of the edge body 103 is performed by sputtering, CVD, MBE, PLD, or ALD. This can be done using methods such as the above. In addition, the amount of water or hydrogen contained in the insulator 103 can be reduced. To achieve this, the film deposition may be carried out while heating the substrate. For example, below transistor 10 When a semiconductor element layer is provided, a relatively low temperature range (for example, 350°C or more, 445°C or more) It may be heated in a temperature range of approximately °C or below.

[0301] Next, the insulator 104 is deposited (see Figures 17(C) and 17(D)). Insulator 10 For 4, the above-mentioned insulator can be used. The insulator 104 is deposited by sputtering, C This can be performed using methods such as the VD method, MBE method, PLD method, or ALD method.

[0302] Furthermore, it is preferable that the upper or lower surface of the semiconductor 106b, which is formed later, has high flatness. Therefore, planarization treatments such as CMP treatment are performed on the upper surface of the insulator 104 to improve its flatness. That's fine.

[0303] Next, it is preferable to perform a heat treatment.

[0304] Next, an insulating film is formed to become the insulating film 106a. The insulating film is the insulating film 106a described above and Any insulator or semiconductor that can be used for this purpose may be used. The deposition of the insulator film is performed by spa This can be done using methods such as tarring, CVD, MBE, PLD, or ALD. Cut.

[0305] Next, a semiconductor film that will become semiconductor 106b is deposited. The semiconductor is the aforementioned semiconductor 106b and Any semiconductor that can be used for this purpose should be used. Semiconductor film deposition can be done by sputtering, C This can be done using methods such as the VD method, MBE method, PLD method, or ALD method. By performing the deposition of the body film and the deposition of the semiconductor film in succession without exposure to the atmosphere, the film and This reduces the inclusion of impurities at the interface.

[0306] Next, it is preferable to perform a heat treatment. By performing the heat treatment, the insulator 105 and insulator 1 The amount of water or hydrogen in 03 and the insulator 104 can be further reduced. It may be possible to introduce excess oxygen into the edge body 104. Heat treatment is performed at 250°C or higher. 650°C or lower, preferably 450°C to 600°C, more preferably 520°C or higher The process should be carried out at temperatures below 70°C. The heat treatment should be performed in an inert gas atmosphere or with 10 pp of oxidizing gas. The procedure should be carried out in an atmosphere containing m or more, 1% or more, or 10% or more. Heat treatment can also be performed under reduced pressure. Good. Alternatively, the heat treatment can be performed by heating in an inert gas atmosphere and then replenishing the desorbed oxygen. Therefore, heat treatment is performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. It may be done. By heat treatment, an insulator 106a and a semiconductor 106b are produced. It can improve the crystallinity of semiconductors and remove impurities such as hydrogen and water. Heat treatment can also be performed using an RTA device with lamp heating. Because it can be done in a shorter time compared to a furnace, it is effective in increasing productivity.

[0307] Furthermore, if a semiconductor element layer is provided below the transistor 10, a relatively low temperature range It can be heated in a range (for example, a temperature range of approximately 350°C to 445°C). If, any of the substrate heating temperatures during film formation of insulator 105, insulator 103, and insulator 104. It is preferable to set the heating temperature below the highest of the above.

[0308] Next, a resist or the like is formed on the semiconductor, and the resist or the like is used for processing to create an insulator 106 Forms a and semiconductor 106b (see Figures 17(E) and 17(F)).

[0309] Next, it is preferable to perform a heat treatment. By performing the heat treatment, the insulator 105 and insulator 1 The amount of water or hydrogen in 03 and the insulator 104 can be further reduced. It may be possible to introduce excess oxygen into the edge body 104. Heat treatment is performed at 250°C or higher. 650°C or lower, preferably 450°C to 600°C, more preferably 520°C or higher The process should be carried out at temperatures below 70°C. The heat treatment should be performed in an inert gas atmosphere or with 10 pp of oxidizing gas. The procedure should be carried out in an atmosphere containing m or more, 1% or more, or 10% or more. Heat treatment can also be performed under reduced pressure. Good. Alternatively, the heat treatment can be performed by heating in an inert gas atmosphere and then replenishing the desorbed oxygen. Therefore, heat treatment is performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. It may be done. By heat treatment, an insulator 106a and a semiconductor 106b are produced. It can improve the crystallinity of semiconductors and remove impurities such as hydrogen and water. Heat treatment can also be performed using an RTA device with lamp heating. Because it can be done in a shorter time compared to a furnace, it is effective in increasing productivity.

[0310] Furthermore, if a semiconductor element layer is provided below the transistor 10, a relatively low temperature range It can be heated in a range (for example, a temperature range of approximately 350°C to 445°C). If, any of the substrate heating temperatures during film formation of insulator 105, insulator 103, and insulator 104. It is preferable to set the heating temperature below the highest of the above.

[0311] Next, the insulator 106c is deposited (see Figures 17(G) and 17(H)). Insulator 1 06c can be an insulator or semiconductor that can be used as the insulator 106c mentioned above. You can use this. The insulator 106c can be deposited by sputtering, CVD, MBE, or This can be done using methods such as the PLD method and ALD method.

[0312] Next, conductive films that will become conductive film 108a and conductive film 108b are formed. You can use conductors that can be used as the conductors 108a and 108b described above. The deposition of conductive films can be done using sputtering, CVD, MBE, PLD, or ALD methods. This can be done using methods such as [mention specific methods].

[0313] Furthermore, here, the semiconductor 106b and the insulator 106c are near the conductor that will become the conductor 108. A low-resistance region 109 may be formed in the adjacent region.

[0314] Next, a resist or the like is formed on the conductive material, and the conductive material 108 is processed using the resist or the like. It forms.

[0315] Next, an insulator 113, which will become the insulator 110, is formed. The insulator 113 is the insulator described above. Any insulator that can be used as 110 is acceptable. The film deposition of insulator 113 is performed spat This can be done using methods such as Taring, CVD, MBE, PLD, or ALD. ru.

[0316] When forming the insulator 110, a region 1 having silicon and oxygen is formed on the surface of the conductor 108. 11 may be formed (see Figures 18(A) and 18(B)). Note that the insulator Even if 110 is not formed, region 111 may be formed, and also the formation of the insulator 110 Depending on the film conditions, region 111 may not be formed during the deposition of the insulator 110.

[0317] Next, a resist or the like is formed on the insulator 113, and the insulator is processed using the resist or the like. 110, region 108c, region 108d, conductor 108a and conductor 108b are formed (See Figures 18(C) and 18(D).) Also, in this case, the low In order to remove the resistive region 109, a portion of the insulator 106c and semiconductor 106b is processed. That's good too.

[0318] Next, high-density plasma treatment may be performed. High-density plasma treatment is performed in an atmosphere containing oxygen. It is preferable to do so. An atmosphere containing oxygen is a gaseous atmosphere containing oxygen atoms, and oxygen , ozone or nitrogen oxides (nitric oxide, nitrogen dioxide, dinitrogen monoxide, dinitrogen trioxide, 4) This refers to an atmosphere containing nitrogen oxides (such as dinitrogen oxide and dinitrogen pentoxide). It also refers to an atmosphere containing oxygen, such as nitrogen. It may contain an inert gas, such as an element or a noble gas (helium, argon, etc.). By performing high-density plasma treatment in an oxygen-containing atmosphere, for example, carbon, hydrogen, It is possible to remove substances such as [unclear]. Also, high-density plasma treatment can be performed in an oxygen-containing atmosphere. This also makes it easier to remove organic compounds such as hydrocarbons from the material being treated.

[0319] Furthermore, annealing may be performed before or after high-density plasma treatment. To increase the temperature, it is sometimes preferable to flow a sufficient amount of gas. Otherwise, the deactivation rate may be higher than the radical generation rate. For example, if the gas is 1 It is preferable to flow at a rate of 00 sccm or more, 300 sccm or more, or 800 sccm or more. be.

[0320] High-density plasma processing is performed, for example, at frequencies of 0.3 GHz to 3.0 GHz or 2.2 Generated using a high-frequency generator with a frequency range of GHz to 2.8GHz (typically 2.45GHz). A microwave with a controlled flow should be used. Furthermore, the processing pressure should be between 10 Pa and 5000 Pa. Preferably 200 Pa to 1500 Pa, more preferably 300 Pa to 1000 Pa a. The substrate temperature is set to 100°C to 600°C (typically 400°C), and oxygen and aluminum are used. This can be done using a gas mixture with GON.

[0321] High-density plasma can be generated, for example, by using microwaves at 2.45 GHz. High-density plasma processing has an electron density of 1 × 10⁻¹⁶. 11 / cm 3 The above 1 x 10 13 / cm 3 below, It is preferable to carry out the process under conditions where the electron temperature is 2 eV or less, or the ion energy is 5 eV or less. This type of high-density plasma processing has low radical kinetic energy, unlike conventional plasma Compared to other processing methods, it causes less damage from plasma. Therefore, it forms a film with fewer defects. It is possible. The distance from the microwave-generating antenna to the object to be processed is 5 mm or more. It is preferable that the length be 0 mm or less, and preferably between 20 mm and 60 mm.

[0322] Alternatively, a plasma that applies an RF (Radio Frequency) bias to the substrate side. It may have a power supply. The RF bias frequency is, for example, 13.56 MHz or 27.1 MHz. Using 2MHz or similar frequencies would suffice. High-density plasma generates high-density oxygen ions. This can be achieved by applying an RF bias to the substrate side, generating a high-density plasma. The oxygen ions can be efficiently guided to the material being processed. It can efficiently guide oxygen ions into areas such as the inside of the opening. Therefore, the substrate bias is It is preferable to perform high-density plasma processing while applying the plasma.

[0323] Furthermore, after high-density plasma treatment, annealing is performed continuously without exposure to the atmosphere. This is also good. Furthermore, high-density plasma treatment can be performed continuously after annealing without exposure to the atmosphere. This can be done by performing high-density plasma treatment and annealing treatment in succession. This suppresses the introduction of impurities during processing. Furthermore, high-density plasma in an oxygen atmosphere... After processing, annealing is performed to remove some of the oxygen added to the treated material. Unnecessary oxygen that was not used to compensate for oxygen deficiency can be removed. Also, as mentioned above, Nealing can be performed, for example, by ramp annealing.

[0324] Furthermore, the processing time for high-density plasma treatment is 30 seconds to 120 minutes, and 1 minute to 90 minutes. Preferably, the duration should be between 2 minutes and 30 minutes, or between 3 minutes and 15 minutes.

[0325] Furthermore, the annealing process is performed at temperatures of 250°C to 800°C, 300°C to 700°C, or 4 Processing times between 00°C and 600°C are 30 seconds to 120 minutes, and 1 minute to 90 minutes. It is preferable to set the duration to between 2 and 30 minutes, or between 3 and 15 minutes.

[0326] By performing high-density plasma treatment and / or annealing treatment, the semiconductor 106b The defect levels in the channel formation region can be reduced. The region can be made to be of high purity and intrinsic. In doing so, a portion of the low-resistance region 109 is also made to have high resistance. It may be separated into low-resistance region 109a and low-resistance region 109b. Also, conductor 1 Regions 108c and 108d are also formed on the sides of 08a and the conductor 108b. This is possible (see Figures 18(E) and 18(F)).

[0327] Next, an insulator 132 is formed. The insulator 132 is the same as the insulator 112 described above. Any insulator that can perform this function should be used. The insulator 132 can be deposited by sputtering or CVD. This can be done using methods such as the MBE method, PLD method, or ALD method. By performing the deposition of film 26c and the deposition of insulator 132 in a continuous manner without exposure to the atmosphere, This reduces the inclusion of impurities in the film and at the interface.

[0328] Next, the conductive film 134 is deposited (see Figures 19(A) and 19(B)). Conductive film 13 For 4, any conductor that can be used as the conductor 114 described above may be used. The film deposition of body 134 is performed by sputtering, CVD, MBE, PLD, ALD, etc. This can be done using the following: The deposition of the insulator 132 and the deposition of the conductor 134 are performed using the following: Performing the process continuously without exposure to the atmosphere reduces the incorporation of impurities into the film and its interface. It is possible.

[0329] Next, the conductor 134 is polished until the insulator 113 is exposed. , forming insulators 112 and 110 (see Figures 19(C) and 19(D)). ). Conductor 114 and insulator 112 are the gate electrode and of transistor 29, respectively. It functions as a gate insulator. By the method described above, the conductor 114 and the insulator 112 can be formed in a self-consistent manner.

[0330] Next, the insulator 116 is deposited (see Figures 19(E) and 19(F)). Insulator 11 For 6, the above-mentioned insulator can be used. The insulator 116 is deposited by sputtering, C This can be performed using methods such as the VD method, MBE method, PLD method, or ALD method.

[0331] Next, it is preferable to perform a heat treatment.

[0332] By following the above steps, a transistor 29 according to one aspect of the present invention can be manufactured.

[0333] By fabricating transistors using the method shown in this embodiment, heat resistance and acid resistance can be achieved. A transistor using a conductive material with chemical properties can be provided.

[0334] Furthermore, it is possible to provide a transistor with stable electrical characteristics. Or, non-conductive It can provide a transistor with low leakage current at normal operation. A transistor having the following electrical characteristics can be provided. Or, subthreshold It is possible to provide transistors with small swing values. Or, reliable transistors We can provide Zista.

[0335] Furthermore, by fabricating transistors using the method shown in this embodiment, relatively low During heating in a high temperature range, the supply of water, hydrogen, etc., to semiconductors such as 106b is suppressed. Therefore, a semiconductor element layer or wiring layer can be placed in the layer below the transistor. Even if formed, the transistor can be manufactured without degradation at high temperatures. ru.

[0336] The configurations and methods shown in this embodiment can be appropriately combined with the configurations and methods shown in other embodiments. They can be used together.

[0337] (Embodiment 3) <Manufacturing equipment> The following describes a manufacturing apparatus for high-density plasma processing according to one aspect of the present invention.

[0338] First, Figure 20 shows the configuration of a manufacturing equipment that minimizes the inclusion of impurities during the manufacturing of semiconductor devices and other equipment. Further explanation will be provided using Figure 22.

[0339] Figure 20 schematically shows a top view of the single-wafer multi-chamber manufacturing apparatus 2700. The manufacturing apparatus 2700 includes a cassette port 2761 for housing the substrate and a mechanism for aligning the substrate. An alignment port 2762 is provided, and an atmospheric substrate supply chamber 2701 is provided, and atmospheric substrate From the supply room 2701, the substrate is transported to the atmospheric substrate transport room 2702, and the substrate is brought in. Furthermore, a load lock chamber 2 switches the pressure inside the room from atmospheric pressure to reduced pressure, or from reduced pressure to atmospheric pressure. 703a and the removal of the substrate, and the room pressure is reduced from reduced pressure to atmospheric pressure, or from atmospheric pressure to reduced pressure. The unload lock chamber 2703b switches to pressure, and the transport chamber 27 transports the substrate in a vacuum. 04, chamber 2706a, chamber 2706b, chamber 2706c, It has a chamber 2706d.

[0340] Furthermore, the atmospheric substrate transport chamber 2702 is equipped with a load lock chamber 2703a and an unload lock chamber. It is connected to room 2703b, load lock room 2703a and unload lock room 2703 b is connected to the transport chamber 2704, and the transport chamber 2704 is a chamber 2706a, chamber - Connects to chambers 2706b, 2706c, and 2706d.

[0341] Furthermore, gate valves GV are provided at the connection points of each chamber, and atmospheric substrate supply chamber 2701 With the exception of the atmospheric substrate transport chamber 2702, each chamber can be independently maintained in a vacuum state. Furthermore, a transport robot 2763a is provided in the atmospheric substrate transport chamber 2702, and transport Room 2704 is equipped with a transport robot 2763b. Transport robot 2763a is also installed. The transport robot 2763b can transport the substrates within the manufacturing apparatus 2700. .

[0342] The back pressure (total pressure) in the transport chamber 2704 and each chamber is, for example, 1 × 10⁻⁶ -4 Below Pa, Preferably 3 × 10 -5 Pa or less, more preferably 1 × 10⁻⁶ -5 It should be Pa or less. , the transport chamber 2704 and the gas molecules (original) whose mass-to-charge ratio (m / z) is 18 in each chamber The partial pressure of the child is, for example, 3 × 10 -5 Pa or less, preferably 1 × 10⁻⁶ -5 Pa and below, Preferably 3 × 10 -6 The Pa level shall be less than or equal to Pa. Also, the transport chamber 2704 and each chamber The partial pressure of a gas molecule (atom) with m / z 28 is, for example, 3 × 10⁻¹⁰ -5 Pa and below are preferable. ku is 1 x 10 -5 Pa or less, more preferably 3 × 10 -6 The Pa level should be less than or equal to the transport level. The partial pressure of gas molecules (atoms) in chamber 2704 and each chamber with a m / z of 44 is, for example, , 3 x 10 -5 Pa or less, preferably 1 × 10⁻⁶ -5 Pa or less, more preferably 3 × 10 -6 It should be Pa or less.

[0343] The total pressure and partial pressure in the transport chamber 2704 and each chamber were measured using a mass spectrometer. It can be determined. For example, the quadrupole mass spectrometer (Q-mass) manufactured by ULVAC, Inc. (Also known as...) You can use Qulee CGM-051.

[0344] Furthermore, the transport chamber 2704 and each chamber are configured to minimize external or internal leaks. It is desirable to do so. For example, the leak rate of the transport chamber 2704 and each chamber is 3 x 10 -6 Pa·m 3 / s or less, preferably 1 × 10 -6 Pa·m 3 Set to / s or less. Also, for example, the leak rate of a gas molecule (atom) with m / z 18 is 1 × 10⁻⁶ -7 Pa ·m 3 / s or less, preferably 3 × 10 -8 Pa·m 3 It should be less than or equal to / s. Also, for example, m The leak rate of a gas molecule (atom) with / z = 28 is 1 × 10⁻⁶ -5 Pa·m 3 / s or less, Preferably 1 × 10 -6 Pa·m 3 The time interval should be less than or equal to / s. Also, for example, m / z is 44. The leak rate of gas molecules (atoms) is 3 × 10 -6 Pa·m 3 / s or less, preferably 1 × 1 0 -6 Pa·m 3 Set to / s or less.

[0345] Regarding the leak rate, the total pressure and partial pressure were measured using the aforementioned mass spectrometer. It can be derived. The leak rate depends on external leaks and internal leaks. External leaks This refers to the inflow of gas from outside the vacuum system due to tiny holes or sealing defects. The problem is caused by leaks from valves and other partitions within the vacuum system, or by the release of gases from internal components. To keep the leak rate below the above-mentioned values, both external and internal leaks are addressed. We need to take countermeasures.

[0346] For example, the opening and closing parts of the transport chamber 2704 and each chamber are sealed with metal gaskets. That is good. Metal gaskets are made of iron fluoride, aluminum oxide, or chromium oxide. It is preferable to use coated metal. Metal gaskets have better adhesion than O-rings. External leakage can be reduced. Also, by using iron fluoride, aluminum oxide, chromium oxide, etc. By using the passivation of the coated metal, impurities released from the metal gasket are included. This suppresses the release of gases and reduces internal leakage.

[0347] Furthermore, as a component of the manufacturing apparatus 2700, aluminum with low emission gas containing impurities is used. The following are used: um, chromium, titanium, zirconium, nickel, or vanadium. The component may be used after being coated with an alloy containing iron, chromium, and nickel. Alloys containing nickel and other materials are rigid, heat-resistant, and easy to process. Therefore, if the surface irregularities of the material are reduced by polishing or other means to reduce the surface area, the discharge It can reduce gas emissions.

[0348] Alternatively, the components of the aforementioned manufacturing apparatus 2700 may be made from iron fluoride, aluminum oxide, chromium oxide, etc. It may be covered with this.

[0349] The components of the manufacturing apparatus 2700 are preferably made of metal as much as possible, for example, quartz. When installing viewing windows or other components, the surface should be treated with iron fluoride or acid to suppress the release of gases. It is best to coat it thinly with aluminum oxide, chromium oxide, or similar materials.

[0350] The adsorbed material present in the transport chamber 2704 and each chamber is adsorbed to the inner walls, etc. This does not affect the pressure in the transport chamber 2704 and each chamber, however, the pressure in the transport chamber 2704 and each chamber This is the cause of gas release when exhausting the exhaust. Therefore, there is a correlation between the leak rate and the exhaust velocity. Although there is no pump with high exhaust capacity, the conveying chamber 2704 and each chamber are being used. It is important to remove as much of the adsorbed material as possible and to evacuate the system beforehand. To facilitate the detachment of the garment, the transport chamber 2704 and each chamber may be baked. Baking can increase the desorption rate of adsorbed substances by about 10 times. The process should be carried out at a temperature between 100°C and 450°C. At this time, an inert gas is supplied to the transport chamber 2704. When adsorbed substances are removed while being introduced into each chamber, they are difficult to remove by exhaust alone. The desorption rate of water and other substances can be further increased. By heating the mixture to a temperature similar to the rind temperature, the desorption rate of adsorbed substances can be further increased. It is preferable to use a noble gas as the inert gas in this case.

[0351] Alternatively, by introducing an inert gas such as a heated noble gas or oxygen, the transport chamber 270 4 and the pressure in each chamber is increased, and after a certain period of time, the transport chamber 2704 and each chamber are increased again. It is preferable to perform a treatment to exhaust the chamber. By introducing heated gas into the conveying chamber 2704 This allows for the removal of adsorbed material from the transport chamber 2704 and each chamber. - It can reduce impurities present within the material. This process should be repeated between 2 and 30 times. Preferably, it is effective to repeat the process in the range of 5 to 15 times. Specifically, temperature An inert gas or By introducing oxygen, etc., the pressure inside the transport chamber 2704 and each chamber can be raised to 0.1 Pa or higher. 10 kPa or less, preferably 1 Pa or more and 1 kPa or less, more preferably 5 Pa or more and 10 The pressure should be 0 Pa or less, and the period for maintaining the pressure should be between 1 minute and 300 minutes, preferably between 5 minutes and 120 minutes. The following should be done. After that, transport chamber 2704 and each chamber should be kept for 5 minutes to 300 minutes. Preferably, the system is ventilated for a period of 10 minutes to 120 minutes.

[0352] Next, the schematic cross-sectional view of chambers 2706b and 2706c is shown in Figure 21. I will explain using diagrams.

[0353] Chambers 2706b and 2706c are, for example, used to process high-density plasma This is a chamber capable of performing a machining process. Note that chamber 2706b and chamber -2706c differs only in the atmosphere used during high-density plasma processing. Since the structure is the same for all of them, we will explain them together below.

[0354] Chambers 2706b and 2706c are connected to the slot antenna plate 2808, It has a dielectric plate 2809, a substrate stage 2812, and an exhaust port 2819. Outside chambers 2706b and 2706c, etc., there is a gas supply source 2801 and Valve 2802, high-frequency generator 2803, waveguide 2804, and mode converter 2805 And gas tube 2806, waveguide 2807, matching box 2815, and high-frequency power supply. A 2816, a vacuum pump 2817, and a valve 2818 are provided.

[0355] The high-frequency generator 2803 is connected to the mode converter 2805 via the waveguide 2804. The mode converter 2805 is connected to the slot antenna board 2808 via the waveguide 2807. The slot antenna plate 2808 is positioned in contact with the dielectric plate 2809. The gas supply source 2801 is connected to the mode converter 2805 via valve 2802. And the gas tube passing through the mode converter 2805, waveguide 2807 and dielectric plate 2809 Gas is supplied to chambers 2706b and 2706c by 2806. Furthermore, the vacuum pump 2817 is connected to the valve 2818 and exhaust port 2819. It also has the function of exhausting gases, etc., from bar 2706b and chamber 2706c. The high-frequency power supply 2816 is connected to the board stage 2812 via the matching box 2815. Connecting.

[0356] The substrate stage 2812 has the function of holding the substrate 2811. For example, substrate 2811 It has the function of electrostatically or mechanically chucking. Also, high-frequency power supply 2816 or It functions as an electrode to which power is supplied. It also has a heating mechanism 2813 inside. It has a function to heat the substrate 2811.

[0357] Vacuum pump 2817 can be used in various ways, such as dry pumps, mechanical booster pumps, etc. On-pump, titanium sublimation pump, cryopump or turbomolecular pump In addition to the vacuum pump 2817, a cryotrap can be used. It is also possible to use a cryopump and cryotrap to efficiently exhaust water. Particularly preferable.

[0358] Furthermore, the heating mechanism 2813 may include, for example, a heating mechanism that uses a resistance heating element to heat. Alternatively, heat can be applied through heat conduction or thermal radiation from a medium such as a heated gas. It may also be used as a heating mechanism. For example, GRTA (Gas Rapid Thermal Annealing) or LRTA (Lamp Rapid Thermal An RTAs such as nealing can be used. GRTA uses high-temperature gas Heat treatment is performed. An inert gas is used as the heat treatment gas.

[0359] Furthermore, the gas supply source 2801 is connected to the purification unit via a mass flow controller. This is also acceptable. The gas used has a dew point of -80°C or lower, preferably -100°C or lower. It is preferable to use oxygen gas, nitrogen gas, and noble gas (such as argon gas). Just be there.

[0360] Examples of dielectric plates 2809 include silicon oxide (quartz), aluminum oxide, or acid Yttrium yttria (yttria) can be used. Also, on the surface of dielectric plate 2809, Another protective layer may be formed. This protective layer may include magnesium oxide, thiosulfate, and other materials. Tan, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silicon oxide, Aluminum oxide or yttrium oxide can be used. Dielectric plate 2809 is later Since it will be exposed to the particularly high-density region of the high-density plasma 2810 described above, a protective layer is provided. This can mitigate damage. As a result, the increase in particles during processing, etc. It can be suppressed.

[0361] The high-frequency generator 2803 can, for example, produce frequencies between 0.3 GHz and 3.0 GHz or 2.2 GHz. It has the function of generating microwaves between Hz and 2.8GHz. High-frequency generator 280 The microwaves generated in step 3 are transmitted to the mode converter 2805 via the waveguide 2804. The mode converter 2805 converts microwaves transmitted in TE mode to TEM mode. The microwaves are then transmitted to the slot antenna plate 2808 via waveguide 2807. It is transmitted. The slot antenna board 2808 has multiple slot holes, micro The wave passes through the slot hole and the dielectric plate 2809. And below the dielectric plate 2809 An electric field can be generated, creating a high-density plasma 2810. 810 contains ions and radicals corresponding to the type of gas supplied from the gas source 2801. Yes, they exist. For example, oxygen radicals or nitrogen radicals exist.

[0362] At this time, ions and radicals generated in the high-density plasma 2810 cause the substrate 2 The film on 811 can be modified. Furthermore, using the high-frequency power supply 2816, the substrate 2 It may be preferable to apply a bias to the 811 side. For example, the high-frequency power supply 2816 has RF (Radio Frequencies) with frequencies such as 13.56MHz and 27.12MHz. A power supply (ncy) can be used. By applying a bias to the substrate side, high-density plasma 28 This allows ions in 10 to efficiently reach deep into openings such as films on the substrate 2811. Cut.

[0363] For example, in chamber 2706b, oxygen is introduced from the gas supply source 2801 to achieve high density. Oxygen radical treatment is performed using plasma 2810, and in chamber 2706c, gas By introducing nitrogen from source 2801, nitrogen radicals can be produced using high-density plasma 2810. It can perform the process.

[0364] Next, the schematic cross-sectional view of chambers 2706a and 2706d is shown in Figure 22. I will explain using diagrams.

[0365] Chambers 2706a and 2706d are, for example, used to irradiate the workpiece with electromagnetic waves. This is a chamber capable of performing the following. Note that chamber 2706a and chamber 27 The only difference between 06d and this model is the type of electromagnetic wave used. Other components are the same. Since there are many points, we will explain them together below.

[0366] Chambers 2706a and 2706d are connected to one or more lamps 2820 and It also has a substrate stage 2825, a gas inlet 2823, and an exhaust port 2830. Outside of chambers 2706a and 2706d, etc., there is a gas supply source 2821 Valve 2822, vacuum pump 2828, and valve 2829 are provided.

[0367] The gas supply source 2821 is connected to the gas inlet 2823 via valve 2822. The empty pump 2828 is connected to the exhaust port 2830 via valve 2829. Lamp 2 820 is positioned opposite the board stage 2825. It has the function of holding the substrate 2824. In addition, the substrate stage 2825 has heating inside. It has a mechanism 2826 and a function for heating the substrate 2824.

[0368] Lamp 2820, for example, has the function of emitting electromagnetic waves such as visible light or ultraviolet light. A light source that meets the following criteria should be used. For example, wavelengths between 10 nm and 2500 nm, and above 500 nm. Emitting electromagnetic waves with peaks below 2000 nm, or between 40 nm and 340 nm. A light source with the necessary functionality should be used.

[0369] For example, lamp 2820 can be a halogen lamp, a metal halide lamp, or a xenon lamp. - such as clamps, carbon arc lamps, high-pressure sodium lamps or high-pressure mercury lamps A light source can be used.

[0370] For example, some or all of the electromagnetic waves emitted from the lamp 2820 reach the substrate 2824. By being absorbed, the film on the substrate 2824 can be modified. For example, the generation of defects. Alternatively, it can be reduced or impurities removed. Note that this can be done while heating the substrate 2824. This allows for efficient generation or reduction of defects, or removal of impurities.

[0371] Alternatively, for example, electromagnetic waves emitted from lamp 2820 may affect the substrate stage 2825 The substrate 2824 may be heated by generating heat. In that case, the inside of the substrate stage 2825 The heating mechanism 2826 is not required.

[0372] For vacuum pump 2828, refer to the description for vacuum pump 2817. Also, the heating mechanism. 2826 refers to the description of the heating mechanism 2813. Also, the gas supply source 2821 is See the description for gas supply source 2801.

[0373] By using the above manufacturing equipment, it is possible to suppress the contamination of the workpiece with impurities while modifying the film, etc. This becomes possible.

[0374] The configurations and methods shown in this embodiment can be appropriately combined with the configurations and methods shown in other embodiments. They can be used together.

[0375] (Embodiment 4) In this embodiment, a semiconductor device utilizing a transistor or the like according to one aspect of the present invention is provided. Let's explain an example of the circuit.

[0376] <Circuit> The following is an example of a semiconductor device circuit using a transistor or the like according to one aspect of the present invention. I will explain about this.

[0377] <CMOSインバータ> The circuit diagram shown in Figure 23(A) is a p-channel type transistor 2200 and an n-channel type transistor This is a so-called CMO (Continuously Multi-Motorized) configuration, where two Rangitar 2100s are connected in series, with each gate connected. This shows the configuration of the S-inverter.

[0378] <Structure of a semiconductor device 1> Figure 24 is a cross-sectional view of the semiconductor device corresponding to Figure 23(A). The semiconductor device shown in Figure 24 It has transistor 2200 and transistor 2100. Also, transistor Transistor 2100 is positioned above transistor 2200. Note that transistor 2100 is... You may refer to the explanation of transistor 20 shown in Figures 9(A) and 9(B) as appropriate, A semiconductor device according to one aspect of the present invention is not limited thereto. The transistor described in [the relevant section] can be used as transistor 2100. Regarding transistor 2100, please refer to the above-mentioned description of transistors as appropriate. do.

[0379] The transistor 2200 shown in Figure 24 is a transistor that uses a semiconductor substrate 450. Transistor 2200 is located in region 472a of the semiconductor substrate 450 and in the semiconductor substrate 450 It has region 472b, an insulator 462, and a conductor 454. The conductor 454 is tang Stainless steel, and a choice of silicon, carbon, germanium, tin, aluminum, or nickel. It is preferable to use a conductor having a region containing one or more elements.

[0380] In transistor 2200, regions 472a and 472b are the source region and It functions as a drain region. In addition, insulator 462 functions as a gate insulator. It has. In addition, the conductor 454 has the function of a gate electrode. Therefore, it is conductive The resistance of the channel formation region can be controlled by the potential applied to body 454. The potential applied to the conductor 454 causes conduction between region 472a and region 472b. Non-conductivity can be controlled.

[0381] The semiconductor substrate 450 can be, for example, a single semiconductor substrate such as silicon or germanium, or Other materials include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, and zinc oxide. A semiconductor substrate such as gallium oxide may be used. Preferably, the semiconductor substrate 450 and A single-crystal silicon substrate is used.

[0382] The semiconductor substrate 450 uses a semiconductor substrate having impurities that impart an n-type conductivity. Furthermore, as the semiconductor substrate 450, a semiconductor substrate having impurities that impart a p-type conductivity is used. It is acceptable to do so. In that case, the region that becomes transistor 2200 should be given an n-type conductivity. Alternatively, even if the semiconductor substrate 450 is i-type That's fine.

[0383] The upper surface of the semiconductor substrate 450 preferably has a (110) plane. This allows the This can improve the ON characteristics of the Rangista 2200.

[0384] Regions 472a and 472b are regions containing impurities that impart a p-type conductivity. In this way, transistor 2200 constitutes a p-channel transistor.

[0385] Furthermore, transistor 2200 is isolated from adjacent transistors by region 460, etc. Region 460 is an insulating region.

[0386] The semiconductor device shown in Figure 24 comprises an insulator 464, an insulator 466, an insulator 468, and a conductor. 480a, conductor 480b, conductor 480c, conductor 478a, conductor 478b And, conductor 478c, conductor 476a, conductor 476b, conductor 474a, conductive Body 474b, conductor 474c, conductor 496a, conductor 496b, conductor 496 c, conductor 496d, conductor 498a, conductor 498b, conductor 498c, Edge body 489, insulator 490, insulator 491, insulator 492, insulator 493, It has a rim 494, a conductor 480a, a conductor 480b, and a conductor 480c. tungsten, and silicon, carbon, germanium, tin, aluminum, or nickel It is preferable to use a conductor having a region containing one or more elements selected from the above.

[0387] Insulator 464 is placed on transistor 2200. Also, insulator 466 is insulator 4 It is placed on 64. Also, insulator 468 is placed on insulator 466. Also, insulator 4 89 is placed on the insulator 468. Also, transistor 2100 is placed on the insulator 489. Place them. Also, the insulator 493 is placed on the transistor 2100. Also, insulator 4 94 is placed on the insulator 493.

[0388] The insulator 464 has an opening that reaches region 472a and an opening that reaches region 472b, and a conductive It has an opening that reaches the body 454, and a conductive material 480a in the opening, and a conductive material A conductive material 480b or conductor 480c is embedded within it.

[0389] Furthermore, the insulator 466 has an opening that reaches the conductor 480a and an opening that reaches the conductor 480b. It has a section and an opening that reaches a conductor 480c. 478a, conductor 478b, or conductor 478c are embedded.

[0390] Furthermore, the insulator 468 has an opening that reaches the conductor 478b and an opening that reaches the conductor 478c. It has a section and a conductor 476a or a conductor 476b embedded in the openings, respectively. It's embedded.

[0391] Furthermore, the insulator 489 has an opening that overlaps with the channel formation region of the transistor 2100, and a conductor It has an opening that reaches the electric body 476a and an opening that reaches the conductor 476b. A conductor 474a, conductor 474b, or conductor 474c is embedded in each opening. It is.

[0392] The conductor 474a may also function as the gate electrode of the transistor 2100. Alternatively, for example, by applying a constant potential to the conductor 474a, the transistor 210 You may also control electrical characteristics such as a threshold voltage of 0. Or, for example, conductor 474 a and the conductor 504 which functions as the gate electrode of transistor 2100 are electrically connected. It is acceptable to connect it. Doing so will increase the on-current of transistor 2100. This can be done. Also, because the punch-through phenomenon can be suppressed, transistor 210 The electrical properties in the saturation region of 0 can be stabilized. Note that the conductor 474a is as described above. Since this corresponds to the conductor 102 in the embodiment, please refer to the description of conductor 102 for details. It is possible.

[0393] Furthermore, the insulator 490 has an opening that reaches the conductor 474b and an opening that reaches the conductor 474c. It has a part and a part. Note that the insulator 490 corresponds to the insulator 103 in the above embodiment, For further details, please refer to the description of insulator 103. As such, an insulator 490 is provided so as to cover the conductors 474a to 474c, except for the opening. By doing so, the conductors 474a to 474c extract oxygen from the insulator 491. This can be prevented. This allows the oxide semiconductor of transistor 2100 to be separated from insulator 491. It can effectively supply oxygen.

[0394] Furthermore, the insulator 491 has an opening that reaches the conductor 474b and an opening that reaches the conductor 474c. It has a part and a part. Note that the insulator 491 corresponds to the insulator 104 in the above embodiment, For further details, please refer to the description of insulator 104.

[0395] As shown in the above embodiment, by reducing the water and hydrogen content of the insulator 491, This makes it possible to suppress the formation of defect levels in the oxide semiconductor of transistor 2100. This allows the electrical characteristics of transistor 2100 to be stabilized.

[0396] Furthermore, this type of insulator with reduced water and hydrogen content is not limited to insulator 491, but also applies to other insulators. It may be used for the following purposes. For example, insulator 466, insulator 468, insulator 489, insulator 493 It can be used in any way.

[0397] Furthermore, in Figure 24, these correspond to insulators 105 and 101 in transistor 20. Although the insulators are not shown in the diagram, it is certainly possible to have a configuration that includes them. For example, An insulator equivalent to the insulator 101 may be provided between the edge 468 and the insulator 489, or an insulating An insulator equivalent to the insulator 105 may be provided between the body 489 and the insulator 490. In particular, Between the edge 468 and the insulator 489 is an insulator equivalent to 101 that blocks water, hydrogen, etc. By providing a functional insulator, the water and hydrogen content of the insulator 491 is reduced as described above. This further suppresses the formation of defect levels in the oxide semiconductor of transistor 2100. It is possible.

[0398] Furthermore, the insulator 492 is located on either the source electrode or the drain electrode of the transistor 2100. An opening that passes through a certain conductor 516b and reaches conductor 474b, and transistor 2100 An opening that reaches the conductor 516a, which is the other of the source electrode or drain electrode, and An opening that reaches the conductor 504, which is the gate electrode of the ZISTA 2100, and an opening that reaches the conductor 474c It has an opening and, Note that the insulator 492 corresponds to the insulator 116 in the above embodiment. For further details, please refer to the description of insulator 116.

[0399] Furthermore, the insulator 493 is located on either the source electrode or the drain electrode of the transistor 2100. An opening that passes through a certain conductor 516b and reaches conductor 474b, and transistor 2100 An opening that reaches the conductor 516a, which is the other of the source electrode or drain electrode, and An opening that reaches the conductor 504, which is the gate electrode of the ZISTA 2100, and an opening that reaches the conductor 474c It has an opening and a conductor 496a and a conductor 496b. , a conductor 496c or conductor 496d is embedded. However, each opening Furthermore, when passing through an opening in any of the components such as transistor 2100. There is.

[0400] Furthermore, the insulator 494 has an opening that reaches the conductor 496a, and the conductor 496b and the conductor It has an opening that reaches 496d and an opening that reaches the conductor 496c. Each of them has a conductor 498a, conductor 498b, or conductor 498c embedded in it. ru.

[0401] Insulator 464, insulator 466, insulator 468, insulator 489, insulator 493 and insulator Examples of 494 include boron, carbon, nitrogen, oxygen, fluorine, magnesium, and aluminum. Um, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium An insulator containing conium, lanthanum, neodymium, hafnium, or tantalum, in a single layer, Alternatively, it can be used in a laminated configuration.

[0402] Insulator 464, insulator 466, insulator 468, insulator 489, insulator 493 or insulator One or more of 494 have an insulator that has the function of blocking impurities such as hydrogen and oxygen. It is preferable to have impurities such as hydrogen and oxygen near transistor 2100. By arranging an insulator that has a locking function, the electrical characteristics of transistor 2100 It can stabilize sexuality.

[0403] Examples of insulators that have the function of blocking impurities such as hydrogen and oxygen include boron. Element, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, Argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium An insulator containing hafnium or tantalum may be used in a single layer or in a multilayer structure.

[0404] Conductor 454, conductor 480a, conductor 480b, conductor 480c, conductor 478a, conductor Conductor 478b, Conductor 478c, Conductor 476a, Conductor 476b, Conductor 474a, Conductor Conductor 474b, Conductor 474c, Conductor 496a, Conductor 496b, Conductor 496c, Conductor The conductive material 496d, conductive material 498a, conductive material 498b, and conductive material 498c are tang Stainless steel, and a choice of silicon, carbon, germanium, tin, aluminum, or nickel. A conductor having a region containing one or more elements can be used. In particular, tungsten A conductor having silicon is preferred. Also, boron, nitrogen, oxygen, fluorine, silicon Cone, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc Gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, A conductor containing one or more of tin, tantalum, and tungsten is used in a single layer or in a multilayer structure. It may also be an alloy or compound, such as a conductor containing aluminum, copper and Conductors containing titanium, conductors containing copper and manganese, indium, tin and oxygen Conductors such as titanium and nitrogen may also be used.

[0405] Note that the semiconductor device shown in Figure 25 is the same as the semiconductor device shown in Figure 24, but with transistor 2200. The only difference is the structure. Therefore, the semiconductor device shown in Figure 25 is the same as the one shown in Figure 24. Refer to the description of the semiconductor device. Specifically, the semiconductor device shown in Figure 25 has two transistors. This indicates that transistor 200 is of the Fin type. The transistor 2200 is of the Fin type. This increases the effective channel width, thereby improving the on-characteristics of transistor 2200. This can be increased. Also, the contribution of the electric field of the gate electrode can be increased, This can improve the off-road characteristics of the Rangista 2200.

[0406] Furthermore, the semiconductor device shown in Figure 26 has the same transistor 2200 as the semiconductor device shown in Figure 24. The only difference is the structure. Therefore, the semiconductor device shown in Figure 26 is the same as the one shown in Figure 24. Refer to the description of the semiconductor device. Specifically, the semiconductor device shown in Figure 26 has two transistors. Figure 26 shows the case where 200 is provided on a semiconductor substrate 450 which is an SOI substrate. This shows a structure in which region 456 is separated from the semiconductor substrate 450 by an insulator 452. By using an SOI substrate as the conductive substrate 450, phenomena such as punch-through can be suppressed. This allows for an improvement in the off-peak characteristics of transistor 2200. The insulator 452 can be formed by making the semiconductor substrate 450 an insulator. For example, silicon oxide can be used as the insulator 452.

[0407] The semiconductor device shown in Figures 24 to 26 uses a semiconductor substrate and a p-channel transistor. To fabricate this and then fabricate an n-channel transistor above it, the occupied area of ​​the element is reduced. This can be done. In other words, the integration density of semiconductor devices can be increased. Also, n-channel A p-channel transistor and a p-channel transistor were fabricated using the same semiconductor substrate. Compared to other methods, the process can be simplified, thus increasing the productivity of semiconductor devices. This can be done. Furthermore, the yield of semiconductor devices can be increased. Also, p-channel type Langista is used in the LDD (Lightly Doped Drain) area and shallow training. In some cases, complex processes such as n-channel structure and strain design can be omitted. Compared to fabricating transistors using semiconductor substrates, this method offers higher productivity and yield. It may be possible to do so.

[0408] <CMOSアナログスイッチ> Furthermore, the circuit diagram shown in Figure 23(B) is for transistors 2100 and 2200. This shows a configuration where the source and drain are connected. It can function as a so-called CMOS analog switch.

[0409] <Storage device 1> A transistor according to one aspect of the present invention is used to retain stored data even when power is not supplied. Figure 27 shows an example of a semiconductor device (memory device) that can be stored and has no limit on the number of write cycles. This will be shown.

[0410] The semiconductor device shown in Figure 27(A) consists of a transistor 3200 using a first semiconductor and a second semiconductor It has a semiconductor transistor 3300 and a capacitive element 3400. For the transistor 3300, the same type of transistor as the transistor 2100 mentioned above is used. It is possible.

[0411] Transistor 3300 is preferably a transistor with a low off-current. Transistor 33 For example, 00 can use a transistor made of an oxide semiconductor. Due to the low off-current of the TA3300, it is possible to write to specific nodes of a semiconductor device over a long period of time. It is possible to retain the stored content. In other words, it does not require a refresh operation, or Because the refresh operation frequency can be made extremely low, low power consumption semiconductors It becomes a body device.

[0412] In Figure 27(A), the first wiring 3001 is electrically connected to the source of transistor 3200. The second wire 3002 is connected and electrically connected to the drain of transistor 3200. Furthermore, the third wire 3003 is electrically connected to one of the source and drain of transistor 3300. The fourth wire 3004 is connected to the gate of transistor 3300 and is electrically connected to the gate of transistor 3300. And the gate of transistor 3200, and the source of transistor 3300, The other end of the drain is electrically connected to one of the electrodes of the capacitive element 3400 and to the fifth wiring 30 05 is electrically connected to the other electrode of the capacitive element 3400.

[0413] The semiconductor device shown in Figure 27(A) is capable of maintaining the gate potential of transistor 3200. Having these characteristics, it is possible to write, hold, and read information as shown below. ru.

[0414] This section will explain how to write and retain information. First, the potential of the fourth wiring 3004 is set to the traction control. The potential is set so that transistor 3300 becomes conductive, and transistor 3300 becomes conductive. This causes the potential of the third wiring 3003 to be the gate of transistor 3200, and the capacitance It is supplied to node FG, which is electrically connected to one of the electrodes of the quantitative element 3400. That is, A predetermined charge is applied (written) to the gate of the ZISTA 3200. Here, different A charge that gives two potential levels (hereinafter referred to as low-level charge and high-level charge). One of the following is given. Then, the potential of the fourth wiring 3004 is set by the transistor The potential is set so that transistor 3300 becomes non-conductive, thereby causing transistor 3300 to become non-conductive. As a result, charge is retained at node FG.

[0415] Because the off-current of transistor 3300 is small, the charge at node FG is maintained over a long period of time. It is held.

[0416] Next, we will explain how to read the information. A predetermined potential (constant potential) is applied to the first wiring 3001. In this state, when an appropriate potential (readout potential) is applied to the fifth wiring 3005, the second wiring 3002 takes on a potential corresponding to the amount of charge held at node FG. This is the transistor. If 3200 is an n-channel type, then a high-level charge will be applied to the gate of transistor 3200. The apparent threshold voltage V when given th_H This is the transistor 3200 Apparent threshold voltage V when a low level charge is applied to the gate th_L Yo This is because it becomes lower. Here, the apparent threshold voltage is defined as the transistor 3200 This refers to the potential of the fifth wiring 3005 necessary to achieve a "conductive state". Then, set the potential of the fifth wiring 3005 to V th_H and V th_L By setting the potential V0 between these points, Therefore, the charge applied to node FG can be determined. For example, in writing, node FG If a high-level charge is applied, the potential of the fifth wiring 3005 will be V0(> V th_H ) In that case, transistor 3200 will be in a "conducting state". On the other hand, node FG If a low-level charge is applied, the potential of the fifth wiring 3005 is V0( <V th_L Even in this state, transistor 3200 remains in a "non-conductive state". By determining the potential of the second wiring 3002, the information held in node FG can be read. It can be released.

[0417] Furthermore, when memory cells are arranged in an array, the information of the desired memory cell is read. The information must be read. In memory cells from which no information is read, the node FG The potential such that transistor 3200 becomes "non-conductive" regardless of the given charge, that is, ri, V th_H By applying a lower potential to the fifth wiring 3005, the desired information of the memory cell can be obtained. The configuration should allow only the information to be read. Alternatively, in a memory cell from which no information is read... This means that transistor 3200 will be in a "conducting state" regardless of the charge applied to node FG. The potential, that is, V th_L By applying a higher potential to the fifth wiring 3005, the desired The configuration should allow only the information from the memory cells to be read.

[0418] In addition, the above example shows how to hold two types of charge at node FG, but this development Semiconductor devices relating to this are not limited to this. For example, at node FG of a semiconductor device A configuration that can hold three or more types of charge is also possible. The memory capacity of the semiconductor device can be increased by making it multi-level.

[0419] <Storage device structure 1> Figure 28 is a cross-sectional view of the semiconductor device corresponding to Figure 27(A). The semiconductor device shown in Figure 28 It comprises a transistor 3200, a transistor 3300, and a capacitive element 3400. Furthermore, transistor 3300 and capacitive element 3400 are located above transistor 3200. It is placed in the following location. Note that transistor 3300 is the same as transistor 2100 mentioned above. Refer to the description below. Also, as transistor 3200, the transistor shown in Figure 24 Refer to the description of transistor 2200. Note that in Figure 24, transistor 2200 is p We have explained the case of a channel-type transistor, but transistor 3200 is an n-channel type transistor. A Nell-type transistor would also be acceptable.

[0420] The transistor 3200 shown in Figure 28 is a transistor that uses a semiconductor substrate 450. Transistor 3200 is located in region 472a of the semiconductor substrate 450 and in the semiconductor substrate 450 It has a region 472b, an insulator 462, and a conductor 454.

[0421] The semiconductor device shown in Figure 28 comprises an insulator 464, an insulator 466, an insulator 468, and a conductor. 480a, conductor 480b, conductor 480c, conductor 478a, conductor 478b And, conductor 478c, conductor 476a, conductor 476b, conductor 474a, conductive Body 474b, conductor 474c, conductor 496a, conductor 496b, conductor 496 c, conductor 496d, conductor 498a, conductor 498b, conductor 498c, Edge body 489, insulator 490, insulator 491, insulator 492, insulator 493, It has a rim 494 and

[0422] Insulator 464 is placed on transistor 3200. Also, insulator 466 is insulator 4 It is placed on 64. Also, insulator 468 is placed on insulator 466. Also, insulator 4 89 is placed on the insulator 468. Also, transistor 3300 is placed on the insulator 489. Place them. Also, the insulator 493 is placed on the transistor 3300. Also, insulator 4 94 is placed on the insulator 493.

[0423] The insulator 464 has an opening that reaches region 472a and an opening that reaches region 472b, and a conductive It has an opening that reaches the body 454, and a conductive material 480a in the opening, and a conductive material A conductive material 480b or conductor 480c is embedded within it.

[0424] Furthermore, the insulator 466 has an opening that reaches the conductor 480a and an opening that reaches the conductor 480b. It has a section and an opening that reaches a conductor 480c. 478a, conductor 478b, or conductor 478c are embedded.

[0425] Furthermore, the insulator 468 has an opening that reaches the conductor 478b and an opening that reaches the conductor 478c. It has a section and a conductor 476a or a conductor 476b embedded in the openings, respectively. It's embedded.

[0426] Furthermore, the insulator 489 has an opening that overlaps with the channel formation region of the transistor 3300, and a conductor It has an opening that reaches the electric body 476a and an opening that reaches the conductor 476b. A conductor 474a, conductor 474b, or conductor 474c is embedded in each opening. It is.

[0427] The conductor 474a may also function as the bottom gate electrode of the transistor 3300. No. Or, for example, by applying a constant potential to the conductor 474a, a transistor can be formed. You may also control electrical characteristics such as the threshold voltage of 3300. Or, for example, a conductor 474a and the conductor 504, which is the top gate electrode of transistor 3300, are electrically connected. You can continue doing this. Doing so will increase the on-current of transistor 3300. This is possible. Furthermore, because the punch-through phenomenon can be suppressed, the transistor 3300 The electrical characteristics in the saturation region can be stabilized.

[0428] Furthermore, the insulator 490 has an opening that reaches the conductor 474b and an opening that reaches the conductor 474c. It has a part and a part. Note that the insulator 490 corresponds to the insulator 103 in the above embodiment, For further details, please refer to the description of insulator 103. As such, an insulator 490 is provided so as to cover the conductors 474a to 474c, except for the opening. By doing so, the conductors 474a to 474c extract oxygen from the insulator 491. This can be prevented. This allows the oxide semiconductor from insulator 491 to transistor 3300. It can effectively supply oxygen.

[0429] Furthermore, the insulator 491 has an opening that reaches the conductor 474b and an opening that reaches the conductor 474c. It has a part and a part. Note that the insulator 491 corresponds to the insulator 104 in the above embodiment, For further details, please refer to the description of insulator 104.

[0430] As shown in the above embodiment, by reducing the water and hydrogen content of the insulator 491, This makes it possible to suppress the formation of defect levels in the oxide semiconductor of transistor 2100. This allows the electrical characteristics of transistor 2100 to be stabilized.

[0431] Furthermore, this type of insulator with reduced water and hydrogen content is not limited to insulator 491, but also applies to other insulators. It may be used for the following purposes. For example, insulator 466, insulator 468, insulator 489, insulator 493 It can be used in any way.

[0432] Furthermore, in Figure 24, these correspond to insulators 105 and 101 in transistor 20. Although the insulators are not shown in the diagram, it is certainly possible to have a configuration that includes them. For example, An insulator equivalent to the insulator 101 may be provided between the edge 468 and the insulator 489, or an insulating An insulator equivalent to the insulator 105 may be provided between the body 489 and the insulator 490. In particular, Between the edge 468 and the insulator 489 is an insulator equivalent to 101 that blocks water, hydrogen, etc. By providing a functional insulator, the water and hydrogen content of the insulator 491 is reduced as described above. This further suppresses the formation of defect levels in the oxide semiconductor of transistor 3300. It is possible.

[0433] Furthermore, the insulator 492 is located on either the source electrode or the drain electrode of the transistor 3300. An opening that passes through a certain conductor 516b and reaches conductor 474b, and transistor 3300 The conductor 516a and the insulator 511, which are the other of the source electrode or drain electrode, are connected by a heavy An opening that reaches the conductive material 514 and the conductive material 5 which is the gate electrode of the transistor 3300 An opening reaching 04 and the other of the source electrode or drain electrode of transistor 3300 It has an opening that passes through a conductor 516a and reaches a conductor 474c. Body 492 corresponds to the insulator 116 in the above embodiment, therefore, for details, refer to insulator 116 The information provided can be taken into consideration.

[0434] Furthermore, the insulator 493 is located on either the source electrode or the drain electrode of the transistor 3300. An opening that passes through a certain conductor 516b and reaches conductor 474b, and transistor 3300 The conductor 516a and the insulator 511, which are the other of the source electrode or drain electrode, are connected by a heavy An opening that reaches the conductive material 514 and the conductive material 5 which is the gate electrode of the transistor 3300 An opening reaching 04 and the other of the source electrode or drain electrode of transistor 3300 It has an opening that passes through a conductor 516a and reaches a conductor 474c. Each part contains a conductor 496a, conductor 496b, conductor 496c, or conductor 496 d is embedded. However, each opening is further occupied by transistor 3300, etc. It may be through an opening in one of the components.

[0435] Furthermore, the insulator 494 has an opening that reaches the conductor 496a and an opening that reaches the conductor 496b. It has a section, an opening that reaches the conductor 496c, and an opening that reaches the conductor 496d. Furthermore, the openings are each connected to a conductor 498a, a conductor 498b, a conductor 498c, and a conductor The 498d battery is embedded.

[0436] Insulator 464, insulator 466, insulator 468, insulator 489, insulator 493 or insulator One or more of 494 have an insulator that has the function of blocking impurities such as hydrogen and oxygen. It is preferable to have impurities such as hydrogen and oxygen near transistor 3300. By arranging an insulator that has a locking function, the electrical characteristics of transistor 3300 It can stabilize sexuality.

[0437] The source or drain of transistor 3200 is connected to conductor 480b and conductor 478b. , via conductor 476a, conductor 474b, and conductor 496c, transistor 33 It is electrically connected to the conductor 516b, which is either the source electrode or the drain electrode of 00. Furthermore, the conductor 454, which is the gate electrode of transistor 3200, is made of conductor 480c and Through the conductive body 478c, conductive body 476b, conductive body 474c, and conductive body 496d, The conductor 516a, which is the source electrode or the other drain electrode of the lampistor 3300, and electricity Connect to the target.

[0438] The capacitive element 3400 is the other of the source electrode or drain electrode of the transistor 3300. It has a conductor 516a, a conductor 514, and an insulator 511. This is formed through the same process as the insulator that functions as the gate insulator of transistor 3300. Therefore, it is desirable that productivity can be increased. Also, as conductor 514 , formed through the same process as the conductor 504 which functions as the gate electrode of transistor 3300. Using a layered structure can be advantageous in some cases as it can increase productivity.

[0439] For other structural details, please refer to the descriptions in Figure 24 and other relevant documents as appropriate.

[0440] Note that the semiconductor device shown in Figure 29 is the same as the semiconductor device shown in Figure 28, but with transistor 3200. The only difference is the structure. Therefore, the semiconductor device shown in Figure 29 is the same as the one shown in Figure 28. Refer to the description of the semiconductor device. Specifically, the semiconductor device shown in Figure 29 has three transistors. This indicates that 200 is of the Fin type. Regarding transistor 3200, which is of the Fin type... For details, please refer to the description of transistor 2200 shown in Figure 25. Note that in Figure 25, We have explained the case where the transistor 2200 is a p-channel type transistor, but The STA3200 can be an n-channel transistor.

[0441] Furthermore, the semiconductor device shown in Figure 30 has transistor 3200 of the semiconductor device shown in Figure 28. The only difference is the structure. Therefore, the semiconductor device shown in Figure 30 is the same as the one shown in Figure 28. Refer to the description of the semiconductor device. Specifically, the semiconductor device shown in Figure 30 has three transistors. This shows the case where 200 is provided on a semiconductor substrate 450 which is an SOI substrate. The transistor 3200 provided on the semiconductor substrate 450 is shown in Figure 26. Refer to the description of transistor 2200. Note that in Figure 26, transistor 2200 is p We have explained the case of a channel-type transistor, but transistor 3200 is an n-channel type transistor. A Nell-type transistor would also be acceptable.

[0442] <Storage device 2> The semiconductor device shown in Figure 27(B) is different from the one in Figure 27(A) in that it does not have transistor 3200. This is different from the semiconductor device shown. In this case, it operates similarly to the semiconductor device shown in Figure 27(A). It allows for more efficient information writing and retention.

[0443] The information readout process in the semiconductor device shown in Figure 27(B) will be explained. When terminal 3300 becomes conductive, the floating third wiring 3003 and the capacitive element 3400 The two circuits become conductive, and charge is redistributed between the third wiring 3003 and the capacitive element 3400. As a result, the potential of the third wiring 3003 changes. The amount of change in the potential of the third wiring 3003 is the capacitance. The potential of one electrode of element 3400 (or the charge accumulated in the capacitive element 3400) They take on different values.

[0444] For example, let V be the potential of one electrode of the capacitive element 3400, C be the capacitance of the capacitive element 3400, and the third The capacitance component of wiring 3003 is CB, and the charge of the third wiring 3003 before redistribution is CB If the potential is VB0, then the potential of the third wiring 3003 after the charge has been redistributed is (CB × VB0 + CV) / (CB + C). Therefore, the state of the memory cell is a capacitive element. If one of the 3400 electrodes has a potential of two states, V1 and V0 (V1 > V0), The potential of the third wiring 3003 when the potential V1 is maintained is (=(CB × VB0 + CV1)) / (CB+C)) is the potential of the third wiring 3003 when the potential V0 is maintained (=(C) It can be seen that this is higher than B × VB0 + CV0) / (CB + C)).

[0445] Then, by comparing the potential of the third wiring 3003 with a predetermined potential, the information is read out. It is possible.

[0446] In this case, the first semiconductor is applied to the drive circuit for driving the memory cell. Using a transistor, a second semiconductor was applied to the transistor 3300. The components should be stacked and arranged on top of the drive circuit.

[0447] The semiconductor device described above utilizes an oxide semiconductor transistor with a low off-current. This makes it possible to retain memory content over a long period of time. In other words, refresh This eliminates the need for refresh operations or makes it possible to significantly reduce the frequency of refresh operations. Therefore, it is possible to realize semiconductor devices with low power consumption. Also, in situations where there is no power supply... Even if the potential is fixed (however, it is preferable that the potential remains fixed), the memory will not be stored for a long period of time. It is possible to maintain the volume.

[0448] Furthermore, since this semiconductor device does not require high voltage for writing information, element degradation does not occur. It is difficult. For example, unlike conventional non-volatile memory, the concentration of electrons on the floating gate Because electrons are not drawn in or out from the floating gate, the insulator does not deteriorate. The problem does not arise. That is, the semiconductor device according to one aspect of the present invention is a conventional non-volatile memory The semiconductor device has no limit on the number of rewrite cycles, which is a problem, and its reliability has been dramatically improved. Furthermore, information is written depending on whether the transistor is in a conductive or non-conductive state. This allows for high-speed operation.

[0449] <Storage device 3> A modified example of the semiconductor device (memory device) shown in Figure 27(A) is shown using the circuit diagram in Figure 31. I will explain.

[0450] The semiconductor device shown in Figure 31 includes transistors 4100 to 4400 and a capacitance element It has a sub-element 4500 and a capacitive element 4600. Here, the transistor 4100 is as described above. A transistor similar to transistor 3200 can be used, and transistor 420 For values ​​from 0 to 4400, the same type of transistor as transistor 3300 described above can be used. It can be done. Note that the semiconductor device shown in Figure 31, although not shown in Figure 31, is arranged in a matrix. Multiple units are provided. The semiconductor device shown in Figure 31 has wiring 4001, wiring 4003, wiring 400 The writing and reading of data voltages is controlled according to the signals or potentials applied to 5 through 4009. It can be controlled.

[0451] Either the source or drain of transistor 4100 is connected to wiring 4003. The source or drain of the transistor 4100 is connected to wiring 4001. In Figure 31, the conductivity type of transistor 4100 is shown as p-channel type, but n-channel type But that's fine.

[0452] The semiconductor device shown in Figure 31 has two data holding units. For example, the first data holding unit is The source or drain of transistor 4400 connected to node FG1, capacitance One electrode of element 4600, and one of the source or drain of transistor 4200 The charge is held between them. Also, the second data holding unit is connected to node FG2 The gate of transistor 4100, the other of the source or drain of transistor 4200, One of the source or drain electrodes of the zista 4300, and one of the electrodes of the capacitive element 4500 It holds charge in between.

[0453] The source or drain of transistor 4300 is connected to wiring 4003. The source or drain of the 4400 is connected to wiring 4001. The gate of transistor 4400 is connected to wiring 4005. The gate of transistor 4200 The gate of transistor 4300 is connected to wiring 4006. The gate of transistor 4300 is connected to wiring 4007. The other electrode of the capacitive element 4600 is connected to the wiring 4008. Capacitive element 45 The other electrode of 00 is connected to wiring 4009.

[0454] Transistors 4200 to 4400 control the writing of data voltage and the holding of charge. It functions as a switch. Transistors 4200 to 4400 are in a non-conductive state. In this case, a transistor with a low off-current (current flowing between the source and drain) is used. It is preferable to have an oxidation in the channel formation region. For transistors with low off-current, oxidation is preferable. It is preferable that the transistor has a semiconductor material (OS transistor). DISTRAs have advantages such as low off-current and the ability to be fabricated by stacking them with silicon transistors. There is. In Figure 31, the conductivity type of transistors 4200 to 4400 is n-channel type. As shown below, a p-channel type is also acceptable.

[0455] Transistors 4200 and 4300, and transistor 4400 are oxidized Even if a transistor using a solid semiconductor is used, it is preferable to place it in a separate layer. That is, Figure 3 The semiconductor device shown in 1, as shown in Figure 31, has a first layer 4 having a transistor 4100. 021 and a second layer 4022 having transistors 4200 and 4300 Preferably, the structure consists of a third layer 4023 having a transistor 4400. By stacking layers containing transistors, the circuit area can be reduced, and semiconductors can be used. This allows for miniaturization of the device.

[0456] Next, we will explain the process of writing information to the semiconductor device shown in Figure 31.

[0457] First, the data voltage is written to the data storage unit connected to node FG1 (hereinafter, This will explain the write operation (called write operation 1). Note that in the following, we will connect to node FG1. The data voltage to be written to the data storage unit is V D1 The threshold voltage of transistor 4100 Let Vth be the pressure.

[0458] In writing operation 1, wire 4003 is V D1 Then, after setting wiring 4001 to ground potential, Set it to an electrically floating state. Also, set wires 4005 and 4006 to a high level. Also, wire 4 Set 007 through 4009 to a low level. Then, node FG2, which is electrically floating, will be affected. The potential rises, and current flows through transistor 4100. As current flows, wiring 40 The potential of 01 rises. Also, transistors 4400 and 4200 become conductive. Therefore, as the potential of wiring 4001 rises, the potentials of nodes FG1 and FG2 rise. The potential of node FG2 rises, and the voltage between the gate and source of transistor 4100 increases. When the voltage (Vgs) reaches the threshold voltage Vth of transistor 4100, transistor 410 The current flowing through 0 becomes small. Therefore, the potential of wiring 4001, nodes FG1 and FG2 The rise has stopped, V D1 From there, only Vth went down, "V D1 -Vth is constant.

[0459] In other words, the V supplied to wiring 4003 D1 This occurs when current flows through transistor 4100. When applied to wiring 4001, the potential of nodes FG1 and FG2 rises. The potential of node FG2 is "V D1 When it becomes "-Vth", the Vgs of transistor 4100 is The current stops because it reaches Vth.

[0460] Next, the data voltage writing operation to the data holding unit connected to node FG2 (hereinafter, write This will explain the input operation, which is called input operation 2. Note that the data storage connected to node FG2 will also be explained. The data voltage to be written to the section is V D2 This will be explained as follows.

[0461] In writing operation 2, wire 4001 is V D2 Then, after setting wiring 4003 to ground potential, Set it to an electrically floating state. Also, set wiring 4007 to a high level. Also, wiring 4005, 4 Set 006, 4008, and 4009 to low levels. Ensure transistor 4300 is in a conductive state. This lowers the level of wiring 4003. As a result, the potential of node FG2 is also lowered. The voltage drops, and current flows through transistor 4100. This current flows through wiring 4003. The position rises. Also, transistor 4300 becomes conductive. Therefore, wiring 4003 As the potential increases, the potential at node FG2 increases. When Vgs becomes Vth of transistor 4100, transistor 4 The current flowing through 100 decreases. Therefore, the potential rise in wiring 4003, FG2 stops. ri, V D2 From there, only Vth went down, "V D2 -Vth is constant.

[0462] In other words, the V supplied to wiring 4001 D2 This occurs when current flows through transistor 4100. The voltage is applied to wiring 4003, causing the potential of node FG2 to rise. Due to the rise in potential, the node The potential of FG2 is "V D2 -Vth" means that the Vgs of transistor 4100 is Vth. Therefore, the current stops. At this time, the potential of node FG1 is, transistor 4200, 4 Both 400 and 400 are in a non-conductive state, and the "V" written in write operation 1 D1 -Vth" is retained It can be done.

[0463] In the semiconductor device shown in Figure 31, data voltages are written to multiple data holding units, and then wiring is performed. Set 4009 to a high level to increase the potential of nodes FG1 and FG2. Then, each By making the transistor non-conductive, charge transfer is eliminated, and the written data voltage is retained. .

[0464] The data voltage writing operation to nodes FG1 and FG2 described above allows multiple data The data holding section can hold the data voltage. The potential to be written is "V D 1-Vth" or "V D2 I explained using "-Vth" as an example, but these are multi-value data This is the data voltage corresponding to the data. Therefore, each data holding section holds 4 bits of data. If you want to retain the 16 values ​​of "V D1 -Vth" or "V D2 -Vth can be taken as an option.

[0465] Next, we will explain the operation of reading information from the semiconductor device shown in Figure 31.

[0466] First, the data voltage read operation to the data holding unit connected to node FG2 (hereinafter, This section will explain the read operation, which is called read operation 1.

[0467] In read operation 1, pre-charging is performed and then the wiring 4003 is set to an electrically floating state. Discharge the battery. Set wiring 4005 to 4008 to a low level. Also, set wiring 4009 to a low level. - As a level, the potential of node FG2, which is in an electrically floating state, is "V D2 -Vth" The potential of node FG2 decreases, causing current to flow through transistor 4100. As current flows, the potential of the electrically floating wiring 4003 decreases. Potential of wiring 4003 As the value decreases, the Vgs of transistor 4100 decreases. When Vgs becomes Vth of transistor 4100, the current flowing through transistor 4100 It becomes smaller. That is, the potential of wiring 4003 becomes the potential of node FG2 "V D2 -Vth" "V" is a value that is Vth larger than Vth. D2 This is the result. The potential of this wiring 4003 is at node F. Corresponds to the data voltage of the data holding unit connected to G2. The data of the read-out analog value The voltage is converted using A / D conversion, and data is acquired from the data storage unit connected to node FG2. .

[0468] In other words, the pre-charged wiring 4003 is left in a floating state, and the potential of wiring 4009 is set to a high level. Switching from the high to low level allows current to flow through transistor 4100. As a result, the potential of wiring 4003, which was in a floating state, decreases, resulting in "V D2 " and Tran In ZISTA 4100, the "V" of node FG2 D2 Vgs between "-Vth" becomes Vth. Therefore, the current stops. And the "V" written in writing operation 2 is connected to wiring 4003. D2 " is read out.

[0469] Once the data from the data storage unit connected to node FG2 is acquired, transistor 4300 As a continuity state, node FG2's "V D2 Discharge "-Vth".

[0470] Next, the charge held at node FG1 is distributed to node FG2, and connected to node FG1 The data voltage of the data holding unit is transferred to the data holding unit connected to node FG2. Set wiring 4001 and 4003 to low level. Set wiring 4006 to high level. Set wiring 4005 and wiring 4007 through 4009 to a low level. Transistor 4200 When the circuit becomes conductive, the charge at node FG1 is distributed between it and node FG2.

[0471] Here, the potential after charge distribution is the written potential "V D1 It decreases from "-Vth". Therefore, the capacitance value of the capacitive element 4600 is set to be larger than the capacitance value of the capacitive element 4500. This is preferable. Alternatively, the potential "V" to be written to node FG1 D1 -Vth" is the same day The potential "V" represents the power of ta. D2 It is preferable to make it larger than -Vth. Thus, the capacity value By changing the ratio and increasing the potential written in advance, the potential after charge distribution can be reduced. This can suppress the downward pressure. The fluctuation in potential due to charge distribution will be discussed later.

[0472] Next, the data voltage reading operation to the data holding unit connected to node FG1 (hereinafter, read This will explain the "outgoing action 2."

[0473] In read operation 2, pre-charging is performed and then the wiring 4003 is set to an electrically floating state. Discharge the battery. Set wiring 4005 to 4008 to a low level. Also, wiring 4009 is Set to high level during pre-charging, and then to low level afterward. Wiring 4009 to low level By doing so, the electrically floating node FG2 is brought to a potential "V" D1 -Vth As the potential of node FG2 decreases, current flows through transistor 4100. As a result, the potential of the electrically floating wiring 4003 decreases. As the voltage decreases, the Vgs of transistor 4100 decreases. When gs becomes Vth of transistor 4100, the current flowing through transistor 4100 becomes small. This means that the potential of wiring 4003 becomes the potential of node FG2 "V D1 -Vth" or Vth is a value that is larger than V D1 This is the result. The potential of this wiring 4003 is at node FG Corresponds to the data voltage of the data holding unit connected to 1. Readout analog value data The voltage is converted using A / D conversion, and data is acquired from the data storage unit connected to node FG1. The above describes the operation of reading the data voltage to the data holding unit connected to node FG1.

[0474] In other words, the pre-charged wiring 4003 is left in a floating state, and the potential of wiring 4009 is set to a high level. Switching from the high to low level allows current to flow through transistor 4100. As a result, the potential of wiring 4003, which was in a floating state, decreases, resulting in "V D1 " and Tran In ZISTA 4100, the "V" of node FG2 D1 Vgs between "-Vth" becomes Vth. Therefore, the current stops. And the "V" written in writing operation 1 is connected to wiring 4003. D1 " is read out.

[0475] The data voltage reading operation from nodes FG1 and FG2 described above allows multiple data The data voltage can be read from the data holding unit. For example, node FG1 and node By storing 4 bits (16 values) of data in each FG2, a total of 8 bits (256 values) are achieved. The data can be stored. Also, in Figure 31, the first layer 4021 to the third layer The structure consists of layer 4023, but by forming further layers, the surface of the semiconductor device This allows for an increase in memory capacity without increasing the product.

[0476] The read-out potential is a voltage that is Vth greater than the written data voltage. Therefore, the "V" written during the write operation D1 -Vth" or "V D2 - It is possible to configure it to read out by canceling out the Vth of "Vth". As a result, the memory cell In addition to improving the storage capacity of each unit, the data being read will be made closer to the correct data. This allows for the creation of highly reliable data.

[0477] Furthermore, Figure 32 shows a cross-sectional view of the semiconductor device corresponding to Figure 31. The semiconductor device shown in Figure 32 is , transistor 4100, transistor 4200, transistor 4300, transistor It has transistor 4400, capacitive element 4500 and capacitive element 4600. Here, transistor 4 100 is formed in the first layer 4021, transistor 4200, transistor 4300, And the capacitive element 4500 is formed in the second layer 4022, and the transistor 4400 and The quantitative element 4600 is formed in the third layer 4023.

[0478] Here, transistor 4200 to 4400 refers to transistor 3300, For transistor 4100, the description of transistor 3200 can be considered. Furthermore, the details in Figure 28 can be appropriately considered for other wiring, insulators, etc.

[0479] In addition, in the capacitive element 3400 of the semiconductor device shown in Figure 28, the conductive layer is provided parallel to the substrate. The configuration was designed to form capacitance, but in the capacitance elements 4500 and 4600, the conductive layer is trench-shaped. This configuration is designed to create capacity by providing a structure that occupies the same area. Even so, a large capacity value can be secured.

[0480] <Storage device 4> The semiconductor device shown in Figure 27(C) has a transistor 3500 and a sixth wiring 3006. It differs in several respects from the semiconductor device shown in Figure 27(A). In this case as well, it differs from the semiconductor device shown in Figure 27(A). Information can be written and retained using the same operation as the device. For transistor 3500, the same type of transistor as transistor 3200 mentioned above can be used.

[0481] The sixth wire 3006 is electrically connected to the gate of transistor 3500, and the transistor One of the sources and drains of transistor 3500 is electrically connected to the drain of transistor 3200. The source and drain of transistor 3500 are electrically connected to the third wire 3003. Connected.

[0482] Figure 33 shows an example of a cross-sectional view of the semiconductor device shown in Figure 27(C). Figure 34 shows the same as in Figure 33. An example of a cross-section roughly perpendicular to the A1-A2 direction is shown in Figures 33 and 34, as shown in Figure 27. The semiconductor device shown in C) has five layers, from layer 1627 to layer 1631. Layer 1627 is It has transistors 3200 to 3600. Layers 1628 and 1629 are It has a transistor 3300.

[0483] Layer 1627 consists of a substrate 1400 and transistors 3200 or more on the substrate 1400. The insulator 1464 above the transistor 3600 and the plug 1541, etc. It has a lug. Plug 1541 etc. is the gate electrode of transistor 3200 etc., for example, source Connect to an electrode or drain electrode, etc. Plug 1541 is designed to fill the insulator 1464. It is preferable that it be formed in this way.

[0484] For transistors 3200 through 3600, the description of transistor 2200 is as follows: The references can be taken into consideration.

[0485] Examples of insulators 1464 include silicon oxide, silicon oxide nitride, silicon nitride oxide, and silicon dioxide. Silicon oxide, aluminum oxide, aluminum nitride, aluminum nitride You can use materials like luminium.

[0486] Insulator 1464 is manufactured using sputtering, CVD (thermal CVD, MOCVD, PECVD) methods. It can be formed by methods such as the law, MBE method, ALD method, or PLD method. In particular, when the insulator is formed by a CVD method, preferably a plasma CVD method, the coverage is It is preferable because it can improve the situation. Also, to reduce damage from plasma, heat CVD, MOCVD, or ALD methods are preferred.

[0487] Furthermore, silicon carbide nitride (silicon carbonitr) is used as the insulator 1464. Using materials such as silicon oxycarbide. It can also be used with USG (Undoped Silicate Glass) and BPS. G(Boron Phosphorus Silicate Glass), BSG(B Orosilicate Glass, etc. can be used. USG, BPSG, etc. It can be formed using atmospheric pressure CVD. Also, for example, HSQ (hydrogen silsesquioxane) The following may be formed using a coating method.

[0488] The insulator 1464 may be a single layer or may be made by laminating multiple materials.

[0489] Here, Figure 33 shows the insulator 1464 as insulator 1464a and the insulator on insulator 1464a An example of a two-layer structure with 1464b is shown.

[0490] Insulator 1464a is located in region 1476 of transistor 3200, and other regions of transistor 3200. It is preferable that the material has good adhesion to and coverage with conductive material 1454, etc., which functions as a gate.

[0491] As an example of insulator 1464a, silicon nitride formed by the CVD method can be used. In this case, it may be preferable for the insulator 1464a to contain hydrogen. By having this element, defects such as those present in the substrate 1400 are reduced, and transistors 3200 etc. In some cases, the properties can be improved. For example, by using a material containing silicon as the substrate 1400. In this case, hydrogen can be used to terminate defects such as dangling bonds in silicon. .

[0492] Here, the conductor below the insulator 1464a, such as conductor 1454, and the insulator such as conductor 1511 It is preferable that the parasitic capacitance formed between the conductor formed on 1464b and the material is small. Therefore, it is preferable that the insulator 1464b has a low dielectric constant. It has a lower dielectric constant than insulator 1462, which functions as a gate insulator in devices such as ZISTA 3200. It is preferable that the dielectric constant of insulator 1464b is lower than that of insulator 1464a. Preferably, the relative permittivity of the insulator 1464b is less than 4, and more preferably less than 3. For example, the relative permittivity of insulator 1464b is 0. A ratio of 7 times or less is preferable, and a ratio of 0.6 times or less is more preferable.

[0493] Here, as an example, silicon nitride is used for insulator 1464a and USG is used for insulator 1464b. It is possible to be there.

[0494] Here, silicon nitride or silicon carbide nitride is used for insulators 1464a and 1581a, etc. By using materials with low copper permeability, such as n, when copper is used in the conductor 1511, etc. In addition, a method is available to suppress the diffusion of copper into the upper and lower layers such as insulator 1464a and insulator 1581a. There is a match.

[0495] Furthermore, for example, impurities such as copper can enter the upper layer from the upper surface of the conductor 1511 via the insulator 1584, etc. The substance may diffuse. Therefore, the insulator 1584 on the conductor 1511 is made of copper and other materials. It is preferable to use a material with low permeability of pure substances. For example, insulator 1584 is used as insulator 1 A laminated structure, such as the laminated structure of 581a and insulator 1581b, can be used.

[0496] Layer 1628 consists of an insulator 1581, an insulator 1584 on the insulator 1581, and an insulator 158 It has an insulator 1571 on 4 and an insulator 1585 on the insulator 1571. The conductor 1511 etc. on the body 1464, and the plug 1543 etc. connected to the conductor 1511 etc. It has a conductor 1513 on an insulator 1571. The conductor 1511 is open to the insulator 1581. It is preferable that it be formed to fill the opening. Plug 1543 etc. is insulated 1584 and It is preferable that the conductor 1513 is formed to fill the openings of the insulator 1571. Preferably, it is formed to fill the opening in the insulator 1585.

[0497] Furthermore, layer 1628 may have a conductor 1413. The conductor 1413 is an insulator 158 It is preferable that it be formed to fill the opening of 5.

[0498] For example, silicon oxide, silicon oxide nitride, etc., can be used as insulators 1584 and 1585. Silicon nitride, silicon nitride, aluminum oxide, aluminum nitride oxide, silicon nitride Aluminum, aluminum nitride, etc., can be used.

[0499] Insulators 1584 and 1585 were manufactured by sputtering, CVD (thermal CVD, M By methods such as OCVD, PECVD, MBE, ALD, or PLD In particular, the insulator can be formed by a CVD method, preferably a plasma CVD method. Depositing the film in this way is preferable because it can improve coverage. To reduce image, thermal CVD, MOCVD, or ALD methods are preferred.

[0500] Furthermore, as insulators 1584 and 1585, silicon carbide, silicon carbide nitride ( silicon carbonitride, silicon oxide (silicon o Xycarbide can be used. Also, USG (Undoped Si licate Glass), BPSG (Boron Phosphorus Sili Uses cate glass, BSG (Borosilicate Glass), etc. This is possible. USG, BPSG, etc., can be formed using atmospheric pressure CVD. Also, for example... For example, HSQ (hydrogen silsesquioxane) or the like may be formed using a coating method.

[0501] Insulators 1584 and 1585 may be single layers or multiple materials may be laminated together. stomach.

[0502] The insulator 1581 may be formed by laminating multiple layers. For example, as shown in Figure 33, Body 1581 consists of two layers: an insulator 1581a and an insulator 1581b on top of the insulator 1581a. That's good too.

[0503] Furthermore, the plug 1543 has a protrusion on the insulator 1571.

[0504] As conductors 1511, 1513, 1413, plug 1543, etc., metal materials Conductive materials such as alloy materials or metal oxide materials can be used. For example, A Aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, niobium, mo Metals such as ribdenum, silver, tantalum, or tungsten, or compounds with these as the main component. Gold can be used in a single-layer or multi-layer structure. Also, tungsten nitride, nitride Metal nitrides such as molybdenum and titanium nitride can be used.

[0505] Here, conductors such as conductor 1511 and conductor 1513 are the semiconductor device shown in Figure 27(C) It is preferable that these conductors function as wiring or wiring layers. It is sometimes referred to as such. Furthermore, these conductors are connected by plugs such as plug 1543. It is preferable.

[0506] For insulator 1581, refer to the description of insulator 1464. Also, insulator 1581 is single It may be a layer, or multiple materials may be laminated together. Here, in Figure 33, the insulator 1581 is An example is shown in which two layers are used: an insulator 1581a and an insulator 1581b on top of the insulator 1581a. Regarding materials that can be used for insulators 1581a and 1581b, and methods for forming them: The materials and shapes that can be used for insulators 1464a and 1464b, respectively. You can refer to the description of the method of production.

[0507] As an example of insulator 1581a, silicon nitride formed by CVD can be used. Here, the semiconductor element of the semiconductor device shown in Figure 27(C), for example, transistor 33 In the case of 00, the properties of the semiconductor element deteriorate due to the diffusion of hydrogen into the semiconductor element. This can occur. Therefore, it is preferable to use a film with a low hydrogen desorption rate as the insulator 1581a. It seems so. The amount of hydrogen desorption can be analyzed using, for example, TDS. Insulator 15 The amount of hydrogen desorption in 81a is measured in TDS in the range of 50°C to 500°C, and the hydrogen source For example, the amount of detachment converted to offspring is 5 × 10 20 atoms / cm 3 The following is preferably 2 × 10 20 atoms / cm 3 More preferably 1 × 10 20 atoms / cm 3 Below Alternatively, the amount of desorption of insulator 1581a, converted to hydrogen atoms, is per unit area of ​​the insulating film. For example, 5 x 10 15 atoms / cm 2 The following is preferably 2 × 10 15 atoms / cm 2 More preferably 1 × 10 15 atoms / cm 2 The following is acceptable.

[0508] Furthermore, silicon nitride with a low hydrogen desorption rate is suitable not only for insulator 1581a, It may also be used as an insulator in the layer above the insulator 1581a shown in Figure 33. Instead of condensate, an insulator similar to the insulator 104 shown in the above embodiment, with reduced hydrogen and water content, can be used. You may use your body.

[0509] Furthermore, it is preferable that the dielectric constant of the insulator 1581b is lower than that of the insulator 1581a. The relative permittivity of the insulator 1581b is preferably less than 4, and more preferably less than 3. Also, for example The relative permittivity of insulator 1581b is preferably 0.7 times or less of the relative permittivity of insulator 1581a. A ratio of 0.6 times or less is preferable.

[0510] The insulator 1571 is preferably formed using an insulating material with low impurity permeability. For example, the insulator 1571 is preferably of low oxygen permeability. Also, for example, insulator 157 Material 1 is preferably low in hydrogen permeability. Also, for example, insulator 1571 is low in water permeability. It is preferable.

[0511] Examples of insulators 1571 include aluminum oxide, hafnium oxide, tantalum oxide, and oxide. Zirconium, lead zirconate titanate (PZT), strontium titanate (SrTiO) 3) Or (Ba,Sr)TiO3 (BST), silicon nitride, etc., used in a single layer or multilayer structure. These insulators can be, for example, aluminum oxide, bismuth oxide, or oxide. Germanium, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yt oxide Zirconium oxide, zirconium oxide, and gallium oxide may be added. Alternatively, these insulators may be nitrogen oxides. It may also be treated to form an oxidized nitride. The above insulator may be silicon oxide, silicon oxidized nitride, Alternatively, silicon nitride may be used in a laminated form. In particular, aluminum oxide is effective against water and hydrogen. It is preferable because it has excellent barrier properties.

[0512] Furthermore, as the insulator 1571, for example, silicon carbide, silicon carbide nitride, silicon oxide carbide You may also use characters like "n".

[0513] The insulator 1571 is constructed by laminating a layer containing other insulating materials onto a layer of material with low water and hydrogen permeability. For example, a layer containing silicon oxide or silicon oxide nitride, or a layer containing a metal oxide. These can also be used in a stacked manner.

[0514] Here, for example, the semiconductor device shown in Figure 27(C) has an insulator 1571, which means that The elements present in the electric element 1513, the conductor 1413, etc., are present in the insulator 1571 and its lower layer (insulator This can suppress diffusion to the body 1584, insulator 1581, layer 1627, etc.

[0515] Here, if the dielectric constant of insulator 1571 is higher than that of insulator 1584, then insulator 1571 The film thickness is preferably smaller than the film thickness of the insulator 1584. Here, the specific induction of the insulator 1584 The electric charge is preferably 0.7 times or less the relative permittivity of the insulator 1571, more preferably 0. It is 0.6 times or less. Also, for example, the film thickness of the insulator 1571 is preferably 5 nm or more and 200 nm. The thickness of the insulator 1584 is preferably less than or equal to m, more preferably between 5 nm and 60 nm. The wavelength is between 30 nm and 800 nm, more preferably between 50 nm and 500 nm. Furthermore, for example, the film thickness of insulator 1571 is less than or equal to one-third of the film thickness of insulator 1584. preferable.

[0516] Figure 33 is a cross-sectional view showing some of the components of the semiconductor device shown in Figure 27(C). This includes an insulator 1464b and a plug 15 formed to be embedded in the insulator 1464b. 41, insulator 1581 on insulator 1464b, plug 1541 and insulator 1464 The conductor 1511 on b, the insulator 1584 on the insulator 1481, and the insulating material on the insulator 1584 The edge body 1571 and the insulator 1584 and the insulator 1571 are formed to be embedded in each other. A plug 1543 located on the conductor 1511, and an insulator 1585 on the insulator 1571, The plug 1543 and the conductor 1513 on the insulator 1571 are shown here. In the cross-section, the height of the highest region on the upper surface of the plug 1543 is the height of the insulator 1571 It is preferable that the height is greater than the height of the highest region on the upper surface.

[0517] Furthermore, when a portion of the insulator 1571 is removed, the opening for forming the conductor 1513 is also formed. There is.

[0518] Here, as an example, silicon nitride is used as insulator 1464a, and carbonized silicon nitride is used as insulator 1581a. Silicon nitride is used. Here, at least one of insulator 1571a or insulator 1571 is used. In this case, a material with low hydrogen permeability is used. For example, titanium nitride is used as the conductor 1513b. By using this, the hydrogen contained in silicon nitride and silicon carbide nitride is used in transistor 3 This can suppress the spread to 300.

[0519] Layer 1629 contains transistor 3300 and plugs such as plug 1544 and plug 1544b. The plugs have a lug and, plugs such as plug 1544 and plug 1544b, and layer 1628 The conductive material 1513, or the gate electrode, source electrode, or of the transistor 3300 Connect to the drain electrode. The configuration of transistor 3300 is as described above for transistor 20, You can refer to descriptions such as those for the Zista 2100.

[0520] Transistor 3300 consists of conductor 1413, insulator 1571a, insulator 1402, and conductor It has 1416a, conductor 1416b, conductor 1404, insulator 1408, and insulator 591. The configuration of transistor 3300 can be determined by taking into consideration the configuration of transistor 20. Yes, it is possible. Conductor 1413 is conductor 102, insulator 1571a is insulator 103, insulator 14 02 is insulator 104, conductor 1416a is conductor 108a, conductor 1416b is conductor 1 08b, Conductor 1404 is Conductor 114, Insulator 1408 is Insulator 116, Insulator 591 The insulator 118 can be taken into consideration. Also, in Figure 33, the transistor 20 Although an insulator equivalent to insulator 105 is not shown in the illustration, of course, a configuration that includes such an insulator is also available. This may also be done. For example, between insulator 1585 and insulator 1571a, there may be an insulator equivalent to insulator 105. An insulator may be provided.

[0521] Similar to the above embodiment, the insulator 1571 corresponds to the insulator 106a of the transistor 20. A laminate of insulating materials is provided between the insulating materials (in this embodiment, insulating material 1585, The amount of water or hydrogen contained in the laminate of insulator 1571a and insulator 1402 is low. This is preferable. As described above, the insulator 1571 has the function of blocking water and hydrogen. If we consider the edge material, the oxides that will become the insulator 106a and semiconductor 106b of transistor 20 are When forming the film, the water and hydrogen supplied to the oxide are insulator 1585 and insulator 1571. a. It is contained in insulator 1402. Therefore, when forming the oxide film, A laminate of edge 1585, insulator 1571a and insulator 1402, and in particular the insulator If the amount of water or hydrogen contained in 1402 is sufficiently small, then the oxide will contain water or hydrogen. The supply can be reduced.

[0522] Furthermore, the conductors 1416a and 1416b are plugs formed in contact with their upper surfaces. It is preferable to have a material with low permeability to the element 1544b.

[0523] Furthermore, the conductors 1416a and 1416b may be arranged as a multilayer film. Hereinafter, The conductors 1416a and 1416b are stacked as the first and second layers. Here, a first layer is formed on the oxide layer 406b, and a second layer is formed on the first layer. For example, tungsten is used as the first layer, and tantalum nitride is used as the second layer. For plugs like plug 1544b, copper is used. Copper has low resistance and is suitable for plugs and wiring. It is preferable to use it as a conductor. On the other hand, copper diffuses easily, and is used in the semiconductor layer of a transistor. This can sometimes degrade transistor characteristics by diffusing into the gate insulating film, etc. The conductors 1416a and 1416b have tantalum nitride, so the plug In some cases, it may be possible to suppress the diffusion of copper present in 1544b, etc., into the oxide layer 406b.

[0524] A semiconductor device shown in Figure 27(C) according to one aspect of the present invention has plugs, wiring, etc. that have characteristics of a semiconductor element. When elements and compounds that cause degradation are present, these elements and compounds may diffuse into the semiconductor device. It is preferable to have a structure that suppresses [the following].

[0525] Layer 1630 consists of an insulator 1592, a conductor such as a conductor 1514, and a plug such as a plug 1545. It has a lug. Plug 1545, etc., connects to a conductor such as conductor 1514.

[0526] Layer 1631 has a capacitive element 3400. The capacitive element 3400 has a conductor 1516. It has a conductor 1517 and an insulator 1571. The insulator 1571 is conductor 1516 It has a region sandwiched between the insulator 1594 and the conductor 1517. Also, layer 1631 has an insulator 1594 and a conductor It is preferable to have a plug 1547 on the body 1517. The plug 1547 is an insulator 15 It is preferable that the layer 1631 is formed to fill the 94 openings. A conductor 1516b connected to a plug that 0 has, and a plug 1547 on the conductor 1516b It is preferable that b is included.

[0527] Layer 1631 may also have a wiring layer that connects to plug 1547 or plug 1547b. i. In the example shown in Figure 33, the wiring layer is a conductor that connects to plug 1547 and plug 1547b. 1518 etc, plug 1548 on conductor 1518, insulator 1595, plug 154 It has a conductor 1519 on 8 and an insulator 1599 on the conductor 1519. Plug 154 8 is preferably formed to fill the opening in the insulator 1595. Also, insulator 1 599 has an opening on the conductor 1519.

[0528] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments. can.

[0529] (Embodiment 5) In this embodiment, an imaging device utilizing a transistor or the like according to one aspect of the present invention Let me give you an example.

[0530] <Imaging device> The following describes an imaging device according to one aspect of the present invention.

[0531] Figure 35(A) is a plan view showing an example of an imaging device 200 according to one aspect of the present invention. The unit 200 includes a pixel unit 210, a peripheral circuit 260 for driving the pixel unit 210, and a peripheral circuit It has a path 270, a peripheral circuit 280, and a peripheral circuit 290. The pixel section 210 has p rows and q columns. It has multiple pixels 211 arranged in a matrix (where p and q are integers greater than or equal to 2). Peripheral circuits 260, 270, 280, and 290 are each multiple It has the function of connecting to a number of pixels 211 and supplying signals to drive multiple pixels 211. Furthermore, in this specification, peripheral circuits 260, 270, and 280 are used. The term "peripheral circuit" or "drive circuit" is sometimes used to refer to all of these components, including peripheral circuitry 290. For example, peripheral circuit 260 can be considered part of the peripheral circuitry.

[0532] Furthermore, it is preferable that the imaging device 200 has a light source 291. The light source 291 is a detection light P It can emit 1.

[0533] Furthermore, the peripheral circuits include at least logic circuits, switches, buffers, amplification circuits, or converters. It has one of the circuits. Furthermore, the peripheral circuits may be formed on the substrate forming the pixel section 210. Furthermore, semiconductor devices such as IC chips may be used in part or all of the peripheral circuits. The peripheral circuits are peripheral circuit 260, peripheral circuit 270, peripheral circuit 280 and peripheral circuit 290. You may omit one or more of the following:

[0534] Furthermore, as shown in Figure 35(B), in the pixel section 210 of the imaging device 200, Pixels 211 may be arranged at an angle. By arranging pixels 211 at an angle, the row direction and The pixel spacing (pitch) in the column direction can be shortened. This allows the imaging device 200 to This allows for a further improvement in the quality of the images being captured.

[0535] <Example of pixel configuration 1> The imaging device 200 has one pixel 211 which is composed of multiple sub-pixels 212, and each sub By combining a filter (color filter) that transmits light in a specific wavelength range with pixel 212... This allows us to obtain the information necessary to display color images.

[0536] Figure 36(A) is a plan view showing an example of pixels 211 for acquiring a color image. The pixel 211 shown in 36(A) is equipped with a color filter that transmits light in the red (R) wavelength range. The sub-pixel 212 (hereinafter also referred to as "sub-pixel 212R") transmits light in the green (G) wavelength range. Sub-pixel 212 (hereinafter also referred to as "sub-pixel 212G") equipped with a color filter. and sub-pixels 212 (hereinafter referred to as follows) are provided with a color filter that transmits light in the blue (B) wavelength range. It has sub-pixels (also called "sub-pixels 212B"). Sub-pixel 212 functions as a photosensor. It can be done.

[0537] Sub-pixels 212 (sub-pixels 212R, 212G, and 212B) are connected to wiring 23 1. It is electrically connected to wires 247, 248, 249, and 250. Pixel 212R, sub-pixel 212G, and sub-pixel 212B are each connected by independent wiring 25 It is connected to 3. Also, in this specification, for example, it is connected to pixel 211 of the nth row. Wires 248 and 249 are denoted as wire 248[n] and wire 249[n], respectively. To include. Also, for example, the wiring 253 connected to the pixel 211 in the mth column is defined as wiring 253[m] This is stated. Note that in Figure 36(A), the subpixel 212R of pixel 211 in the mth column Wiring 253[m]R is connected to the sub-pixel 212G, and wiring 253 is connected to the sub-pixel 212G. Wiring 253 connected to line 253[m]G and sub-pixel 212B is connected to wiring 253[m]B As described above, the sub-pixel 212 is electrically connected to the peripheral circuitry via the above wiring.

[0538] Furthermore, the imaging device 200 uses color filters that transmit light in the same wavelength range for adjacent pixels 211. The configuration includes sub-pixels 212, each equipped with a luta, being electrically connected to each other via a switch. Figure 36(B) shows n rows (where n is an integer between 1 and p) and m columns (where m is an integer between 1 and q). The sub-pixels 212 of the placed pixel 211 and the adjacent n+1 row m column An example of the connection of subpixels 212 of the placed pixel 211 is shown. In Figure 36(B), row n Sub-pixel 212R located in column m and sub-pixel 212R located in row n+1 and column m are switched. It is connected via Chi 201. Also, the subpixels 212G arranged in n rows and m columns, and n+ Sub-pixels 212G, arranged in 1 row and m columns, are connected via switch 202. Sub-pixels 212B arranged in n rows and m columns, and sub-pixels 212B arranged in n+1 rows and m columns It is connected via switch 203.

[0539] Furthermore, the color filters used for sub-pixel 212 are limited to red (R), green (G), and blue (B). Color film that transmits cyan (C), yellow (Y), and magenta (M) light respectively. A LUTA may be used. A sub-pixel 2 detects light in three different wavelength ranges in one pixel 211. By adding 12, a full-color image can be obtained.

[0540] Alternatively, color filters that transmit red (R), green (G), and blue (B) light, respectively, are provided. In addition to the sub-pixels 212 that have been cut off, a sub-pixel with a color filter that transmits yellow (Y) light is provided. A pixel 211 having pixel 212 may be used. Alternatively, cyan (C) and yellow (Y) may be used, respectively. In addition to sub-pixels 212 equipped with a color filter that transmits ) and magenta (M) light, A pixel 21 has a sub-pixel 212 that is provided with a color filter that transmits blue (B) light. 1 may be used. A sub-pixel 21 detects light in four different wavelength ranges in one pixel 211. By adding step 2, the color reproduction accuracy of the acquired images can be further improved.

[0541] Furthermore, for example, in Figure 36(A), sub-pixel 212 detects light in the red wavelength range, and green wave Sub-pixels 212 for detecting long-range light, and pixels of sub-pixels 212 for detecting blue wavelength light. The numerical ratio (or light-receiving area ratio) does not have to be 1:1:1. For example, the pixel ratio (light-receiving area ratio) Alternatively, a Bayer array with an area ratio of red:green:blue = 1:2:1 may be used. Or, the number of pixels The ratio (light-receiving area ratio) can also be set to red:green:blue = 1:6:1.

[0542] Note that while one sub-pixel 212 may be provided in pixel 211, two or more are preferable. By providing two or more sub-pixels 212 that detect light in the same wavelength range, redundancy is increased, and imaging This can improve the reliability of device 200.

[0543] Furthermore, IR (Infrared) absorbs or reflects visible light and transmits infrared light. By using a filter, an imaging device 200 that detects infrared light can be realized.

[0544] Also, an ND (Neutral Density) filter (light-reducing filter) is used. This is because when a large amount of light is incident on a photoelectric conversion element (light-receiving element), the output saturation occurs. This can prevent this. By using a combination of ND filters with different light reduction amounts, the imaging device This allows for a wider dynamic range in the image.

[0545] In addition to the filter mentioned above, a lens may also be provided at pixel 211. Here, Figure 37 An example of the arrangement of pixels 211, filter 254, and lens 255 will be explained using a cross-sectional diagram. By providing the 255 element, the photoelectric conversion element can efficiently receive incident light. Specifically, as shown in Figure 37(A), a lens 255 and a filter 25 are formed on the pixel 211. 4 (filters 254R, 254G, and 254B), and pixel circuit 2 The structure can be configured to allow light 256 to be incident on the photoelectric conversion element 220 through 30, etc.

[0546] However, as shown in the area enclosed by the dashed line, a portion of the light 256 indicated by the arrow is connected to wiring 257. It may be partially blocked by something. Therefore, as shown in Figure 37(B), the photoelectric The lens 255 and filter 254 are placed on the side of the conversion element 220, and the photoelectric conversion element 220 A structure that efficiently receives light 256 is preferred. Light 256 is received from the photoelectric conversion element 220 side. By injecting light into the photoelectric conversion element 220, an imaging device 200 with high detection sensitivity is provided. It is possible.

[0547] As shown in Figure 37, the photoelectric conversion element 220 has a pn-type junction or a pin-type junction formed on it. Photoelectric conversion elements may also be used.

[0548] Furthermore, the photoelectric conversion element 220 uses a material that has the function of absorbing radiation and generating electric charge. It may be formed by absorbing radiation and generating an electric charge. Len, lead iodide, mercury iodide, gallium arsenide, cadmium telluride, cadmium zinc alloy These include:

[0549] For example, if selenium is used in the photoelectric conversion element 220, in addition to visible light, ultraviolet light, and infrared light, Photoelectric conversion element 22 having an optical absorption coefficient over a wide wavelength range, including X-rays and gamma rays. It is possible to achieve 0.

[0550] Here, one pixel 211 of the imaging device 200 is, in addition to the sub-pixel 212 shown in Figure 36, Furthermore, it may have a sub-pixel 212 having a first filter.

[0551] <Example of pixel configuration 2> Below, we will discuss transistors using silicon and transistors using oxide semiconductors. An example of how pixels are constructed using this method will be explained.

[0552] Figures 38(A) and 38(B) are cross-sectional views of the elements constituting the imaging device. The imaging device shown in A) is a silicon transistor provided on a silicon substrate 300. 351, A transistor using oxide semiconductors stacked on top of transistor 351 352 and transistor 353, and photodie provided on silicon substrate 300 Includes diode 360. Each transistor and photodiode 360 ​​is plugged into various plugs 3 It has electrical connections with 70 and wiring 371. Also, the photodiode 360 ​​has an outlet. Part 361 has an electrical connection with plug 370 via a low-resistance region 363.

[0553] The imaging device also includes a transistor 351 and a photodie provided on the silicon substrate 300. A layer 310 having an ore 360, and a layer 3 provided in contact with the layer 310 and having wiring 371 20 is provided in contact with layer 320 and has transistors 352 and 353. A layer 330, and a layer 330 provided in contact with the layer 330, having wiring 372 and wiring 373. It has 40.

[0554] In the example cross-sectional view in Figure 38(A), the transistor 35 is located on the silicon substrate 300. The configuration includes a photodiode 360 ​​with a light-receiving surface on the side opposite to the surface on which 1 is formed. This configuration ensures that the optical path is not affected by various transistors, wiring, etc. This allows for the formation of pixels with a high aperture ratio. The 360-degree light-receiving surface can also be the same as the surface on which transistor 351 is formed.

[0555] Furthermore, when constructing pixels using only transistors made of oxide semiconductors, layer 31 Layer 0 can be a layer containing a transistor made of oxide semiconductor. Alternatively, layer 310 can be omitted. In short, pixels may be constructed using only transistors made of oxide semiconductors.

[0556] Furthermore, when constructing pixels using only silicon transistors, layer 330 can be omitted. It can be omitted. An example of a cross-sectional view with layer 330 omitted is shown in Figure 38(B).

[0557] Furthermore, the silicon substrate 300 may be an SOI substrate. Replace with germanium, silicon germanium, silicon carbide, gallium arsenide, arsenide Using a substrate having gallium dioxide, indium phosphide, gallium nitride, or an organic semiconductor. It is possible to stay there.

[0558] Here, a layer 310 having a transistor 351 and a photodiode 360, and An insulator 380 is provided between the layer 330 having the diast 352 and the transistor 353. It can be kicked. However, the position of the insulator 380 is not limited.

[0559] The hydrogen in the insulator located near the channel formation region of transistor 351 is a silicon d This terminates the ring bond and improves the reliability of transistor 351. , hydrogen in an insulator provided near transistors 352 and 353 This is one of the factors that generate carriers in oxide semiconductors. Therefore, transistor 3 This can be a factor that reduces the reliability of transistors such as 52 and 353. So, a transistor using an oxide semiconductor on top of a silicon-based semiconductor transistor... When stacking the elements, an insulator 380 having the function of blocking hydrogen is placed between them. It is preferable to provide it. By confining hydrogen in the layer below the insulator 380, the transistor The reliability of 351 can be improved. Furthermore, from below the insulator 380, the insulator Because hydrogen diffusion to the layer above 380 can be suppressed, transistors 352 and 380 This can improve the reliability of devices such as the 353.

[0560] As the insulator 380, for example, an insulator having the function of blocking oxygen or hydrogen is used. Yes, they are.

[0561] Furthermore, in the cross-sectional view of Figure 38(A), the photodiode 360 ​​provided in layer 310 and layer The transistors provided at 330 can be formed to overlap with the pixels. This allows for an increase in the integration density, that is, an increase in the resolution of the imaging device.

[0562] Also, as shown in FIGS. 39(A1) and 39(B1), part or all of the imaging device may be bent. FIG. 39(A1) shows the state in which the imaging device is bent in the direction of the dashed-dotted line X1-X2 in the figure. FIG. 39(A2) is a cross-sectional view of the part indicated by the dashed-dotted line X1-X 2 in FIG. 39(A1). FIG. 39(A3) is a cross-sectional view of the part indicated by the dashed-dotted line Y1- Y2 in FIG. 39(A1).

[0563] FIG. 39(B1) shows the state in which the imaging device is bent in the direction of the dashed-dotted line X3-X4 in the figure and also bent in the direction of the dashed-dotted line Y3-Y4 in the figure. FIG. 39(B2) is a cross-sectional view of the part indicated by the dashed-dotted line X3-X4 in FIG. 39(B1). FIG. 39(B3) is a cross-sectional view of the part indicated by the dashed-dotted line Y3-Y4 in FIG. 39(B1).

[0564] By bending the imaging device, curvature of the image plane and aberration can be reduced. Therefore, the optical design of a lens or the like used in combination with the imaging device can be facilitated. For example, since the number of lens elements for aberration correction can be reduced, miniaturization and weight reduction of an electronic device or the like using the imaging device can be achieved. Also, the quality of the captured image can be improved .

[0565] The configuration shown in this embodiment can be used in appropriate combination with the configuration shown in other embodiments .

[0566] (Embodiment 6) In this embodiment, an example of a CPU including a semiconductor device such as a transistor according to an aspect of the present invention and the above-described memory device will be described.

[0567] <Configuration of CPU> Figure 40 is a block diagram showing an example configuration of a CPU that uses the transistors described above in part. be.

[0568] The CPU shown in Figure 40 is an ALU1191 (ALU: Arithmet) mounted on board 1190. IC logic unit, arithmetic circuit, ALU controller 1192, instruction Timing decoder 1193, interrupt controller 1194, timing controller 1195, Register 1196, Register Controller 1197, Bus Interface 1 It has 198, a rewritable ROM 1199, and a ROM interface 1189. The substrate 1190 uses semiconductor substrates, SOI substrates, glass substrates, etc. ROM1 199 and the ROM interface 1189 may be provided on a separate chip. Of course, The CPU shown in Figure 40 is merely one example of a simplified configuration; an actual CPU is different. They have a wide variety of configurations depending on the application. For example, the CPU or arithmetic circuit shown in Figure 40. A configuration including this is considered one core, and there are multiple such cores, with each core operating in parallel. This configuration is also acceptable. Furthermore, the number of bits that the CPU can handle in its internal arithmetic circuits and data bus is: For example, it can be 8-bit, 16-bit, 32-bit, 64-bit, etc.

[0569] Instructions input to the CPU via the bus interface 1198 are instructions The signal is input to decoder 1193, decoded, and then processed by ALU controller 1192, interface Raptor controller 1194, register controller 1197, timing controller It is entered into 1195.

[0570] ALU controller 1192, interrupt controller 1194, register controller R1197 and timing controller 1195 control various commands based on the decoded instructions. To perform the operation. Specifically, the ALU controller 1192 controls the operation of the ALU 1191. It generates a signal for that purpose. Also, the interrupt controller 1194 is the CPU programmer. During execution, interrupt requests from external input / output devices and peripheral circuits are prioritized and masked. The state is judged and processed. The register controller 1197 adds register 1196 It generates a response and reads or writes to register 1196 depending on the CPU state.

[0571] Furthermore, the timing controller 1195 is connected to the ALU 1191 and the ALU controller 119 2. Instruction decoder 1193, interrupt controller 1194, and It generates signals to control the timing of the operation of the register controller 1197. For example, The timing controller 1195 generates an internal clock signal based on the reference clock signal. It is equipped with an internal clock generation unit that supplies the internal clock signal to the various circuits mentioned above.

[0572] In the CPU shown in Figure 40, a memory cell is located in register 1196. The transistors and memory devices mentioned above can be used as 1196 memory cells. ru.

[0573] In the CPU shown in Figure 40, the register controller 1197 receives information from the ALU 1191. Following the instructions, select the hold operation in register 1196. That is, register 1196 In the memory cell it possesses, data is held by a flip-flop, or capacitive elements Choose whether to retain data using flip-flops. Selecting to retain data using flip-flops is selected. If so, power voltage is supplied to the memory cell in register 1196. If data retention is selected for the quantitative element, data will be rewritten to the capacitive element. We can stop supplying power voltage to the memory cell in register 1196.

[0574] Figure 41 shows an example of a circuit diagram of a memory element 1200 that can be used as register 1196. The memory element 1200 has a circuit 1201 in which the stored data volatilizes when the power is cut off, and Circuit 1202 that prevents data from volatilizing when disconnected, switch 1203, switch 1204 It has a logic element 1206, a capacitive element 1207, and a circuit 1220 having a selection function. Circuit 1202 consists of a capacitive element 1208, a transistor 1209, and a transistor 12 It has 10 and. The memory element 1200 may also have a diode, a resistor, if necessary. It may further include other elements such as inductors.

[0575] Here, the memory device described above can be used in circuit 1202. Memory element 1200 When the power supply voltage to is cut off, the gate of transistor 1209 in circuit 1202 is G The configuration is such that ND (0V) or a potential that turns off transistor 1209 is continuously input. For example, the gate of transistor 1209 is grounded via a load such as a resistor. .

[0576] Switch 1203 uses a single-conductivity (e.g., n-channel) transistor 1213. The switch 1204 is configured to have a conductivity type opposite to that of a single-conductivity type (for example, a p-channel type). An example using transistor 1214 is shown. Here, the first terminal of switch 1203 The child corresponds to one of the source and drain of t...

Claims

[Claim 1] Semiconductors and, A first insulator having a region in contact with the semiconductor, A first conductor having a region in contact with the first insulator and a region overlapping with the semiconductor via the first insulator, It comprises a second conductor and a third conductor, each having a region in contact with the semiconductor, A semiconductor device wherein one or more of the first to third conductors have regions comprising tungsten and one or more elements selected from silicon, carbon, germanium, tin, aluminum, or nickel.

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