Nitride semiconductor device and method for manufacturing a nitride semiconductor device

Abstract

This invention provides a technology that can effectively reduce the contact resistance between the p-type region and the electrode in nitride semiconductors. [Solution] The nitride semiconductor device comprises a nitride semiconductor substrate in which a p-type region is exposed on at least a portion of the surface. The nitride semiconductor device comprises an intermediate layer containing magnesium and nitrogen, disposed on at least a portion of the upper surface of the p-type region. The nitride semiconductor device comprises an electrode layer disposed on at least a portion of the upper surface of the intermediate layer.

Description

[Technical Field]

[0001] The technologies disclosed herein relate to nitride semiconductor devices and methods for manufacturing nitride semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a technique for reducing the contact resistance between a p-type GaN substrate and an electrode. In this technique, a source layer (e.g., Mg, MgF2, MgO) and a cap layer (e.g., Pt, Au, Ni) are laminated on the surface of a p-type GaN substrate and annealed. Gallium from the p-type GaN substrate diffuses into the cap layer, forming gallium vacancies in the p-type GaN substrate. Magnesium from the source layer also diffuses into the p-type GaN and combines with the gallium vacancies, activating it. Subsequently, the source layer and cap layer are removed, and an electrode is formed on the p-type GaN. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] U.S. Patent Application Publication No. 2019 / 0393038 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] However, the reduction in contact resistance in the technology described in Patent Document 1 is insufficient. This specification provides a technology that can effectively reduce the contact resistance between p-type GaN and an electrode. [Means for solving the problem]

[0005] One embodiment of a nitride semiconductor device disclosed herein comprises a nitride semiconductor substrate in which a p-type region is exposed on at least a portion of the surface. The nitride semiconductor device comprises an intermediate layer disposed on at least a portion of the upper surface of the p-type region and containing magnesium and nitrogen. The nitride semiconductor device comprises an electrode layer disposed on at least a portion of the upper surface of the intermediate layer.

[0006] The inventors have found a configuration in which an intermediate layer containing magnesium and nitrogen is placed between the p-type region of a nitride semiconductor substrate and the electrode layer. This makes it possible to significantly reduce the contact resistance between the p-type region and the electrode layer compared to the case without the intermediate layer.

[0007] The intermediate layer may have an amorphous structure.

[0008] The intermediate layer may contain gallium. The concentration of gallium in the intermediate layer may decrease as it moves away from the interface between the p-type region and the intermediate layer.

[0009] The acceptor concentration and other impurity concentrations in the p-type region are 1 × 10⁻⁶. 16 ~1 × 10 20 cm -3 It may also be within that range.

[0010] The thickness of the intermediate layer may be 1000 nm or less.

[0011] The nitride semiconductor substrate may further include an n-type region exposed on a portion of its surface. The electrode layer may span both the n-type and p-type regions. An intermediate layer may be placed between the p-type region and the electrode layer, but an intermediate layer may not be placed between the n-type region and the electrode layer.

[0012] The nitride semiconductor substrate may be gallium nitride. The intermediate layer may be magnesium nitride.

[0013] One embodiment of a method for manufacturing a nitride semiconductor device disclosed in this specification includes a magnesium layer forming step of forming a magnesium layer containing magnesium as a main component on at least a part of the surface of a p-type region of a nitride semiconductor substrate in which the p-type region is exposed on at least a part of the surface. The manufacturing method includes an annealing step of annealing the nitride semiconductor substrate on which the magnesium layer is formed in an atmosphere containing nitrogen. The annealing step changes the magnesium layer into an intermediate layer containing magnesium and nitrogen. The manufacturing method includes an electrode layer forming step of forming an electrode layer on at least a part of the upper surface of the intermediate layer. Details of the effects will be described in the examples.

[0014] After the annealing step, a step of reducing the film thickness of the intermediate layer may be further provided. The electrode layer forming step may form an electrode layer on the upper surface of the intermediate layer after the film thickness reduction.

[0015] The magnesium layer forming step may selectively form a magnesium layer in a specific region of at least a part of the surface of the p-type region.

[0016] The magnesium layer forming step may include a step of forming a mask layer having an opening corresponding to the specific region on the surface of the nitride semiconductor substrate. The magnesium layer forming step may include a step of depositing the magnesium layer through the mask layer.

[0017] An n-type region may be exposed on a part of the surface of the nitride semiconductor substrate. The magnesium layer forming step may form a magnesium layer on at least a part of the surface of the p-type region and may not form a magnesium layer on the surface of the n-type region. The electrode layer forming step may form an electrode layer so as to span between the intermediate layer formed in the p-type region and the n-type region.

Brief Description of Drawings

[0018] [Figure 1] It is a schematic cross-sectional view of a semiconductor device 1 according to Example 1. [Figure 2] It is a flowchart for explaining a method for manufacturing a semiconductor device 1. [Figure 3] This is a cross-sectional view illustrating a method for manufacturing a semiconductor device 1. [Figure 4] This is a cross-sectional view illustrating a method for manufacturing a semiconductor device 1. [Figure 5] This is a cross-sectional view illustrating a method for manufacturing a semiconductor device 1. [Figure 6] This figure shows the measurement results of the current-voltage characteristics. [Figure 7] This is a schematic cross-sectional view of the semiconductor device 101 according to Example 2. [Figure 8] This is a flowchart illustrating the manufacturing method of the semiconductor device 101. [Figure 9] This is a cross-sectional view illustrating a method for manufacturing a semiconductor device 101. [Figure 10] This is a schematic cross-sectional view of the comparative example semiconductor device 201. [Modes for carrying out the invention] [Examples]

[0019] (Configuration of semiconductor device 1) Figure 1 shows a schematic cross-sectional view of a semiconductor device 1 according to Embodiment 1. The semiconductor device 1 has a structure in which a semiconductor substrate 10, an intermediate layer 13, and an electrode layer 14 are stacked in this order. The semiconductor substrate 10 has a structure in which a p-type GaN layer 12 is stacked on a GaN substrate 11. That is, the p-type GaN layer 12 is exposed over the entire surface of the semiconductor substrate 10. The impurity of the p-type GaN layer 12 is magnesium, and its concentration is 1 × 10⁻⁶. 16 ~1 × 10 20 cm -3 It is within the range.

[0020] The intermediate layer 13 is disposed over the entire upper surface of the p-type GaN layer 12. The intermediate layer 13 is a compound containing magnesium and nitrogen. In this example, the intermediate layer 13 is magnesium nitride (MgNx). The thickness T3 of the intermediate layer 13 is 1000 nm or less, preferably 300 nm or less.

[0021] The nitrogen concentration in the intermediate layer 13 decreases as you move from the upper surface 13u of the intermediate layer 13 toward the p-type GaN layer 12. As will be described later, this is because the intermediate layer 13 is formed by annealing the magnesium layer in a nitrogen atmosphere, thereby diffusing nitrogen from the upper surface 13u.

[0022] Furthermore, the intermediate layer 13 contains gallium, and the p-type GaN layer 12 contains magnesium. The concentration of gallium in the intermediate layer 13 decreases as it moves away from the interface IF1 between the p-type GaN layer 12 and the intermediate layer 13. The concentration of magnesium in the p-type GaN layer 12 also decreases as it moves away from the interface IF1. This is because interdiffusion occurs at the interface IF1 due to the annealing process described later.

[0023] Furthermore, the intermediate layer 13 has an amorphous structure. This is because the intermediate layer 13 is a magnesium nitride layer formed by nitrogen annealing. The amorphous structure of the intermediate layer 13 can be confirmed by XPS (X-ray photoelectron spectroscopy).

[0024] It is also possible to form a magnesium nitride layer without using nitrogen annealing. For example, by sputtering magnesium in a nitrogen atmosphere. However, a magnesium nitride layer formed without nitrogen annealing may not have an amorphous structure and may contain microcrystals. Also, the nitrogen concentration does not change in the thickness direction. Therefore, by analyzing the presence or absence of an amorphous structure and the distribution of nitrogen concentration in the thickness direction, it is possible to determine whether or not the intermediate layer 13 is a layer formed by nitrogen annealing.

[0025] The electrode layer 14 is arranged across the entire upper surface of the intermediate layer 13. The structure and thickness of the electrode layer 14 are not particularly limited. In this embodiment, the electrode layer 14 has a structure in which gold is laminated on nickel.

[0026] (Method of manufacturing semiconductor device 1) The manufacturing method of the semiconductor device 1 will be described with reference to the flowchart in Figure 2 and the schematic cross-sectional diagrams in Figures 3 to 5. In step S1, a semiconductor substrate 10 is formed on which a p-type GaN layer 12 is laminated on a GaN substrate 11. The semiconductor substrate 10 may be formed by growing a p-type GaN layer 12 on the GaN substrate 11 using an epitaxial growth method (e.g., MOVPE method, HVPE method, MBE method). In this embodiment, the magnesium concentration of the p-type GaN layer 12 is set to 1 × 10⁻¹⁶ 17 cm -3 That's what I decided.

[0027] In step S2, a magnesium layer formation process is carried out. Specifically, a magnesium layer 13A is formed on the surface of the p-type GaN layer 12 (see Figure 3). The magnesium layer 13A is a layer mainly composed of magnesium. The magnesium layer 13A may also contain other elements such as fluorine and oxygen. In this example, the thickness T1 of the magnesium layer 13A was set to 50 nm. The magnesium layer 13A can be formed using various methods and apparatuses. For example, an EB deposition apparatus, a resistance heating deposition apparatus, a sputtering apparatus, etc., may be used.

[0028] In step S3, an annealing process is performed. Specifically, the semiconductor substrate 10 on which the magnesium layer 13A is formed is annealed in a nitrogen-containing atmosphere. The annealing temperature can be in the range of 300 to 1000°C. The annealing time can be set as appropriate. Annealing can be carried out using various methods and apparatus. In this embodiment, annealing at 800°C for 60 minutes was performed using an RTA (Rapid Thermal Annealing) apparatus.

[0029] By the annealing process, nitrogen in the atmosphere can be diffused from the surface of the magnesium layer 13A. Therefore, the magnesium layer 13A can be changed into the intermediate layer 13 (magnesium nitride) (see Fig. 4). The thickness T2 of the intermediate layer 13 after annealing becomes larger than the thickness T1 before annealing. In this embodiment, the thickness T1 was 50 nm, and the thickness T2 was 80 - 100 nm. Also, by the annealing process, interdiffusion can occur between the p-type GaN layer 12 and the magnesium layer 13A.

[0030] In step S4, a process of reducing the film thickness of the intermediate layer 13 is performed. As a result, the film thickness of the intermediate layer 13 decreases from the thickness T2 (Fig. 4) to the thickness T3 (Fig. 5). This process can be performed by various methods such as wet etching using aqua regia or hydrofluoric acid, dry etching, polishing, etc. In this embodiment, by wet etching with aqua regia, the film was thinned from the thickness T2 (80 - 100 nm) to the thickness T3 (about 20 nm).

[0031] In step S5, an electrode layer forming process is performed. Specifically, an electrode layer 14 is formed on the upper surface of the intermediate layer 13 after the film thickness reduction. In this embodiment, the electrode layer 14 has a structure in which nickel and gold are laminated in this order.

[0032] In step S6, the semiconductor device 1 on which the electrode layer 14 is formed is annealed in an oxygen atmosphere. Thereby, a contact by nickel oxide can be formed. In this embodiment, annealing was performed at 525 °C for 5 minutes. Thus, the semiconductor device 1 shown in Fig. 1 is completed.

[0033] (Measurement results of current - voltage characteristics) The current - voltage characteristics between the p-type GaN layer 12 and the electrode layer 14 were measured. The impurity concentration of the p-type GaN layer 12 was 1×10 17 cm -3The measurement results are shown in Figure 6. The horizontal axis represents voltage. The forward voltage is defined as the case where a positive voltage is applied to the electrode layer 14 relative to the p-type GaN layer 12. The reverse voltage is defined as the case where a positive voltage is applied to the p-type GaN layer 12 relative to the electrode layer 14. The vertical axis represents current.

[0034] Graph G0 shows the measured values ​​for the comparative example semiconductor device. The comparative example semiconductor device does not have an intermediate layer 13, and has a structure in which the electrode layer 14 is directly placed on the p-type GaN layer 12. Graphs G1 and G2 show the measured values ​​for the semiconductor device of this embodiment. Graph G1 shows the measured values ​​for the semiconductor device in which the electrode layer 14 is placed on a thick intermediate layer 13 (Figure 4, thickness T2). Graph G2 shows the measured values ​​for the semiconductor device in which the electrode layer 14 is placed on a thin intermediate layer 13 (Figure 1, thickness T3).

[0035] As can be seen from graphs G0 and G1, the semiconductor device of this embodiment can increase the current value by up to 1 million times compared to the semiconductor device of the comparative example. In other words, by providing the intermediate layer 13, it is possible to significantly reduce the contact resistance. Furthermore, as can be seen from graphs G1 and G2, by thinning the intermediate layer 13, the current value can be increased by up to 1,000 times. In other words, by thinning the intermediate layer 13, it is possible to further reduce the contact resistance.

[0036] Furthermore, in graph G1, the current value at the reverse voltage is about 10 times higher than the current value at the forward voltage. On the other hand, in graph G2, the current values ​​at the reverse voltage and the current values ​​at the forward voltage are almost equal. In other words, by thinning the intermediate layer 13, the rectification effect can be suppressed. This makes it possible to form good ohmic contact.

[0037] This section describes a model in which contact resistance can be reduced by interposing an intermediate layer 13. In gallium nitride, a compound semiconductor, p-type gallium nitride has many defects, resulting in band bending at the material surface. This increases the energy barrier for holes. Therefore, in the technique described herein, magnesium can be diffused onto the surface of the p-type GaN layer 12 by depositing a magnesium layer 13A on the p-type GaN layer 12 and annealing it. The magnesium terminates defects in the gallium nitride and increases the acceptor concentration, thereby reducing the degree of band bending. This reduces the energy barrier for holes. Furthermore, in the technique described herein, an electrode layer 14 is formed on the intermediate layer 13. This allows for the formation of electrodes while maintaining a reduced energy barrier for holes. As a result, contact resistance can be reduced.

[0038] (effect) Conventionally, the impurity concentration was low (1 × 10 16 ~1 × 10 20 cm -3 In electrodes formed on a p-type GaN layer of a certain degree, it was difficult to reduce contact resistance and form ohmic contact. This is because a high concentration (2 × 10) of p-type GaN was present between the low-concentration p-type GaN layer and the electrode. 19 cm -3 This is because it is necessary to interpose the p-type GaN layer as described above. Furthermore, when high-concentration p-type GaN is formed by epitaxial regrowth, a Si pile-up layer is introduced at the interface of the regrowth layer. In the technology described herein, an intermediate layer 13 (magnesium nitride) formed by nitrogen annealing is placed between the low-concentration p-type GaN layer and the electrode. This makes it possible to lower the contact resistance with the electrode even with a low-concentration p-type GaN layer, and to achieve ohmic contact. In addition, since it is not necessary to regrow high-concentration p-type GaN, it is possible to reduce man-hours and costs. [Examples]

[0039] (Configuration of semiconductor device 101) Figure 7 shows a schematic cross-sectional view of the semiconductor device 101 according to Embodiment 2. The semiconductor device 101 is a lateral MOSFET equipped with a planar gate. The semiconductor device 101 includes a semiconductor substrate 110. The semiconductor substrate 110 is a high-concentration n-type (n + Drain layer 111a is GaN (type), low concentration n-type (n - Drift layer 111b is GaN (type), low concentration p-type (p - The body layer 112 is made of GaN and has a laminated structure. In this embodiment, the magnesium concentration of the body layer 112 is 1 × 10 18 cm -3 That's what I decided.

[0040] The source region 116 and drain region 117 of n-type GaN are located on the upper part of the body layer 112. The source region 116 and drain region 117 are regions formed by ion implantation and are regions exposed on a part of the surface of the semiconductor substrate 110. A gate insulating film 119 and a gate electrode 118 are located in the region between the source region 116 and the drain region 117. The gate electrode 118 is located on the upper surface of the body layer 112 via the gate insulating film 119.

[0041] An intermediate layer 113 is placed in the region of the body layer 112 exposed on the surface of the semiconductor substrate 110 where the gate insulating film 119 is not located. The structure of the intermediate layer 113 is the same as that of the intermediate layer 13 in Example 1, so its description is omitted.

[0042] The source electrode 114s is in contact with the upper surface of the source region 116 and the upper surface of the intermediate layer 113. That is, the source electrode 114s is positioned across the source region 116 and the body layer 112. The intermediate layer 113 is positioned between the source electrode 114s and the body layer 112. On the other hand, the intermediate layer 113 is not positioned between the source electrode 114s and the source region 116. A body contact BC is formed by the contact area between the source electrode 114s and the body layer 112. The function of the body contact BC is well known, so its explanation is omitted.

[0043] Similarly, the drain electrode 114d is positioned across the drain region 117 and the body layer 112. An intermediate layer 113 is positioned between the drain electrode 114d and the body layer 112. On the other hand, the intermediate layer 113 is not positioned between the drain electrode 114d and the drain region 117. A body contact BC is formed by the contact region between the drain electrode 114d and the body layer 112.

[0044] (Manufacturing method for semiconductor device 101) The manufacturing method of the semiconductor device 101 will be described with reference to the flowchart in Figure 8 and the schematic cross-sectional view in Figure 9. In step S11, the semiconductor substrate 110 is formed. Specifically, a drift layer 111b and a body layer 112 are epitaxially grown on the drain layer 111a. In step S12, a source region 116 and a drain region 117 are formed. Specifically, silicon or germanium is ion-implanted into the body layer 112 through a mask having openings corresponding to the source region 116 and the drain region 117.

[0045] In step S13, a gate electrode formation process is performed. Specifically, a gate electrode 118 is formed on the upper surface of the body layer 112 in the region between the source region 116 and the drain region 117, via a gate insulating film 119. The gate insulating film 119 is an insulating film formed by depositing SiO2 or Al2O3, etc., by atomic deposition or the like. The gate electrode 118 is polysilicon doped with impurities such as boron. The gate electrode 118 can be formed using well-known photolithography techniques and dry etching processes.

[0046] In step S14, a magnesium layer formation process is carried out. Specifically, a mask layer having openings corresponding to a specific region is formed. The specific region is the region where the magnesium layer 113A is formed. In this embodiment, the specific region is the region where the body contact BC is formed. Next, magnesium is deposited through the mask layer. Finally, the mask layer is removed. As a result, as shown in Figure 9, the magnesium layer 113A is selectively formed on the surface of the body layer 112. The magnesium layer 113A is not formed on the surfaces of the source region 116 and the drain region 117. Note that the structure of the magnesium layer 113A is the same as that of the magnesium layer 13A in Example 1, so a description is omitted.

[0047] In step S15, an annealing process is performed. Specifically, the semiconductor substrate 110 on which the magnesium layer 113A is formed is annealed in a nitrogen-containing atmosphere. The details of the annealing process are the same as in step S3 of Example 1, so the explanation is omitted. This transforms the magnesium layer 113A into an intermediate layer 113 which is magnesium nitride. The structure of the intermediate layer 113 is the same as that of the intermediate layer 13 in Example 1, so the explanation is omitted.

[0048] In step S16, a process is carried out to reduce the film thickness of the intermediate layer 113. The details of this process are the same as in step S4 of Example 1, so a description will be omitted.

[0049] In step S17, the electrode formation process is carried out. Specifically, a metal layer is formed. Next, using well-known photolithography techniques and dry etching, the metal layer is processed into a source electrode 114s and a drain electrode 114d. The source electrode 114s is formed so as to span between the intermediate layer 113 formed in the body layer 112 and the source region 116. The drain electrode 114d is formed so as to span between the intermediate layer 113 formed in the body layer 112 and the drain region 117. This completes the semiconductor device 101 shown in Figure 7.

[0050] (effect) The problem will be explained using the comparative example semiconductor device 201 shown in Figure 10. The comparative example semiconductor device 201 differs from the semiconductor device 101 of Example 2 (Figure 7) only in that the intermediate layer 113 is replaced by a contact layer 213. The contact layer 213 is a high-concentration p-type (p + This is a GaN layer. Common parts are given the same reference numeral to omit further explanation. The MOSFET body layer 112 controls the magnesium concentration (for example, 1 × 10) based on the threshold voltage. 16 ~1 × 10 20 cm -3 It is necessary to do so to a certain extent. In order to lower the contact resistance of the body contact BC and to form ohmic contact, it is necessary to interpose a high-concentration p-type GaN layer (contact layer 213). In a common method for forming this contact layer 213, the contact layer 213 is regrown on the entire surface of the body layer 112, and then the contact layer 213 in the opening region R1 is removed by dry etching. However, regrowth introduces a Si pile-up layer SL at the interface between the contact layer 213 and the body layer 112. Therefore, it is difficult to lower the contact resistance of the body contact BC and to form ohmic contact. In addition, a damage layer DL is formed in the channel by dry etching, which may degrade the device characteristics.

[0051] In the semiconductor device 101 of this embodiment (Figure 7), an intermediate layer 113 (magnesium nitride) is placed in the region where the body contact BC is formed. Since regrowth of the high-concentration p-type GaN layer is unnecessary, the Si pile-up layer SL is not formed. This makes it possible to lower the contact resistance of the body contact BC and to form ohmic contacts. Furthermore, by using lithography technology, the intermediate layer 113 can be selectively formed in the region where the body contact BC is formed. Since the process of removing the intermediate layer 113 by dry etching is unnecessary, the damage layer DL is not formed in the channel. This suppresses the degradation of device characteristics.

[0052] Furthermore, the intermediate layer 113 (magnesium nitride) increases the contact resistance with respect to n-type GaN. In the semiconductor device 101 of this embodiment (Figure 7), the intermediate layer 113 is not placed between the source region 116 and the source electrode 114s, and between the drain region 117 and the drain electrode 114d. This makes it possible to suppress the increase in contact resistance.

[0053] Although specific examples of the present invention have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technologies illustrated in this specification or drawings can achieve multiple objectives simultaneously, and achieving even one of these objectives itself constitutes technical usefulness.

[0054] (modified version) The steps of reducing the thickness of the intermediate layer (steps S4 and S16) are optional.

[0055] The magnesium nitride (MgNx) that makes up the intermediate layers 13 and 113 may also contain other elements such as fluorine and oxygen.

[0056] The device structures to which the technology described herein can be applied are not limited to the lateral MOSFET shown in Example 2. It can be applied to a variety of device structures. For example, it may be applied to vertical MOSFETs with trench gates, superjunction MOSFETs, PN diodes, heterojunction bipolar transistors (HBTs), HEMTs, and the like.

[0057] The nitride semiconductors to which the techniques described herein can be applied are not limited to GaN, but may also be, for example, AlGaN (aluminum gallium nitride), AlN (aluminum nitride), InN (indium nitride), InGaN (indium gallium nitride), or mixed crystals thereof.

[0058] The heating method used in the annealing process (steps S3 and S15) can be various. For example, lamp heating, heater heating, high-frequency heating, etc., may be used. Also, the atmosphere in the annealing process is not limited to a pure nitrogen atmosphere, but may be a mixture of, for example, H2, NH3, Ar, Xe, He, Ne, etc. [Explanation of symbols]

[0059] 1, 101: Semiconductor device 10, 110: Semiconductor substrate 11: GaN substrate 12: p-type GaN layer 13: Interlayer 14: Electrode layer 112: Body layer 113: Interlayer 116: Source region 117: Drain region 114s: Source electrode 114d: Drain electrode 118: Gate electrode 119: Gate insulating film BC: Body contact

Claims

1. Nitride semiconductor device, A nitride semiconductor substrate in which a p-type region is exposed on at least a portion of the surface, An intermediate layer containing magnesium and nitrogen is disposed in at least a portion of the upper surface of the p-type region, An electrode layer disposed on at least a portion of the upper surface of the intermediate layer, A nitride semiconductor device comprising the above features.

2. The nitride semiconductor device according to claim 1, wherein the intermediate layer has an amorphous structure.

3. The aforementioned intermediate layer contains gallium, The nitride semiconductor device according to claim 1 or 2, wherein the concentration of gallium in the intermediate layer decreases with increasing distance from the interface between the p-type region and the intermediate layer.

4. The impurity concentration in the p-type region is 1 × 10⁻⁶ １６ ~1 x 10 ２０ cm －３ A nitride semiconductor device according to any one of claims 1 to 3, within the range of [specified range].

5. The nitride semiconductor device according to any one of claims 1 to 4, wherein the thickness of the intermediate layer is 1000 nm or less.

6. The aforementioned nitride semiconductor substrate further comprises an n-type region exposed on a part of its surface, The electrode layer is arranged to span the n-type region and the p-type region. The nitride semiconductor device according to any one of claims 1 to 5, wherein the intermediate layer is disposed between the p-type region and the electrode layer, and the intermediate layer is not disposed between the n-type region and the electrode layer.

7. The nitride semiconductor substrate is gallium nitride. The nitride semiconductor device according to any one of claims 1 to 6, wherein the intermediate layer is magnesium nitride.

8. A magnesium layer formation step in which a magnesium layer mainly composed of magnesium is formed on at least a portion of the surface of a p-type region of a nitride semiconductor substrate in which a p-type region is exposed on at least a portion of the surface of the said p-type region, An annealing step in which the nitride semiconductor substrate on which the magnesium layer is formed is annealed in a nitrogen-containing atmosphere, The annealing step involves transforming the magnesium layer into an intermediate layer containing magnesium and nitrogen, An electrode layer formation step in which an electrode layer is formed on at least a portion of the upper surface of the intermediate layer, A method for manufacturing a nitride semiconductor device.

9. The process further comprises reducing the film thickness of the intermediate layer after the annealing process, The method for manufacturing a nitride semiconductor device according to claim 8, wherein the electrode layer formation step involves forming the electrode layer on the upper surface of the intermediate layer after the film thickness has decreased.

10. The impurity concentration in the p-type region is 1 × 10⁻⁶ １６ ~1 x 10 ２０ A method for manufacturing a nitride semiconductor device according to claim 8 or 9, which is within the range of [specify range].

11. The magnesium layer formation step is, A method for manufacturing a nitride semiconductor device according to any one of claims 8 to 10, wherein the magnesium layer is selectively formed in a specific region of at least a part of the surface of the p-type region.

12. The magnesium layer formation step is, A step of forming a mask layer having an opening corresponding to the specific region on the surface of the nitride semiconductor substrate, A step of depositing the magnesium layer via the mask layer, A method for manufacturing a nitride semiconductor device according to claim 11, comprising:

13. A portion of the surface of the nitride semiconductor substrate shows an n-type region. The magnesium layer formation step involves forming the magnesium layer on at least a portion of the surface of the p-type region, while not forming the magnesium layer on the surface of the n-type region. The method for manufacturing a nitride semiconductor device according to claim 11 or 12, wherein the electrode layer formation step involves forming the electrode layer so as to span between the intermediate layer formed in the p-type region and the n-type region.

14. The method for manufacturing a nitride semiconductor device according to any one of claims 8 to 13, wherein the nitride semiconductor substrate is gallium nitride.

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