Semiconductor equipment

Abstract

To provide a semiconductor device capable of improving dielectric strength. [Solution] The semiconductor device A1 comprises a first die pad 21, a second die pad 22, a first semiconductor element, a second semiconductor element 12, an insulating element 13, a first wire 51, and a sealing resin 6. The first wire 51 includes a first upright portion 511, a first inclined portion 512, a first extension portion 513, a first bent portion 514, and a second bent portion 515. The length of the first extension portion 513 is greater than the length of each of the other elements constituting the first wire 51. When a virtual plane is set with a first direction x and a second direction orthogonal to each of the thickness direction z and the first direction x as in-plane directions, the inclination angle of the first extension portion 513 with respect to the virtual plane is smaller than the inclination angle of the first inclined portion 512 with respect to the virtual plane. The inclination angle of the first upright portion 511 with respect to the virtual plane is greater than the inclination angles of the first extension portion 513 and the first inclined portion 512 with respect to the virtual plane.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. In particular, the present disclosure relates to a semiconductor device in which signal transmission is performed between a plurality of semiconductor elements via an insulating element.

Background Art

[0002] In electric vehicles, hybrid vehicles, or home appliances, an inverter device is used. Such an inverter device includes, for example, a semiconductor device for control and drive, and a power semiconductor such as an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). In the inverter device, a control signal output from an ECU (Engine Control Unit) is input to a control element in the semiconductor device. The control element converts the control signal into a PWM (Pulse Width Modulation) control signal and transmits the converted control signal to a drive element in the semiconductor device. The drive element switches, for example, six power semiconductors at a desired timing based on the PWM control signal. By the six power semiconductors performing a switching operation at a desired timing, three-phase AC power for motor drive is generated from the DC power of an in-vehicle battery. Patent Document 1 discloses an example of a semiconductor device (drive circuit) used in a motor drive device.

[0003] In the above-described semiconductor device for control and drive, the power supply voltage required for the control element and the power supply voltage required for the drive element may be different. More specifically, there may be a difference between the voltage value applied to the conduction path to the control element and the voltage value applied to the conduction path to the drive element. In such a case, in a configuration in which a plurality of semiconductor elements are mounted in one package, an improvement in the breakdown voltage between these conduction paths is required.

Prior Art Documents

Patent Documents

[0004] [Patent Document 1] Japanese Patent Publication No. 2014-155412 [Overview of the Initiative] [Problems that the invention aims to solve]

[0005] In view of the circumstances described above, one of the objectives of this disclosure is to provide a semiconductor device capable of improving dielectric strength. [Means for solving the problem]

[0006] The semiconductor device provided by this disclosure includes a first die pad, a second die pad spaced apart from the first die pad in a first direction and having a potential different from that of the first die pad, a first semiconductor element mounted on the first die pad and constituting a first circuit together with the first die pad, a second semiconductor element mounted on the second die pad and constituting a second circuit together with the second die pad, and when one of the first die pad and the second die pad is referred to as a specific die pad and the other as a non-specific die pad, the first die pad is mounted on the specific die pad and the first The device comprises: an insulating element that relays the transmission and reception of signals between the path and the second circuit and insulates the first circuit and the second circuit from each other; a first wire joined to the insulating element and the specific semiconductor element, where the one mounted on the non-specific die pad is referred to as the specific semiconductor element and the one mounted on the specific die pad is referred to as the non-specific semiconductor element; and a sealing resin that covers the first die pad, the second die pad, the first semiconductor element, the second semiconductor element, and the insulating element, and insulates the first die pad and the second die pad from each other. The first wire straddles the pad gap provided between the first die pad and the second die pad in the first direction. The first wire includes a first upright portion, a first inclined portion, a first extended portion, a first bent portion, and a second bent portion. The first upright portion rises from the insulating element in the thickness direction of the first die pad. The first inclined portion extends inclined with respect to the thickness direction from the specific semiconductor element toward the insulating element. The first extension portion is located between the first upright portion and the first inclined portion when viewed along the thickness direction. The first bent portion is connected to the first upright portion and the first extension portion, and the second bent portion is connected to the first inclined portion and the first extension portion. The inclination angle of the first extension portion with respect to a plane perpendicular to the thickness direction is smaller than the inclination angle of the first inclined portion with respect to the plane.

[0007] Preferably, the first extension spans the pad gap.

[0008] Preferably, in the thickness direction, the boundary between the first extension and the first bend is further away from the insulating element than the boundary between the first extension and the second bend.

[0009] Preferably, when viewed along the thickness direction, the boundary between the first inclined portion and the second bent portion is separated from the specific semiconductor element.

[0010] Preferably, the semiconductor device further comprises a second wire. In the first direction, the insulating element is located between the first semiconductor element and the second semiconductor element. The second wire is bonded to the insulating element and the non-specific semiconductor element and is covered with the sealing resin. The second wire also has a second upright portion, a second inclined portion, a second extension portion, a third bend portion, and a fourth bend portion. The second upright portion rises from the insulating element in the thickness direction. The second inclined portion extends from the non-specific semiconductor element toward the insulating element at an angle with respect to the thickness direction. The second extension portion is located between the second upright portion and the second inclined portion when viewed along the thickness direction. The third bend portion connects to the second upright portion and the second extension portion, and the fourth bend portion connects to the second inclined portion and the second extension portion. The length of the second extension portion is less than the length of the first extension portion.

[0011] Preferably, the inclination angle of the second extension with respect to the plane is smaller than the inclination angle of the second inclined portion with respect to the plane.

[0012] Preferably, when viewed along the thickness direction, the boundary between the second inclined portion and the fourth bent portion is separated from the semiconductor element mounted on the specific die pad.

[0013] Preferably, in the first wire, the dimension in the thickness direction of the first tip of the first inclined portion that is joined to the specific semiconductor element becomes smaller as it moves away from the first extension. In the second wire, the dimension in the thickness direction of the second tip of the second inclined portion that is joined to the semiconductor element mounted on the specific die pad becomes smaller as it moves away from the second extension.

[0014] Preferably, when a power supply voltage is supplied to both the first circuit and the second circuit, the power supply voltage supplied to the second circuit is greater than the power supply voltage supplied to the first circuit.

[0015] Preferably, the semiconductor device further comprises a plurality of first terminals, each including a portion located on one side in the first direction relative to the first die pad, and a plurality of second terminals, each including a portion located on the other side in the first direction relative to the second die pad. The plurality of first terminals are spaced apart from each other in a second direction perpendicular to the thickness direction and the first direction, and at least one of them is conductive to the first circuit. The plurality of second terminals are spaced apart from each other in the second direction, and at least one of them is conductive to the second circuit. The sealing resin has a pair of first surfaces spaced apart from each other in the first direction, and a pair of second surfaces spaced apart from each other in the second direction. Each of the plurality of first terminals is exposed from one of the pair of first surfaces, and each of the plurality of second terminals is exposed from the other of the pair of first surfaces.

[0016] Preferably, when viewed along the first direction, the second die pad overlaps the first die pad.

[0017] Preferably, the first die pad, the second die pad, the plurality of first terminals, and the plurality of second terminals are spaced apart from the pair of second sides.

[0018] Preferably, when viewed along the thickness direction, each of the plurality of first terminals includes a portion protruding along the first direction from the one first side surface. When viewed along the thickness direction, each of the plurality of second terminals includes a portion protruding along the first direction from the other first side surface.

[0019] Preferably, the plurality of first terminals include a pair of first support terminals spaced apart from each other in the second direction. The first die pad has a pair of first edges spaced apart from each other in the second direction, and the pair of first support terminals are respectively connected to the pair of first edges.

[0020] Preferably, the plurality of second terminals include a pair of second support terminals spaced apart from each other in the second direction. The second die pad has a pair of second edges spaced apart from each other in the second direction, and the pair of second support terminals are respectively connected to the pair of second edges.

[0021] Preferably, the specific die pad is provided with a hole penetrating in the thickness direction. When viewed along the thickness direction, the hole is located between the insulating element and the non-specific semiconductor element.

[0022] Preferably, the insulating element is of an inductive type.

Effects of the Invention

[0023] According to the above configuration, in a semiconductor device, it is possible to improve the dielectric breakdown voltage.

[0024] Other features and advantages of the present disclosure will become more apparent from the following detailed description based on the accompanying drawings.

Brief Description of the Drawings

[0025] [Figure 1] It is a plan view of a semiconductor device according to a first embodiment of the present disclosure. [Figure 2]This is a plan view corresponding to Figure 1, and it shows the encapsulating resin. [Figure 3] Figure 1 is a front view of the semiconductor device shown. [Figure 4] Figure 1 is a left side view of the semiconductor device shown. [Figure 5] Figure 1 is a right side view of the semiconductor device shown. [Figure 6] This is a cross-sectional view along the line VI-VI in Figure 2. [Figure 7] This is a cross-sectional view along the line VII-VII in Figure 2. [Figure 8] This is a magnified section of Figure 6. [Figure 9] This is a magnified view of a portion of Figure 8. [Figure 10] This is a magnified section of Figure 6. [Figure 11] This is a magnified view of a portion of Figure 10. [Figure 12] This is a magnified view of a portion of Figure 2. [Figure 13] This is a cross-sectional view along the line XIII-XIII in Figure 12. [Figure 14] Figure 1 is a cross-sectional view illustrating the manufacturing process of a semiconductor device. [Figure 15] Figure 1 is a cross-sectional view illustrating the manufacturing process of a semiconductor device. [Figure 16] Figure 1 is a cross-sectional view illustrating the manufacturing process of a semiconductor device. [Figure 17] Figure 1 is a plan view illustrating the manufacturing process of a semiconductor device. [Figure 18] This is a plan view of a semiconductor device according to a second embodiment of the present disclosure, which is permeable to the sealing resin. [Figure 19] This is a cross-sectional view along the line XIX-XIX in Figure 18. [Figure 20] This is a plan view of a semiconductor device according to a third embodiment of the present disclosure, and shows a transparent encapsulating resin. [Figure 21] This is a cross-sectional view along the line XXI-XXI in Figure 20. [Figure 22] This is a magnified view of a portion of Figure 21. [Figure 23]This is a magnified view of a portion of Figure 21. [Modes for carrying out the invention]

[0026] The forms for implementing this disclosure will be described based on the attached drawings.

[0027] A semiconductor device A1 according to a first embodiment of this disclosure will be described based on Figures 1 to 17. The semiconductor device A1 comprises a first semiconductor element 11, a second semiconductor element 12, an insulating element 13, a first die pad 21, a second die pad 22, a plurality of first terminals 3, a plurality of second terminals 4, a plurality of first wires 51, a plurality of second wires 52, a plurality of third wires 53, a plurality of fourth wires 54, and a sealing resin 6. The semiconductor device A1 is surface-mounted on a wiring board of an inverter device of an electric vehicle (or hybrid vehicle, etc.). The package format of the semiconductor device A1 is SOP (Small Outline Package). However, the package format of the semiconductor device A1 is not limited to SOP. In Figure 2, for ease of understanding, the sealing resin 6 is shown to be transparent. In Figure 2, the transparent sealing resin 6 is shown by dashed lines.

[0028] In the following description, three mutually orthogonal directions, namely directions x, y, and z, will be referred to as appropriate. For example, as can be seen from Figure 3, direction z is the direction that extends parallel to the normal of the first die pad 21 (or second die pad 22). In other words, direction z is the direction that extends through the thickness of the first die pad 21 (or second die pad 22). For this reason, direction z will be referred to as the "thickness direction z" below. Also, direction x will be referred to as the "first direction x" and direction y as the "second direction y" below, but this disclosure is not limited to these terms.

[0029] The first semiconductor element 11, the second semiconductor element 12, and the insulating element 13 are the core elements of the semiconductor device A1. As shown in Figure 2, in the semiconductor device A1, each of the first semiconductor element 11, the second semiconductor element 12, and the insulating element 13 is composed of individual elements. Viewed along the thickness direction z, each of the first semiconductor element 11, the second semiconductor element 12, and the insulating element 13 is rectangular in shape with a longer side extending along the second direction y.

[0030] The first semiconductor element 11 includes a circuit that converts a control signal input from an ECU or the like into a PWM control signal, a transmitting circuit for transmitting the PWM control signal to the second semiconductor element 12, and a receiving circuit that receives an electrical signal from the second semiconductor element 12.

[0031] The second semiconductor element 12 includes a receiving circuit for receiving a PWM control signal, a circuit (gate driver) for performing switching operations of a switching element (such as an IGBT or MOSFET) based on the PWM control signal, and a transmitting circuit for transmitting an electrical signal to the first semiconductor element 11. The electrical signal may be, for example, an output signal from a temperature sensor located near the motor.

[0032] The insulating element 13 is an element for transmitting PWM control signals and other electrical signals in an isolated state. In semiconductor device A1, the insulating element 13 is of the inductive type. An example of an inductive type insulating element 13 is an isolated transformer. An isolated transformer transmits electrical signals in an isolated state by inductively coupling two inductors (coils). The insulating element 13 has a substrate made of Si. An inductor made of Cu is formed on the substrate. The inductor includes a transmitting inductor and a receiving inductor, and these inductors are stacked in the thickness direction z. A dielectric layer made of SiO2 or the like is interposed between the transmitting inductor and the receiving inductor. The dielectric layer electrically insulates the transmitting inductor and the receiving inductor. In addition, the insulating element 13 may be of the capacitive type. An example of a capacitive type insulating element 13 is a capacitor. Furthermore, the insulating element 13 may be a photocoupler.

[0033] In semiconductor device A1, the second semiconductor element 12 requires a higher power supply voltage than the first semiconductor element 11. Therefore, a significant potential difference arises between the first semiconductor element 11 and the second semiconductor element 12. To address this, in semiconductor device A1, the first circuit, which includes the first semiconductor element 11, and the second circuit, which includes the second semiconductor element 12, are insulated from each other by an insulating element 13. In semiconductor device A1, the first circuit operates at a relatively low voltage, while the second circuit operates at a relatively high voltage. Furthermore, the insulating element 13 relays the transmission and reception of signals between the first and second circuits. For example, in an inverter device for an electric vehicle (and hybrid vehicle), the voltage applied to the ground of the first semiconductor element 11 is approximately 5V, while the voltage applied to the ground of the second semiconductor element 12 can transiently exceed 600V.

[0034] As shown in Figures 2 and 10, the insulating element 13 is located between the first semiconductor element 11 and the second semiconductor element 12 in the first direction x. The first semiconductor element 11 and the insulating element 13 are mounted on the first die pad 21. The second semiconductor element 12 is mounted on the second die pad 22. For the sake of explanation, the die pad on which the insulating element 13 is mounted will be called the "specific die pad 20". Furthermore, the semiconductor elements mounted on a die pad different from the specific die pad 20 will be called the "specific semiconductor element 10". In semiconductor device A1, the first die pad 21 corresponds to the specific die pad 20, and the second semiconductor element 12 corresponds to the specific semiconductor element 10.

[0035] As shown in Figures 2 and 6, a plurality of electrodes 111 are provided on the upper surface of the first semiconductor element 11 (the surface facing the same direction as the first main surface 211 of the first die pad 21, which will be described later). The plurality of electrodes 111 are conductive to the circuit configured in the first semiconductor element 11. Similarly, a plurality of electrodes 121 are provided on the upper surface of the second semiconductor element 12 (the surface facing the same direction as the first main surface 211). The plurality of electrodes 121 are conductive to the circuit configured in the second semiconductor element 12. A plurality of first electrodes 131 and a plurality of second electrodes 132 are provided on the upper surface of the insulating element 13 (the surface facing the same direction as the first main surface 211). Each of the plurality of first electrodes 131 and the plurality of second electrodes 132 is conductive to either the transmitting inductor or the receiving inductor.

[0036] As shown in Figure 12, in the insulating element 13, a plurality of first electrodes 131 are arranged along the second direction y. Similarly, a plurality of second electrodes 132 are also arranged along the second direction y. As shown in Figure 13, the insulating element 13 has a passivation film 133 and a surface protective film 134. Both the passivation film 133 and the surface protective film 134 have electrical insulating properties. The passivation film 133 is located at one end in the thickness direction z of the insulating element 13. The passivation film 133 consists of, for example, a silicon dioxide (SiO2) film and a silicon nitride (Si3N4) film deposited on the silicon dioxide film. The passivation film 133 is in contact with the plurality of first electrodes 131 and the plurality of second electrodes 132. The surface protective film 134 is deposited on the passivation film 133. The surface protective film 134 consists of, for example, a material containing polyimide. Each of the multiple first electrodes 131 and the multiple second electrodes 132 is exposed from the surface protective film 134. The surface protective film 134 includes a first film 134A and a second film 134B. The first film 134A is located between the multiple first electrodes 131 and the multiple second electrodes 132 in a first direction x. The second film 134B is the portion of the surface protective film 134 excluding the first film 134A. The first film 134A is provided with multiple slits that penetrate in the thickness direction z and extend along a second direction y. These multiple slits make it possible to increase the creepage distance (the shortest distance along the respective surfaces of the passivation film 133 and the first film 134A) from any of the multiple first electrodes 131 to any of the multiple second electrodes 132. This contributes to improving the dielectric strength of the insulating element 13.

[0037] The first die pad 21, the second die pad 22, the plurality of first terminals 3, and the plurality of second terminals 4 are conductive members that constitute a conductive path between the first semiconductor element 11, the second semiconductor element 12, and the insulating element 13 and the wiring board of the inverter device. These conductive members are made of, for example, an alloy containing Cu in its composition. As shown in Figure 2, the first die pad 21 is positioned on one side in the first direction x. The second die pad 22 is positioned on the other side of the first direction x relative to the first die pad 21 and is located away from the first die pad 21 in the first direction x. Therefore, a pad gap 23 is provided between the first die pad 21 and the second die pad 22 in the first direction x. Viewed along the thickness direction z, the pad gap 23 extends along the second direction y.

[0038] As shown in Figures 2 and 6, the first die pad 21 is mounted with a first semiconductor element 11 and an insulating element 13. The first die pad 21 is electrically connected to the first semiconductor element 11. The first die pad 21 is included in the components of the first circuit described above. The first die pad 21 is substantially rectangular when viewed along the thickness direction z. The thickness of the first die pad 21 (dimension in the thickness direction z) is, for example, 100 μm or more and 300 μm or less. As shown in Figures 6 and 7, the first die pad 21 has a first main surface 211 and a first back surface 212. The first main surface 211 and the first back surface 212 are spaced apart from each other in the thickness direction z. The first main surface 211 and the first back surface 212 face opposite each other in the thickness direction z. Each of the first main surface 211 and the first back surface 212 is flat (or substantially flat). The first semiconductor element 11 and the insulating element 13 are joined to the first main surface 211 by a conductive bonding material (solder, metal paste, sintered metal, etc.) not shown.

[0039] As shown in Figures 2 and 6, a second semiconductor element 12 is mounted on the second die pad 22. The second die pad 22 is electrically connected to the second semiconductor element 12. The second die pad 22 is included in the components of the second circuit described above. Therefore, the potential of the second die pad 22 is different from that of the first die pad 21. The second die pad 22 is approximately rectangular when viewed along the thickness direction z. The first die pad 21 and the second die pad 22 are positioned apart from each other, but are aligned in the first direction x. When viewed along the first direction x, the second die pad 22 overlaps the first die pad 21. The first die pad 21 and the second die pad 22 are galvanically insulated. The thickness of the second die pad 22 (dimension in the thickness direction z) is, for example, 100 μm or more and 300 μm or less. As shown in Figure 6, the second die pad 22 has a second main surface 221 and a second back surface 222. The second main surface 221 and the second back surface 222 are located apart from each other in the thickness direction z. The second main surface 221 and the second back surface 222 face opposite each other in the thickness direction z. Each of the second main surface 221 and the second back surface 222 is flat (or substantially flat). The thickness of each of the first die pad 21 and the second die pad 22 is between 0.2 and 1.2 times the length of the pad gap 23. The second semiconductor element 12 is bonded to the second main surface 221 by a conductive bonding material (solder, metal paste, sintered metal, etc.) not shown.

[0040] As shown in Figures 1 and 2, the multiple first terminals 3 include portions located on one side in the first direction x relative to the first die pad 21. The multiple first terminals 3 are arranged along the second direction y. At least one of the multiple first terminals 3 is conductive to the first circuit described above. As shown in Figures 1 and 4, each of the multiple first terminals 3 is exposed from one of the pair of first side surfaces 63 of the sealing resin 6, which will be described later, located on one side in the first direction x. The multiple first terminals 3 include a plurality of first intermediate terminals 31, a pair of first side terminals 32, and a pair of first support terminals 33.

[0041] As shown in Figures 2 and 4, the multiple first intermediate terminals 31 are arranged in the second direction y, sandwiched between a pair of first side terminals 32. Each of the multiple first intermediate terminals 31 has a lead portion 311 and a pad portion 312.

[0042] As shown in Figure 2, when viewed along the thickness direction z, the lead portion 311 is a strip extending along the first direction x. The lead portion 311 includes a portion that protrudes from the sealing resin 6 along the first direction x when viewed along the thickness direction z, and a portion that is covered by the sealing resin 6. As shown in Figure 3, the portion of the lead portion 311 that protrudes from the sealing resin 6 is bent into a gull-wing shape. In addition, the portion of the lead portion 311 that is exposed from the sealing resin 6 may be plated. The plating layer formed by this plating process is made of an alloy containing Sn, such as solder, and covers the portion exposed from the sealing resin 6. When the semiconductor device A1 is surface-mounted onto the wiring board of the inverter device by soldering, this plating layer ensures good adhesion of solder to the exposed portion while preventing erosion of the exposed portion caused by soldering.

[0043] As shown in Figure 2, the pad portion 312 is connected to the lead portion 311 and is covered with a sealing resin 6. The dimension of the pad portion 312 in the second direction y is larger than the dimension of the lead portion 311 in the same direction. The upper surface of the pad portion 312 (the surface facing the same direction as the first main surface 211 of the first die pad 21) may be plated. The plating layer formed by this plating treatment consists of a metal layer containing, for example, Ag. This plating layer enhances the bonding strength of any of the multiple third wires 53 (described later) to the pad portion 312, while protecting the pad portion 312 from impacts caused by the bonding of the third wires 53. The pad portion 312 is flat (or substantially flat).

[0044] As shown in Figures 2 and 4, a pair of first-side terminals 32 are arranged on both sides of the plurality of first intermediate terminals 31 in the second direction y. Each of the pair of first-side terminals 32 has a lead portion 321 and a pad portion 322.

[0045] As shown in Figure 2, when viewed along the thickness direction z, the lead portion 321 is a strip extending along the first direction x. The lead portion 321 includes a portion that protrudes from the sealing resin 6 along the first direction x when viewed along the thickness direction z, and a portion that is covered by the sealing resin 6. As shown in Figure 3, the portion of the lead portion 321 that protrudes from the sealing resin 6 is bent into a gull-wing shape. In addition, the portion of the lead portion 321 that is exposed from the sealing resin 6 may be covered with a plating layer (for example, an alloy containing Sn such as solder), similar to the lead portion 311.

[0046] As shown in Figure 2, the pad portion 322 is connected to the lead portion 321 and is covered with a sealing resin 6. The dimension of the pad portion 322 in the second direction y is larger than the dimension of the lead portion 321 in the same direction. The upper surface of the pad portion 322 (the surface facing the same direction as the first main surface 211 of the first die pad 21) may be covered with a plating layer (for example, a metal containing Ag), similar to the upper surface of the pad portion 312. The pad portion 322 is flat (or substantially flat).

[0047] As shown in Figures 2 and 4, the pair of first support terminals 33 are located apart from each other in the second direction y. The pair of first support terminals 33 are connected to both ends of the first die pad 21 in the second direction y. Thus, the first die pad 21 is supported by the pair of first support terminals 33. In semiconductor device A1, the pair of first support terminals 33 are located on both sides of the pair of first side terminals 32 in the second direction y. Each of the pair of first support terminals 33 has a lead portion 331 and a pad portion 332.

[0048] As shown in Figure 2, when viewed along the thickness direction z, the lead portion 331 is a strip extending along the first direction x. When viewed along the thickness direction z, the lead portion 331 includes a portion that protrudes from the sealing resin 6 along the first direction x and a portion that is covered by the sealing resin 6. As shown in Figure 3, the portion of the lead portion 331 that protrudes from the sealing resin 6 is bent into a gull-wing shape. In addition, the portion of the lead portion 331 that is exposed from the sealing resin 6 may be covered with a plating layer (for example, an alloy containing Sn such as solder), similar to the lead portion 311. The length of the portion of the lead portion 331 covered by the sealing resin 6 is greater than the length of the respective portions of the lead portion 311 and lead portion 321 covered by the sealing resin 6.

[0049] As shown in Figure 2, the pad portion 332 is connected to the lead portion 331 and is covered with sealing resin 6. The end of the pad portion 332 is connected to the first die pad 21. The upper surface of the pad portion 332 (the surface facing the same direction as the first main surface 211 of the first die pad 21) may be covered with a plating layer (for example, a metal containing Ag), similar to the upper surface of the pad portion 312. The pad portion 332 is flat (or substantially flat).

[0050] As shown in Figures 1 and 2, the multiple second terminals 4 include portions located on the other side of the first direction x relative to the second die pad 22. The multiple second terminals 4 are arranged along the second direction y. At least one of the multiple second terminals 4 is conductive to the aforementioned second circuit. As shown in Figures 1 and 5, each of the multiple second terminals 4 is exposed from one of a pair of first side surfaces 63 of the sealing resin 6, which will be described later, located on the other side of the first direction x. The multiple second terminals 4 include a multiple second intermediate terminals 41, a pair of second side terminals 42, and a pair of second support terminals 43.

[0051] As shown in Figures 2 and 5, the multiple second intermediate terminals 41 are arranged between a pair of second support terminals 43 in the second direction y. Each of the multiple second intermediate terminals 41 has a lead portion 411 and a pad portion 412.

[0052] As shown in Figure 2, when viewed along the thickness direction z, the lead portion 411 is a strip extending along the first direction x. The lead portion 411 includes a portion that protrudes from the sealing resin 6 along the first direction x when viewed along the thickness direction z, and a portion that is covered by the sealing resin 6. As shown in Figure 3, the portion of the lead portion 411 that protrudes from the sealing resin 6 is bent into a gull-wing shape. In addition, the portion of the lead portion 411 that is exposed from the sealing resin 6 may be covered with a plating layer (for example, an alloy containing Sn such as solder), similar to the lead portion 311.

[0053] As shown in Figure 2, the pad portion 412 is connected to the lead portion 411 and is covered with sealing resin 6. The dimension of the pad portion 412 in the second direction y is larger than the dimension of the lead portion 411 in the same direction. The upper surface of the pad portion 412 (the surface facing the same direction as the first main surface 211 of the first die pad 21) may be plated. The plating layer formed by this plating treatment consists of a metal layer containing, for example, Ag. This plating layer enhances the bonding strength of any of the multiple fourth wires 54 (described later) to the pad portion 412, while protecting the pad portion 412 from impacts caused by the bonding of the fourth wires 54. The pad portion 412 is flat (or substantially flat).

[0054] As shown in Figures 2 and 5, a pair of second-side terminals 42 are arranged on both sides of the plurality of second intermediate terminals 41 in the second direction y. Each of the pair of second-side terminals 42 has a lead portion 421 and a pad portion 422.

[0055] As shown in Figure 2, when viewed along the thickness direction z, the lead portion 421 is a strip extending along the first direction x. The lead portion 421 includes a portion that protrudes from the sealing resin 6 along the first direction x when viewed along the thickness direction z, and a portion that is covered by the sealing resin 6. As shown in Figure 3, the portion of the lead portion 421 that protrudes from the sealing resin 6 is bent into a gull-wing shape. In addition, the portion of the lead portion 421 that is exposed from the sealing resin 6 may be covered with a plating layer (for example, an alloy containing Sn such as solder), similar to the lead portion 311. The length of the portion of the lead portion 421 covered by the sealing resin 6 is greater than the length of the portion of the lead portion 411 covered by the sealing resin 6.

[0056] As shown in Figure 2, the pad portion 422 is connected to the lead portion 421 and is covered with a sealing resin 6. The dimension of the pad portion 422 in the second direction y is larger than the dimension of the lead portion 421 in the same direction. The upper surface of the pad portion 422 (the surface facing the same direction as the first main surface 211 of the first die pad 21) may be covered with a plating layer (for example, a metal containing Ag), similar to the upper surface of the pad portion 312. The pad portion 422 is flat (or substantially flat).

[0057] As shown in Figures 2 and 5, the pair of second support terminals 43 are located apart from each other in the second direction y. The pair of second support terminals 43 are connected to both ends of the second die pad 22 in the second direction y. Thus, the second die pad 22 is supported by the pair of second support terminals 43. In semiconductor device A1, the pair of second support terminals 43 are arranged on both sides of the plurality of second intermediate terminals 41 in the second direction y, and are positioned between the pair of second side terminals 42 in the second direction y. Each of the pair of second support terminals 43 has a lead portion 431, a pad portion 432, and a connecting portion 433.

[0058] As shown in Figure 2, when viewed along the thickness direction z, the lead portion 431 is a strip extending along the first direction x. The lead portion 431 includes a portion that protrudes from the sealing resin 6 along the first direction x when viewed along the thickness direction z, and a portion that is covered by the sealing resin 6. As shown in Figure 3, the portion of the lead portion 431 that protrudes from the sealing resin 6 is bent into a gull-wing shape. In addition, the portion of the lead portion 431 that is exposed from the sealing resin 6 may be covered with a plating layer (for example, an alloy containing Sn such as solder), similar to the lead portion 311.

[0059] As shown in Figure 2, the pad portion 432 is connected to the lead portion 431 and is covered with a sealing resin 6. The dimension of the pad portion 432 in the second direction y is larger than the dimension of the lead portion 431 in the same direction. The pad portion 432 extends in the first direction x. The upper surface of the pad portion 432 (the surface facing the same direction as the first main surface 211 of the first die pad 21) may be covered with a plating layer (for example, a metal containing Ag), similar to the upper surface of the pad portion 312. The pad portion 432 is flat (or substantially flat).

[0060] As shown in Figure 2, the connecting portion 433 is connected to the pad portion 432 and is covered with sealing resin 6. The connecting portion 433 extends in the second direction y. The end of the connecting portion 433 is connected to the second die pad 22. The upper surface of the connecting portion 433 (the surface facing the same direction as the first main surface 211 of the first die pad 21) may be covered with a plating layer (for example, a metal containing Ag), similar to the upper surface of the pad portion 312.

[0061] Multiple first wires 51, multiple second wires 52, multiple third wires 53, and multiple fourth wires 54, together with the first die pad 21, the second die pad 22, multiple first terminals 3, and multiple second terminals 4, constitute a conductive path for the first semiconductor element 11, the second semiconductor element 12, and the insulating element 13 to perform predetermined functions. The material of each of the multiple first wires 51, multiple second wires 52, multiple third wires 53, and multiple fourth wires 54 is a metal, for example, containing one of Au, Cu, or Al.

[0062] As shown in Figures 2 and 6, the multiple first wires 51 are joined to the insulating element 13 and a specific semiconductor element 10 (the second semiconductor element 12 in semiconductor device A1). The multiple first wires 51 provide electrical conductivity between the insulating element 13 and the specific semiconductor element 10. In semiconductor device A1, each of the multiple first wires 51 is joined to one of the multiple second electrodes 132 of the insulating element 13 and one of the multiple electrodes 121 of the second semiconductor element 12. The multiple first wires 51 are arranged along the second direction y. Each of the multiple first wires 51 straddles the pad gap 23.

[0063] As shown in Figure 8, each of the plurality of first wires 51 has a first upright portion 511, a first inclined portion 512, a first extension portion 513, a first bend portion 514, and a second bend portion 515. The first upright portion 511 rises in the thickness direction z from one of the plurality of second electrodes 132 of the insulating element 13. The first inclined portion 512 extends inclined with respect to the thickness direction z from one of the plurality of electrodes 121 of the second semiconductor element 12 toward the insulating element 13. The first extension portion 513 is located between the first upright portion 511 and the first inclined portion 512 when viewed along the thickness direction z. The first bend portion 514 connects to the first upright portion 511 and the first extension portion 513. The second bend portion 515 connects to the first inclined portion 512 and the first extension portion 513.

[0064] As shown in Figure 8, a first extension 513 of each of the multiple first wires 51 straddles the pad gap 23. In each of the multiple first wires 51, the inclination angle β1 of the first extension 513 with respect to a plane along the first direction x and the second direction y is smaller than the inclination angle α1 of the first inclined portion 512 with respect to the same plane. As a result, when viewed along a direction perpendicular to the thickness direction z, each of the multiple first wires 51 has a trapezoidal shape. The inclination angle β1 of the first extension 513 is preferably 0° (or substantially 0°).

[0065] As shown in Figure 8, in the thickness direction z, the boundary 513A between the first extension 513 and the first bent portion 514 is located further from the insulating element 13 than the boundary 513B between the first extension 513 and the second bent portion 515. Furthermore, viewed along the thickness direction z, the boundary 512B between the first inclined portion 512 and the second bent portion 515 is located further from the specific semiconductor element 10.

[0066] As shown in Figure 9, each of the multiple first wires 51 has a first inclined portion 512 that is joined to a specific semiconductor element 10 (in semiconductor device A1, one of the multiple electrodes 121 of the second semiconductor element 12). The dimension t1 in the thickness direction z of the first tip 512A gradually decreases as it moves away from the first extension portion 513 of the first wire 51.

[0067] As shown in Figures 2 and 6, the multiple second wires 52 are joined to the insulating element 13 and to a semiconductor element (first semiconductor element 11 in semiconductor device A1) mounted on a specific die pad 20 (first die pad 21 in semiconductor device A1) among the first semiconductor element 11 and the second semiconductor element 12. The multiple second wires 52 provide electrical conductivity between the insulating element 13 and the semiconductor element mounted on the specific die pad 20. In semiconductor device A1, each of the multiple second wires 52 is joined to one of the multiple first electrodes 131 of the insulating element 13 and one of the multiple electrodes 111 of the first semiconductor element 11. The multiple second wires 52 are arranged along the second direction y. When viewed along the thickness direction z, the multiple second wires 52 overlap the specific die pad 20.

[0068] As shown in Figure 10, each of the plurality of second wires 52 has a second upright portion 521, a second inclined portion 522, a second extension portion 523, a third bend portion 524, and a fourth bend portion 525. The second upright portion 521 rises in the thickness direction z from one of the plurality of first electrodes 131 of the insulating element 13. The second inclined portion 522 extends inclined with respect to the thickness direction z from one of the plurality of electrodes 111 of the first semiconductor element 11 toward the insulating element 13. The second extension portion 523 is located between the second upright portion 521 and the second inclined portion 522 when viewed along the thickness direction z. The third bend portion 524 connects to the second upright portion 521 and the second extension portion 523. The fourth bend portion 525 connects to the second inclined portion 522 and the second extension portion 523.

[0069] As shown in Figure 10, the length L2 of each second extension 523 of the plurality of second wires 52 is smaller than the length L1 of each first extension 513 of the plurality of first wires 51 shown in Figure 8 (see Figure 8). Here, the length L2 of the second extension 523 corresponds to the distance from the boundary 523A between the second extension 523 and the third bend 524 to the boundary 523B between the second extension 523 and the fourth bend 525. The length L1 of the first extension 513 corresponds to the distance from the boundary 513A between the first extension 513 and the first bend 514 to the boundary 513B between the first extension 513 and the second bend 515. In each of the plurality of second wires 52, the inclination angle β2 of the second extension 523 with respect to a plane along the first direction x and the second direction y is smaller than the inclination angle α2 of the second inclined portion 522 with respect to the same plane. As a result, when viewed along a direction perpendicular to the thickness direction z, each of the multiple second wires 52 has a trapezoidal shape. The inclination angle β2 of the second extension 523 is preferably 0° (or substantially 0°). Furthermore, when viewed along the thickness direction z, the boundary 522B between the second inclined portion 522 and the fourth bent portion 525 is located away from the semiconductor element mounted on the specific die pad 20.

[0070] As shown in Figure 11, each of the second inclined portions 522 of the multiple second wires 52 has a second tip 522A that is joined to a semiconductor element mounted on a specific die pad 20 (in the case of semiconductor device A1, one of the multiple electrodes 111 of the first semiconductor element 11). The dimension t2 in the thickness direction z of the second tip 522A gradually decreases as it moves away from the second extension portion 523 of the second wire 52.

[0071] The shape of the first tip 512A of each of the first inclined portion 512 of the multiple first wires 51 shown in Figure 9 is obtained by the method of forming the multiple first wires 51 shown in Figures 14 and 15. As shown in Figure 14, the capillary 80 is moved directly above one of the multiple electrodes 121 of the second semiconductor element 12 (specific semiconductor element 10), and then the tip of the capillary 80 is pressed against the electrode 121 by lowering the capillary 80. Next, as shown in Figure 15, the wire 81 is cut by raising the capillary 80. The shape of the first tip 512A is obtained by this forming method.

[0072] The shape of the second tip 522A of each second inclined portion 522 of the multiple second wires 52 shown in Figure 11 is obtained by the method of forming the multiple second wires 52 shown in Figures 16 and 17. As shown in Figure 16, a capillary 80 is moved directly above one of the multiple electrodes 111 of the first semiconductor element 11 (a semiconductor element mounted on a specific die pad 20), and then the tip of the capillary 80 is pressed against the electrode 111 by lowering the capillary 80. Next, as shown in Figure 17, the wire 81 is cut by raising the capillary 80. The shape of the second tip 522A is obtained by this forming method.

[0073] After forming the first tip 512A of the first inclined portion 512 of any of the multiple first wires 51 using the forming method shown in Figures 14 and 15, the second tip 522A of the second inclined portion 522 of any of the multiple second wires 52 is formed using the forming method shown in Figures 16 and 17. By employing this forming method when forming the multiple first wires 51 and the multiple second wires 52, the wire residue 81 adheres uniformly along the inner circumferential surface at the tip of the capillary 80. As a result, the diameters of each of the multiple first wires 51 and the multiple second wires 52 become uniform. This contributes to preventing breakage of each of the multiple first wires 51 and the multiple second wires 52.

[0074] Each of the multiple third wires 53 is connected to one of the multiple electrodes 111 of the first semiconductor element 11 and to one of the multiple first terminals 3 (either the pad portions 312 of the multiple first intermediate terminals 31, the pad portions 322 of the pair of first side terminals 32, or the pad portions 332 of the pair of first support terminals 33), as shown in Figures 2 and 6. The multiple third wires 53 make the first semiconductor element 11 electrically connected to at least one of the multiple first terminals 3.

[0075] Each of the multiple fourth wires 54 is connected to one of the multiple electrodes 121 of the second semiconductor element 12 and to one of the multiple second terminals 4 (one of the pad portions 412 of the multiple second intermediate terminals 41, the pad portions 422 of the pair of second side terminals 42, and the pad portions 432 of the pair of second support terminals 43), as shown in Figures 2 and 6. The multiple fourth wires 54 make the second semiconductor element 12 electrically connected to at least one of the multiple second terminals 4.

[0076] As shown in Figure 1, the encapsulating resin 6 covers the first semiconductor element 11, the second semiconductor element 12, the insulating element 13, the first die pad 21 and the second die pad 22, and a portion of each of the multiple first terminals 3 and the multiple second terminals 4. As shown in Figure 6, the encapsulating resin 6 further covers the multiple first wires 51, the multiple second wires 52, the multiple third wires 53, and the multiple fourth wires 54. The encapsulating resin 6 is electrically insulating. The encapsulating resin 6 insulates the first die pad 21 and the second die pad 22 from each other. The encapsulating resin 6 is made of a material including, for example, black epoxy resin. Viewed along the thickness direction z, the encapsulating resin 6 is rectangular in shape.

[0077] As shown in Figures 3 to 5, the sealing resin 6 has a top surface 61, a bottom surface 62, a pair of first side surfaces 63, and a pair of second side surfaces 64.

[0078] As shown in Figures 3 to 5, the top surface 61 and the bottom surface 62 are located apart from each other in the thickness direction z. The top surface 61 and the bottom surface 62 face opposite each other in the thickness direction z. Each of the top surface 61 and the bottom surface 62 is flat (or nearly flat).

[0079] As shown in Figures 3 to 5, the pair of first sides 63 are connected to the top surface 61 and the bottom surface 62, and are located apart from each other in the first direction x. Each of the multiple first terminals 3 is exposed from the first side 63 located on one side of the pair of first sides 63 in the first direction x. Each of the multiple second terminals 4 is exposed from the first side 63 located on the other side of the pair of first sides 63 in the first direction x.

[0080] As shown in Figures 3 to 5, each of the pair of first sides 63 includes a first upper section 631, a first lower section 632, and a first intermediate section 633. The first upper section 631 has one end in the thickness direction z connected to the top surface 61 and the other end in the thickness direction z connected to the first intermediate section 633. The first upper section 631 is inclined with respect to the top surface 61. The first lower section 632 has one end in the thickness direction z connected to the bottom surface 62 and the other end in the thickness direction z connected to the first intermediate section 633. The first lower section 632 is inclined with respect to the bottom surface 62. The first intermediate section 633 has one end in the thickness direction z connected to the first upper section 631 and the other end in the thickness direction z connected to the first lower section 632. The first intermediate section 633 is aligned along both the thickness direction z and the second direction y. Viewed along the thickness direction z, the first intermediate section 633 is located outward from the top surface 61 and the bottom surface 62. From the first intermediate section 633, a portion of each of the multiple first terminals 3, or a portion of each of the multiple second terminals 4, is exposed.

[0081] As shown in Figures 3 to 5, the pair of second sides 64 are connected to the top surface 61 and the bottom surface 62, and are located apart from each other in the second direction y. As shown in Figures 1 and 2, the first die pad 21, the second die pad 22, the multiple first terminals 3, and the multiple second terminals 4 are located apart from the pair of second sides 64.

[0082] As shown in Figures 3 to 5, each of the pair of second sides 64 includes a second upper 641, a second lower 642, and a second intermediate 643. The second upper 641 has one end in the thickness direction z connected to the top surface 61 and the other end in the thickness direction z connected to the second intermediate 643. The second upper 641 is inclined with respect to the top surface 61. The second lower 642 has one end in the thickness direction z connected to the bottom surface 62 and the other end in the thickness direction z connected to the second intermediate 643. The second lower 642 is inclined with respect to the bottom surface 62. The second intermediate 643 has one end in the thickness direction z connected to the second upper 641 and the other end in the thickness direction z connected to the second lower 642. The second intermediate 643 is aligned along both the thickness direction z and the second direction y. Viewed along the thickness direction z, the second intermediate 643 is located outward from the top surface 61 and the bottom surface 62.

[0083] In the motor driver circuit of an inverter device, a half-bridge circuit including a low-side (low-potential side) switching element and a high-side (high-potential side) switching element is generally configured. In the following explanation, we will assume that these switching elements are MOSFETs. Here, in the case of a low-side switching element, the reference potential of the source of the switching element and the reference potential of the gate driver that drives the switching element are both ground. On the other hand, in the case of a high-side switching element, the reference potential of the source of the switching element and the reference potential of the gate driver that drives the switching element are both equivalent to the potential at the output node of the half-bridge circuit. Since the potential at the output node changes depending on the operation of the high-side and low-side switching elements, the reference potential of the gate driver that drives the high-side switching element changes. When the high-side switching element is on, the reference potential is equivalent to the voltage applied to the drain of the switching element (for example, 600V or higher). In semiconductor device A1, the ground of the first semiconductor element 11 and the ground of the second semiconductor element 12 are configured to be separate. Therefore, when semiconductor device A1 is used as a gate driver to drive the high-side switching element, a voltage equivalent to the voltage applied to the drain of the high-side switching element is transiently applied to the ground of the second semiconductor device 12.

[0084] Next, we will explain the effects and benefits of semiconductor device A1.

[0085] The semiconductor device A1 includes an insulating element 13 that insulates a first circuit, which includes a first semiconductor element 11 mounted on a first die pad 21, from a second circuit, which includes a second semiconductor element 12 mounted on a second die pad 22. The insulating element 13 is mounted on a specific die pad 20 (the first die pad 21 in the case of semiconductor device A1). This makes it possible to improve the dielectric strength between the first circuit and the second circuit when there is a difference between the power supply voltage supplied to the first semiconductor element 11 and the power supply voltage supplied to the second semiconductor element 12.

[0086] The semiconductor device A1 further comprises a first wire 51 bonded to an insulating element 13 and a specific semiconductor element 10 (a second semiconductor element 12 in semiconductor device A1). The first wire 51 is covered with a sealing resin 6. As shown in Figure 8, the first wire 51 has a first upright portion 511, a first inclined portion 512, a first extension portion 513, a first bent portion 514, and a second bent portion 515. The inclination angle β1 of the first extension portion 513 with respect to a plane along the first direction x and the second direction y is smaller than the inclination angle α1 of the first inclined portion 512 with respect to the same plane. As a result, the first wire 51 forms a framework structure with the first bent portion 514 and the second bent portion 515 as contact points. Therefore, when forming the sealing resin 6 during the manufacturing process of semiconductor device A1, deformation of the first wire 51 caused by the flow of the molten resin is suppressed. As a result, the distance between the insulating element 13 and the first extension portion 513 is made larger. Therefore, semiconductor device A1 makes it possible to improve the dielectric strength.

[0087] As shown in Figure 8, in the thickness direction z, the boundary 513A between the first extension 513 and the first bent portion 514 is located further from the insulating element 13 than the boundary 513B between the first extension 513 and the second bent portion 515. As a result, when viewed along the thickness direction z, the distance in the thickness direction z between the portion of the first extension 513 that overlaps with the insulating element 13 and the insulating element 13 can be made larger than the distance between other portions and the insulating element 13. This contributes to improving the dielectric strength of the semiconductor device A1.

[0088] As shown in Figure 8, when viewed along the thickness direction z, the boundary 512B between the first inclined portion 512 and the second bent portion 515 is located away from the specific semiconductor element 10. This improves the dielectric strength of the semiconductor device A1 while preventing the length of the first wire 51 from becoming excessively large.

[0089] The semiconductor device A1 further comprises an insulating element 13 and a second wire 52 bonded to a semiconductor element (first semiconductor element 11 in semiconductor device A1) mounted on a specific die pad 20. The second wire 52 is covered with a sealing resin 6. As shown in Figure 10, the second wire 52 has a second upright portion 521, a second inclined portion 522, a second extension portion 523, a third bent portion 524, and a fourth bent portion 525. The inclination angle β2 of the second extension portion 523 with respect to a plane along the first direction x and the second direction y is smaller than the inclination angle α2 of the second inclined portion 522 with respect to the same plane. As a result, the second wire 52 forms a framework structure with the third bent portion 524 and the fourth bent portion 525 as contact points. Therefore, when forming the sealing resin 6 during the manufacturing process of the semiconductor device A1, deformation of the second wire 52 caused by the flow of the molten resin is suppressed. As a result, the distance between the insulating element 13 and the second extension 523 becomes larger, making it possible to further improve the dielectric strength of the semiconductor device A1.

[0090] As shown in Figure 10, when viewed along the thickness direction z, the boundary 522B between the second inclined portion 522 and the fourth bent portion 525 is located away from the semiconductor element mounted on the specific die pad 20. This improves the dielectric strength of the semiconductor device A1 while preventing the length of the second wire 52 from becoming excessively large.

[0091] In the first direction x, the insulating element 13 is located between the first semiconductor element 11 and the second semiconductor element 12. The length L2 of the second extension 523 of the second wire 52 (see Figure 10) is shorter than the length L1 of the first extension 513 of the first wire 51 (see Figure 8). This improves the dielectric strength of the semiconductor device A1 while reducing the distance between the insulating element 13 and the semiconductor elements mounted on the specific die pad 20. This suppresses the increase in size of the semiconductor device A1.

[0092] In semiconductor device A1, the multiple first terminals 3 are exposed from one of the pair of first side surfaces 63 of the sealing resin 6 located in the first direction x. The multiple second terminals 4 are exposed from the first side surface 63 located in the other of the pair of first side surfaces 63 in the first direction x. In this case, the first die pad 21, the second die pad 22, the multiple first terminals 3, and the multiple second terminals 4 are located away from the pair of second side surfaces 64 of the sealing resin 6. Therefore, in semiconductor device A1, no metal members such as island supports are exposed from each of the pair of second side surfaces 64. With this configuration, there are no metal members exposed from the sealing resin 6 near the multiple second terminals 4 to which a higher voltage than that of the multiple first terminals 3 is applied. Therefore, semiconductor device A1 can achieve further improvement in dielectric strength.

[0093] A semiconductor device A2 according to a second embodiment of the present disclosure will be described with reference to Figures 18 and 19. In these figures, elements that are the same as or similar to those in the semiconductor device A1 described above are denoted by the same reference numerals, and redundant explanations are omitted. Here, for ease of understanding, Figure 18 shows the sealing resin 6 being permeable. In Figure 18, the permeable sealing resin 6 is shown by dashed lines.

[0094] In semiconductor device A2, the configuration of the first die pad 21 differs from that of semiconductor device A1 described above.

[0095] As shown in Figures 18 and 19, a specific die pad 20 (first die pad 21 in A2) has a plurality of holes 213 formed therein. Each of the plurality of holes 213 is formed in a region of the first die pad 21 located between the first semiconductor element 11 and the insulating element 13 in the first direction x. The number of holes 213 is not particularly limited, but in semiconductor device A2, three holes 213 are formed. Each of the plurality of holes 213 is an elongated hole extending in the second direction y. The shape of each of the plurality of holes 213 can be freely set. As shown in Figure 18, in the first die pad 21, the pair of first support terminals 33 and the plurality of holes 213 are arranged on a straight line N (dotted line) along the second direction y.

[0096] Next, we will explain the effects and benefits of semiconductor device A2.

[0097] The semiconductor device A2 includes an insulating element 13 that insulates a first circuit, which includes a first semiconductor element 11 mounted on a first die pad 21, from a second circuit, which includes a second semiconductor element 12 mounted on a second die pad 22. The insulating element 13 is mounted on a specific die pad 20 (the first die pad 21 in semiconductor device A2). The semiconductor device A2 further includes a first wire 51 bonded to the insulating element 13 and the specific semiconductor element 10 (the second semiconductor element 12 in semiconductor device A2). The first wire 51 is covered with a sealing resin 6. As shown in Figure 8, the first wire 51 has a first upright portion 511, a first inclined portion 512, a first extension portion 513, a first bent portion 514, and a second bent portion 515. The inclination angle β1 of the first extension portion 513 with respect to a plane along the first direction x and the second direction y is smaller than the inclination angle α1 of the first inclined portion 512 with respect to the same plane. Therefore, semiconductor device A2 can also improve the dielectric strength. Furthermore, by adopting a configuration common to semiconductor device A1, semiconductor device A2 can achieve the same effect as semiconductor device A1.

[0098] In semiconductor device A2, a hole 213 is formed in a specific die pad 20. Viewed along the thickness direction z, the area of ​​the first die pad 21 is larger than the area of ​​the second die pad 22. Therefore, when forming the sealing resin 6, voids are likely to occur in the portion of the sealing resin 6 located near the specific die pad 20. By forming a hole 213 in the specific die pad 20, the molten resin injected into the mold during the formation of the sealing resin 6 can be sufficiently filled. In other words, semiconductor device A2 can effectively suppress the occurrence of voids in the sealing resin 6 compared to a case where the specific die pad 20 does not have a hole 213.

[0099] A semiconductor device A3 according to a third embodiment of this disclosure will be described based on Figures 20 to 23. In these figures, elements that are the same as or similar to those in the semiconductor device A1 described above are denoted by the same reference numerals, and redundant explanations are omitted. Here, for ease of understanding, Figure 20 shows the sealing resin 6 being permeable. In Figure 20, the permeable sealing resin 6 is shown by dashed lines.

[0100] In semiconductor device A3, the arrangement of the insulating element 13 differs from that of semiconductor device A1 described above.

[0101] As shown in Figures 20 and 21, the insulating element 13 is mounted on the second main surface 221 of the second die pad 22. Therefore, in semiconductor device A3, the second die pad 22 corresponds to the specific die pad 20, and the first semiconductor element 11 corresponds to the specific semiconductor element 10.

[0102] As shown in Figure 22, in semiconductor device A3, each of the multiple first wires 51 is joined to one of the multiple first electrodes 131 of the insulating element 13 and one of the multiple electrodes 111 of the first semiconductor element 11. As a result, the first upright portion 511 of each of the multiple first wires 51 rises up in the thickness direction z from one of the multiple first electrodes 131 of the insulating element 13. The first inclined portion 512 of each of the multiple first wires 51 extends inclined with respect to the thickness direction z from one of the multiple electrodes 111 of the first semiconductor element 11 toward the insulating element 13.

[0103] As shown in Figure 23, in semiconductor device A3, each of the multiple second wires 52 is joined to one of the multiple second electrodes 132 of the insulating element 13 and one of the multiple electrodes 121 of the second semiconductor element 12. As a result, the second upright portion 521 of each of the multiple second wires 52 rises in the thickness direction z from one of the multiple second electrodes 132 of the insulating element 13. The second inclined portion 522 of each of the multiple second wires 52 extends inclined with respect to the thickness direction z from one of the multiple electrodes 121 of the second semiconductor element 12 toward the insulating element 13.

[0104] Next, we will explain the effects and benefits of semiconductor device A3.

[0105] The semiconductor device A3 includes an insulating element 13 that insulates a first circuit, which includes a first semiconductor element 11 mounted on a first die pad 21, from a second circuit, which includes a second semiconductor element 12 mounted on a second die pad 22. The insulating element 13 is mounted on a specific die pad 20 (the second die pad 22 in the case of semiconductor device A3). The semiconductor device A3 further includes a first wire 51 bonded to the insulating element 13 and the specific semiconductor element 10 (the first semiconductor element 11 in the case of semiconductor device A3). The first wire 51 is covered with a sealing resin 6. As shown in Figure 22, the first wire 51 has a first upright portion 511, a first inclined portion 512, a first extension portion 513, a first bent portion 514, and a second bent portion 515. The inclination angle β1 of the first extension portion 513 with respect to a plane along the first direction x and the second direction y is smaller than the inclination angle α1 of the first inclined portion 512 with respect to the same plane. Therefore, semiconductor device A3 can also improve the dielectric strength. Furthermore, by adopting a configuration common to semiconductor device A1, semiconductor device A3 achieves the same effect as semiconductor device A1.

[0106] This disclosure is not limited to the embodiments described above. The specific configuration of each part of this disclosure can be modified in various ways. [Explanation of symbols]

[0107] A1, A2, A3: Semiconductor equipment 10: Specific semiconductor elements 11: First semiconductor element (control element) 111: Electrode 12: Second semiconductor element (driving element) 121: Electrode 13: Insulating element 131: First electrode 132: Second electrode 133: Passivation membrane 134: Surface protective film 134A: First film 134B: Second membrane 20: Specific die pad 21: First die pad 211: First main surface 212: Reverse side 213: Hole 22: Second die pad 221: Second main surface 222: Second reverse side 23: Pad gap 3: First terminal 31: First intermediate terminal 311: Lead section 312: Pad section 32: First terminal 321: Lead section 322: Pad section 33: First support terminal 331: Lead section 332: Pad section 4: Second terminal 41: Second intermediate terminal 411: Lead section 42: Pad section 42: Second terminal 421: Lead section 422: Pad section 43: Second support terminal 431: Lead section 432: Pad section 433: Connecting section 51: First wire 511: 1st standing part 512: 1st inclined part 512A: 1st tip 512B: Boundary 513: First extension part 513A, 513B: Boundary 514: First bent part 515: Second bent part 52: Second wire 521: Second standing section 522: Second slope part 522A: Second tip 522B: Boundary 523: Second extension part 523A, 523B: Boundary 524: Third bending part 525: Fourth bend 53: Third wire 54; Fourth wire 6: Sealing resin 61:Top 62:Bottom 63: 1st side 631: 1st top 632: First lower section 633: First middle section 64:Second side 641:Second top 642: Second lower section 643: Second middle section 80: Capillary 81: Wire z: thickness direction x: first direction y: second direction

Claims

1. First die pad and A second die pad that is separated from the first die pad in a first direction and has a potential difference relative to the first die pad, A first semiconductor element mounted on the first die pad and constituting a first circuit together with the first die pad, A second semiconductor element mounted on the second die pad and constituting a second circuit together with the second die pad, When either the first die pad or the second die pad is referred to as a specific die pad and the other as a non-specific die pad, an insulating element is mounted on the specific die pad, relays the transmission and reception of signals between the first circuit and the second circuit, and insulates the first circuit and the second circuit from each other, In a case where, of the first semiconductor element and the second semiconductor element, the one mounted on the non-specific die pad is referred to as the specific semiconductor element, and the one mounted on the specific die pad is referred to as the non-specific semiconductor element, the insulating element and the first wire joined to the specific semiconductor element, The device comprises a sealing resin that covers the first die pad, the second die pad, the first semiconductor element, the second semiconductor element, and the insulating element, and also insulates the first die pad and the second die pad from each other. The first wire spans the pad gap provided between the first die pad and the second die pad in the first direction. The first wire includes a first upright portion, a first inclined portion, a first extended portion, a first bent portion, and a second bent portion. The first upright portion rises from the insulating element in the thickness direction of the first die pad, The first inclined portion extends inclined with respect to the thickness direction from the specific semiconductor element toward the insulating element, The first extension is located between the first upright portion and the first inclined portion when viewed in the thickness direction. The first bent portion is connected to the first upright portion and the first extended portion, The second bent portion is connected to the first inclined portion and the first extended portion, The length of the first extension is greater than the lengths of the first upright portion, the first inclined portion, the first bent portion, and the second bent portion. Each of the first and second bends includes a section composed of a curve, Of the entire first wire, the boundary between the first extension and the first bend is the furthest from the specific die pad in the thickness direction. When a virtual plane is set with the first direction and a second direction perpendicular to the thickness direction and the first direction as in-plane directions, the inclination angle of the first extension with respect to the virtual plane is smaller than the inclination angle of the first inclined portion with respect to the virtual plane. A semiconductor device in which the inclination angle of the first upright portion with respect to the virtual plane is greater than the inclination angles of the first extension portion and the first inclined portion with respect to the virtual plane.

2. The semiconductor device according to claim 1, wherein the first extension spans the pad gap.

3. The semiconductor device according to claim 2, wherein, in the thickness direction, the boundary between the first extension and the first bend is further away from the insulating element than the boundary between the first extension and the second bend.

4. The semiconductor device according to claim 2, wherein, when viewed in the thickness direction, the boundary between the first inclined portion and the second bent portion is separated from the specific semiconductor element.

5. Further equipped with a second wire, In the first direction, the insulating element is located between the first semiconductor element and the second semiconductor element. The second wire is bonded to the insulating element and the non-specific semiconductor element and is covered with the sealing resin. The second wire has a second upright portion, a second inclined portion, a second extended portion, a third bent portion, and a fourth bent portion. The second upright portion rises from the insulating element in the thickness direction, The second inclined portion extends inclined with respect to the thickness direction from the non-specific semiconductor element toward the insulating element, The second extension is located between the second upright portion and the second inclined portion when viewed in the thickness direction. The third bent portion is connected to the second upright portion and the second extended portion, The fourth bent portion is connected to the second inclined portion and the second extension portion, The semiconductor device according to any one of claims 2 to 4, wherein the length of the second extension is less than the length of the first extension.

6. The semiconductor device according to claim 5, wherein the inclination angle of the second extension with respect to the virtual plane is smaller than the inclination angle of the second inclined portion with respect to the virtual plane.

7. The semiconductor device according to claim 6, wherein, when viewed in the thickness direction, the boundary between the second inclined portion and the fourth bent portion is separated from the non-specific semiconductor element.

8. In the first wire, the dimension of the first tip of the first inclined portion joined to the specific semiconductor element in the thickness direction becomes smaller as it moves away from the first extension portion. The semiconductor device according to claim 6 or 7, wherein the dimension in the thickness direction of the second tip of the second inclined portion joined to the non-specific semiconductor element in the second wire becomes smaller as it moves away from the second extension portion.

9. With power supply voltage supplied to each of the first and second circuits, The semiconductor device according to any one of claims 5 to 8, wherein the power supply voltage supplied to the second circuit is greater than the power supply voltage supplied to the first circuit.

10. Each of the first terminals includes a portion located on one side in the first direction relative to the first die pad, The present invention further comprises a plurality of second terminals, each including a portion located on the other side in the first direction relative to the second die pad, The plurality of first terminals are separated from each other in the second direction, and at least one of them is conductive to the first circuit. The plurality of second terminals are separated from each other in the second direction, and at least one of them is conductive to the second circuit. The sealing resin has a pair of first surfaces that are separated from each other in the first direction, and a pair of second surfaces that are separated from each other in the second direction. The semiconductor device according to claim 9, wherein each of the plurality of first terminals is exposed from one of the pair of first sides, and each of the plurality of second terminals is exposed from the other of the pair of first sides.

11. The semiconductor device according to claim 10, wherein, in view of the first direction, the second die pad overlaps the first die pad.

12. The semiconductor device according to claim 10 or 11, wherein the first die pad, the second die pad, the plurality of first terminals, and the plurality of second terminals are separated from the pair of second sides.

13. Viewed in the thickness direction, each of the plurality of first terminals includes a portion that protrudes from one of the first sides along the first direction, The semiconductor device according to claim 12, wherein, viewed in the thickness direction, each of the plurality of second terminals includes a portion that protrudes from the other first side surface along the first direction.

14. The plurality of first terminals include a pair of first support terminals that are separated from each other in the second direction. The first die pad has a pair of first edges that are separated from each other in the second direction, The semiconductor device according to claim 13, wherein the pair of first support terminals are each connected to the pair of first end edges.

15. The plurality of second terminals include a pair of second support terminals that are separated from each other in the second direction. The second die pad has a pair of second edges spaced apart from each other in the second direction, The semiconductor device according to claim 14, wherein the pair of second support terminals are each connected to the pair of second end edges.

16. The aforementioned die pad is provided with a hole that penetrates in the thickness direction, The semiconductor device according to any one of claims 10 to 15, wherein, viewed in the thickness direction, the hole is located between the insulating element and the non-specific semiconductor element.

17. The semiconductor device according to any one of claims 1 to 16, wherein the insulating element is of the inductive type.

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