Non-synchronous ASIC

Abstract

Providing asynchronous ASICs. [Solution] An electronic device is disclosed. The electronic device comprises a first clock configured to operate at a certain frequency. A first circuit configuration of the electronic device is configured to synchronize with the first clock. A second circuit configuration is configured to determine a second clock based on the first clock. The second clock is configured to operate at the frequency of the first clock and further configured to operate with a phase shift relative to the first clock. A third circuit configuration is configured to synchronize with the second clock.

Description

Technical Field

[0001] (Cross - Reference to Related Applications) This application claims priority to U.S. Provisional Patent Application No. 62 / 750,180, filed on October 24, 2018, the content of which is hereby incorporated by reference in its entirety.

[0002] (Field) The present disclosure relates to electronic circuits, and more particularly, to systems and methods for providing a clock signal to components of an electronic device.

Background Art

[0003] (Background) Almost all digital logic devices use a clock signal to initiate or control the synchronized behavior of the electronic components of these devices. For example, a clock signal provided to the clock input of a register causes the register to transfer a data input to a data output. At a low level, a clock signal (e.g., a periodic digital logic signal that alternates between logic 1 and logic 0) can cause one or more semiconductor devices (e.g., the transistors of a register) to switch from a conductive state to a non - conductive state, or vice versa.

[0004] In devices including application-specific integrated circuits (ASICs), the ASIC can be thought of as containing individual functional units (or "blocks"), each with its own registers synchronized to the block's local clock. A block may contain circuit configurations (including programmable logic circuit configurations) configured to perform one or more functions associated with the block. In so-called synchronous circuit designs, two or more blocks may be synchronized to the same global clock in a single "clock domain." By synchronizing blocks within a clock domain, synchronous circuits can avoid problems common to using multiple independent local clocks, namely clock drift, which may require inefficient rebuffering operations to compensate for. However, by providing the same clock signal to multiple clocks simultaneously, synchronous circuits may experience unwanted higher-order effects, such as resonant circuit noise ("transistor resonance") caused by the large number of transistors switching at once. For modern digital devices, the number of such transistors is astonishing (on the order of tens of billions for some devices), and the resulting resonant circuit noise can be extremely noticeable. Moreover, these unwanted effects can be amplified as the clock frequency increases. It is desirable to use a timing scheme that retains the advantages of a synchronized clock while avoiding the unwanted noise that a synchronized clock may introduce. As described herein, this can be achieved by dividing the clock domain into a "phase-shifted clock domain," which exchanges data asynchronously but is synchronized to a "phase-shifted clock" derived from a common reference clock. [Overview of the Initiative] [Means for solving the problem]

[0005] (Brief overview) Systems and methods for indicating a clock signal in a digital device are disclosed. In some examples, an electronic device is disclosed having a first clock configured to operate at a certain frequency. A first circuit configuration of the electronic device is configured to synchronize with the first clock. A second circuit configuration is configured to determine a second clock based on the first clock. The second clock is configured to operate at the frequency of the first clock and further configured to operate with a phase shift relative to the first clock. A third circuit configuration is configured to synchronize with the second clock. The present invention provides, for example, the following: (Item 1) A first clock configured to operate at a certain frequency, A first circuit configuration configured to synchronize with the first clock, A second circuit configuration configured to determine a second clock based on the first clock, wherein the second clock is configured to operate at the frequency of the first clock and further configured to operate with a phase shift relative to the first clock, A third circuit configuration configured to synchronize with the second clock and An electronic device equipped with the following features. (Item 2) Determining the second clock mentioned above is The method involves generating multiple clock candidates, each of which is configured to operate at the frequency of the first clock, and further configured to operate with a phase shift relative to the first clock. Selecting the second clock from the multiple clock candidates and An electronic device as described in item 1, comprising the features described in item 1. (Item 3) The electronic device according to item 2, wherein the second clock is selected from among the plurality of clock candidates, each having the phase shift closest to 180 degrees. (Item 4) The electronic device according to item 2, wherein the second clock is selected to reduce the transistor resonance of the electronic device. (Item 5) The electronic device according to item 1, wherein the electronic device is an ASIC, the first circuit configuration corresponds to a first functional block of the ASIC, the second circuit configuration includes a delay-locked loop, and the third circuit configuration corresponds to a second functional block of the ASIC. (Item 6) The aforementioned electronic device further includes memory, The electronic device is configured to perform a data write operation to the memory, and the data write operation is synchronized with the first clock. The electronic device is configured to perform a data read operation to the memory, and the data read operation is synchronized with the second clock. The electronic devices listed in item 1. (Item 7) The electronic device according to item 1, wherein the first circuit configuration is further configured to transmit data to the third circuit configuration. (Item 8) The electronic device further comprises a data bus electronically coupled to the first circuit configuration and the third circuit configuration, the data bus comprising one or more wires including a first wire, The first circuit configuration is further configured to transmit the data to the third circuit configuration via the data bus. The electronic device further comprises one or more latches, including a first latch, the first latch being configured to receive data via a first wire, and the first latch being configured to synchronize with a third clock determined based on the first clock. Determining the third clock based on the first clock means The method involves generating multiple clock candidates, each of which is configured to operate at the frequency of the first clock, and further configured to operate with a phase shift relative to the first clock. Selecting the third clock from the multiple clock candidates and Equipped with, The third clock is selected from the plurality of clock candidates based on the latency between the first circuit configuration that transmits the data and the first latch that receives the data. The electronic devices listed in item 7. (Item 9) Each of the one or more latches is configured to correspond to each of the one or more wires and to receive the data through each of the wires. Each of the one or more latches is configured to synchronize with each of the clocks selected from the plurality of clock candidates. Each clock is selected from the plurality of clock candidates based on the latency between the first circuit configuration that transmits the data and the latch of that respective clock that receives the data. The electronic devices listed in item 8. (Item 10) In an electronic device comprising a first circuit configuration, a second circuit configuration, and a third circuit configuration, Synchronizing the first circuit configuration with a first clock operating at a certain frequency, The method involves determining a second clock based on the first clock, wherein the second clock operates at the same frequency as the first clock and further operates with a phase shift relative to the first clock. The third circuit configuration is synchronized with the second clock. A method that includes [a certain feature]. (Item 11) Determining the second clock mentioned above is Generating a plurality of clock candidates, wherein each clock candidate among the plurality of clock candidates operates at the frequency of the first clock and further operates with a respective phase shift relative to the first clock; Selecting the second clock from the plurality of clock candidates; The method according to item 10, comprising: (Item 12) The method according to item 11, wherein the second clock is selected to be a clock candidate having a respective phase shift closest to 180 degrees among the plurality of clock candidates. (Item 13) The method according to item 11, wherein the second clock is selected to reduce transistor resonance of the electronic device. (Item 14) The method according to item 10, wherein the first circuit configuration corresponds to a first functional block of an ASIC, the second circuit configuration includes a delay lock loop, and the third circuit configuration corresponds to a second functional block of the ASIC. (Item 15) Performing a data writing operation on a memory of the electronic device according to a transition of the first clock; Performing a data reading operation on the memory according to a transition of the second clock; The method according to item 10, further comprising: (Item 16) The method according to item 10, further comprising transmitting data from the first circuit configuration to the third circuit configuration. (Item 17) A method of transmitting data, the method comprising: Synchronizing a first circuit configuration with a first clock operating at a certain frequency, wherein the first clock is associated with a first clock domain; Determining a second clock based on the first clock, wherein the second clock operates at the frequency of the first clock and further operates with a phase shift relative to the first clock, and the second clock is associated with a second clock domain, Synchronizing a second circuit configuration with the second clock, wherein the second circuit configuration is configured to receive data from the first circuit configuration via one or more latches electronically coupled to a data bus, the data bus comprises one or more wires including a first wire, and the one or more latches include a first latch configured to receive the data via the first wire, Generating a plurality of clock candidates, each of the plurality of clock candidates being configured to operate at the frequency of the first clock and further configured to operate with a respective phase shift relative to the first clock, Synchronizing the first latch with a third clock selected from the plurality of clock candidates, Transmitting the data from the first circuit configuration to the second circuit configuration via the data bus and the first latch A method comprising. (Item 18) The method according to item 17, wherein the third clock is selected from the plurality of clock candidates based on the latency between the first circuit configuration transmitting the data and the first latch receiving the data. (Item 19) Each of the one or more latches corresponds to a respective one of the one or more wires and is configured to receive the data via the respective wire, The method comprises For each of the one or more latches, selecting a respective clock from the plurality of clock candidates based on the latency between the latch and the first circuit configuration transmitting the data, and synchronizing the latch with the respective clock The method described in item 18, further comprising: [Brief explanation of the drawing]

[0006] (Brief explanation of the drawing) [Figure 1] Figure 1 illustrates an example electronic device with blocks grouped into clock domains, according to several embodiments.

[0007] [Figure 2] Figure 2 illustrates an example electronic device with blocks grouped into clock domains and phase-shifted clock domains, according to several embodiments.

[0008] [Figure 3] Figure 3 illustrates an example of two phase-shifted clock domains in an electronic device configured to exchange data, according to several embodiments.

[0009] [Figure 4] Figure 4 illustrates a first-in, first-out (FIFO) buffer, which is an example configured to transfer data between two phase-shifted clock domains of an electronic device, according to several embodiments.

[0010] [Figure 5] Figure 5 illustrates an example of generating a phase-shifted clock from a reference clock according to several embodiments.

[0011] [Figure 6] Figure 6 illustrates a block diagram of an example process for configuring data transfer between two phase-shifted clock domains of an electronic device, according to several embodiments. [Modes for carrying out the invention]

[0012] (Detailed explanation) The following examples refer to the accompanying drawings, which form part of this specification, illustrating specific examples that may be put into practice. It will be understood that other examples may be used and that structural modifications may be made without departing from the scope of the examples disclosed.

[0013] Figure 1 illustrates a high-level diagram of ASIC 100 according to several embodiments. ASIC 100 includes seven functional blocks 110, 112, 114, 116, 118, 120, and 122, three reference clocks 130, 132, and 134, and three clock domains 140, 142, and 144, where clock domain 140 is synchronized to reference clock 130, clock domain 142 is synchronized to reference clock 132, and clock domain 144 is synchronized to reference clock 134. As shown in Figure 1, the three clock domains (140, 142, and 144) are shared among the seven blocks (110, 112, 114, 116, 118, 120, and 122) of ASIC 100 so that multiple blocks (e.g., 110, 112, and 114) are synchronized to the same clock domain (e.g., clock domain 140). Blocks synchronized to the same clock domain enjoy benefits such as the elimination of clock drift (removing the need to synchronize blocks to independent clocks). In such a system, data can be transmitted synchronously between two blocks within the same clock domain (for example, between block 110 and block 112 in this example).

[0014] However, synchronizing multiple blocks (e.g., blocks 110, 112, and 114) to the same clock domain (e.g., clock domain 140) can introduce unique problems. For example, the length of the wires connecting a transmit block (e.g., block 110) and a receive block (e.g., block 112) can cause propagation delays in data signals sent from the transmit block to the receive block, and these signals may not all arrive at their respective destinations within the receive block simultaneously (partly due to the different lengths of the wires carrying these signals). Correcting such timing errors introduces overhead and complexity. For example, data signals may need to be buffered along the transmission path as they propagate from the transmit block to the receive block, and the buffering process generally increases the power consumption of the digital logic device, including the transmit and receive blocks. Worse still, the need for buffering increases with the size and complexity of the digital logic device, which requires a larger number of blocks and thinner wires for inter-chip communication.

[0015] Furthermore, synchronizing multiple blocks of digital logic devices within a single clock domain means that the conducted state transition activity of semiconductor devices within these blocks is synchronized. For example, all transistors in blocks within the same clock domain (e.g., blocks 110, 112, and 114 within clock domain 140) may change state simultaneously. The resulting resonance can introduce unwanted digital noise that increases or decreases with the size, complexity, and transistor density of the ASIC 100. While such noise can be reduced by adding noise isolation to the ASIC blocks, adding noise isolation generally results in unnecessary power consumption and can introduce undesirable constraints on layout and design. It is desirable to stagger the transition times of such transistors between the on and off states within a single clock domain.

[0016] Therefore, to reduce the power consumption and complexity of the ASIC, the need to rebuffer data signals transmitted between two ASIC blocks synchronized to the same clock domain can be reduced. Furthermore, noise caused by synchronized switching of semiconductors within a single clock domain can be reduced. Moreover, these objectives can be achieved while retaining the benefits (e.g., simplicity, reliability) of synchronizing multiple ASIC blocks to a single reference clock within a single clock domain.

[0017] In some embodiments, this can be achieved by generating one or more phase-shifted clocks from a reference clock within a single clock domain synchronized to a single reference clock, and by coupling each phase-shifted clock to a subset of registers within that phase-shifted clock domain. Phase-shifted clocks generated from a reference clock may share the same frequency as the reference clock but may operate with a phase shift relative to the reference clock. Since the phase-shifted clocks are generated from the same reference clock and operate at the same frequency as the reference clock, there is no clock drift between two phase-shifted clocks within the same phase-shifted clock domain, nor between a phase-shifted clock and its reference clock. Registers within a clock domain may be divided into subgroups ("phase-shifted clock domains"), each subgroup timing to a phase-shifted clock, and the phase shift of each phase-shifted clock determines when the transistors of the corresponding registers change state relative to the reference clock. The timing of these state changes may be staggered by the circuit designer to achieve the desired "load balancing." Load balancing may reflect the designer's efforts to control the switching peaks of the design. For example, an ASIC in which many or all registers switch at the same moment may experience high peak current and high levels of noise from the power supply. However, by synchronizing the ASIC block to a phase-shifted clock so that many registers do not switch at the same moment, lower peak current and lower noise from the power supply can be achieved.

[0018] Figure 2 illustrates an example of dividing the clock domain of an example ASIC 100 into phase-shifted clock domains according to several embodiments. As shown in Figure 2, the clock domain 140 (synchronized to the reference block 130) is subdivided into three phase-shifted clock domains 140A, 140B, and 140C. Phase-shifted clock domain 140A may be synchronized to phase-shifted clock 130A, phase-shifted clock domain 140B may be synchronized to phase-shifted clock 130B, and phase-shifted clock domain 140C may be synchronized to phase-shifted clock 130C, where the phase-shifted clocks 130A, 130B, and 130C are derived from the reference clock 130 and operate at the same frequency as the reference clock 130. Similarly, in this example, clock domain 142 is subdivided into phase-shifted clock domains 142A, 142B, and 142C, where phase-shifted clock domain 142A is synchronized to phase-shifted clock 132A, phase-shifted clock domain 142B is synchronized to phase-shifted clock 132B, and phase-shifted clock domain 142C is synchronized to phase-shifted clock 132C, and these phase-shifted clocks are derived from reference clock 132. Not all clock domains need to be divided into phase-shifted clock domains; for example, in the example shown, clock domain 144 is not divided into phase-shifted clock domains and remains synchronized to reference clock 134.

[0019] An ASIC block can be synchronized to one or more phase-shifted clock domains. For example, in the example shown in Figure 2, block 110 is synchronized to phase-shifted clock domain 140A, block 112 is synchronized to phase-shifted clock domain 140B, and block 114 is synchronized to phase-shifted clock domain 140C. In some cases, two or more ASIC blocks can be synchronized to a single phase-shifted clock domain. Furthermore, two or more parts of a single ASIC block (e.g., a group of components or registers) can be synchronized to different phase-shifted clock domains. For example, as shown, the first part of block 120 is synchronized to phase-shifted clock domain 142B, and the second part of block 120 is synchronized to phase-shifted clock domain 142C. Circuit designers can divide an ASIC block or a region of an ASIC block into phase-shifted clock domains based on application-specific design considerations.

[0020] A phase-shifted clock can be generated using various techniques known in the art for generating a clock from a reference clock. For example, a delay-locked loop (DLL) may be used to generate a phase-shifted clock (e.g., phase-shifted clock 130A) as a phase-shifted version of a reference clock (e.g., reference clock 130) (with the same frequency as the reference clock).

[0021] Figure 3 illustrates an example of two phase-shifted clock domains in an ASIC, such as an example ASIC 100, configured to exchange data asynchronously according to several embodiments. As illustrated in Figure 3, block 110 (synchronous to phase-shifted clock domain 140A) exchanges data asynchronously with block 112 (synchronous to phase-shifted clock domain 140B). Block 110 includes an asynchronous transfer module 310A for sending data and / or control signals to block 112 via bus 150A, and block 112 includes an asynchronous receive module 312A for receiving data from block 110 (via transfer module 310A). Modules 310A and 312A may be arranged in a master / slave configuration, with module 310A configured as the master and module 312A configured as the slave. Similarly, in an example where block 112 is configured to send data and block 110 is configured to receive data, block 112 may include an asynchronous transfer module 312B for sending data and / or control signals to block 110 via bus 150B (which may be the same as bus 150A in some examples), and block 110 may include an asynchronous receive module 310B for receiving data from block 112 (via transfer module 312B). Modules 312B and 310B may be arranged in a master / slave configuration, with module 312B configured as the master and module 310B configured as the slave. Each transfer / receive module in each block is timed to the phase-shifted clock of its respective phase-shifted clock domain; for example, the transfer module 310A and receive module 310B of block 110 are timed to phase-shifted clock 130A, and the transfer module 312B and receive module 312A of block 112 are timed to phase-shifted clock 130B.(In some examples, the transfer and receive modules described herein do not need to be separate units, but may overlap or share common parts.)

[0022] Data bus 150A and / or data bus 150B can carry data and / or control signals in any suitable configuration. Various problems can arise when data traverses asynchronously between clock domains or phase-shifted clock domains. For example, data on bus 150A / bus 150B risks becoming incoherent if data from one "lane" of the data bus arrives at the receiving end earlier or later than expected (e.g., due to differences in the length of electrical wiring data must travel across each lane). In addition, data transmitted from a phase-shifted clock domain for transmission may be lost if it is not captured within the receiving phase-shifted clock domain due to data instability. Such phase-shifted clock domain crossing problems can lead to functional errors in the receiving phase-shifted clock domain. Various technologies suitable for dealing with clock domain crossing can be adapted to phase-shifted clock domain crossing, and one example of a system for addressing the problems of phase-shifted clock domain crossing is the first-in, first-out (FIFO) buffer described below. The clock domain crossing logic may be implemented in whole or in part, for example, within the asynchronous receive module 312A of block 112, within the asynchronous transfer module 310A of block 110, within the asynchronous receive module 310B of block 110, within the asynchronous transfer module 312B of block 112, within a circuit configuration between block 110 and block 112, or in any other suitable location or combination of locations.

[0023] Figure 4 illustrates a portion of an example FIFO buffer 400 configured to pass data between phase-shifted clock domains of an ASIC (such as phase-shifted clock domains 140A and 140B in an example ASIC 100) according to several embodiments. In some examples, the FIFO buffer 400 may be implemented in whole or in part within the asynchronous receive module 312A of block 112, within the asynchronous transfer module 310A of block 110, within the asynchronous receive module 310B of block 110, within the asynchronous transfer module 312B of block 112, within a circuit configuration between block 110 and block 112, or in any other suitable location or combination of locations. As illustrated in Figure 4, input 402 (shown in the figure as 402(K)) is data sent to the FIFO buffer 400, which, for example, may correspond to data sent via one or more wires of bus 150A from block 110 to block 112, as shown in Figure 3. In the example shown, input 402 has a width K of four bits (which may correspond to the number of wires K on bus 150A), and the four bits are shown as 402A, 402B, 402C, and 402D. However, the value of K may correspond to any appropriate data width. Each of bits 402A through 402D is shown as an input to the respective registers 404A through 404D. Each of the registers 404A through 404D is timed by the respective lane clocks 406A through 406D. Each of the lane clocks 406A to 406D is a phase-shifted clock selected for each register 404A to 404D as described below. Lane clocks 406A to 406D advance each data bit 402A to 402D through each register 404A to 404D to the multiplexer 408. Generally, the number of registers 404, the number of lane clocks 406, and the number of inputs to the multiplexer 408 are all equal to the data width K of input 402 (any suitable data width can be used, but in this example it is 4).

[0024] Lane clocks 406A to 406D are selected so that input bits 402A to 402D arrive at the input of the multiplexer 408 in an order arranged according to the bit positions of these input bits in input 402. Lane clocks 406A to 406D may be generated from a reference clock (e.g., reference clock 130) and may be selected as described below with respect to Figures 5 and 6. With bits 402A to 402D arriving at the multiplexer 408 in the ordered order, the multiplexer 408 may write the ordered data to memory 410 (which may include RAM or any other suitable type of storage). The ordered data may be read from memory 410 as data 440. The details of memory 410 may be selected to suit a near-future application; for example, example memory 410 may have enough storage to store 10 stages for each data bit 402A to 402D.

[0025] The write address for writing input 402 to memory 410 may be controlled by a write pointer 420, which can be advanced sequentially by a write clock 422 while the write enable 424 is active. Similarly, the read address for reading data 440 from memory 410 may be controlled by a read pointer 430, which can be advanced sequentially by a read clock 432 while the read enable 434 is active. In this example, the write clock 422 belongs to a phase-shifted clock domain 140A, and the write clock 432 belongs to a phase-shifted clock domain 140B. The phase-shifted clock domain 140A (and thus the write clock 422) may be synchronized to a phase-shifted clock 130A, and the phase-shifted clock domain 140B (and thus the write clock 432) may be synchronized to a phase-shifted clock 130B. As described above, one or more of the phase-shifted clocks 130A and 130B may be synchronized to the reference clock 130, and another or more of the phase-shifted clocks 130A and 130B may be a phase-shifted version of the reference clock 130 (but operating at the same frequency as the reference clock 130). Thus, the FIFO buffer 400 illustrates an example of transmitting data from a first block (e.g., 110) in a first phase-shifted clock domain (e.g., 140A) to a second block (e.g., 112) in a second phase-shifted clock domain (e.g., 140B). Furthermore, data may be transmitted in the reverse direction in a similar manner (i.e., from block 112 to block 110 via bus 150B).

[0026] Lane clocks 406A to 406D, write clock 422, and read clock 432 correspond to phase-shifted clocks generated from a reference clock (e.g., reference clock 130) as described above. Write clock 422 may correspond to the phase-shifted clock 130A (to which phase-shifted clock domain 140A is synchronized), and read clock 342 may correspond to the phase-shifted clock 130B (to which phase-shifted clock domain 140B is synchronized). In some examples, lane clocks 406A to 406D, write clock 422, and read clock 432 may be selected from one or more phase-shifted clock "candidates," where each phase-shifted clock candidate is generated from a reference clock (e.g., via a DLL), shares the frequency of the reference clock, and differs from other phase-shifted clock candidates in terms of its phase shift relative to the reference clock.

[0027] Figure 5 illustrates an example of generating a phase-shifted clock from a reference clock according to several embodiments. The DLL can take a reference clock 502 with period T (which may correspond to, for example, a reference clock 130) as input and N phase-shifted clock candidates (e.g., eight clock signals 506A to 506H) as outputs. The number of phase-shifted clock candidates N may be equal to, but does not have to be equal to, the number of lane clocks (e.g., 406A to 406D). In the example shown in Figure 5, each of the phase-shifted clock candidates 506A to 506H is phase-shifted relative to the reference clock 502 by a multiple of T / N. For example, if the reference clock 502 has a period of 24 ns (e.g., the time difference between t0 and t1 in Figure 5) and N is 8 as shown in this example, then the phase-shifted clock candidate 506A may have a phase shift of 0 ns (i.e., 0 * 24 / 8 ns), the phase-shifted clock candidate 506B may have a phase shift of 3 ns (i.e., 1 * 24 / 8 ns), the phase-shifted clock candidate 506C may have a phase shift of 6 ns (i.e., 2 * 24 / 8 ns), and so on. The technique of using a DLL to generate phase-shifted clocks (e.g., phase-shifted clock candidates 506A to 506H) from a reference clock is well known to those skilled in the art. T is the reciprocal of the reference clock frequency, and the number N can be selected by the circuit designer based on considerations such as the desired precision, latency requirements, complexity requirements, and the reference clock frequency. For example, a larger number N of phase-shifted clock candidates may potentially result in lower latency at the expense of complexity (because more suitable phase-shifted clock candidates may potentially be selected).

[0028] Once phase-shifted clock candidates 506A to 506H are generated, a lane clock (e.g., 406A to 406D) can be selected for each bit of the input data (e.g., K bits 402A to 402D of input data 402). In some examples, the clock selection may proceed as follows: Assuming T is the length of one cycle of the reference clock (e.g., a cycle that starts at time t0 and ends at time t1), it is known that each of the N phase-shifted clock candidates 506A to 506H is phase-shifted by a different multiple of T / N relative to the reference clock, so it is known that each of 506A to 506H has a rising edge at a different moment within a single cycle of the reference clock. That is, among the N phase-shifted clock candidates, the phase-shifted clock candidate with index i may have a rising edge at time t0 + i*((t1 - t0 / N)). For example, if t0 is 10, t1 is 14, and N is 8, then a phase-shifted clock candidate with index 0 (corresponding to, for example, phase-shifted clock candidate 506A) may have a rising edge at time 10 + 0 * ((14 - 10) / 8) = 10. Similarly, a phase-shifted clock candidate with index 1 (corresponding to, for example, phase-shifted clock candidate 506B) may have a rising edge at time 10 + 1 * ((14 - 10) / 8) = 10.5, a phase-shifted clock candidate with index 2 may have a rising edge at time 10 + 2 * ((14 - 10) / 8) = 11, and so on.

[0029] Using the knowledge that each of the N phase-shifted clock candidates may contain rising edges at equally spaced intervals within a single cycle of the reference clock, it can be predicted that a half-cycle data pulse (e.g., a data pulse 504 that may be delivered along bus 150A as a bit of data input 402) will be captured by N / 2 phase-shifted clock candidates. That is, if a half-cycle data pulse is directed to N latches (each latch gated by one of the N phase-shifted clock candidates), then half of the N latches (each gate transitioning from low to high while the data pulse was high) will produce a logic 1 at their respective outputs. Furthermore, if the phase-shifted clock candidates are arranged in order (i.e., each of the phase-shifted clock candidates in a sequence features a longer phase shift than the preceding phase-shifted clock candidate), then a half-cycle data pulse may be captured by adjacent groups of phase-shifted clock candidates. As an example, Figure 5 shows that data pulse 504 transitions from low to high at time t0, and then transitions from high to low at the midpoint between time t0 and time t1 (from that midpoint onward, data pulse 504 remains low). In this example, data pulse 504 is captured by four of the eight phase-shifted clock candidates (for example, phase-shifted clock candidates 506A to 506D, which correspond to the four phase-shifted clock candidates that transition from low to high while data pulse 504 is high).

[0030] From a set of phase-shifted clock candidates that capture half-cycle data pulses 504, a preferred phase-shifted clock candidate may be selected as the lane clock. It may be desirable for the lane clock to capture the data after the data has arrived and stabilized (i.e., in a receive block (e.g., 112), after the transient has settled and the data has entered a sufficiently stable state, so that the data is guaranteed to be valid). Furthermore, it may be desirable for the lane clock to capture the data at a significant temporal distance from either the rising or falling edge of the data to increase tolerance to intra-chip variation (OCV), jitter, temperature drift, and other sources of variation in the data or clock signal. Various metrics may be used to identify a preferred phase-shifted clock candidate from a set of phase-shifted clock candidates, according to the criteria that exemplify them, and as a result, to select the lane clock. In some embodiments, the lane clock may be selected so that its rising edge is closest to the midpoint of the reference clock cycle (i.e., the phase-shifted clock candidate whose phase shift relative to the reference clock is closest to 180 degrees), which may be because, throughout normal device operation, data arrives gradually in accordance with the full cycle of the reference clock, and therefore, the phase-shifted clock candidate whose rising edge is closest to the midpoint of the reference clock may best guarantee data stability. In some embodiments, the lane clock may be selected so that it is the last phase-shifted clock candidate in a group of phase-shifted clock candidates that capture half-cycle data pulses (i.e., the last phase-shifted clock candidate before the midpoint of the reference clock cycle). In some embodiments, the lane clock may be selected so that it is the first phase-shifted clock candidate following a group of phase-shifted clock candidates that capture half-cycle data pulses (i.e., the first phase-shifted clock candidate after the midpoint of the reference clock cycle).In some embodiments, the lane clock may be selected to be any one of a group of phase-shifted clock candidates that capture data pulses.

[0031] The number N of phase-shifted clock candidates can affect the accuracy of the lane clock. A larger value of N results in a smaller difference in phase shift between two adjacent phase-shifted clock candidates, increasing the likelihood of selecting an ideal lane clock. However, increasing the number of phase-shifted clock candidates N generally increases the time and circuit complexity required to perform the lane clock calibration process. The desired value of N can be chosen by the designer depending on the requirements of the specific device in the near future.

[0032] The lane clock selection process described above may be repeated (sequentially or in parallel) for two or more of the K data bits of the example data 402. For example, a half-cycle data pulse 504 may be provided on a path corresponding to each data bit of data 402 (e.g., data bits 402A to 402D), and for each bit, the best lane clock may be selected from N phase-shifted clock candidates. Since data travel times may differ slightly between data bits, some phase-shifted clock candidates may be better suited to a particular data bit than others. Selecting individual lane clocks based on each bit and timing each data bit 402A to 402D separately according to its respective lane clock promotes the correct order of data bits entering the memory 410, as described above.

[0033] In addition to selecting one or more lane clocks, the read clock (e.g., 432) may be selected from one of the phase-shifted clock candidates 506A to 506H. Similar to the lane clocks described above, the selected read clock shares the frequency of the reference clock but differs in phase. In this example, the read clock may correspond to the phase-shifted clock 130B described above with respect to Figure 2, and for example, all components in phase-shifted clock domain 140B that receive data from phase-shifted clock domain 140A may be synchronized to the selected read clock. To minimize the noise effects described above (which can be amplified by resonance caused by synchronizing most electronic devices to the same clock), the circuit designer may wish to select the read clock to be the phase-shifted clock candidate that is most phase-different from the other reference clocks and other phase-shifted clocks of the device. This can help, to the extent possible, minimize the degree to which the states of transistors switch simultaneously. For example, in a device where many blocks of the device are synchronized to a reference clock, the read clock may be selected as a phase-shifted clock candidate with a half-cycle phase shift from the reference clock.

[0034] Similarly, in some examples, the write clock (e.g., 422) may be selected from one of the phase-shifted clock candidates 506A to 506H. In this example, the write clock may correspond to the phase-shifted clock 130A described above with respect to Figure 2, and for example, all components of the phase-shifted clock domain 140A that transmit data to the phase-shifted clock domain 140B may be synchronized to the selected write clock. In some examples, the write clock may be selected following a procedure similar to the one described above for the read clock. In some examples, the write clock may simply be a buffered version of the reference clock (e.g., 130), or in some cases, the reference clock itself.

[0035] Designers may wish to avoid, as far as possible, selecting a phase-shifted clock that has the same phase shift as the reference clock or phase-shifted clock to which a significant portion of the device is synchronized. By appropriately assigning digital devices to phase-shifted clock domains, and by selecting phase-shifted clocks for those phase-shifted clock domains that are sufficiently different in phase, resonance (and associated noise) generated by tuned-switching transistors can be managed.

[0036] Figure 6 illustrates an example process 600 in which a device (e.g., device 100 described above) is configured to transmit data between a transmit block associated with a first phase-shifted clock domain (e.g., 140A) and a receive block associated with a second phase-shifted clock domain (e.g., 140B). In the example process shown, the stages on the left side of the figure may correspond to steps performed by a “master” transmit block (e.g., by the asynchronous transfer module 310A described above), and the stages on the right side of the figure may correspond to steps performed by a “slave” receive module (e.g., by the asynchronous receive module 312A described above). However, other suitable configurations are possible, and various steps in the example process may be performed by a transmit block, by a receive block, by a circuit configuration separate from the transmit and receive blocks, or by any suitable combination of the above.

[0037] In stage 610, the master block may send an initialization signal across all data buses and control buses to initialize the phase-shifted clock selection and data transmission processes. For example, this initialization signal may be a logic zero across all data buses and control buses. In stage 612, the master block may send a test pulse (e.g., a two-clock cycle pulse) to reset all latches in the slave block (e.g., 614).

[0038] In stage 616, the slave block may enter the lane clock selection phase described above, and the DLL may generate a desired number of phase-shifted clock candidates as described above, which are provided as clock inputs to their respective latches as described above. In stage 618, the master block may send a half-cycle data test pulse to the latch, followed by a logic low for signal 504 as described above (stage 620). The master block then waits for a ready signal from the slave (stage 622). Meanwhile, in stage 624, the latch of the slave block samples the data test pulse as described above. In stage 626, the slave block may select a preferred lane clock for each data bit as described above. Once the lane clock is selected, the read clock (e.g., corresponding to phase-shifted clock 130B) is selected as described above (stage 628). (In some examples, a write clock, such as one corresponding to phase-shifted clock 130A, may also be selected as described above.)

[0039] After the lane clock and read clock have been selected, the slave block may send a ready signal to the master block (stage 630) indicating that the clock has been selected and data transfer should begin. The read pointer (stage 632) and write pointer (stage 634) for memory 410, as shown above with respect to Figure 4, may be initialized in this stage. To avoid potential race conditions that could compromise the data integrity of the memory, it may be desirable that the read and write pointers be initialized to values ​​offset from each other. Following the initialization of the read and write pointers, as described above, data transmission may begin in the master block (stage 636) and data reception may begin in the slave block (stage 638).

[0040] Some embodiments disclosed herein are directed to an electronic device comprising: a first clock configured to operate at a certain frequency; a first circuit configuration configured to synchronize with the first clock; a second circuit configuration configured to determine a second clock based on the first clock; a second clock configured to operate at the frequency of the first clock and further configured to operate with a phase shift relative to the first clock; and a third circuit configuration configured to synchronize with the second clock. In addition to or alternative to one or more embodiments disclosed herein, in some embodiments, determining the second clock comprises generating a plurality of clock candidates, each of which is configured to operate at the frequency of the first clock and further configured to operate with a respective phase shift relative to the first clock; and selecting the second clock from among the plurality of clock candidates. In addition to or alternative to one or more embodiments disclosed herein, in some embodiments, the second clock is selected such that it is the clock candidate among the plurality of clock candidates having the respective phase shift closest to 180 degrees. In addition to or alternative to one or more embodiments disclosed herein, in some embodiments, a second clock is selected to reduce transistor resonance in the electronic device. In addition to or alternative to one or more embodiments disclosed herein, in some embodiments, the electronic device is an ASIC, where a first circuit configuration corresponds to a first functional block of the ASIC, a second circuit configuration comprises a delay-locked loop, and a third circuit configuration corresponds to a second functional block of the ASIC. In addition to or alternative to one or more embodiments disclosed herein, in some embodiments, the electronic device further comprises memory, the electronic device is configured to perform data write operations to the memory (synchronized to the first clock), and the electronic device is further configured to perform data read operations to the memory (synchronized to the second clock).In addition to or instead of one or more embodiments disclosed herein, in some embodiments, the first circuit configuration is further configured to transmit data to a third circuit configuration. In addition to or instead of one or more embodiments disclosed herein, in some embodiments, the electronic device further comprises a data bus ( comprising one or more wires, including a first wire) electronically coupled to a first circuit configuration and a third circuit configuration, the first circuit configuration further configured to transmit data to the third circuit configuration via the data bus, the electronic device comprising one or more latches ( comprising a first latch, configured to receive data via a first wire, and further configured to synchronize with a third clock determined on basis of a first clock), wherein determining the third clock on basis of a first clock comprises generating a plurality of clock candidates, each of the plurality of clock candidates being configured to operate at the frequency of the first clock, and further configured to operate with a respective phase shift relative to the first clock, and selecting a third clock from the plurality of clock candidates, the third clock being selected from the plurality of clock candidates based on the latency between the first circuit configuration transmitting data and the first latch receiving data. In addition to or instead of one or more embodiments disclosed herein, in some embodiments, each of one or more latches is configured to correspond to each of one or more wires and to receive data through each wire, and each of the one or more latches is configured to synchronize with each clock selected from a plurality of clock candidates, each clock being selected from a plurality of clock candidates based on the latency between a first circuit configuration that transmits data and its respective latch that receives data.

[0041] Some embodiments disclosed herein relate to a method for an electronic device comprising a first circuit configuration, a second circuit configuration, and a third circuit configuration, comprising: synchronizing the first circuit configuration with a first clock operating at a certain frequency; determining a second clock based on the first clock, wherein the second clock operates at the frequency of the first clock and further operates with a phase shift relative to the first clock; and synchronizing the third circuit configuration with the second clock. In addition to or alternative to one or more embodiments disclosed herein, in some embodiments, determining the second clock comprises generating a plurality of clock candidates, each of which operates at the frequency of the first clock and further operates with a respective phase shift relative to the first clock; and selecting the second clock from the plurality of clock candidates. In addition to or alternative to one or more embodiments disclosed herein, in some embodiments, the second clock is selected such that it is the clock candidate among the plurality of clock candidates having the respective phase shift closest to 180 degrees. In addition to or alternative to one or more embodiments disclosed herein, in some embodiments, a second clock is selected to reduce transistor resonance in the electronic device. In addition to or alternative to one or more embodiments disclosed herein, in some embodiments, a first circuit configuration corresponds to a first functional block of the ASIC, a second circuit configuration includes a delay-locked loop, and a third circuit configuration corresponds to a second functional block of the ASIC. In addition to or alternative to one or more embodiments disclosed herein, in some embodiments, the method further comprises performing a data write operation to the memory of the electronic device according to a transition of the first clock and performing a data read operation to the memory according to a transition of the second clock. In addition to or alternative to one or more embodiments disclosed herein, in some embodiments, the method further comprises transmitting data from the first circuit configuration to the third circuit configuration.

[0042] Some embodiments disclosed herein are directed to a method for transmitting data, the method comprising: synchronizing a first circuit configuration with a first clock operating at a certain frequency, the first clock being associated with a first clock domain; determining a second clock based on the first clock, the second clock operating at the frequency of the first clock and further operating with a phase shift relative to the first clock, and being associated with a second clock domain; and synchronizing a second circuit configuration with a second clock, the second circuit configuration receiving data from the first circuit configuration via one or more latches electronically coupled to a data bus. The configuration includes: a data bus comprising one or more wires including a first wire, and one or more latches including a first latch configured to receive data via the first wire; generating a plurality of clock candidates, each of which is configured to operate at the frequency of the first clock and further configured to operate with a respective phase shift relative to the first clock; synchronizing the first latch with a third clock selected from the plurality of clock candidates; and transmitting data from a first circuit configuration to a second circuit configuration via the data bus and the first latch. In addition to or instead of one or more of the embodiments disclosed herein, in some embodiments, the third clock is selected from the plurality of clock candidates based on the latency between the first circuit configuration transmitting data and the first latch receiving data. In addition to or instead of one or more embodiments disclosed herein, in some embodiments, each of one or more latches is configured to correspond to each of one or more wires and to receive data through each wire, and the method further comprises, for each of the one or more latches, selecting a clock from a plurality of clock candidates based on the latency between the latch and a first circuit configuration that transmits data, and synchronizing the latch to its respective clock.

[0043] While the disclosed embodiments are described in full with reference to the accompanying drawings, it should be noted that various modifications and improvements will be obvious to those skilled in the art. For example, elements in one or more implementations may be combined, removed, improved, or added to form further implementations. Such modifications and improvements will be understood to fall within the scope of the disclosed embodiments as defined by the appended claims.

Claims

1. An electronic device, The aforementioned electronic device comprises a circuit configuration, The aforementioned circuit configuration is, Receiving a first clock signal, wherein the first clock signal has a first frequency, Receiving a second clock signal having the first frequency and a first phase shift with respect to the first clock signal, Receiving a third clock signal having the first frequency and a second phase shift with respect to the first clock signal, The process involves selecting a clock signal candidate from a plurality of clock signal candidates, wherein the plurality of clock signal candidates include candidates associated with each of the second clock signal and the third clock signal. It is configured to do the following: The circuit configuration is configured to select the associated clock signal candidate for the second clock signal from the plurality of clock signal candidates by performing an operation, the operation including comparing the first phase shift with the timing of the clock cycle of the first clock signal for a data bit among a plurality of data bits. The circuit configuration is configured to select the associated clock signal candidate for the third clock signal from the plurality of clock signal candidates by performing an operation, the operation comprising comparing the second phase shift with the timing of the clock cycle of the first clock signal for another data bit among the plurality of data bits.

2. The electronic device according to claim 1, wherein each of the plurality of clock signal candidates has a frequency equal to the first frequency of the first clock signal.

3. The electronic device according to claim 1, wherein the second phase shift is 180 degrees.

4. The electronic device according to claim 1, wherein the circuit configuration is further configured to synchronize with the first clock signal.

5. Comparing the first phase shift with the timing of the clock cycle of the first clock signal with respect to the data bit among the plurality of data bits includes comparing the first phase shift with the transition edge of the clock cycle, The electronic device according to claim 1, wherein comparing the second phase shift with the timing of the clock cycle of the first clock signal with respect to another data bit among the plurality of data bits includes comparing the second phase shift with the transition edge of the clock cycle.

6. The electronic device comprises a reference clock, The electronic device according to claim 1, wherein the first clock signal, the second clock signal, and the third clock signal are generated from signals provided by the reference clock.

7. The electronic device further comprises a memory, The electronic device is configured to perform a data write operation in the memory, and the data write operation is synchronized with the first clock signal. The electronic device according to claim 1, further configured to perform a data read operation in the memory, wherein the data read operation is synchronized with the second clock signal.

8. The electronic device is The second circuit configuration of the aforementioned electronic device, The data bus electronically coupled to the first circuit configuration and the second circuit configuration Furthermore, The electronic device according to claim 1, wherein the first circuit configuration is further configured to transmit data to the second circuit configuration via the data bus, and the second circuit configuration is configured to synchronize with the second clock signal.

9. The electronic device comprises one or more latches, Each of the one or more latches mentioned above is Receiving data from the aforementioned circuit configuration, Based on the latency between the latch and the circuit configuration, each clock signal selected from the plurality of clock signal candidates is synchronized. The electronic device according to claim 1, configured to perform the following:

10. The first clock signal is associated with the first part of the circuit configuration, The aforementioned second clock signal is associated with the second part of the circuit configuration, The third clock signal is associated with the third part of the circuit configuration, The first part of the circuit configuration differs from the second part of the circuit configuration, and further differs from the third part of the circuit configuration, The electronic device according to claim 1, wherein the second part of the circuit configuration is different from the third part of the circuit configuration.

11. A method, wherein the method is In an electronic device, the receiving of a first clock signal, wherein the first clock signal has a first frequency, The electronic device receives a second clock signal having the first frequency and a first phase shift with respect to the first clock signal. The electronic device receives a third clock signal having the first frequency and a second phase shift with respect to the first clock signal. In the aforementioned electronic device, a clock signal candidate is selected from a plurality of clock signal candidates, wherein the plurality of clock signal candidates include candidates associated with each of the second clock signal and the third clock signal. Includes, The electronic device is configured to select the associated clock signal candidate for the second clock signal from the plurality of clock signal candidates by performing an operation, the operation including comparing the first phase shift with the timing of the clock cycle of the first clock signal for a data bit among a plurality of data bits. The electronic device is configured to select the associated clock signal candidate for the third clock signal from the plurality of clock signal candidates by performing an operation, the operation comprising comparing the second phase shift with the timing of the clock cycle of the first clock signal for another data bit among the plurality of data bits.

12. The method according to claim 11, wherein each of the plurality of clock signal candidates has a frequency equal to the first frequency of the first clock signal.

13. The method according to claim 11, wherein the second phase shift is 180 degrees.

14. The method according to claim 11, further comprising synchronizing the circuit configuration of the electronic device with the first clock signal.

15. The electronic device comprises a reference clock, The method according to claim 11, wherein the first clock signal, the second clock signal, and the third clock signal are generated from signals provided by the reference clock.

16. The method according to claim 11, wherein one or more of the respective clock signal candidates are selected to reduce noise in the electronic device associated with transistor resonance.

17. The method described above is: The operation involves performing a data write operation within the memory of the electronic device, wherein the data write operation is synchronized with the first clock signal. The operation involves performing a data read operation within the memory, wherein the data read operation is synchronized with the second clock signal. The method according to claim 11, further comprising:

18. The method described above is: Receiving data via a latch, Based on the latency between the latch and the circuit configuration of the electronic device, each clock signal selected from the plurality of clock signal candidates is synchronized. The method according to claim 11, further comprising:

19. The first clock signal is associated with a first part of the circuit configuration of the electronic device, The aforementioned second clock signal is associated with the second part of the circuit configuration, The third clock signal is associated with the third part of the circuit configuration, The first part of the circuit configuration differs from the second part of the circuit configuration, and further differs from the third part of the circuit configuration, The method according to claim 11, wherein the second part of the circuit configuration is different from the third part of the circuit configuration.

20. A non-transient computer-readable medium storing instructions, When the instruction is executed by one or more processors, it causes the one or more processors to perform the method, The aforementioned method, In an electronic device, the receiving of a first clock signal, wherein the first clock signal has a first frequency, The electronic device receives a second clock signal having the first frequency and a first phase shift with respect to the first clock signal. The electronic device receives a third clock signal having the first frequency and a second phase shift with respect to the first clock signal. In the aforementioned electronic device, a clock signal candidate is selected from a plurality of clock signal candidates, wherein the plurality of clock signal candidates include candidates associated with each of the second clock signal and the third clock signal. Includes, The electronic device is configured to select the associated clock signal candidate for the second clock signal from the plurality of clock signal candidates by performing an operation, the operation including comparing the first phase shift with the timing of the clock cycle of the first clock signal for a data bit among a plurality of data bits. The electronic device is configured to select the associated clock signal candidate for the third clock signal from a plurality of clock signal candidates by performing an operation, the operation comprising comparing the second phase shift with the timing of the clock cycle of the first clock signal for another data bit among the plurality of data bits, in a non-transient, computer-readable medium.

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