Image sensor

Abstract

Autonomous exposure control within the image sensor. [Solution] The image sensor comprises a first semiconductor substrate in which a pixel section includes a first output section and a second output section having first and second photoelectric conversion sections arranged in a row direction that convert light into electric charge, first and second transfer sections that transfer the converted electric charge, first and second storage sections that store the transferred electric charge, and first and second selection sections that are electrically connected to the first and second signal lines in order to output first and second signals based on each stored electric charge to the first and second signal lines; and a second semiconductor substrate laminated thereon, which has first and second exposure processing sections that calculate first and second evaluation values ​​related to the charge storage time using the signal, first and second pixel driving sections that output first and second transfer control signals to each transfer control line for individually controlling each transfer section based on each evaluation value, and a driving section that outputs a selection control signal for controlling the first and second selection sections via a common selection control line.

Description

Incorporation by Reference

[0001] This application claims the priority of Japanese Patent Application No. 2021-137343, filed on August 25, 2021, and incorporates its content by reference into this application.

Technical Field

[0002] The present invention relates to an imaging device and an imaging apparatus.

Background Art

[0003] Solid-state imaging devices including a plurality of pixel cells are known (for example, Patent Document 1). Conventionally, an expansion of the dynamic range has been demanded.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

[0005] The image sensor of the first disclosed technology includes a first semiconductor substrate having a pixel section that includes: a first photoelectric conversion unit for converting light into electric charge; a second photoelectric conversion unit for converting light into electric charge, which is arranged alongside the first photoelectric conversion unit in the row direction; a first transfer unit for transferring the charge converted by the first photoelectric conversion unit; a second transfer unit for transferring the charge converted by the second photoelectric conversion unit; a first storage unit for storing the charge transferred from the first photoelectric conversion unit by the first transfer unit; a second storage unit for storing the charge transferred from the second photoelectric conversion unit by the second transfer unit; a first output unit for outputting a first signal based on the charge transferred to the first storage unit to a first signal line, which has a first selection unit electrically connected to the first signal line; and a second output unit for outputting a second signal based on the charge transferred to the second storage unit to a second signal line, which has a second selection unit electrically connected to the second signal line; and a semiconductor substrate laminated with the first semiconductor substrate. The second semiconductor substrate comprises: a first exposure processing unit that uses the first signal to calculate a first evaluation value relating to the storage time for storing the charge converted by the first photoelectric conversion unit; a second exposure processing unit that uses the second signal to calculate a second evaluation value relating to the storage time for storing the charge converted by the second photoelectric conversion unit; a first pixel driving unit that outputs a first transfer control signal for controlling the first transfer unit based on the first evaluation value; a second pixel driving unit that outputs a second transfer control signal for controlling the second transfer unit based on the second evaluation value; and a driving unit that outputs a selection control signal for controlling the first selection unit and the second selection unit. The first transfer unit is electrically connected to a first transfer control line on which the first transfer control signal is output, the second transfer unit is electrically connected to a second transfer control line on which the second transfer control signal is output, and the first selection unit and the second selection unit are electrically connected to a selection control line on which the selection control signal is output.

[0006] The imaging device of the second disclosed technology is equipped with an image sensor of the first disclosed technology. [Brief explanation of the drawing]

[0007] [Figure 1] Figure 1 is an exploded perspective view showing an example of an image sensor. [Figure 2] Figure 2 is an explanatory diagram showing an example of a specific configuration of the pixel section. [Figure 3] Figure 3 is a circuit diagram showing an example of a pixel circuit configuration. [Figure 4] Figure 4 is an explanatory diagram showing an example of a specific configuration of the control circuit section. [Figure 5] Figure 5 is an explanatory diagram showing an example of the internal configuration of a control block. [Figure 6] Figure 6 is an explanatory diagram showing an example of signal transmission between the first semiconductor substrate and the second semiconductor substrate in an image sensor. [Figure 7] Figure 7 is an explanatory diagram showing an example of a cross-sectional view in the XZ direction of the image sensor according to this embodiment. [Figure 8] Figure 8 is a timing chart showing example 1 of the imaging operation of the image sensor. [Figure 9] Figure 9 is a timing chart showing example 2 of the image sensor's imaging operation. [Figure 10] Figure 10 is a timing chart showing the imaging operation of the image sensor in the comparative example. [Figure 11] Figure 11 is an explanatory diagram showing an example of a subject captured by the image sensor. [Figure 12] Figure 12 is a timing chart showing the exposure times for each region 1 to 5 shown in Figure 11. [Figure 13] Figure 13 is a plan view showing an example layout of multiple control blocks. [Figure 14] Figure 14 is a circuit diagram showing another example of a pixel circuit configuration. [Figure 15] Figure 15 is a timing chart showing example 3 of the imaging operation of the image sensor. [Figure 16] Figure 16 is an exploded perspective view showing another example of an image sensor. [Figure 17] Figure 17 is an explanatory diagram showing another example of the specific configuration of the control circuit section. [Figure 18] Figure 18 is an explanatory diagram showing the connection relationship between the first semiconductor substrate and the second semiconductor substrate in the image sensor. [Figure 19] FIG. 19 is an explanatory diagram showing an example of signal transmission between a first semiconductor substrate and a second semiconductor substrate in an image sensor. [Figure 20] FIG. 20 is an explanatory diagram showing the connection relationship between an ADC unit and pixel blocks. [Figure 21] FIG. 21 is a timing chart showing an imaging operation within a pixel block of an image sensor. [Figure 22] FIG. 22 is an explanatory diagram showing an example of exposure timing for each pixel block. [Figure 23] FIG. 23 is a block diagram showing a configuration example of the self - exposure control method 1. [Figure 24] FIG. 24 is a block diagram showing a configuration example of the self - exposure control method 2. [Figure 25] FIG. 25 is a block diagram showing a configuration example of the self - exposure control method 3. [Figure 26] FIG. 26 is a block diagram showing a layout example when a self - exposure processing unit is implemented in adjacent control blocks. [Figure 27] FIG. 27 is a block diagram showing a layout example when a self - exposure processing unit is implemented in a peripheral circuit. [Figure 28] FIG. 28 is a block diagram showing a detailed internal configuration of the peripheral circuit part shown in FIG. 27. [Figure 29] FIG. 29 is an explanatory diagram showing a delay example of the reflection period of the exposure time. [Figure 30] FIG. 30 is an explanatory diagram showing a first example of shortening the reflection period of the exposure time. [Figure 31] FIG. 31 is an explanatory diagram showing a second example of shortening the reflection period of the exposure time. [Figure 32] FIG. 32 is a timing chart 1 - 1 when an exposure time change occurs. [Figure 33] FIG. 33 is a timing chart 1 - 2 when an exposure time change occurs. [Figure 34] FIG. 34 is a timing chart 2 - 1 when an exposure time change occurs. [Figure 35]Figure 35 shows timing chart 2-2 when exposure time changes occur. [Figure 36] Figure 36 is a timing chart 3-1 for when exposure time changes occur. [Figure 37] Figure 37 shows the timing chart 3-2 when the exposure time is changed. [Figure 38] Figure 38 shows the timing chart 3-3 when the exposure time is changed. [Figure 39] Figure 39 is an explanatory diagram showing method 1 for reading the exposure value outside the second semiconductor substrate. [Figure 40] Figure 40 is an explanatory diagram showing method 2 for reading the exposure value outside the second semiconductor substrate. [Figure 41] Figure 41 is a block diagram showing an example 1 of speeding up autonomous exposure control within the control block. [Figure 42] Figure 42 is an explanatory diagram showing an example of a counter latch in Example 1 of speeding up autonomous exposure control within the control block. [Figure 43] Figure 43 is an explanatory diagram showing a specific example of autonomous exposure control in Example 1 of speeding up autonomous exposure control within the control block. [Figure 44] Figure 44 is an explanatory diagram showing an example of a counter latch in Example 2 of speeding up autonomous exposure control within the control block. [Figure 45] Figure 45 is an explanatory diagram showing a specific example of autonomous exposure control in Example 2 of speeding up autonomous exposure control within the control block. [Figure 46] Figure 46 is a block diagram showing example 3 of speeding up autonomous exposure control within the control block. [Figure 47] Figure 47 is a circuit diagram showing an example of a comparator. [Figure 48] Figure 48 is an explanatory diagram showing an example of exposure control 1 by switching exposure values ​​inside and outside the control block. [Figure 49] Figure 49 is an explanatory diagram showing an example of exposure control 2 by switching exposure values ​​inside and outside the control block. [Figure 50]Figure 50 is an explanatory diagram showing an example of exposure control 3 by switching exposure values ​​inside and outside the control block. [Figure 51] Figure 51 is an explanatory diagram showing an example of reading exposure values ​​for each control block. [Figure 52] Figure 52 is an explanatory diagram showing an example of reading exposure values ​​for each control block (Example 2). [Figure 53] Figure 53 is a block diagram showing a detailed block configuration example of the control block in Example 2 of reading exposure values ​​for each control block. [Figure 54] Figure 54 is a block diagram showing an example of the internal configuration of the pre-processing unit in color shift reduction example 1. [Figure 55] Figure 55 is an explanatory diagram showing an example of pixel blocking in color shift reduction example 2. [Figure 56] Figure 56 is a block diagram showing an example of the internal configuration of the pre-processing unit in color shift reduction example 3. [Figure 57] Figure 57 is a block diagram showing an example of the internal configuration of the image sensor in color shift reduction example 4. [Figure 58] Figure 58 is a circuit diagram showing an example of defect analysis of bonding pads between semiconductor substrates in a pixel drive signal line. [Figure 59] Figure 59 is a circuit diagram showing example 1 of defect analysis of bonding pads between semiconductor substrates in a vertical signal line. [Figure 60] Figure 60 is a circuit diagram showing example 2-1 of defect analysis of bonding pads between semiconductor substrates in a vertical signal line. [Figure 61] Figure 61 is a circuit diagram showing example 2-2 of failure analysis of bonding pads between semiconductor substrates in vertical signal 2. [Figure 62] Figure 62 is a circuit diagram showing an example of failure analysis of bonding pads between semiconductor substrates when signal paths are shared among multiple circuits. [Figure 63] Figure 63 is a circuit diagram showing an example of settings after failure analysis of bonding pads between semiconductor substrates when signal paths are shared between multiple circuits. [Figure 64]Figure 64 is a circuit diagram showing example 1 of failure analysis of bonding pads between semiconductor substrates when multiple circuits share a junction. [Figure 65] Figure 65 is a circuit diagram showing example 2 of failure analysis of bonding pads between semiconductor substrates when multiple circuits share a junction. [Figure 66] Figure 66 is a block diagram showing an example of the configuration of an imaging device according to an embodiment. [Modes for carrying out the invention]

[0008] The present invention will be described below through embodiments, but these embodiments are not intended to limit the scope of the claims. Furthermore, not all combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0009] In this specification, the X and Y axes are orthogonal to each other, and the Z axis is orthogonal to the XY plane. The XYZ axes constitute a right-handed system. The direction parallel to the Z axis may be referred to as the stacking direction of the image sensor 100. In this specification, the terms "up" and "down" are not limited to the up and down directions in the direction of gravity. These terms merely refer to relative directions in the Z axis direction. In this specification, the arrangement in the X axis direction is described as a "row," and the arrangement in the Y axis direction is described as a "column," but the matrix direction is not limited to these.

[0010] <Image sensor configuration> First, the configuration of the image sensor will be explained using Figures 1 to 22. The structure of the image sensor may be either back-illuminated or front-illuminated.

[0011] Figure 1 is an exploded perspective view showing an example of an image sensor 100A. The image sensor 100A captures an image of a subject. The image sensor 100A generates image data of the captured subject. The image sensor 100A comprises a first semiconductor substrate 110, a second semiconductor substrate 120, and a third semiconductor substrate 130. As shown in Figure 1, the first semiconductor substrate 110 is laminated on the second semiconductor substrate 120, and the second semiconductor substrate 120 is laminated on the third semiconductor substrate 130.

[0012] The first semiconductor substrate 110 has a pixel section 101. The pixel section 101 outputs a pixel signal based on incident light.

[0013] The second semiconductor substrate 120 has a control circuit section 102 and a peripheral circuit section 121.

[0014] The control circuit unit 102 receives the pixel signal output from the first semiconductor substrate 110. The control circuit unit 102 processes the input pixel signal. The control circuit unit 102 is positioned on the second semiconductor substrate 120 opposite to the pixel unit 101. For example, the control circuit unit 102 is positioned so as to overlap with the pixel unit 101 in the direction in which the first semiconductor substrate 110 and the second semiconductor substrate 120 are stacked. The control circuit unit 102 may output a control signal to the pixel unit 101 to control the driving of the pixel unit 101.

[0015] The peripheral circuit section 121 controls the driving of the control circuit section 102. The peripheral circuit section 121 is arranged on the second semiconductor substrate 120 around the control circuit section 102. Specifically, the peripheral circuit section 121 is arranged on the second semiconductor substrate 120 in an area outside the area where the control circuit section 102 is arranged. The peripheral circuit section 121 may also be electrically connected to the first semiconductor substrate 110 and control the driving of the pixel section 101. The peripheral circuit section 121 is arranged along two sides of the second semiconductor substrate 120, but the arrangement of the peripheral circuit section 121 is not limited to this example.

[0016] The third semiconductor substrate 130 has a data processing unit 103. The data processing unit 103 performs addition, decimation, and other image processing using the digital data output from the second semiconductor substrate 120.

[0017] Figure 2 is an explanatory diagram showing an example of a specific configuration of the pixel section 101. The pixel section 101 has a plurality of pixel blocks 200. The plurality of pixel blocks 200 are arranged in the row and column directions in the pixel section 101. Specifically, the plurality of pixel blocks 200 have M × N (M,N are natural numbers) pixel blocks 200 arranged in the row and column directions in the pixel section 101. The case where M is equal to N is shown, but M and N may be different.

[0018] A pixel block 200 has multiple pixels 201. These multiple pixels 201 are arranged in rows and columns within the pixel block 200. The pixel block 200 has m × n pixels 201 (where m and n are natural numbers) arranged in rows and columns. For example, a pixel block 200 has 16 × 16 pixels 201 arranged in rows and columns. The number of pixels 201 corresponding to a pixel block 200 is not limited to this. The diagram shows the case where m is equal to n, but m may be different from n.

[0019] The pixel block 200 has a plurality of pixels 201 connected in the row direction to a common control line (for example, a transfer control line 311 and an output control line 312, described later). For example, each pixel 201 of the pixel block 200 is connected to the common control line so that it is set to the same exposure time. Specifically, for example, every n pixels 201 arranged in the row direction are connected by the common control line.

[0020] On the other hand, between different pixel blocks 200, one pixel block 200 may be set to have a different exposure time than the other pixel block 200. For example, if one pixel block 200 and the other pixel block 200 are arranged in a row, the multiple pixels 201 of one pixel block 200 and the multiple pixels 201 of the other pixel block 200 are connected by different control lines. The multiple pixels 201 of the mth row of one pixel block 200 are commonly connected by a control line different from the common control line to which the multiple pixels 201 of the mth row of the other pixel block 200 are connected. Also, if one pixel block 200 and the other pixel block 200 are arranged in a column, the multiple pixels 201 of one pixel block 200 and the multiple pixels 201 of the other pixel block 200 are connected by different control lines. Multiple pixels 201 in the mth row of one pixel block 200 are connected in common by a control line that is different from the common control line to which multiple pixels 201 in the mth row of the other pixel block 200 are connected.

[0021] Furthermore, for example, if one pixel block 200 and the other pixel block 200 are arranged side by side in the row direction, the multiple pixels 201 of one pixel block 200 and the multiple pixels 201 of the other pixel block 200 are connected by different signal lines 202. The multiple pixels 201 in the nth column of one pixel block 200 are commonly connected by a signal line 202 that is different from the common signal line 202 to which the multiple pixels 201 in the nth column of the other pixel block 200 are connected.

[0022] The pixel block 200 is arranged in correspondence with the control blocks 400A and 400B (see Figures 4 and 17), which will be described later. That is, one pixel block 200 is arranged for each control block 400A and 400B.

[0023] Furthermore, multiple pixel blocks 200 may be arranged for a single control block 400A, 400B. Even when multiple pixel blocks 200 are arranged for a single control block 400A, 400B, each pixel block 200 may be set to a different exposure time. When two pixel blocks 200 arranged in a column direction are arranged for a single control block, control blocks 400A, 400B control 2m × n pixels 201. Specifically, for example, control blocks 400A, 400B control 32 × 16 pixels 201. The number of pixels 201 corresponding to control blocks 400A, 400B is not limited to this.

[0024] Figure 3 is a circuit diagram showing an example of the circuit configuration of a pixel 201. The pixel 201 comprises a photoelectric conversion unit 300 and a readout unit 310. The readout unit 310 has a transfer unit 301, an output unit 302, an FD (floating diffusion) 303, a reset unit 304, and a pixel output unit 305, and reads out the pixel signal based on the charge converted by the photoelectric conversion unit 300 to the signal line 202. The pixel output unit 305 has an amplification unit 351 and a selection unit 352. The transfer unit 301, output unit 302, FD 303, reset unit 304, amplification unit 351, and selection unit 352 are referred to as the readout unit 310. The readout unit 310 is described as an N-channel FET, but the type of transistor is not limited to this.

[0025] The photoelectric conversion unit 300 has a photoelectric conversion function that converts light into electric charge. The photoelectric conversion unit 300 stores the photoelectrically converted charge. The photoelectric conversion unit 300 is composed of, for example, a photodiode.

[0026] The transfer unit 301 transfers the charge from the photoelectric conversion unit 300 to the FD303. The transfer unit 301 controls the electrical connection between the photoelectric conversion unit 300 and the FD303. The transfer unit 301 is composed of, for example, a transistor. Alternatively, the transfer unit 301 may be an element that has at least a gate terminal and constitutes part of a transistor with a portion of the photoelectric conversion unit 300 as the source terminal and a portion of the FD303 as the drain terminal. The gate terminal of the transfer unit 301 is connected to a transfer control line 311 for inputting a transfer control signal φTX. The transfer control line 311 will be described later.

[0027] The discharge unit 302 discharges the charge accumulated in the photoelectric conversion unit 300 to the power supply wiring supplied with the power supply voltage VDD. The discharge unit 302 controls the connection between the photoelectric conversion unit 300 and the power supply wiring. The discharge unit 302 is composed of, for example, a transistor. Alternatively, the discharge unit 302 may be an element that constitutes part of a transistor having at least a gate terminal, with a portion of the photoelectric conversion unit 300 as the source terminal and a portion of the diffusion region connected to the power supply wiring as the drain terminal. The gate terminal of the discharge unit 302 is connected to the discharge control line 312 for inputting the discharge control signal φPDRST. Although the discharge unit 302 has been described as discharging the charge of the photoelectric conversion unit 300 to the power supply wiring supplied with the power supply voltage VDD, it may also discharge to a power supply wiring supplied with a power supply voltage different from the power supply voltage VDD.

[0028] FD303 receives charge from the photoelectric conversion unit 300 via the transfer unit 301. FD303 stores the charge transferred from the photoelectric conversion unit 300.

[0029] The reset unit 304 discharges the charge accumulated in the FD303 to the power supply wiring to which the power supply voltage VDD is supplied. The reset unit 304 resets the potential of the FD303 to the power supply voltage VDD, which is the reference potential. The reset unit 304 controls the electrical connection between the FD303 and the power supply wiring. The reset unit 304 is composed of, for example, a transistor. Alternatively, the reset unit 304 may be an element that constitutes part of a transistor having at least a gate terminal, with a portion of the FD303 as the source terminal and a portion of the diffusion region connected to the power supply wiring as the drain terminal. The gate terminal of the reset unit 304 is connected to a reset control line 313 for inputting a reset control signal φRST. The reset control line 313 will be described later.

[0030] The pixel output unit 305 outputs a pixel signal based on the potential of FD303 to the signal line 202. The pixel output unit 305 includes an amplification unit 351 and a selection unit 352. The amplification unit 351 is composed of transistors. The gate terminal of the amplification unit 351 is connected to FD303, the drain terminal is connected to the power supply wiring to which the power supply voltage VDD is supplied, and the source terminal is connected to the drain terminal of the selection unit 352.

[0031] The selection unit 352 controls the electrical connection between the pixel 201 and the signal line 202. When the selection unit 352 electrically connects the pixel 201 and the signal line 202, a pixel signal is output from the pixel 201 to the signal line 202. The selection unit 352 is composed of a transistor. Alternatively, the selection unit 352 may be an element that constitutes part of a transistor having at least a gate terminal, with a portion of the amplification unit 351 as the source terminal and a portion of the diffusion region connected to the signal line 202 as the drain terminal. The gate terminal of the selection unit 352 is connected to a selection control line 314 that spans multiple pixel blocks 200 for inputting a selection control signal φSEL. The source terminal of the selection unit 352 is connected to a load current source 306.

[0032] The load current source 306 is connected to the signal line 202 and supplies current for reading the pixel signal from the pixel 201. This stabilizes the operation of the amplification unit 351. The load current source 306 is also connected to the signal line 202. The load current source 306 may be provided on the first semiconductor substrate 110 or on the second semiconductor substrate 120.

[0033] Furthermore, the FD303 and pixel output unit 305 may be shared with other pixels 201. For example, the FD303 and pixel output unit 305 may be shared among multiple pixels 201 arranged in rows or columns. Also, a pixel 201 may be composed of multiple photoelectric conversion units 300 and transfer units 301.

[0034] Figure 4 is an explanatory diagram showing an example of a specific configuration of the control circuit unit 102. The control circuit unit 102 has a plurality of control blocks 400A. The plurality of control blocks 400A are arranged in the row direction and column direction in the control circuit unit 102. Specifically, the control circuit unit 102 has M × N control blocks 400A. When one pixel block 200 is arranged for one control block 400A, the control circuit unit 102 has a control block 400A directly below the pixel block 200. One pixel block 200 and one control block 400A are approximately the same shape and size. Also, when a plurality of pixel blocks 200 arranged in the column direction are arranged for one control block 400A, the control circuit unit 102 has one control block 400A directly below the plurality of pixel blocks 200 arranged in the column direction.

[0035] The control block 400A is provided in correspondence with the pixel block 200. As an example of the correspondence between the control block and the pixel block, for example, the control block 400A is located directly below the pixel block 200 in the direction in which the first semiconductor substrate 110 and the second semiconductor substrate 120 are stacked (stacking direction). The control block 400A is also electrically connected to the pixel block 200 by signal lines 202, transfer control lines 311 and ejection control lines 312. Specifically, the control block 400A, located directly below the pixel block 200 in the stacking direction, is electrically connected to the pixel block 200 directly above it in the stacking direction (hereinafter, the corresponding pixel block 200) by local control lines such as the transfer control line 311 and the ejection control line 312. The control block 400A also receives the pixel signal output from the pixel 201 of the corresponding pixel block 200 via the signal line 202.

[0036] The control block 400A controls the driving of the corresponding pixel block 200. For example, the control block 400A controls the exposure time of the pixel 201 included in the corresponding pixel block 200. The control block 400A also has a signal processing unit 402 that processes input signals and processes the pixel signals output from the pixel 201 included in the corresponding pixel block 200. For example, the control block 400A converts the analog pixel signal output from the pixel 201 included in the corresponding pixel block 200 into a digital signal.

[0037] The control block 400A includes a pixel control unit 401 and a signal processing unit 402. The pixel control unit 401 includes an autonomous exposure processing unit 411, an exposure control unit 412, and a pixel driving unit 413, and controls the pixels 201 of the pixel unit 101. The signal processing unit 402 includes a signal input unit 421, a signal conversion unit 422, and a signal output unit 423, and converts the analog pixel signals from the pixel unit 101 into digital signals and transfers them to the pixel control unit 401 and the data processing unit 103.

[0038] The autonomous exposure processing unit 411 is a circuit that calculates the exposure time of a pixel 201 included in the corresponding pixel block 200 based on the pixel signal converted into a digital signal by the signal processing unit 402. Details of the autonomous exposure processing unit 411 will be described later.

[0039] The exposure control unit 412 is a circuit that controls the exposure of pixels 201 included in the corresponding pixel block 200 based on the exposure time calculated by the autonomous exposure processing unit 411. Specifically, the exposure control unit 412 generates a control signal to control the exposure time (charge storage time of the photoelectric conversion unit 300) of pixels 201 included in the corresponding pixel block 200. For example, the exposure control unit 412 controls the exposure time for each pixel block 200 by adjusting the start or end timing of the exposure of pixels 201 included in the corresponding pixel block 200. The exposure control unit 412 is provided extending in the row direction in the control block 400A.

[0040] The pixel drive unit 413 outputs a control signal generated by the exposure control unit 412 to the pixels 201 included in the corresponding pixel block 200. The pixel drive unit 413 is a drive circuit that drives the pixels 201 included in the corresponding pixel block 200. The pixel drive unit 413 drives the pixels 201 of a selected pixel row from among the pixels 201 included in the corresponding pixel block 200. The pixel drive unit 413 is provided extending in the column direction. As a result, the pixel drive unit 413 is positioned in a location corresponding to m pixels 201 arranged in the column direction. In the control block 400A, the autonomous exposure processing unit 411, exposure control unit 412, and pixel drive unit 413 are arranged in an L-shape, with the pixel drive unit 413 extending in the column direction and the autonomous exposure processing unit 411 and exposure control unit 412 extending in the row direction.

[0041] The signal input unit 421 receives the pixel signal output from the pixel 201 included in the corresponding pixel block 200. The signal input unit 421 outputs the input pixel signal to the signal conversion unit 422. The signal input unit 421 may be provided for every n pixels 201 arranged in the row direction in the corresponding pixel block 200. The signal input unit 421 may have a processing circuit that performs signal processing such as noise reduction on the pixel signal output from the first semiconductor substrate 110. The signal input unit 421 may also have a voltage adjustment circuit that adjusts the voltage of the signal line 202 connected to the pixel 201 included in the corresponding pixel block 200 so that it does not fall below a predetermined value. When the load current source 306 is located on the second semiconductor substrate, it may be located on the signal input unit 421 included in the corresponding control block 400A.

[0042] The signal conversion unit 422 converts the pixel signals output from the signal input unit 421 into digital signals. The signal conversion unit 422 sequentially converts the pixel signals output from m pixels 201 arranged in the column direction in the corresponding pixel block 200 into digital signals. The signal conversion unit 422 converts the pixel signals output from n pixels 201 arranged in the row direction in the corresponding pixel block 200 into digital signals in parallel.

[0043] The signal output unit 423 stores the pixel signals converted to digital signals by the signal conversion unit 422. The signal output unit 423 may have a latch circuit for storing the digital signals. The signal output unit 423 is located in the column direction between the signal conversion unit 422 and the autonomous exposure processing unit 411. The signal output unit 423 outputs the pixel signals converted to digital signals to the outside of the control circuit unit 102. The signal output unit 423 is provided extending in the row direction in the control block 400A. The signal output unit 423 is located in the column direction between the signal conversion unit 422 and the autonomous exposure processing unit 411.

[0044] Figure 5 is an explanatory diagram showing an example of the internal configuration of the control block 400A. The signal conversion unit 422 comprises n comparators 501 and n memory units 502. The exposure control unit 412 comprises a pixel block control unit 503 and a level shift unit 504. One comparator 501 and a memory unit 502 connected to that comparator 501 form one ADC (Analog-to-Digital Converter) 500.

[0045] The comparator 501 is provided in the control block 400A, extending in the column direction. The n comparators 501 are arranged in the row direction. The comparator 501 is provided for every m pixels 201 arranged in the column direction in the corresponding pixel block 200. The comparator 501 sequentially reads the pixel signals of the m pixels 201 arranged in the column direction in the corresponding pixel block 200 and converts them into digital signals.

[0046] The memory unit 502 stores the pixel signals converted into digital signals using the comparator 501. The memory unit 502 is located on the negative side in the Y-axis direction relative to the comparator 501 in the signal conversion unit 422. For example, the memory unit 502 has a latch circuit. The memory unit 502 may have a memory composed of SRAM or the like.

[0047] The pixel block control unit 503 controls the operation of the transfer unit 301 and the ejection unit 302 of the pixel 201 included in the corresponding pixel block 200. Specifically, the pixel block control unit 503 outputs a transfer control signal φTX for controlling the transfer unit 301 of the pixel 201 included in the corresponding pixel block 200, and an ejection control signal φPDRST for controlling the ejection unit 302 of the pixel 201 included in the corresponding pixel block 200. The pixel block control unit 503 is provided extending in the row direction in the control block 400A. The pixel block control unit 503 is positioned between the level shift unit 504 and the autonomous exposure processing unit 411 in the column direction.

[0048] The level shift unit 504 adjusts the voltage level of the control signals output from the pixel block control unit 503. Specifically, the level shift unit 504 increases the voltage level of the transfer control signal φTX output from the pixel block control unit 503. In addition, the level shift unit 504 increases the voltage level of the output control signal φPDRST output from the pixel block control unit 503.

[0049] The transfer unit 301 receives the transfer control signal φTX, which has been boosted by the pixel block control unit 503, via the transfer control line 311. The discharge unit 302 receives the discharge control signal φPDRST, which has been boosted by the pixel block control unit 503, via the discharge control line 312.

[0050] In this manner, the pixel block control unit 503 boosts the transfer control signal φTX and the ejection control signal φPDRST to the voltage levels used in the transfer unit 301 and the ejection unit 302 of the readout unit 310 of the pixel 201. The level shift unit 504 is provided in the control block 400A, extending in the row direction.

[0051] The level shift unit 504 is located on the outer periphery of the control block 400A, further than the pixel block control unit 503. The positive end in the X-axis direction and the negative end in the Y-axis direction of the level shift unit 504 are located on the outermost part of the control block 400A. The negative end in the X-axis direction of the level shift unit 504 is in contact with the pixel drive unit 413.

[0052] The level shift unit 504 and the pixel drive unit 413 handle the signal after level shifting. Meanwhile, the autonomous exposure processing unit 411, the pixel block control unit 503, the level shift unit 504, and the pixel drive unit 413 handle the pixel signal output from the first semiconductor substrate 110.

[0053] Here, each component of the control block 400A is formed in well regions provided on the second semiconductor substrate 120. The well regions are separated according to the voltage level of the signal being handled. The well regions are separated depending on whether the power supply used is a digital power supply or an analog power supply. Furthermore, even when the same analog power supply is used, the signal conversion unit 422 may be separated from regions using other analog power supplies from a noise perspective. Separation of well regions requires well separation regions with intervals according to the manufacturing process rules.

[0054] The control block 400A separates the well regions for forming the level shift section 504 and the pixel drive section 413 from other well regions. For example, by arranging the level shift section 504 and the pixel drive section 413 in an L-shape, the well regions of the level shift section 504 and the pixel drive section 413 can be shared. By sharing the well regions, the well separation region can be omitted, thereby improving layout efficiency.

[0055] The L-shaped pixel control unit 401 forms part of the outer perimeter of the control block 400A. This allows it to share the well area with other adjacent control blocks 400A in the row and column directions.

[0056] Figure 6 is an explanatory diagram showing an example of signal transmission between the first semiconductor substrate 110 and the second semiconductor substrate 120 in the image sensor 100A. The global drive unit 600 is provided in the peripheral circuit section 121, which is arranged on both ends of the control circuit section 102.

[0057] The transfer control line 311a and the ejection control line 312a are each connected to a pixel 201 included in the pixel block 200a. The transfer control line 311a is connected to the gate terminal of the transfer unit 301 of the pixel 201 included in the pixel block 200a, and the ejection control line 312a is connected to the gate terminal of the ejection unit 302 of the pixel 201 included in the pixel block 200a. The transfer control line 311a supplies the transfer control signal φTX output from the control block 400Aa to the transfer unit 301 of the pixel 201 included in the pixel block 200a. The ejection control line 312a supplies the ejection control signal φPDRST output from the control block 400Aa to the ejection unit 302 of the pixel 201 included in the pixel block 200a.

[0058] Similarly, the transfer control line 311b and the ejection control line 312b are connected to the pixels 201 included in the pixel block 200b, respectively. The transfer control line 311b is connected to the gate terminal of the transfer unit 301 of the pixel 201 included in the pixel block 200b, and the ejection control line 312b is connected to the gate terminal of the ejection unit 302 of the pixel 201 included in the pixel block 200b. The transfer control line 311b supplies the transfer control signal φTX output from the control block 400Ab to the transfer unit 301 of the pixel 201 included in the pixel block 200b. The ejection control line 312b supplies the ejection control signal φPDRST output from the control block 400Ab to the ejection unit 302 of the pixel 201 included in the pixel block 200b.

[0059] If transfer control lines 311a and 311b are not distinguished, they shall be referred to as transfer control line 311. If discharge control lines 312a and 312b are not distinguished, they shall be referred to as discharge control line 312.

[0060] The transfer control line 311 and the ejection control line 312 are examples of local control lines connected to the first pixel of the pixel block 200. The transfer control line 311 and the ejection control line 312 are commonly connected to n pixels 201 arranged in the row direction within the pixel block 200.

[0061] The global drive unit 600 outputs a reset control signal φRST, a selection control signal φSEL, and a transfer selection control signal φTXSEL. The global drive unit 600 is connected to the reset control line 313, the selection control line 314, and the transfer selection control line 603, which output control signals to each pixel block 200.

[0062] The global drive unit 600 supplies a reset control signal φRST and a selection control signal φSEL to a plurality of pixel blocks 200 via a reset control line 313 and a selection control line 314. The global drive unit 600 also supplies a transfer selection control signal φTXSEL to a plurality of control blocks 400A via a transfer selection control line 603.

[0063] The transfer selection control signal φTXSEL is supplied from the global drive unit 600 to the control block 400A to control the exposure time for each pixel block 200. The control block 400A, upon receiving the transfer selection control signal φTXSEL, outputs the transfer selection control signal φTXSEL to the corresponding pixel block 200. The control block 400A then decides whether or not to input the transfer selection control signal φTXSEL to the pixel 201 as either the transfer control signal φTX or the ejection control signal φPDRST. As a result, the input of either the transfer control signal φTX or the ejection control signal φPDRST to the pixel 201 is skipped.

[0064] For example, if the transfer control signal φTX determines the end time of exposure, control block 400A can extend the exposure time by skipping the transfer control signal φTX. Conversely, if the transfer control signal φTX determines the start time of exposure, control block 400A can shorten the exposure time by skipping the transfer control signal φTX. In this way, the exposure time of pixel block 200 can be adjusted by the transfer selection control signal φTXSEL. The same applies when the ejection control signal φPDRST determines the start or end time of exposure.

[0065] The reset control line 313, the selection control line 314, and the transfer selection control line 603 are provided in common to multiple pixel blocks 200. The reset control line 313, the selection control line 314, and the transfer selection control line 603 are routed to traverse the first semiconductor substrate 110 in the row direction. The reset control line 313, the selection control line 314, and the transfer selection control line 603 may also be routed to traverse the first semiconductor substrate 110 in the column direction.

[0066] For example, the reset control line 313 is connected to the gate terminal of the reset unit 304 of the pixel 201 in the pixel block 200 and supplies a reset control signal φRST. The selection control line 314 is connected to the gate terminal of the selection unit 352 of the pixel 201 in the pixel block 200 and supplies a selection control signal φSEL. The transfer selection control line 603 is connected to each of the multiple control blocks 400A and supplies a transfer selection control signal φTXSEL to the pixel control unit 401.

[0067] The global drive unit 600 outputs the transfer selection control signal φTXSEL from the second semiconductor substrate 120 to the control block 400A via the first semiconductor substrate 110. However, the transfer selection control signal φTXSEL may be output to the control block 400A without going through the first semiconductor substrate 110. In this case, the transfer selection control line 603 is provided on the second semiconductor substrate 120.

[0068] The joint portion 610 is provided on the bonding surface where the first semiconductor substrate 110 and the second semiconductor substrate 120 are joined to each other. The joint portion 610 aligns the transfer control line 311, the discharge control line 312, and the transfer selection control line 603 between the first semiconductor substrate 110 and the second semiconductor substrate 120. Each of the joint portions 610 is composed of a pair of conductive bonding pads and is bonded to the first semiconductor substrate 110 and the second semiconductor substrate 120 by pressurization or the like, thereby electrically connecting them.

[0069] The image sensor 100A controls the exposure time for each pixel block 200 by changing the timing of at least one of the transfer unit 301 and the ejection unit 302 using local control lines such as the transfer control line 311 and the ejection control line 312. The image sensor 100A can achieve exposure time control with fewer control lines by combining local control lines such as the transfer control line 311 and the ejection control line 312 with global control lines such as the reset control line 313, the selection control line 314, and the transfer selection control line 603.

[0070] Figure 7 is an explanatory diagram showing an example of a cross-section in the XZ direction of the image sensor 100A according to this embodiment. Although Figure 7 shows a back-illuminated image sensor 100A, the image sensor 100A is not limited to a back-illuminated type. The image sensor 100A comprises a microlens layer 700, a color filter layer 702, a first semiconductor substrate 110, a second semiconductor substrate 120, and a third semiconductor substrate 130. As shown in the figure, light from the subject is incident in the direction indicated by the white arrow (negative Z-axis direction in the figure). The side of the first semiconductor substrate 110 from which light is incident (positive Z-axis side in the figure) is sometimes referred to as the front surface, and the opposite side (negative Z-axis side in the figure) is sometimes referred to as the back surface.

[0071] The microlens layer 700 has a plurality of microlenses 701. The plurality of microlenses 701 are stacked on the positive Z-axis side of the color filter layer 702. Light is incident on the microlenses 701. The microlenses 701 focus the incident light onto the photoelectric conversion unit 300. A microlens 701 may be provided for each photoelectric conversion unit 300. The optical axis L of the microlenses 701 is in the stacking direction (parallel to the Z-axis) of the first semiconductor substrate 110, the second semiconductor substrate 120, and the third semiconductor substrate 130.

[0072] The color filter layer 702 comprises a plurality of color filters 703 and a passivation film 704. The color filter layer 702 is stacked on the positive Z-axis side of the first semiconductor layer 711. The color filters 703 are optical filters that transmit light in a specific wavelength range. The color filters 703 are optical filters that have specific spectral characteristics. The plurality of color filters 703 consist of multiple optical filters with different spectral characteristics and transmit light in different wavelength ranges from each other. The plurality of color filters 703 are arranged in a specific arrangement (for example, a Bayer arrangement).

[0073] An example of the first semiconductor substrate 110 is a back-illuminated CMOS image sensor. The first semiconductor substrate 110 has a first semiconductor layer 711 and a first wiring layer 712. The first semiconductor layer 711 is located on the positive Z-axis side of the first wiring layer 712. The first semiconductor layer 711 has a plurality of pixel blocks 200 arranged two-dimensionally in the row direction and column direction. The first semiconductor layer 711 has a plurality of pixels 201 arranged two-dimensionally in the row direction and column direction. Each of the plurality of pixels 201 has a plurality of photoelectric conversion units 300 that accumulate charge based on incident light and a plurality of readout units 310.

[0074] The first wiring layer 712 is located on the second semiconductor substrate 120 side (negative Z-axis side in the figure) of the first semiconductor layer 711. The first wiring layer 712 has a plurality of wirings 713 made of a conductive film (metal film), a plurality of bonding pads 714, and an insulating film (insulating layer).

[0075] The first wiring layer 712 has a plurality of wirings 713 that are electrically connected to a power supply or circuit, etc. Specifically, in the first semiconductor substrate 110, the wirings 713 include, for example, power supply wiring to which a predetermined power supply voltage is supplied, signal lines 202 that transmit pixel signals from the first semiconductor substrate 110 (pixels) to the second semiconductor substrate 120, transfer control lines 311, ejection control lines 312, reset control lines 313, selection control lines 314, and transfer selection control lines 603 that transmit control signals from the second semiconductor substrate 120 to the first semiconductor substrate 110 (pixels). The first wiring layer 712 may be multilayer, and passive and active elements may be provided.

[0076] The bonding pad 714 is provided on the surface (the negative Z-axis side) of the first wiring layer 712 and is connected to the wiring 713. As will be described later, the bonding pad 714 is also used to assist in connecting layers. The bonding pad 714 is made of a conductive material such as copper. The bonding pad 714 may also be made of gold, silver, or aluminum. An insulating layer (insulating film) is formed between the multiple wirings 713 and between the multiple bonding pads 714.

[0077] The second semiconductor substrate 120 has a second semiconductor layer 721, a second wiring layer 722, and a wiring layer 723. The second wiring layer 722 is located on the side of the first semiconductor substrate 110 (positive Z-axis side in the figure) relative to the second semiconductor layer 721. The wiring layer 723 is located on the side of the third semiconductor substrate 130 (negative Z-axis side in the figure) relative to the second semiconductor layer 721, and is located between the second semiconductor layer 721 and the third semiconductor substrate 130. The second semiconductor layer 721 has a control circuit section 102 and a peripheral circuit section 121. The control circuit section 102 has a plurality of control blocks 400A arranged two-dimensionally in the row and column directions.

[0078] The second semiconductor substrate 120, like the first semiconductor substrate 110, has a plurality of wirings 713 provided on the second wiring layer 722, a plurality of bonding pads 714 provided on the second wiring layer 722 and the wiring layer 723, and an insulating film (insulating layer) provided on the second wiring layer 722 and the wiring layer 723.

[0079] The second wiring layer 722 has a plurality of wirings 713 and bonding pads 714 for electrically connecting to a power supply or circuit, transmitting signals from the pixel unit 101 to the control circuit unit 102, and transmitting signals from the control circuit unit 102 to the pixel unit 101. Specifically, the wirings 713 in the second semiconductor substrate 120 are, for example, power supply wiring to which a predetermined power supply voltage is supplied, signal lines 202 for transmitting pixel signals from the first semiconductor substrate 110 (pixels) to the second semiconductor substrate 120, transfer control lines 311, ejection control lines 312, reset control lines 313, selection control lines 314, and transfer selection control lines 603 for transmitting control signals from the second semiconductor substrate 120 to the first semiconductor substrate 110 (pixels). The second wiring layer 722 may be multilayer, and passive and active elements may be provided. The wirings 713 and bonding pads 714 may be further provided on the wiring layer 723.

[0080] The second semiconductor substrate 120 further includes TSVs (Through-Silicon Vehicles) 724 that connect circuits provided on its front and back surfaces. The TSVs 724 are preferably provided in the peripheral region. The TSVs 724 transmit image data and the like generated by the data processing unit 103 to the first semiconductor substrate 110. The TSVs 724 may also be provided on the first semiconductor substrate 110 and the third semiconductor substrate 130.

[0081] The third semiconductor substrate 130 has a third semiconductor layer 731 on which a data processing unit 103 is provided, and a third wiring layer 732. The third wiring layer 732 is provided between the third semiconductor layer 731 and the second semiconductor substrate 120.

[0082] The third semiconductor substrate 130, like the first semiconductor substrate 110, has wiring 713 and a plurality of bonding pads 714 provided on the third wiring layer 732. The third wiring layer 732 has a plurality of wiring 713 and bonding pads 714 for electrically connecting to a power supply or circuit, for transmitting signals from the control circuit unit 102 to the data processing unit 103, and for transmitting signals from the data processing unit 103 to the control circuit unit 102 of the second semiconductor substrate 120.

[0083] The first semiconductor substrate 110, the second semiconductor substrate 120, and the third semiconductor substrate 130 are stacked by electrical connections between bonding pads 714 provided on each layer and bonding between the wiring layers (insulating layers) of each layer.

[0084] When the first semiconductor substrate 110 and the second semiconductor substrate 120 are stacked, an interface 720 is formed by the Z-negative side of the first wiring layer 712 and the Z-positive side of the second wiring layer 722. Similarly, when the second semiconductor substrate 120 and the third semiconductor substrate 130 are stacked, an interface 730 is formed by the Z-negative side of the wiring layer 723 and the Z-positive side of the third wiring layer 732. Multiple bonding pads 714 are placed on the interface 720 and interface 730. Specifically, the corresponding bonding pads 714 are aligned with each other, and when the two layers are stacked, the aligned bonding portions are electrically connected.

[0085] The first semiconductor substrate 110, the second semiconductor substrate 120, and the third semiconductor substrate 130 may be formed by stacking wafers before they are chipped and then dicing the stacked wafers (making them into individual pieces), or they may be formed by stacking each of the wafers of the first semiconductor substrate 110, the second semiconductor substrate 120, and the third semiconductor substrate 130 after they have been diced.

[0086] Figure 8 is a timing chart showing example 1 of imaging operation of the image sensor 100A. Figure 8 is an example of imaging operation in which the drive of the image sensor 100A is controlled by the transfer control signal φTX, the ejection control signal φPDRST, the reset control signal φRST, and the selection control signal φSEL. In Figure 8, the ejection control signal φPDRST is locally controlled, while the transfer control signal φTX, the reset control signal φRST, and the selection control signal φSEL are globally controlled. Note that the end of each signal on the left is <1> , <2> ... <m>This indicates the row number of pixel 201 within the pixel block.

[0087] The emission control signal φPDRST controls the timing of the exposure start. The exposure start timing corresponds to the falling edge timing of the emission control signal φPDRST (for example, time T1). That is, before the exposure start time T1, the emission control signal φPDRST turns on the emission unit 302 to discharge the charge accumulated in the photoelectric conversion unit 300, and exposure starts on the falling edge of the emission control signal φPDRST. Since the emission control signal φPDRST is locally controlled, the exposure time can be adjusted for each pixel block 200.

[0088] The transfer control signal φTX controls the timing of the end of exposure. At time T3, the transfer control signal φTX turns on the transfer unit 301, thereby transferring the charge accumulated in the photoelectric conversion unit 300 to the FD303. The timing of the end of exposure corresponds to the falling edge timing of the transfer control signal φTX (for example, time T4). Since the transfer control signal φTX is a globally controlled signal, the timing of the end of exposure is the same for each pixel block 200.

[0089] The reset control signal φRST controls the timing of the discharge of charge accumulated in FD303. At time T2, the reset control signal φRST turns on the reset unit 304, thereby discharging the charge from FD303. By discharging the charge from FD303 before the end of exposure, the influence of the remaining charge in FD303 during charge transfer from the photoelectric conversion unit 300 can be suppressed.

[0090] The selection control signal φSEL is a signal for selecting any pixel 201. The selection control signal φSEL controls the on / off state of the selection unit 352. At time T2, the selection control signal φSEL is set to high. At time T3, the pixel 201 for which the selection control signal φSEL is set to high outputs a pixel signal to the signal line 202 in response to the ON state of the transfer control signal φTX. On the other hand, the pixel 201 for which the selection control signal φSEL is not set to high does not output a pixel signal.

[0091] The image sensor 100A can control the exposure time for each pixel block 200 by locally controlling the ejection control signal φPDRST, thereby changing the exposure start timing for each pixel block 200. Alternatively, the image sensor 100A may control the exposure end timing for each pixel block 200 by locally controlling the transfer control signal φTX. Furthermore, the image sensor 100A may control both the exposure start and end timings for each pixel block 200 by locally controlling both the transfer control signal φTX and the ejection control signal φPDRST.

[0092] Figure 9 is a timing chart showing example 2 of the imaging operation of the image sensor 100A. Figure 9 shows an example of imaging operation in which the drive of the image sensor 100A is controlled by the transfer control signal φTX, the reset control signal φRST, and the selection control signal φSEL. The image sensor 100A differs from the case in Figure 8 in that the timing of the start of exposure is controlled by the transfer control signal φTX. The differences from Figure 8 will be explained in particular.

[0093] The transfer control signal φTX controls the start and end timing of exposure. In frame (n), exposure starts at time T5 and ends at time T7.

[0094] At the exposure start time T5, exposure begins when the transfer control signal φTX falls. That is, before the exposure start time T5, the transfer control signal φTX turns on the transfer unit 301 with the reset control signal φRST turned on, thereby discharging the charge accumulated in the photoelectric conversion unit 300, and exposure begins when the transfer control signal φTX falls. Since the transfer control signal φTX is a locally controlled signal, the timing of exposure start can be changed in each pixel block 200. However, the timing of exposure start may be synchronized in each pixel block 200.

[0095] Furthermore, at the exposure end time T7, the exposure ends when the transfer control signal φTX falls. That is, before the exposure end time T7, the transfer control signal φTX turns on the transfer unit 301 with the reset control signal φRST turned off, transferring the charge accumulated in the photoelectric conversion unit 300 to the FD303, and the exposure ends when the transfer control signal φTX falls. Since the transfer control signal φTX is a locally controlled signal, the timing of the exposure termination can be changed in each pixel block 200. However, the timing of the exposure termination may be synchronized in each pixel block 200.

[0096] The selection control signal φSEL is a signal for selecting any pixel 201. At time T6, a pixel 201 for which the selection control signal φSEL is set to high outputs a pixel signal to the signal line 202.

[0097] The reset control signal φRST controls the timing of the discharge of charge accumulated in FD303. The reset control signal φRST may be a globally controlled signal. Since the reset control signal φRST is always on except at the read timing, no charge accumulates in FD303. On the other hand, by turning off the reset control signal φRST and turning on the transfer control signal φTX at the read timing, charge is transferred from the photoelectric conversion unit 300 to FD303. Since the switching timing of the reset control signal φRST is the same as that of the read timing, it can be shared with the pulse of the selection control signal φSEL.

[0098] The image sensor 100A can control the exposure time for each pixel block 200 by locally controlling the transfer control signal φTX, thereby changing the start or end timing of exposure for each pixel block 200. Furthermore, since the image sensor 100A shares pulses for the reset control signal φRST and the selection control signal φSEL, the control circuit can be further simplified.

[0099] Figure 10 is a timing chart showing the imaging operation of an image sensor according to a comparative example. Figure 10 is an example of imaging operation in which the drive of the image sensor is controlled by a transfer control signal φTX, a reset control signal φRST, and a selection control signal φSEL, and the exposure time is not controlled for each pixel block 200.

[0100] In the comparative example, the start of exposure is controlled by the transfer control signal φTX and the reset control signal φRST. The exposure start timing is the falling edge timing (time t1) of the transfer control signal φTX and the reset control signal φRST. The exposure end timing is the falling edge timing (time t2) of the transfer control signal φTX. In the comparative example, the exposure start and end timings are globally controlled, and the exposure time is not controlled for each pixel block 200.

[0101] Figure 11 is an explanatory diagram showing an example of a subject captured by the image sensor 100A. In Figure 11, the image sensor 100A controls the exposure time for each pixel block 200 in a situation where the setting sun is shining outside the tunnel.

[0102] Regions 1 through 5 are five regions divided according to brightness. Regions 1 through 5 are numbered in order of brightness. Region 1 is the brightest region where the setting sun is directly visible. Region 2 corresponds to the tunnel exit and is darker than Region 1. Region 3 is the region within the tunnel where the setting sun is reflected and is darker than Region 2. Region 4 is the region within the tunnel that is illuminated by the setting sun from the exit and is darker than Region 3. Region 5 is the darkest region within the tunnel that is not illuminated by the setting sun from the exit.

[0103] The image sensor 100A controls the exposure time for each pixel block 200 according to the brightness of each region. The image sensor 100A controls the exposure time so that the exposure time becomes shorter for pixel blocks 200 in brighter regions. The exposure time for region 1 is set to be the shortest, and the exposure time for region 5 is set to be the longest. For example, the exposure times for regions 1 to 5 are 1 / 19200s, 1 / 1920s, 1 / 960s, 1 / 240s, and 1 / 120s.

[0104] Figure 12 is a timing chart showing the exposure time for each region 1 to 5 shown in Figure 11. In Figure 12, the image sensor 100A controls the exposure time for each pixel block 200 in regions 1 to 5 shown in Figure 11. The interval from time T11 to time T19 corresponds to the video frame rate.

[0105] In region 1, control block 400A controls the drive so that the exposure time in pixel block 200 becomes a predetermined exposure time ET1. Control block 400A controls the start of exposure with the ejection control signal φPDRST and the end of exposure with the transfer control signal φTX. In region 1, exposure ends at each of the times T12 to T19.

[0106] In region 2, control block 400A controls the drive so that the exposure time ET2 for pixel block 200 is longer than ET1. Control block 400A sets the exposure start time in region 2 earlier than in region 1 and the exposure end time to coincide with that of region 1. Therefore, in region 2, exposure ends at times T12 to T19. The exposure time ET2 in region 2 is shorter than the period of the sensor rate.

[0107] In region 3, control block 400A controls the drive so that the exposure time ET3 for pixel block 200 is longer than ET2. Control block 400A sets the exposure start time in region 3 earlier than in region 2 and the exposure end time to match that of region 2. Therefore, in region 3, exposure ends at times T12 to T19. The exposure time ET3 in region 3 is set to be the same as the period of the sensor rate.

[0108] In region 4, control block 400A controls the drive so that the exposure time ET4 for pixel block 200 is longer than ET3. Control block 400A sets the exposure start time for region 4 to be the same as for region 3, but skips the exposure end time using the transfer selection control signal φTXSEL. By skipping three times using the transfer selection control signal φTXSEL, control block 400A achieves an exposure time four times that of region 3. In region 4, the transfer selection control signal φTXSEL is supplied at each of the times T12 to T14.

[0109] In region 5, control block 400A controls the drive so that the exposure time ET5 for pixel block 200 is longer than ET4. While setting the exposure start time for region 5 to be the same as region 4, control block 400A increases the number of times the exposure end time is skipped by the transfer selection control signal φTXSEL. By skipping 7 times with the transfer selection control signal φTXSEL, control block 400A achieves twice the exposure time of region 4. The exposure time ET5 in region 5 is set to be the same as the period of the video frame rate. In region 5, the transfer selection control signal φTXSEL is supplied at each time from time T12 to time T18.

[0110] The image sensor 100A achieves short exposure times by reducing the interval between the transfer control signal φTX and the ejection control signal φPDRST. Furthermore, the image sensor 100 achieves long exposure times by skipping the control of the transfer control signal φTX using the transfer selection control signal φTXSEL. This expands the dynamic range.

[0111] Figure 13 is a plan view showing an example layout of multiple control blocks 400A. The multiple control blocks 400A are arranged in a reversed configuration with respect to adjacent control blocks 400A. Figure 13 illustrates 12 of the multiple control blocks 400A provided in the control circuit unit 102.

[0112] Inverted configuration means that the areas where each component of the control block 400A (for example, the exposure control unit 412, the pixel driving unit 413, the signal input unit 421, the signal conversion unit 422, and the signal output unit 423) is formed are arranged in a mirror-inverted configuration (arranged symmetrically along a line) with respect to the boundary line between the control blocks 400A. The circuits of each component of the control block 400A do not necessarily have to be inverted. Furthermore, the reading order of each pixel of the control block 400A is not limited to being read in an inverted manner.

[0113] For example, if multiple control blocks 400A that are adjacent to each other in the row direction are arranged in a reversed manner, each component of the control block 400A will be arranged in a reversed manner in the row direction, so that at the boundary between the two control blocks 400A, the respective pixel drive units 413 will be arranged adjacent to each other. This allows multiple pixel drive units 413 that are adjacent to each other in the row direction to be laid out as a single pixel drive unit 413, thereby improving the layout efficiency of the control block 400A.

[0114] Similarly, when multiple control blocks 400A that are adjacent to each other in the column direction are arranged in reverse order, each component of the control block 400A is arranged in reverse order in the column direction, so that identical components are arranged adjacent to each other at the boundary between the two control blocks 400A. This allows multiple signal input units 421 that are adjacent to each other in the column direction to be laid out as a single signal input unit 421, thereby improving the layout efficiency of the control block 400A.

[0115] Each control block 400A is arranged in a reversed configuration with respect to the adjacent control block 400A. All control blocks 400A are arranged in a reversed configuration in both the row and column directions, but they may also be arranged in a reversed configuration in either the row or column direction. For example, the signal conversion unit 422 of a control block 400A is arranged in a reversed configuration with respect to the signal conversion unit 422 of an adjacent control block 400A in the row direction. Also, the signal conversion unit 422 of a control block 400A is arranged in a reversed configuration with respect to the signal conversion unit 422 of an adjacent control block 400A in the column direction.

[0116] Control blocks 400Aa and 400Ab are arranged adjacent to each other in the row direction. Control block 400Aa is arranged in reverse order to control block 400Ab. The level shift unit 504 of control block 400Aa is provided in the same well area as the level shift unit 504 of control block 400Ab. Similarly, the pixel block control unit 503, the storage unit 502, and the signal output unit 423 are provided in the same well area for control block 400Aa and control block 400Ab.

[0117] Control blocks 400Ab and 400Ac are arranged adjacent to each other in the row direction. Control block 400Ab is arranged in reverse order to control block 400Ac. The pixel drive unit 413 of control block 400Ab is provided in the same well area as the pixel drive unit 413 of control block 400Ac. The well area of ​​the pixel drive unit 413 may also be shared with the well area of ​​the level shift unit 504.

[0118] Control blocks 400Aa and 400Ad are arranged adjacent to each other in the column direction. Control block 400Aa is arranged in reverse order to control block 400Ad. The pixel drive unit 413 of control block 400Aa is provided in the same well area as the pixel drive unit 413 of control block 400Ad. Also, the signal conversion unit 422 of control block 400Aa is provided in the same well area as the signal conversion unit 422 of control block 400Ad.

[0119] Control blocks 400Ad and 400Ae are arranged adjacent to each other in the column direction. Control block 400Ad is positioned inversely to control block 400Ae. The pixel drive unit 413 and level shift unit 504 of control block 400Ad are located within the same well region as the pixel drive unit 413 and level shift unit 504 of control block 400Ae.

[0120] The image sensor 100 can optimize its layout even when signal processing is performed in parallel for each control block 400A by inverting the arrangement of the control blocks 400A. By inverting the arrangement of multiple control blocks 400A in the XY plane, adjacent control blocks 400A can share the well area. This reduces the number of well area switches and improves area efficiency.

[0121] Figure 14 is a circuit diagram showing another example of the circuit configuration of pixel 201. In pixel 201, the same components as in Figure 3 are given the same reference numerals and their explanations are omitted. In pixel 201, the discharge unit 302 that was provided in pixel 201 is not provided. When the charge accumulated in the photoelectric conversion unit 300 is discharged to the power supply wiring to which the power supply voltage VDD is supplied, a transfer control signal φTX is input to the gate terminal of the transfer unit 301, and a reset control signal φRST is input to the gate terminal of the reset unit 304.

[0122] Figure 15 is a timing chart showing example 3 of the imaging operation of the image sensor 100A. In Figure 15, the pixel 201 shown in Figure 14 is used, and the driving of the image sensor 100A is controlled by the transfer control signal φTX, the reset control signal φRST, and the selection control signal φSEL. The image sensor 100A differs from the case in Figure 12 in that the timing of the start of exposure is controlled by the transfer control signal φTX. The differences from Figure 12 will be explained in particular.

[0123] The transfer control signal φTX controls the start and end timing of exposure. In frame (n), exposure starts at time T5 and ends at time T7.

[0124] At the exposure start time T5, exposure begins when the transfer control signal φTX falls. That is, before the exposure start time T5, the transfer control signal φTX turns on the transfer unit 301 with the reset control signal φRST turned on, thereby discharging the charge accumulated in the photoelectric conversion unit 300, and exposure begins when the transfer control signal φTX falls. Since the transfer control signal φTX is a locally controlled signal, the timing of exposure initiation can also be changed for each pixel block 200.

[0125] Furthermore, at the exposure end time T7, the exposure ends when the transfer control signal φTX falls. That is, before the exposure end time T7, the transfer control signal φTX turns on the transfer unit 301 with the reset control signal φRST turned off, transferring the charge accumulated in the photoelectric conversion unit 300 to the FD303, and the exposure ends when the transfer control signal φTX falls. Since the transfer control signal φTX is a locally controlled signal, the timing of the exposure termination can also be changed in each pixel block 200.

[0126] The selection control signal φSEL is a signal for selecting any pixel 201. At time T6, a pixel 201 for which the selection control signal φSEL is set to high outputs a pixel signal to the signal line 202.

[0127] The reset control signal φRST controls the timing of the discharge of charge accumulated in FD303. The reset control signal φRST may be a globally controlled signal. Since the reset control signal φRST is always on except at the read timing, no charge is accumulated in FD303. On the other hand, by turning off the reset control signal φRST and turning on the transfer control signal φTX at the read timing, charge is transferred from the photoelectric conversion unit 300 to FD303. Since the switching timing of the reset control signal φRST is the same as that of the read timing, it can be shared with the pulse of the selection control signal φSEL.

[0128] As described above, with the configuration of the image sensor 100A shown in Figures 1 to 15, exposure is performed in units of pixel blocks 200, which consist of multiple pixels 201, and the pixel signals from the pixel blocks 200 are read out in units of control blocks 400A corresponding to the pixel blocks 200, thereby converting the analog signals into digital signals. Furthermore, the image sensor 100A reads out the pixel signals in parallel for each pixel block 200 using control blocks 400A provided for each pixel block 200. Therefore, the image sensor 100A can set the exposure time for each pixel block 200 according to the intensity of the incident light, thereby expanding the dynamic range.

[0129] Next, using Figures 16 to 22, we will describe the configuration of the image sensor 100B, which exposes in units of 200 pixel blocks, sequentially reads out the pixel signal for each pixel row, and performs AD conversion for each pixel column.

[0130] Figure 16 is an exploded perspective view showing another example of an image sensor. The image sensor 100B comprises a first semiconductor substrate 110, a second semiconductor substrate 120, and a third semiconductor substrate 130. As shown in Figure 16, the first semiconductor substrate 110 is laminated on the second semiconductor substrate 120, and the second semiconductor substrate 120 is laminated on the third semiconductor substrate 130.

[0131] The first semiconductor substrate 110 has a pixel section 101 and a connection area 1601. The pixel section 101 outputs a pixel signal based on incident light. The connection area 1601 is arranged around the pixel section 101. In the example in Figure 16, a pair of connection areas 1601 are arranged along two opposite sides of the first semiconductor substrate 110, one in front of and one behind the pixel section 101.

[0132] The second semiconductor substrate 120 includes a control circuit section 102, a peripheral circuit section 121, and a signal processing section 1602.

[0133] The control circuit unit 102 outputs control signals to the pixel unit 101 for controlling the driving of the pixel unit 101. The control circuit unit 102 is located on the second semiconductor substrate 120 at a position opposite to the pixel unit 101.

[0134] The peripheral circuit section 121 controls the driving of the control circuit section 102. The peripheral circuit section 121 is located around the control circuit section 102 on the second semiconductor substrate 120. The peripheral circuit section 121 may also be electrically connected to the first semiconductor substrate 110 and control the driving of the pixel section 101. The peripheral circuit section 121 is located along two opposite sides of the second semiconductor substrate 120, but the arrangement of the peripheral circuit section 121 is not limited to this example.

[0135] The signal processing unit 1602 receives analog pixel signals output from the first semiconductor substrate 110. The signal processing unit 1602 performs signal processing on the pixel signals. For example, the signal processing unit 1602 converts analog pixel signals into digital signals. The signal processing unit 1602 may perform other signal processing. Examples of other signal processing include noise reduction processing such as analog or digital CDS (correlated double sampling). The signal processing unit 1602 is located around, i.e., outside, the control circuit unit 102. In the example in Figure 16, a pair of signal processing units 1602 are arranged in front of and behind the control circuit unit 102, along two opposing sides of the second semiconductor substrate 120. The signal processing unit 1602 may also be a circuit included in the peripheral circuit unit 121.

[0136] The third semiconductor substrate 130 has a data processing unit 103. The data processing unit 103 performs addition, decimation, and other image processing using the digital data output from the second semiconductor substrate 120.

[0137] Figure 17 is an explanatory diagram showing another example of the specific configuration of the control circuit unit 102. In Figure 17, the control block 400B has a pixel control unit 401 (autonomous exposure processing unit 411, exposure control unit 412, and pixel driving unit 413), but does not have a signal processing unit 402.

[0138] Instead of providing one control block 400B for each pixel block 200, one control block 400B may be provided for N pixel blocks 200 (where N is a natural number greater than or equal to 2). N pixel blocks 200 corresponding to one pixel block are sometimes referred to as a pixel block group. For example, two pixel blocks 200 arranged side-by-side in a column direction may be treated as one pixel block group, and one control block 400B may be provided for each. In this case, the control block 400B may control the exposure time for each pixel block 200.

[0139] Furthermore, the control block 400B can be described as the smallest unit of circuitry that is electrically connected to at least one pixel block 200 and controls the exposure of the pixel 201 of that at least one pixel block 200.

[0140] Figure 18 is an explanatory diagram showing the connection relationship between the first semiconductor substrate 110 and the second semiconductor substrate 120 in the image sensor 100B. The first semiconductor substrate 110 includes connection regions 1801 and 1601 provided around the pixel portion 101 and electrically connected to the pixel portion 101. The second semiconductor substrate 120 includes connection regions 1802 and 1803 provided around the control circuit portion 102 and electrically connected to the control circuit portion 102.

[0141] Each pair of connection regions 1801 is connected to a pair of connection regions 1802 located opposite each other. The connected connection regions 1801 and 1802 input control signals from the global drive unit 600 to the pixel unit 101 using global control lines.

[0142] Each pair of connection regions 1601 is connected to a pair of connection regions 1803 located opposite each other. The connected connection regions 1601 and 1803 input pixel signals from the pixel region 101 to the corresponding ADC regions 1820 and 1830 using a common signal line.

[0143] Figure 19 is an explanatory diagram showing an example of signal transmission between the first semiconductor substrate 110 and the second semiconductor substrate 120 in the image sensor 100B. The global drive unit 600 outputs a reset control signal φRST, a selection control signal φSEL, and a transfer selection control signal φTXSEL. The global drive unit 600 is connected to reset control lines 1903 and selection control lines 1904, which output signals to each pixel block 200. The global drive unit 600 supplies the reset control signal φRST to multiple pixel blocks 200 via the reset control line 1903 and the selection control signal φSEL via the selection control line 1904. The global drive unit 600 supplies the transfer selection control signal φTXSEL to multiple control blocks 400B via the transfer selection control line 1905.

[0144] The transfer selection control signal φTXSEL is supplied from the global drive unit 600 to the control block 400B to control the exposure time for each pixel block 200. The control block 400B, upon receiving the transfer selection control signal φTXSEL, outputs the transfer selection control signal φTXSEL to the corresponding pixel block 200. The pixel block 200 decides whether or not to input the transfer selection control signal φTXSEL to the pixel 201 as a transfer control signal φTX or an ejection control signal φPDRST. As a result, the input of the transfer control signal φTX or the ejection control signal φPDRST to the pixel 201 is skipped.

[0145] For example, if the transfer control signal φTX determines the end time of exposure, control block 400B can extend the exposure time by skipping the transfer control signal φTX. Conversely, if the transfer control signal φTX determines the start time of exposure, control block 400B can shorten the exposure time by skipping the transfer control signal φTX. In this way, the exposure time of pixel block 200 can be adjusted by the transfer selection control signal φTXSEL. The same applies when the ejection control signal φPDRST determines the start or end time of exposure.

[0146] The reset control line 1903, the selection control line 1904, and the transfer selection control line 1905 are globally wired, that is, they are provided in common to multiple pixel blocks 200. The reset control line 1903, the selection control line 1904, and the transfer selection control line 1905 are wired to traverse the pixel section 101 in the row direction. The reset control line 1903, the selection control line 1904, and the transfer selection control line 1905 may also be wired to traverse the pixel section 101 in the column direction.

[0147] For example, the reset control line 1903 is connected to the gate terminal of the reset unit 304 of the pixel block 200 and supplies the reset control signal φRST. The selection control line 1904 is connected to the gate terminal of the selection unit 352 of the pixel block 200 and supplies the selection control signal φSEL. In addition, the transfer selection control line 1905 is connected to each of the multiple control blocks 400B and supplies the transfer selection control signal φTXSEL to the pixel control unit 401.

[0148] The global drive unit 600 outputs a transfer selection control signal φTXSEL from the second semiconductor substrate 120 to the first semiconductor substrate 110, but it may also output the transfer selection control signal φTXSEL to the control block 400B without supplying it to the first semiconductor substrate 110. In this case, the transfer selection control line 1905 is provided on the second semiconductor substrate 120.

[0149] Meanwhile, the transfer control line 1901a and the ejection control line 1902a are connected to the pixel block 200a. The transfer control line 1901a is connected to the gate terminal of the transfer unit 301 provided in the pixel block 200a. The transfer control line 1901a supplies the transfer control signal φTX output from the control block 400Ba to the pixel block 200a. The ejection control line 1902a is connected to the gate terminal of the ejection unit 302 provided in the pixel block 200a. The ejection control line 1902a supplies the ejection control signal φPDRST output from the control block 400Ba to the pixel block 200a.

[0150] The transfer control line 1901b and the ejection control line 1902b are connected to the pixel block 200b. The transfer control line 1901b is connected to the gate terminal of the ejection unit 301 provided on the pixel block 200b. The transfer control line 1901b supplies the transfer control signal φTX output from the control block 400Bb to the pixel block 200b. The ejection control line 1902b is connected to the gate terminal of the ejection unit 302 provided on the pixel block 200b. The ejection control line 1902b supplies the ejection control signal φPDRST output from the control block 400Bb to the pixel block 200b.

[0151] Multiple junctions 610 are provided on the junction surfaces where the first semiconductor substrate 110 and the second semiconductor substrate 120 are joined to each other. The junctions 610 of the first semiconductor substrate 110 are aligned with the junctions 610 of the second semiconductor substrate 120. Multiple opposing junctions 610 are joined and electrically connected by pressurization or the like on the first semiconductor substrate 110 and the second semiconductor substrate 120. In this case, the junctions 610 of the global control lines may be located below the corresponding pixel block 200, or in connection area 1801 or connection area 1802. On the other hand, the junctions 610 of the local control lines are provided below the corresponding pixel block 200 (or on the control block 400B).

[0152] The image sensor 100B controls the exposure time for each pixel block 200 by changing the timing of at least one of the transfer unit 301 and the output unit 302 using local control lines. By combining local and global control lines, the image sensor 100B can achieve exposure time control with fewer control lines.

[0153] Figure 20 is an explanatory diagram showing the connection relationship between the ADC unit and the pixel block. As shown in Figure 20, a common signal line 202 is arranged within each row of the pixel block 200c, extending in the direction of that row. Furthermore, this signal line 202 is common to multiple pixel blocks 200c and 200d arranged in the row direction. Therefore, in this example, one signal line 202 is connected to m × M pixels 201 arranged in a row, and pixel signals from these pixels 201 are output.

[0154] Each of the signal lines 202 is connected to an ADC 2000 on the side of the second semiconductor substrate 120 via a junction 610. Multiple ADCs 2000 corresponding to multiple signal lines 202 constitute the ADC unit 1820.

[0155] In the example shown in Figure 20, ADC2000 corresponding to the odd-numbered pixel blocks 200c and 200d is provided in ADC unit 1820, and ADC2000 corresponding to the even-numbered pixel blocks 200e and 200f is provided in ADC unit 1830. However, the arrangement of pixel blocks 200c, etc., and their corresponding ADC units 1820, etc., is not limited to this.

[0156] With the above configuration, each ADC 2000 converts the pixel signals output sequentially from the m × M pixels 201 in a connected row into digital signals and outputs them. In this case, the ADC units 1820 and 1830 as a whole convert the pixel signals from the n × N rows of pixels 201 in the row direction into digital signals in parallel. From this viewpoint, this digital conversion can be said to be a type of so-called column ADC. A single-slope ADC is given as an example of an ADC, but other digital conversion methods may be used. Also, the connection position between each pixel 201 and the signal line 202 is not limited to the configuration shown in Figure 20, and may be within each pixel block 200c, etc.

[0157] Figure 21 is a timing chart showing the imaging operation within the pixel block 200 of the image sensor 100B. The drive of the pixel block 200 is controlled by the transfer control signal φTX, the ejection control signal φPDRST, the reset control signal φRST, and the selection control signal φSEL.

[0158] The emission control signal φPDRST controls the timing of the exposure start. The exposure start timing corresponds to the falling edge timing of the emission control signal φPDRST (for example, time T1). That is, before the exposure start time T1, the emission control signal φPDRST turns on the emission unit 302 to discharge the charge accumulated in the photoelectric conversion unit 300, and exposure starts on the falling edge of the emission control signal φPDRST. Since the emission control signal φPDRST is controlled locally, the exposure time can be adjusted for each pixel block 200.

[0159] The transfer control signal φTX controls the timing of the end of exposure. At time T3, the transfer control signal φTX turns on the transfer unit 301, thereby transferring the charge accumulated in the photoelectric conversion unit 300 to the FD303. The timing of the end of exposure corresponds to the falling edge timing of the transfer control signal φTX (for example, time T4).

[0160] The reset control signal φRST controls the timing of the discharge of charge accumulated in FD303. At time T2, the reset control signal φRST turns on the reset unit 304, thereby discharging the charge from FD303. By discharging the charge from FD303 before the end of exposure, the influence of the remaining charge in FD303 during charge transfer from the photoelectric conversion unit 300 can be suppressed.

[0161] The selection control signal φSEL is a signal for selecting any pixel 201. The selection control signal φSEL controls the on / off state of the selection unit 352. At time T2, the selection control signal φSEL is set to high. At time T3, the pixel 201 for which the selection control signal φSEL is set to high outputs a pixel signal to the signal line 202 in response to the ON state of the transfer control signal φTX. On the other hand, the pixel 201 for which the selection control signal φSEL is not set to high does not output a pixel signal.

[0162] The image sensor 100B can control the exposure time for each pixel block 200 by locally controlling the ejection control signal φPDRST, thereby changing the exposure start timing for each pixel block 200. Alternatively, the image sensor 100B may control the exposure end timing for each pixel block 200 by locally controlling the transfer control signal φTX. Furthermore, the image sensor 100B may control both the exposure start and end timings for each pixel block 200 by locally controlling both the transfer control signal φTX and the ejection control signal φPDRST.

[0163] The pixel signal of each pixel 201 corresponds to the amount of charge stored in the photoelectric conversion unit 300. Therefore, controlling the exposure timing of the pixel 201 can be said to be controlling the timing of charge storage in the photoelectric conversion unit 300. More specifically, controlling the exposure timing of the pixel 201 can be said to be controlling the timing and length of the charge storage time from charge discharge to transfer.

[0164] Figure 22 is an explanatory diagram showing an example of exposure timing for each pixel block 200. For three pixel blocks 200 arranged in a row, the exposure time is controlled for each pixel block 200. Here, the image sensor 100B changes the exposure amount by shifting the pixel reset time for each pixel block 200.

[0165] On the other hand, the timing of reading out the pixel signals is sequential, starting from the top pixel block 200. That is, the pixel signal is read out from pixel 201 of "pixel block 1," then from pixel 201 of "pixel block 2," and then from pixel 201 of "pixel block 3."

[0166] Furthermore, within the pixel block 200, as explained in Figure 21, the pixel signals are read sequentially from the top row of pixels 201. Therefore, when considering the entire pixel unit 101, the pixel signals are read sequentially from the top row of the m × M pixels 201 in the same row connected to the common signal line 202. In other words, the global drive unit 600 sets the selection control signal φSEL to high for each row, spanning multiple pixel blocks 200 arranged in a single column from the first row to the m × M rows.

[0167] In this case, as explained in Figure 20, for multiple pixel blocks 200 arranged in a single row, a common selection control line 1904 is connected to n × N pixels in the same row. Therefore, pixel signals are read in parallel from n × N pixels 201 connected to the row in which the selection control signal φSEL is set to high. This makes it possible to output pixel signals for one frame.

[0168] These pixel signals are digitally converted by the ADC units 1820 and 252, as explained in Figure 20. The digitally converted pixel signals are output to the subsequent image processing stage to form an image for one frame.

[0169] As described above, the pixel signal readout is performed sequentially from the top row of the same column among multiple pixel blocks 200. From this perspective, the readout method of this embodiment can be said to be a so-called rolling shutter method for the entire pixel unit 101. However, it should be added that even in this case, different exposure times can be set for each pixel block 200.

[0170] As described above, the image sensor 100B shown in Figures 16 to 22 exposes in units of 200 pixel blocks, but sequentially reads out the pixel signal for each pixel row and performs AD conversion for each pixel column. Specifically, the image sensor 100B reads out the pixel signal from the pixel 201 of the upper pixel block 200, and then reads out the pixel signal from the pixel 201 of the lower pixel block 200, among the multiple pixel blocks 200 arranged in a row. Therefore, when imaging a moving subject, the distortion of the image due to the reading order is smoothed out, and the sense of discomfort the viewer may feel with the image can be reduced. More specifically, when reading out a moving subject in parallel from multiple pixel blocks 200 arranged in a row, multiple sawtooth-like steps corresponding to the pixel blocks 200 appear in the vertical direction of the image (i.e., corresponding to the pixel column direction), causing discomfort to the viewer. In contrast, with the image sensor 100B shown in Figures 16 to 22, these multiple steps do not appear in the image.

[0171] Furthermore, the image sensor 100B shown in Figures 16 to 22 does not have an ADC unit for converting analog signals to digital signals within the control block 400B, and the signal processing unit 1602 is located outside the control circuit unit 102. Therefore, the area of ​​the control block 400B can be reduced, and the size of the pixel block 200 located at the position corresponding to the control block 400B can be reduced, meaning that exposure control by the control block 400B can be performed in units of fewer pixels. As a result, the exposure time can be precisely controlled within the image, and the boundaries of the pixel block 200 can be made less noticeable on the image. Moreover, since digital conversion is not performed directly beneath the pixel 201, the impact of heat generation on noise affecting the pixel 201 can be suppressed.

[0172] Furthermore, the signal processing unit 1602 does not need to be provided in multiple separate regions; it may be provided in a single region for the entire pixel section 101.

[0173] As described above, the readout method of the image sensor 100B can be said to be a so-called rolling shutter method, as the entire pixel section 101 is read out sequentially from the top row of the same column among multiple pixel blocks 200, similar to the image sensor 100A. However, even in this case, different exposure times can be set for each pixel block 200, just as with the image sensor 100A. As a result, the image distortion caused by the readout order when capturing a moving subject is smoothed out in the image sensor 100B, just as in the image sensor 100A, and the sense of unnaturalness in the image perceived by the viewer is reduced.

[0174] [Autonomous exposure processing unit 411] Next, the details of the autonomous exposure processing unit 411 described above will be explained. In the following explanation, if the image sensors 100A and 100B are not distinguished, they will be referred to as image sensor 100, and if the control blocks 400A and 400B are not distinguished, they will be referred to as control block 400.

[0175] The autonomous exposure processing unit 411 is implemented within the control block 400, as shown in Figures 4 and 17. Alternatively, the autonomous exposure processing unit 411 can be implemented within the peripheral circuit section 121 instead of the control block 400, or it can be implemented in both the control block 400 and the peripheral circuit section 121. These three patterns will be explained below using Figures 23 to 25.

[0176] Figure 23 is a block diagram showing an example configuration of autonomous exposure control method 1. Autonomous exposure control method 1 is an example configuration in which the autonomous exposure processing unit 411 is implemented within the control block 400. Adding the autonomous exposure processing unit 411 to the control block 400 increases the circuit size of the control block 400, but this may result in each pixel 201 of the pixel block 200 becoming larger, thus making it possible to expand the light-receiving area.

[0177] Figure 23 illustrates the control block 400A as an example (Figure 25 is similar). The control block 400A includes a signal conversion unit 422, a signal output unit 423, an autonomous exposure processing unit 411, an exposure control unit 412, and a pixel driving unit 413. For the sake of explanation, the signal input unit 421 is omitted. In the case of control block 400B, the signal input unit 421, the signal conversion unit 422, and the signal output unit 423 are not included within the control block 400B, but are arranged on the second semiconductor substrate 120 as a signal processing unit 1602 (Figure 25 is similar).

[0178] The signal conversion unit 422 has n ADCs 500. Each of the n ADCs 500 converts analog pixel signals from m pixels 201 in the connected column direction into digital signals. The ADC 500 consists of a comparator 501 and a memory unit 502.

[0179] The column selection circuit 2301 is included in the signal output unit 423. The column selection circuit 2301 sequentially selects a column of the pixel block 200 each time a read column selection signal is input from an external source K. Each time a horizontal transfer clock is input from an external source, the column selection circuit 2301 outputs the digital pixel signals from m pixels 201 of the selected column to the peripheral circuit unit 121 via the horizontal transfer line 2300, and also outputs them to the autonomous exposure processing unit 411.

[0180] The autonomous exposure processing unit 411 calculates an exposure value indicating the exposure time of the pixel block 200. Specifically, for example, the autonomous exposure processing unit 411 includes a pre-processing unit 2311, a controller 2312, and an exposure value calculation unit 2313.

[0181] The preprocessor unit 2311 acquires digital pixel signals for each pixel column of the pixel block 200 from the column selection circuit 2301. The preprocessor unit 2311 then calculates statistical values ​​(for example, mean, median, maximum, or minimum) of the acquired pixel signals. The preprocessor unit 2311 outputs these calculation results to the exposure value calculation unit 2313.

[0182] The controller 2312 inputs a reset signal to the preprocessing unit 2311, causing the preprocessing performed by the preprocessing unit 2311 to reset. As a result, the preprocessing unit 2311 calculates statistical values ​​of the pixel signals from the pixel block 200 each time it resets, that is, for each frame.

[0183] The exposure value calculation unit 2313 determines the next exposure value based on the calculation result (statistical value of the pixel signal) from the preprocessing unit 2311. Specifically, for example, the exposure value calculation unit determines the next exposure value based on the calculation result so as not to result in underexposure or overexposure. For example, the exposure value calculation unit 2313 maintains a first threshold and a second threshold. The first threshold is a threshold used to determine whether the calculation result is underexposed or not. The second threshold is a threshold greater than the first threshold and is a threshold used to determine whether the calculation result is overexposed or not.

[0184] The exposure value calculation unit 2313 determines whether the calculation result is between a first threshold and a second threshold. If the calculation result is between a first threshold and a second threshold, the exposure value calculation unit outputs the calculation result as the exposure value to the latch circuit 2321 of the exposure control unit 412. If the calculation result is less than the first threshold, the exposure value calculation unit 2313 outputs the first threshold as the exposure value to the latch circuit 2321 of the exposure control unit 412. If the calculation result exceeds the second threshold, the exposure value calculation unit outputs the second threshold as the exposure value to the latch circuit 2321 of the exposure control unit 412.

[0185] Furthermore, the exposure value calculation unit 2313 may maintain multiple exposure value ranges. In this case, if the calculation result is between a first threshold and a second threshold, the exposure value calculation unit 2313 outputs the number of steps in the exposure value range that includes the calculation result as the exposure value to the latch circuit 2321 of the exposure control unit 412.

[0186] Furthermore, if the calculation result is less than the first threshold, the exposure value calculation unit 2313 outputs to the latch circuit 2321 of the exposure control unit 412 an exposure value that is one or more steps higher than the number of steps in the exposure value range that includes the calculation result. Furthermore, if the calculation result exceeds the second threshold, the exposure value calculation unit 2313 outputs to the latch circuit 2321 of the exposure control unit 412 an exposure value that is one or more steps lower than the number of steps in the exposure value range that includes the calculation result.

[0187] The exposure control unit 412 includes, for example, a latch circuit 2321, a shift register 2322, a pixel block control unit, and a level shift unit. The latch circuit 2321 holds the exposure value from the autonomous exposure processing unit. Each time a latch pulse is input from an external source, the latch circuit 2321 outputs the held exposure value to the pixel block control unit and the shift register 2322.

[0188] The shift register 2322 converts the exposure value from the latch circuit 2321 into a parallel-to-serial format and outputs it as a serial signal to the data processing unit.

[0189] If the exposure time is calculated by an external system outside the image sensor 100 and the calculation result is fed back to the image sensor 100, it takes time for the exposure time to be reflected in the image sensor 100, and power consumption increases. In contrast, by providing an autonomous exposure processing unit 411 within the control block 400, it is possible to improve the speed at which the exposure time is reflected in the pixel block 200 and reduce power consumption.

[0190] In Figure 23, the case where one control block 400 controls the exposure of one pixel block 200 was described. However, when one control block 400 controls the exposure of multiple pixel blocks 200, the autonomous exposure processing unit 411 may sequentially select one pixel block 200 from the multiple pixel blocks 200 in synchronization with the reset signal and calculate the exposure value. A selector is provided on the output side of the exposure value calculation unit 2313, and the controller 2312 outputs a selection signal to the selector to select one pixel block 200 from the multiple pixel blocks 200.

[0191] In this case, the exposure control unit 412 has a latch circuit 2321 and a shift register 2322 for each pixel block 200. Each latch circuit 2321 is connected to a selector (not shown) in the autonomous exposure processing unit 411, and when an exposure value is input from the selector, the held exposure value is output to the pixel block control unit 503 and the shift register 2322 each time a latch pulse is input. This makes it possible to achieve autonomous exposure even when one control block 400 controls the exposure of multiple pixel blocks 200.

[0192] Figure 24 is a block diagram showing an example configuration of autonomous exposure control method 2. Autonomous exposure control method 2 is an example configuration in which the autonomous exposure processing unit 411 is implemented within the peripheral circuit unit 121. The autonomous exposure processing unit 411 is implemented in the peripheral circuit unit 121 rather than within the control block. Therefore, the circuit size of the control block 400 can be reduced compared to the case shown in Figure 23.

[0193] The peripheral circuit section 121 is connected to the pixel section 101 via the horizontal transfer section 2410. The horizontal transfer section 2410 is connected to each pixel block 200 (hereinafter referred to as a pixel block row) arranged in the row direction, and for each pixel block row, it transfers the pixel signal to the peripheral circuit section 121. Since the pixel section 101 is a collection of M rows and N columns of pixel blocks 200, the horizontal transfer section 2410 transfers the pixel signal to the peripheral circuit section 121 for each M pixel block row.

[0194] The peripheral circuit section 121 has row-direction autonomous exposure processing groups 2400-1 to 2400-M for each row of pixel blocks (when not distinguished, they are simply referred to as row-direction autonomous exposure processing group 2400). Each row-direction autonomous exposure processing group 2400 includes a data sampling unit 2411 and autonomous exposure processing units 411 (pre-processing unit 2311, controller 2312, and exposure value calculation unit 2313) for the number of columns N of the pixel block. In Figure 24, since N=4, four sets of the pre-processing unit 2311, controller 2312, and exposure value calculation unit 2313 are implemented.

[0195] The data sampling unit 2411 divides the pixel signal sequence of a pixel block row from the horizontal transfer unit 2410 into N equal parts and samples them. The data sampling unit 2411 outputs each of the sampled pixel signal sequences to the corresponding preprocessing unit 2311.

[0196] As described above, the preprocessing unit 2311 calculates statistical values ​​of the pixel signals from the corresponding pixel block 200. Furthermore, since the peripheral circuit unit 121 can have a larger circuit scale than the control block 400, the preprocessing unit 2311 can perform other processes besides calculating statistical values ​​of the pixel signals.

[0197] For example, the preprocessing unit 2311 has a memory that stores the pixel numbers of defective pixels in the corresponding pixel block 200 during manufacturing. When the data sampling unit 2411 samples the pixel signal of that pixel number, the preprocessing unit 2311 does not use it to calculate the statistical value of that pixel signal. This makes it possible to improve the accuracy of calculating the statistical value of the pixel signal.

[0198] Furthermore, the preprocessing unit 2311 may obtain calculation results from other preprocessing units 2311 responsible for the corresponding pixel block 200 and adjacent pixel blocks 200, and calculate statistical values ​​of the pixel signals from the corresponding pixel block 200 based on the calculation results obtained from the other preprocessing units 2311. This makes it possible to smooth out the exposure step difference between adjacent pixel blocks 200.

[0199] Furthermore, although the exposure value calculation unit 2313 is set to a first threshold and a second threshold, at least one of the first threshold and the second threshold may be changed depending on the shooting mode of the imaging device on which the image sensor 100 is mounted. This makes it possible to calculate the optimal exposure according to the shooting mode.

[0200] Furthermore, the peripheral circuit section 121 has a latch circuit 2321 and a shift register 2322 for each exposure value calculation unit 2313. The shift register 2322 converts the exposure value from the latch circuit 2321 to a parallel serial signal and outputs it to the data processing unit 103, and also outputs the exposure value to the exposure control unit 412 in the control block 400 corresponding to the pixel block 200.

[0201] The configuration shown in Figure 24 allows for a smaller circuit size of the control block 400 compared to the case in Figure 23, and thus reduces the size of the corresponding pixel block 200. Consequently, the number of pixel blocks increases, enabling more precise autonomous exposure control. Alternatively, the exposure control unit 412 and the pixel drive unit 413 may be mounted in the peripheral circuit unit 121. This further reduces the circuit size of the control block 400 and the size of the corresponding pixel block 200.

[0202] Figure 25 is a block diagram showing an example configuration of the autonomous exposure control method 3. The autonomous exposure control method 3 is an example configuration in which the autonomous exposure processing unit 411 is implemented both within the control block 400A and within the peripheral circuit unit 121. When automatic exposure control is performed within the control block 400A, data transmission such as sending pixel signals from the control block 400A to the peripheral circuit unit 121 or sending exposure values ​​from the peripheral circuit unit 121 to the pixel block 200 becomes unnecessary. Therefore, feedback to the corresponding pixel block 200 is faster compared to when it is performed in the peripheral circuit unit 121.

[0203] On the other hand, since the area of ​​the control block 400A is constrained by its dependence on the area of ​​the corresponding pixel block 200, the circuit size of the autonomous exposure processing unit 411 can be increased by implementing it in the peripheral circuit section 121 rather than implementing it in the control block 400A. For this reason, implementing it in the peripheral circuit section 121 allows for the implementation of more advanced functions for autonomous exposure control (for example, removal of pixel signals from defective pixels as explained in Figure 24, exposure step control between adjacent pixel blocks 200, and calculation of optimal exposure according to the shooting mode).

[0204] Therefore, in autonomous exposure control method 3, the image sensor 100 performs autonomous exposure control in the peripheral circuit section 121 when performing high-function calculations related to autonomous exposure control, and in the control block 400A when performing high-speed feedback of exposure values, depending on the situation. In Figure 25, as an example, in autonomous exposure control method 3, autonomous exposure control is performed by the row-direction autonomous exposure processing group 2400 in the peripheral circuit section 121, but the image sensor 100 performs autonomous exposure control for each control block 400A when some trigger is given to the control circuit section 102.

[0205] For example, the image sensor 100 performs autonomous exposure control in the peripheral circuit section 121 if a high-performance calculation related to autonomous exposure control is selected by the user, and in the control block 400A if high-speed execution of exposure value feedback is selected. In addition, when the battery level falls below a predetermined amount, the image sensor 100 may select and execute a low-power processing method from among the high-performance calculation related to autonomous exposure control and high-speed execution of exposure value feedback.

[0206] The row-direction autonomous exposure processing unit 2400, which is mounted on the peripheral circuit section 121, has the same configuration as shown in Figure 24, and is therefore omitted in Figure 25.

[0207] The column selection circuit 2301 outputs an n-bit digital pixel signal to n OR circuits 2501. The autonomous exposure processing unit 2500 in the control block 400A includes a controller 2312, n OR circuits 2501, an output data latch circuit 2502, and an n-bit AND circuit 2503.

[0208] When the controller 2312 receives an n-bit signal from the output data latch circuit 2502, it inputs a reset signal to the output data latch circuit 2502.

[0209] The OR gate 2501 is a two-input, one-output logic circuit. One input of the OR gate 2501 is connected to a column selection circuit, and the other input is connected to the output of an n-bit AND gate 2503.

[0210] The n OR gates 2501 are connected to the input of the output data latch circuit 2502. The output data latch circuit 2502 holds the n-bit signals from the n OR gates 2501. When the horizontal transfer clock is input to the output data latch circuit 2502, it outputs an n-bit signal to the n-bit AND gate 2503. Also, when the output data latch circuit 2502 receives a reset signal from the controller 2312, it resets the n-bit signal it holds and outputs an n-bit signal to the n-bit AND gate 2503 in which at least one bit of the n bits is 0.

[0211] The n-bit AND circuit 2503 is an n-input, 1-output AND circuit, and the output of the output data latch circuit 2502 is connected to the input of the n-bit AND circuit 2503. The output of the n-bit AND circuit 2503 is connected to the selector 2512 and each OR circuit 2501 of the exposure control unit 412. If the output from the n-bit AND circuit 2503 is "0", it indicates that the pixel sequence that output the n-bit digital pixel signal is not saturated. If the output from the n-bit AND circuit 2503 is "1", it indicates that the pixel sequence that output the n-bit digital pixel signal is saturated. Hereinafter, the 1-bit signal with an output of "1" from the n-bit AND circuit 2503 will be referred to as the saturation detection signal.

[0212] If the value of the digital pixel signal from pixel 201 in a pixel sequence is "1", it indicates that pixel 201 is saturated. If the values ​​of all n-bit signals from the sequence selection circuit 2301 are "1", it indicates that the entire pixel sequence is saturated. In this case, all "1"s are input to one input of each OR circuit 2501, so each OR circuit 2501 outputs a 1-bit signal with a value of "1" to the output data latch circuit 2502.

[0213] The output data latch circuit 2502 holds these n bit signals, all of which have a value of "1," and when a horizontal transfer clock is input, it outputs the held n bit signals to the n-bit AND circuit 2503.

[0214] When the n-bit AND gate 2503 receives an n-bit signal in which all values ​​are "1", it outputs a saturation detection signal with a value of "1" to the selector 2512 and each OR gate 2501. As a result, the output data latch circuit 2502 outputs an n-bit signal in which all values ​​are "1" to the n-bit AND gate 2503 until a reset signal is input. Therefore, the n-bit AND gate 2503 outputs a saturation detection signal to the output data latch circuit 2502 until a reset signal is input from the controller 2312.

[0215] In addition to the configuration shown in Figure 24, the exposure control unit 412 also includes a shift register 2511 and a selector 2512. The shift register 2511 converts the exposure value from the peripheral circuit unit 121 from serial to parallel and outputs it to the level shift unit 504 and the selector 2512.

[0216] The selector 2512 receives the exposure value and the set exposure value from the shift register 2511 as input. The selector 2512 selects either the exposure value or the set exposure value from the shift register 2511 based on the output signal from the n-bit AND circuit 2503, and outputs the selected exposure value to the latch circuit 2321. The set exposure value is an exposure value corresponding to an exposure time such that the pixel 201 does not saturate, for example, an exposure value set to minimize the exposure time.

[0217] The set exposure value is calculated and set by an external system outside the control block 400A, for example. The set exposure value may be a fixed value or may be selected from the external system. The external system may be, for example, the peripheral circuit section 121 within the image sensor 100, the data processing unit 103 of the third semiconductor substrate 130, or an image processing unit connected to the image sensor 100 within an imaging device having the image sensor 100.

[0218] Specifically, the selector 2512, for example, selects an exposure value from the shift register 2511 and outputs it to the latch circuit 2321 if the output signal from the n-bit AND circuit 2503 is not a saturation detection signal. On the other hand, if the output signal from the n-bit AND circuit 2503 is a saturation detection signal, the selector 2512 selects a set exposure value and outputs it to the latch circuit 2321.

[0219] Within the control block 400A, the autonomous exposure processing unit 2500 and the exposure control unit 412 perform autonomous exposure control using the exposure value from the peripheral circuit unit 121 until saturation is detected in the control block 400A. Once saturation is detected in the control block 400A, autonomous exposure control is performed using the set exposure value in the exposure control unit 412.

[0220] This makes it possible to select between two processes: one in which a highly accurate exposure value is set for unsaturated pixel rows based on the exposure value from the peripheral circuit section 121, and another in which a simple and fast feedback process is performed to change the exposure value for saturated pixel rows to a setting that makes them unsaturated.

[0221] Furthermore, the autonomous exposure processing unit 2500 within the control block 400 may be the autonomous exposure processing unit 411 shown in Figure 23. In this case, for example, the user may be able to select between the autonomous exposure processing unit 411 in the peripheral circuit unit 121 and the autonomous exposure processing unit 411 in the control block 400.

[0222] For example, an imaging device equipped with an image sensor 100 may be able to select between an autonomous exposure processing unit 411 in the peripheral circuit unit 121 and an autonomous exposure processing unit 411 in the control block 400 based on the remaining battery level. In this case, the imaging device may select autonomous exposure control by the autonomous exposure processing unit 411 in the peripheral circuit unit 121 if the remaining battery level is above a predetermined value, and select autonomous exposure control by the autonomous exposure processing unit 411 in the control block 400 if it is below the predetermined value. Furthermore, if the user wants to perform high-quality imaging, they can select the autonomous exposure processing unit 411 in the peripheral circuit unit 121, and if they want to reduce power consumption, they can select the autonomous exposure processing unit 411 in the control block 400.

[0223] <Layout of the autonomous exposure control system> Next, the layout of the autonomous exposure control system will be described. The autonomous exposure processing unit 411 may be implemented within the control block 400 as shown in Figures 23 and 25, or within the peripheral circuit section 121 as shown in Figures 24 and 25. The former will be explained in Figure 26, and the latter in Figures 27 and 28. Figures 26 to 28 will use the circuit configuration of control block 400A as an example, but in the case of control block 400B, the signal processing unit 402 within control block 400A will be laid out as signal processing unit 1602 on the second semiconductor substrate 120 outside of control block 400B.

[0224] Figure 26 is a block diagram showing an example layout when an autonomous exposure processing unit is implemented in adjacent control blocks. Figure 13 shows an example layout of multiple control blocks 400A. In Figure 26, the internal configuration of two adjacent control blocks 400Aa and 400Ab in the row direction, without passing through the pixel driving unit 413, as shown in Figure 13, is explained in detail.

[0225] Specifically, for example, Figure 26 illustrates this using two adjacent control blocks 400Aa and 400Ab in the row direction shown in Figure 13, without going through the pixel driving unit 413. To indicate which of the control blocks 400Aa or 400Ab the internal configuration is being described, the internal configuration of control block 400Aa is denoted with 'a' at the end of its code, and the internal configuration of control block 400Ab is denoted with 'b' at the end of its code.

[0226] Furthermore, the signal lines shown in the legend indicate the connection relationships of the internal configuration. Solid arrows represent global pixel signal lines 2601G, and dotted arrows represent local pixel signal lines 2601L. Thick solid arrows represent global control signal lines 2602G, and thick dotted arrows represent local control signal lines 2602L. A dashed-dotted line represents data lines 2603 between control blocks. Pixel signal lines are signal lines that transmit pixel signals, and control signal lines are signal lines that transmit control signals.

[0227] The global pixel signal line 2601G is a pixel signal line (horizontal transfer line) shared by row-direction control blocks 400A. The local pixel signal line 2601L is a pixel signal line within its own control block 400A. The global control signal line 2602G is a control signal line shared by row-direction control blocks 400A. The local control signal line 2602L is a control signal line within its own control block 400A. The inter-control block data line 2603 is a data line for sending and receiving data between exposure value calculation units 2313a and 2313b.

[0228] In control blocks 400Aa and 400Ab, as explained in Figure 13, the signal conversion units 422a and 422b, the autonomous exposure processing units 411a and 411b, and the exposure control units 412a and 412b are arranged in a mirror configuration.

[0229] Furthermore, a signal output unit 423 common to control blocks 400Aa and 400Ab is placed between signal conversion units 422a and 422b. This improves the layout efficiency between control blocks 400Aa and 400Ab.

[0230] Since the internal layout of the autonomous exposure processing units 411a and 411b is also mirrored, the pre-processing units 2311a and 2311b are arranged along the row direction. Digital pixel signals from the signal conversion units 422a and 422b are horizontally transferred to the global pixel signal line 2601G via the signal output unit 423. For this reason, each of the pre-processing units 2311a and 2311b is positioned in close proximity to the signal conversion units 422a and 422b and the signal output unit 423 (row selection circuit 2301).

[0231] This allows the local pixel signal line 2601L between the pre-processing units 2311a and 2311b and the signal output unit 423 to be routed without bypassing other internal components. Consequently, the transmission efficiency of digital pixel signals between the pre-processing units 2311a and 2311b and the signal output unit 423 is improved.

[0232] Controllers 2312a, 2312b and exposure value calculation units 2313a, 2313b are also arranged along the row direction. Specifically, for example, in the row direction, exposure value calculation units 2313a, 2313b are arranged in close proximity, while controllers 2312a, 2312b are arranged at a distance apart. For example, when exposure value calculation unit 2313b calculates an exposure value using the exposure value from exposure value calculation unit 2313a, communication occurs between exposure value calculation units 2313a, 2313b. This communication distance is shortened compared to when controllers 2312a, 2312b are arranged at a distance apart. Therefore, the calculation efficiency of exposure value calculation unit 2313b is improved.

[0233] Furthermore, the local pixel signal line 2601L connects the signal output unit 423 to the pre-processing units 2311a, 2311b, the pre-processing units 2311a, 2311b to the exposure value calculation units 2313a, 2313b, and the exposure value calculation units 2313a, 2313b to the exposure control units 412a, 412b. Therefore, in order to shorten the wiring length of the local pixel signal line 2601L, the pre-processing units 2311a, 2311b, the exposure value calculation units 2313a, 2313b, and the exposure control units 412a, 412b are positioned closer to the boundary between the control blocks 400Aa, 400Ab, rather than closer to the pixel driving units 413a, 413b.

[0234] This arrangement allows for a reduction in the amount of wiring required within control blocks 400Aa and 400Ab.

[0235] Figure 27 is a block diagram showing an example layout when the autonomous exposure processing unit 411 is mounted on the peripheral circuit section 121. Figure 28 is a block diagram showing the detailed internal configuration of the peripheral circuit section 121 shown in Figure 27. On the second semiconductor substrate 120, the peripheral circuit sections 121a and 121b are arranged on both sides of the control circuit section 102.

[0236] The control circuit unit 102 has a signal processing unit 402 (signal input unit 421, signal conversion unit 422, signal output unit 423) and an exposure control unit 412 for each control block 400A.

[0237] The peripheral circuit section 121 includes a pixel driving unit 413, a row-direction autonomous exposure processing unit group 2400, and a digital signal processing circuit 2701. The peripheral circuit section 121 also includes a timing generator 2702.

[0238] Furthermore, the output IF2703 is located outside the peripheral circuit section 121, in close proximity to the digital signal processing circuit 2701. Similarly, the PLL circuit 2704 is located outside the peripheral circuit section 121, in close proximity to the timing generator 2702.

[0239] The timing generator 2702 sequentially outputs the addresses of all rows of a pixel block sequence to the data sampling unit 2411 during one frame. The timing generator 2702 also outputs a reset signal to each autonomous exposure processing unit.

[0240] As shown in Figure 28, the signal output unit 423 in the control block 400A outputs the digital pixel signal to the data sampling unit 2401. The data sampling unit 2401 refers to the column address of the pixel block sequence from the timing generator 2702, distributes the digital pixel signal from the control block 400A to each pixel block sequence, and outputs it to the autonomous exposure processing unit 411. The data sampling unit 2401 also outputs the digital pixel signal to the digital signal processing unit.

[0241] The autonomous exposure processing unit 411 calculates the exposure value and outputs it to the exposure control unit 412. When the autonomous exposure processing unit 411 receives a reset signal from the timing generator, it resets the exposure value.

[0242] In the row-direction autonomous exposure processing units 2400-1 to 2400-M, the data sampling unit 2401 and the row-direction autonomous exposure processing unit 411 are arranged alternately in the column direction. This reduces the wiring length of the control signal lines and data signal lines.

[0243] The digital signal processing circuit 2701 uses the output signal from the PLL circuit 2704 to serially convert the exposure value from the row-direction autonomous exposure processing unit 2400 and send it to the output IF 2703. The timing generator 2702 supplies a clock signal to the row-direction autonomous exposure processing unit 2400 for generating various timing signals used by the row-direction autonomous exposure processing unit 2400.

[0244] In Figure 27, the signal from the control circuit unit 102 (for example, the digital pixel signal) is output to the autonomous exposure processing unit 411 via the pixel drive unit 413, the exposure value from the autonomous exposure processing unit 411 is output to the digital signal processing circuit 2701, and the output from the digital signal processing circuit 2701 is output to the output IF 2703. Therefore, between the control circuit unit 102 and the output IF 2703, the pixel drive unit 413, the autonomous exposure processing unit 411, and the digital signal processing circuit 2701 are arranged in order of proximity from the control circuit unit 102.

[0245] In addition, since the row-direction self-timing exposure processing unit group 2400 communicates with the timing generator 2702, it is also disposed in proximity to the timing generator 2702. The digital signal processing circuit 2701 and the timing generator 2702 are disposed in proximity within an automatic placement and wiring area 2700 that is automatically placed and wired by a computer (not shown).

[0246] In this way, the self-timing exposure processing unit 411 is disposed in proximity to the automatic placement and wiring area 2700 in accordance with the signal flow within the peripheral circuit unit 121. Therefore, it is possible to reduce the wiring scale within the peripheral circuit unit 121.

[0247] <Reduction of the reflection period when the exposure time is changed> Next, the reduction of the reflection period when changing the exposure time will be described using FIGS. 29 to 38.

[0248] FIG. 29 is an explanatory diagram showing an example of a delay in the reflection period of the exposure time. In FIG. 29, the case of changing from the exposure time for a half frame (hereinafter, half-frame exposure) to the exposure time for one frame (hereinafter, one-frame exposure) will be described as an example. The horizontal axis in FIG. 29 is time, and the vertical axis is the row number within the pixel block. In FIG. 29, the number of pixel rows m of the pixel block 200 is 32 rows.

[0249] In the half-frame exposure, when the discharge control signal φPDRST is sequentially input to the gate terminal of the discharge unit 302 for each pixel 201 of the pixel rows of the pixel block 200, the accumulation of charges, that is, the start of exposure, is performed for the pixel 201 for each pixel row (reset 1 to 3).

[0250] In the half-frame exposure, when the transfer control signal φTX is sequentially input to the gate terminal of the transfer unit 301 for each pixel 201 of the pixel rows of the pixel block 200 at the time when half-frame exposure has elapsed from each of resets 1 to 3, the reading 1 of the pixel block 200 in the frame Fi is started, and when the analog pixel signal is read from the last pixel row, the reading period i of the pixel block 200 in the frame F1 ends.

[0251] The pixel signal read out during the read period i is externally data - transferred i as a digital signal by the signal processing unit 402. Also, for the pixel signal read out and digitally converted during the read period i, the control block 400 executes an exposure value calculation i.

[0252] Here, assume that an instruction to change from 1 / 2 - frame exposure to 1 - frame exposure is input to the control block 400 before the elapse of the read period i. When reflecting the calculation result of the exposure value calculation i in the 1 - frame exposure of frame F(i + 1), it must be after the end of the exposure value calculation i. For this reason, after the end of the exposure value calculation i, reset 4 is executed at the timing of the first - arriving read start point (read 3). That is, since reset 2 has started before the end of the exposure value calculation i, the calculation result of the exposure value calculation i cannot be reflected in the 1 - frame exposure of frame F(i + 1) at the timing of read 2.

[0253] In addition, in the updated 1 - frame exposure, when the transfer control signal φTX is sequentially input to the gate terminals of the transfer unit 301 for each pixel 201 of the pixel row of the pixel block 200 at the time when 1 - frame exposure has elapsed from reset 4, the read 4 of the pixel block 200 in frame F(i + 1) is started, and when the analog pixel signal is read out from the last pixel row, the read period i + 1 of the pixel block 200 in frame F(i + 1) ends.

[0254] The pixel signal read out during the read period i + 1 is externally data - transferred i + 1 as a digital signal by the signal processing unit 402. Also, for the pixel signal read out and digitally converted during the read period i + 1, the control block 400 executes an exposure value calculation i + 1.

[0255] Thus, in FIG. 29, when changing from 1 / 2 - frame exposure to 1 - frame exposure, a delay of two frames occurs until the 1 - frame exposure is reflected. The same applies when changing from less than 1 / 2 - frame exposure to 1 - frame exposure.

[0256] Figure 30 is an explanatory diagram showing example 1 of shortening the exposure time reflection period. In Figure 30, as in Figure 29, the case of changing from 1 / 2 frame exposure to 1 frame exposure is used as an example. The difference from Figure 29 is that in Figure 30, forced reset 1-4 for 1 frame exposure is input at the timing of readouts 1-4.

[0257] Forced resets 1-4, like resets 1-4, are emission control signals φPDRST that are sequentially input to the gate terminal of the emission unit 302 for each pixel 201 in each pixel row of the pixel block 200. This causes charge accumulation, i.e., exposure, to begin in each pixel 201 in each pixel row.

[0258] Here, let's assume that a command to change from 1 / 2 frame exposure to 1 frame exposure is input to the control block 400 before the read period i has elapsed. If the result of the exposure value calculation i is to be reflected in the 1 frame exposure of frame F(i+1), in Figure 29 it had to be after the exposure value calculation i has finished, but in Figure 30 when forced reset 2 is input, charge accumulation starts in the pixel 201 for each pixel row in the pixel block 200 of frame F(i+1) without waiting for the exposure value calculation i to finish. In this case, the control block 400 drives the pixel 201 so as not to input reset 3.

[0259] After this, exposure for one frame continues. That is, readout 4 starts at the end of readout period i+1, and forced reset 4 is applied. As a result, charge accumulation begins in pixel block 200 in frame F(i+2). In this case, control block 400 drives pixel 201 in a way that prevents the input of reset 5.

[0260] As shown in Figure 30, when changing from 1 / 2 frame exposure to 1 frame exposure, the delay until the 1 frame exposure is reflected is reduced to 1 frame. This reduction is also true when changing from less than 1 / 2 frame exposure to 1 frame exposure.

[0261] Furthermore, even when changing from 1 frame exposure to 1 / 2 exposure or less, a forced reset is still input, but a reset is also input. For example, if an instruction to change from 1 frame exposure to 1 / 2 exposure or less is input to the control block 400 before the end of exposure value calculation i+1, the calculation result of exposure value calculation i+1 (for example, 1 / 2 frame exposure) will be reflected in the reset 5 that occurs first after the end of exposure value calculation i+1, and charge accumulation will begin in the pixel block 200 in frame F(i+2).

[0262] Figure 31 is an explanatory diagram showing example 2 of shortening the exposure time reflection period. In Figure 31, all pixels 201 within one pixel block 200 are controllable in each of K pixel regions (where K is an integer greater than or equal to 2). In Figure 31, the number of rows in one pixel block 200 is 32, the number of rows in one pixel block 200 is 8, and one control block 400 controls four pixel regions 3101 to 3104.

[0263] In Figure 30, exposure value calculation and exposure value reflection were not possible until the reading of 32 rows of pixel block 200 was completed. However, in Figure 31, once the reading of 8 rows of pixel region 3101 is completed, the control block 400 can perform exposure value calculation and reflect the exposure value for pixel region 3101, even if the reading of pixel regions 3102 to 3104 has not yet been completed.

[0264] In this way, even when controlling multiple pixel regions 3102 to 3104 with a single control block 400, the delay until the exposure of one frame is reflected is reduced to one frame, and data output for one frame exposure becomes possible for each pixel region 3101 to 3104 in the first or second readout frame.

[0265] Figure 32 is timing chart 1-1 when exposure time is changed, and Figure 33 is timing chart 1-2 when exposure time is changed. Figures 32 and 33 are timing charts in the example shown in Figure 29.

[0266] Figures 32 and 33 show that when 1 / 2 frame exposure starts for frame Fi and then changes to 1 frame exposure, the change to 1 frame exposure occurs in frame F(i+3), three frames after frame Fi.

[0267] Figure 34 is timing chart 2-1 when exposure time is changed, and Figure 35 is timing chart 2-2 when exposure time is changed. Figures 34 and 35 are timing charts in the example shown in Figure 30.

[0268] Figures 34 and 35 show that when 1 / 2 frame exposure starts for frame Fi and then changes to 1 frame exposure, the change to 1 frame exposure occurs in frame F(i+2), two frames after frame Fi. If 1 frame exposure continues from frame F(i+2) onward, only a forced reset will be triggered.

[0269] Figure 36 is the timing chart 3-1 when the exposure time is changed, Figure 37 is the timing chart 3-2 when the exposure time is changed, and Figure 38 is the timing chart 3-3 when the exposure time is changed. Figures 36 to 38 are timing charts for the case where a forced reset is driven as in Figure 30, and the exposure is changed from 1 frame to 1 / 2 frame.

[0270] For 1-frame exposure, forced resets 0 to 3 are driven for each frame N. When the exposure is changed to 1 / 2 frame exposure in frame N, 1 / 2 frame exposure reset 1 is driven for frame F(i+2) after the calculation of the exposure value for frame N is complete. Subsequently, 1 / 2 frame exposure reset 2 is driven for frame F(i+3) at the same timing. In Figure 38, both forced reset and 1 / 2 frame exposure reset are driven within one frame, but since the 1 / 2 frame exposure reset is driven after the forced reset, the forced reset is not reflected by the 1 / 2 frame exposure reset drive, and the exposure time becomes 1 / 2 frame exposure.

[0271] <Reading the exposure value outside the second semiconductor substrate 120> Next, the reading of the exposure value outside the second semiconductor substrate 120 will be described. There are two methods for reading the exposure value outside the second semiconductor substrate 120 in addition to the method of outputting from the shift register shown in FIGS. 23 to 25.

[0272] One is a method of reading the exposure value through a path different from the pixel signal (hereinafter, the image signal) for every 1 pixel block 200 and outputting it as the header of the image signal, which will be described in FIG. 39. The other is a method of reading the exposure value via the horizontal transfer line together with the digital pixel signal and outputting it outside the second semiconductor substrate 120 together with the image signal, which will be described in FIG. 41.

[0273] FIG. 39 is an explanatory diagram showing a method 1 for reading the exposure value outside the second semiconductor substrate 120. The horizontal transfer line 3900 is, for example, a 16-bit transfer line that connects each control block 400A and the digital signal processing circuit 2701. The data line 3901 connects the pixel control unit 401 of each control block 400A and the digital signal processing circuit 2701.

[0274] The digital pixel signal for each pixel 201 from the signal processing unit 402 of each control block 400A is output to the digital signal processing circuit 2701 by the horizontal transfer line 3900. The reading of the exposure value is through a path different from the horizontal transfer line 3900. Therefore, the signal line 4100 can output the exposure value at a lower frequency than the horizontal transfer line 3900.

[0275] The digital signal processing circuit 2701 assigns the exposure value from the signal line 4100 as the header (or footer) of the image signal and outputs the image data composed of the header and the image signal to the data processing unit 103. According to the configuration of FIG. 39, compared with the case of FIG. 41 described later, the amount of image data transmitted to the data processing unit 103 is reduced.

[0276] Figure 40 is an explanatory diagram showing method 2 for reading exposure values ​​outside the second semiconductor substrate 120. The horizontal transfer line 3900 is, for example, a 16-bit transfer line and connects each control block 400 to the digital signal processing circuit 2701. The digital pixel signal for each pixel 201 from the signal processing unit 402 of each control block 400 is output to the digital signal processing circuit 2701 via the horizontal transfer line 3900. The exposure value from the pixel control unit 401 of each control block 400 is output outside the second semiconductor substrate 120 via the horizontal transfer line 3900 at the same timing as the corresponding digital pixel signal.

[0277] The digital signal processing circuit 2701 is connected to the data processing unit 103 of the third semiconductor substrate 130 via the output IF 2703. The digital signal processing circuit 2701 embeds the exposure value from the pixel control unit 401 of the same control block 400 into the image signal from the signal processing unit 402 and outputs it to the data processing unit 103. For example, if the digital pixel signal for one pixel is 12 bits and the exposure value is 4 bits, it is output outside the second semiconductor substrate 120 as a 16-bit digital pixel signal.

[0278] In this way, since the exposure value is included in a portion of the digital pixel signal for one pixel, the data processing unit 103 can easily correct the exposure time for each pixel.

[0279] In Figures 39 and 40, in the case of control block 400B, instead of signal processing unit 402, signal processing unit 1602 outside the control circuit unit 210 is connected to the horizontal transfer line 3900, and the digital pixel signal for each pixel 201 from signal processing unit 1602 is output to the digital signal processing circuit 2701 via the horizontal transfer line 3900.

[0280] <Faster autonomous exposure control within the control block 400 and improved exposure control accuracy by switching exposure values ​​inside and outside the control block 400> Next, other examples of autonomous exposure control shown in Figure 23 will be explained using Figures 41 to 51. Figures 41 to 51 demonstrate the acceleration of autonomous exposure control within the control block 400 and exposure control by switching exposure values ​​inside and outside the control block 400. First, Figures 41 to 47 will be used to explain the acceleration of autonomous exposure control within the control block 400. Although Figures 41 to 47 use control block 400A as an example, it can also be implemented in control block 400B by arranging the same configuration as in signal processing unit 402 in signal processing unit 1602.

[0281] [High-speed autonomous exposure control within control block 400] Figure 41 is a block diagram illustrating an example of high-speed autonomous exposure control within the control block 400A. The control block 400A includes n ADCs 500 and an SRAM 4100, which is an example of a signal output unit 423. In Figure 41, for the sake of simplicity, only one ADC 500 is shown.

[0282] In this example, the pixel signal for each of the 201 pixels, digitally converted by the ADC500, is converted into a 13-bit digital pixel signal. This digital pixel signal is stored in the SRAM4100 and output to the peripheral circuit section 121 via the column selection circuit 2301 and the horizontal transfer line 2300, as shown in Figure 23. The upper 4 bits of the 13-bit digital pixel signal are output to the autonomous exposure processing unit 4101.

[0283] The autonomous exposure processing unit 4101 is connected to the selector 4103 in the exposure control unit 412. The exposure control unit 412 also includes a pixel block control unit 503, a level shift unit 504, and a latch circuit 2321, as well as a shift register 4102 and the selector 4103. The shift register 4102 holds the set exposure value.

[0284] The selector 4103 is connected to the shift register 4102 and the autonomous exposure processing unit 4101 on the input side, and to the latch circuit 2321 on the output side. Based on the selection signal, the selector 4103 selects either the set exposure value from the shift register 4102 or the exposure value from the autonomous exposure processing unit 4101. The selection signal is a signal that selects either the set exposure value or the exposure value from the autonomous exposure processing unit 4101. The selection signal is input to the selector 4103 from the external system described above. The exposure value selected by the selector 4103 is output to the latch circuit 2321.

[0285] Figure 42 is an explanatory diagram showing an example of a counter latch in Example 1 of High-Speed ​​Autonomous Exposure Control within Control Block 400A. The counter latch (storage unit) 502 holds a 13-bit digital pixel signal and outputs it to the SRAM 4100. In Figure 42, "x" represents "0" or "1". The hatched upper 4 bits of the digital signal are output to the autonomous exposure processing unit 4101 via the SRAM 4100.

[0286] Figure 43 is an explanatory diagram showing a specific example of autonomous exposure control in Example 1 of High-Speed ​​Autonomous Exposure Control within Control Block 400A. The autonomous exposure processing unit 4101 maintains a lookup table 4300. The lookup table 4300 is a table that associates the upper 4 bits 4301 with the exposure time 4302. For convenience, the range of values ​​that the 13-bit digital pixel signal can take to associate the upper 4 bits 4301 with the exposure time 4302 is indicated.

[0287] When the upper 4 bits signal is input from the SRAM 4100, the autonomous exposure processing unit 4101 refers to the lookup table 4300 to identify the upper 4 bits 4301 and reads out the corresponding exposure time 4302. The autonomous exposure processing unit 4101 outputs a 4-bit signal indicating the read exposure time 4302 to the selector 4103.

[0288] The shift register 4102 has a setting value table 4310 that associates setting values ​​4311 with exposure times 4312. The shift register 4102 outputs to the selector 4103 a setting value 4311 that matches a 4-bit input setting value from an external system, or a setting value 4311 that corresponds to an exposure time 4312 that matches the input exposure time, as the set exposure value.

[0289] Since it is important whether or not pixel 201 is saturated, a counter latch (hereinafter referred to as counter latch 502), which is an example of a memory unit 502, does not need to output all 13 bits of the digital pixel signal to the autonomous exposure processing unit 4101. Also, since the lower 9 bits contain noise, it is not important whether or not pixel 201 is saturated in those bits. Therefore, the autonomous exposure processing unit 4101 refers to the lookup table 4300 and identifies the exposure time 4302 using the upper 4 bits of the signal. This enables faster processing by the autonomous exposure processing unit 4101.

[0290] Next, we will describe Example 2 of speeding up autonomous exposure control within control block 400A. In Example 2 of speeding up autonomous exposure control within control block 400A, the exposure value is determined by using the higher bits of the digital pixel signal to select one of the following: maintain the previously output exposure value, increase it by one step, or decrease it by one step. The block configuration is the same as in Figure 41, so it will be omitted.

[0291] Figure 44 is an explanatory diagram showing an example of a counter latch 502 in Example 2 of High-Speed ​​Autonomous Exposure Control within the Control Block 400A. In Example 2, the counter latch 502 outputs the hatched upper 3 bits of the digital signal to the autonomous exposure processing unit 4101 via the SRAM 4100.

[0292] Figure 45 is an explanatory diagram showing a specific example of autonomous exposure control in Example 2 of High-Speed ​​Autonomous Exposure Control within Control Block 400A. The autonomous exposure processing unit 4101 maintains a lookup table 4500. The lookup table 4500 is a table that associates the upper 3 bits 4501 with the treatment 4502. For convenience, the range of values ​​that the 13-bit digital pixel signal can take, which associates the upper 3 bits 4501 with the treatment 4502, is indicated.

[0293] The autonomous exposure processing unit 4101 sets the value of the upper 3 bits 4501 of the lookup table 4500, which is "001" (corresponding to "keep" in the procedure 4502), as the reference value. The autonomous exposure processing unit 4101 also holds the setting value 4311 of the shift register for the first time, and for subsequent times, it holds the setting value output from the selector 4103 in the previous frame (referred to as the previous output value).

[0294] When the upper 3 bits signal is input from the SRAM 4100, the autonomous exposure processing unit 4101 refers to the lookup table 4500 to identify the upper 3 bits 4501 and reads the corresponding procedure 4502. The autonomous exposure processing unit 4101 updates the previous output value with the read procedure 4502.

[0295] Here, the previous output value is set to "0011". If the upper 3 bits 4501 are "000", then the action 4502 is "1 step up". In this case, the autonomous exposure processing unit 4101 increases the previous output value "0011" by 1 step to "0100" and outputs the updated setting value "0100" to the selector 4103.

[0296] Furthermore, if the upper three bits 4501 are "001", then the action 4502 is "keep", meaning maintain the current state. In this case, the autonomous exposure processing unit 4101 outputs the previous output value "0011" to the selector 4103. Also, if the upper three bits 4501 are, for example, "011", then the action 4502 is "1 step down". In this case, the autonomous exposure processing unit 4101 lowers the previous output value "0011" by one step to "0010", updates it, and outputs the updated setting value "0010" to the selector 4103.

[0297] Similar to application example 1, since it is important whether or not pixel 201 is saturated, the counter latch 502 does not need to output all 13 bits of the digital pixel signal to the autonomous exposure processing unit 4101. Also, since the lower 10 bits contain noise, it is not important whether or not pixel 201 is saturated.

[0298] Therefore, the autonomous exposure processing unit 4101 refers to the lookup table 4500 and executes the procedure 4502 with an exposure time of 4302 using the upper 3 bit signal. This enables faster processing by the autonomous exposure processing unit 4101.

[0299] In Example 2, the autonomous exposure processing unit 4101 performs a procedure 4502 that increases or decreases the exposure time 4312 by one stop, so 3 bits are sufficient for handling the higher bits instead of 4 bits. Therefore, the bit width transmitted from the counter latch 502 to the autonomous exposure processing unit 4101 can be reduced compared to Example 1.

[0300] Furthermore, the lookup table 4500 is just an example, and the ranges for 1-step up, keep, and 1-step down may be expanded or narrowed. Also, for example, the action 4502 for "1xx" in the upper 3 bits 4501 may be set to "2-step down". Additionally, any one of the values ​​"1-step up", "1-step down", and "keep" in action 4502 may be excluded.

[0301] Next, we will describe Example 3 of speeding up autonomous exposure control within the control block 400A. Unlike the above-mentioned examples 1 and 2, Example 3 of speeding up autonomous exposure control within the control block 400A is an example in which the analog pixel signal from the signal line 202 is output to the autonomous exposure processing unit 4101 to perform autonomous exposure control.

[0302] Figure 46 is a block diagram showing an example 3 of speeding up autonomous exposure control within the control block 400A. The autonomous exposure processing unit 4101 is connected to the signal line 202 of each pixel row of the pixel block 200. The autonomous exposure processing unit 4101 includes a comparator 4601, a 1-bit latch 4602, and a down counter 4603.

[0303] Figure 47 is a circuit diagram showing an example of comparator 4601. Comparator 4601 is a so-called CMOS inverter that compares the voltage of the analog pixel signal with a voltage threshold. The less charge accumulated in the photoelectric conversion unit 300, the higher the potential of the analog pixel signal flowing from the pixel 201 to the comparator 4601 via the signal line 202. When the voltage of the analog pixel signal exceeds the threshold voltage, comparator 4601 outputs "0" to the 1-bit latch 4602. The 1-bit latch 4602 then holds "0".

[0304] As the charge accumulated in the photoelectric conversion unit 300 increases, the analog pixel signal flowing from the pixel 201 to the comparator 4601 via the signal line 202 becomes lower in potential. When the voltage of the analog pixel signal falls below the threshold voltage, the comparator 4601 outputs "1" to the 1-bit latch 4602. The 1-bit latch 4602 then holds "1" and outputs it to the down counter 4603.

[0305] Returning to Figure 46, the down counter 4603 does not output a signal to the selector 4103 until it receives a 1-bit signal indicating "1" from the 1-bit latch 4602. This causes the selector 4103 to select the exposure value set in the shift register 4102 and output it to the latch circuit 2321. On the other hand, when the down counter 4603 receives a 1-bit signal indicating "1" from the 1-bit latch 4602, it lowers the setting value 4311, which is the exposure value set in the shift register 4102, by one step. For example, if the exposure value set is "0111" (setting value 4311), the shift register 4102 lowers it by one step from "0111" to "0110" and outputs it to the selector 4103 as the exposure value set. The selector 4103 selects the updated setting value "0110" and outputs it to the latch circuit 2321.

[0306] According to an example of using signal line 202, the saturation of pixel 201 is detected using the analog pixel signal before digital conversion, and the exposure time is autonomously shortened and controlled. This allows for faster processing compared to autonomous exposure control using the digital pixel signal.

[0307] Furthermore, if a 1-bit signal of "0" is input to the 1-bit latch 4602 multiple times in a row, the 1-bit latch 4602 may output a 1-bit signal indicating "1" to the down counter 4603. In this case, since the pixel 201 remains in a dark state, the down counter 4603 may control the set exposure value to increase by one stop.

[0308] [Exposure control by switching exposure values ​​inside and outside control block 400] Next, exposure control by switching exposure values ​​inside and outside the control block 400 will be explained using Figures 48 to 51. Exposure control by switching exposure values ​​inside and outside the control block 400 is performed by an external system.

[0309] Figure 48 is an explanatory diagram showing an example of exposure control 1 by switching the exposure value inside and outside the second semiconductor substrate 120. Exposure control example 1 aims to improve the accuracy of exposure by reducing the exposure time difference (step difference) between adjacent pixel blocks 200. The external system creates an exposure table 4810 for the image data 4800 obtained from the pixel section 101. The exposure table 4810 is a table that calculates the TV value for each pixel block 200. The TV value indicates the exposure time set for the pixel block 200.

[0310] The external system identifies locations where the step in TV values ​​exceeds a threshold at the boundary of one or more pixel blocks arranged in the column direction (pixel block column) or one or more pixel blocks arranged in the row direction (pixel block row). For example, in image data 4800, for example, in image region 4801 which includes a light-emitting filament and its black background, the step in TV values ​​exceeds a threshold at the boundary, and noise increases.

[0311] Therefore, the external system identifies the pixel block column or row at the boundary and updates it so that the step in TV values ​​does not exceed a threshold. In Figure 48, the step in TV values ​​between pixel block column 4812 (second column from the left) and pixel block column 4813 (third column from the left) in the exposure table 4810 exceeds the threshold, so pixel block columns 4812 and 4813 become the boundary. Then, the TV value of pixel block column 4813 (third column from the left) is updated. For example, the external system sets the average value (fractions can be rounded down or up) of each TV value in pixel block column 4812 (second column from the left) and each TV value in pixel block column 4814 (fourth column from the left) to the TV value of pixel block column 4813 (third column from the left).

[0312] Alternatively, the external system may set the TV value of the second column from the left, pixel block 4812, to the average value of each TV value in the first column from the left, pixel block 4811, and each TV value in the third column from the left, pixel block 4813 (fractions may be rounded down or up).

[0313] The external system writes the updated TV value to the shift register 4102 as the set exposure value for the control block 400 responsible for the pixel block 200 with the updated TV value, and outputs a selection signal to the selector 4103 to select the set exposure value from the shift register 4102. This makes it possible to obtain image data with reduced noise at the boundaries between light and dark areas.

[0314] Figure 49 is an explanatory diagram showing an example of exposure control 2 by switching the exposure value inside and outside the second semiconductor substrate 120. In exposure control example 2, when the phase of the light emission frequency, movement frequency, or rotation frequency of a subject such as a light-emitting element, moving element, or rotating element does not match the sampling frequency of the image sensor 100, exposure stabilization is achieved by switching from autonomous exposure control by the control block 400 to exposure control by an external system.

[0315] If the emission frequency, movement frequency, or rotation frequency of the subject does not match the sampling frequency of the image sensor 100, the brightness of a certain pixel block 200 will repeatedly fluctuate between bright and dark. Since the exposure value in the autonomous exposure processing unit is reflected with a 1-frame delay, when the brightness of a pixel block 200 is "bright", it becomes a long exposure value with a 1-frame delay, and that pixel block 200 will be overexposed in the captured image.

[0316] Furthermore, when the brightness of pixel block 200 is "dark," the exposure value becomes a short second with a 1-frame delay, and pixel block 200 becomes underexposed in the captured image. In this way, the phase mismatch between the subject frequency and the exposure value in pixel block 200 causes overexposure and underexposure to occur alternately, resulting in continuous oscillation.

[0317] In such cases, the external system detects the number of repetitions or duration of overexposure and underexposure for each pixel block 200, and outputs a selection signal to the selector 4103 for the pixel block 200 in which oscillation is detected, selecting a set exposure value from the shift register 4102. This prevents oscillation of overexposure and underexposure, and stabilizes the exposure of the pixel block 200. After exposure stabilization, the external system may output a selection signal to the selector 4103 for the exposure value from the autonomous exposure processing units 411 and 4101.

[0318] Figure 50 is an explanatory diagram showing exposure control example 3, which involves switching exposure values ​​inside and outside the control block 400. Exposure control example 3 optimizes exposure by setting for each pixel block 200 whether to apply autonomous exposure control within the control block 400 or exposure control by an external system.

[0319] For pixel blocks 200 (hereinafter referred to as the first pixel block 5001) where the number of defective pixels is less than or equal to the allowable number, the external system outputs a selection signal to the selector 4103 to select the exposure value obtained by the autonomous exposure processing unit 411. On the other hand, for pixel blocks 200 (hereinafter referred to as the second pixel block 5002) where the number of defective pixels is not less than or equal to the allowable number, or for pixel blocks 200 (hereinafter referred to as the third pixel block 5003) which include partially light-shielded AF pixels, the external system outputs a selection signal to the selector 4103 to select the set exposure value from the shift register 4102.

[0320] Furthermore, if a defective pixel is identified after shipment and the pixel block 200 is changed from the first pixel block 5001 to the second pixel block 5002, the external system will output a selection signal to the selector 4103 of the control block 400 responsible for that pixel block 200, to select the set exposure value from the shift register 4102.

[0321] Furthermore, for the second pixel block 5002 and the third pixel block 5003, whose number of defective pixels is known at the time of shipment, offset data is set in the autonomous exposure processing unit 411 of their control block 400. For the pixel block 200 to which the offset data has been set, the external system outputs a selection signal to the selector 4103 to select the exposure value obtained by the autonomous exposure processing unit 411.

[0322] Here, the offset data is a parameter used to correct the exposure value in the pixel block 200, and in the case of the second pixel block 5002, it is the position of the defective pixel. This allows the autonomous exposure processing unit 411 to exclude defective pixels in the preprocessing unit and calculate the maximum or average value of the digital pixel signal.

[0323] Furthermore, in the case of the third pixel block 5003, the offset data is the position and weight of the AF pixel. Since a portion of the light-receiving area of ​​the AF pixel is blocked, if the blocked area is half the original light-receiving area of ​​the AF pixel, the digital pixel signal from the AF pixel needs to be doubled, so the weight is 2.

[0324] Similarly, if the light-shielding area is 1 / 3 of the original light-receiving area of ​​the AF pixel, the digital pixel signal from the AF pixel needs to be tripled, so the weight is 3. Thus, the weight is the light-receiving area of ​​pixel 201 divided by the light-shielding area of ​​the AF pixel. Also, for the third pixel block 5003, similar to the second pixel block 5002, the offset data may be the position of the AF pixel. Furthermore, the autonomous exposure processing unit 411 may calculate the maximum or average value of the digital pixel signal after excluding the AF pixel in the pre-processing unit 2311.

[0325] Furthermore, if a defective pixel is identified after shipment and the pixel block 200 is changed from the first pixel block 5001 to the second pixel block 5002, the external system may set offset data for the defective pixel in the autonomous exposure processing unit 411 of the control block 400 responsible for that pixel block 200.

[0326] In this way, depending on the degree of pixel loss within the pixel block 200, it is possible to set whether to apply autonomous exposure control within the control block 400 or exposure control by an external system, thereby optimizing the exposure for each pixel block 200.

[0327] <Method for reading exposure values ​​for each of the 400 control blocks> Next, the method for reading the exposure value for each control block 400 will be explained. When generating an image by outputting the exposure value for each pixel block 200 to an external system, the external system outside the image sensor 100 needs to demodulate (gain) the digital image signal of each pixel 201 of the pixel block 200 based on the exposure value for each pixel block 200. In this case, the image sensor 100 sets additional information, including the image block ID and exposure value, to the digital image signal of each pixel 201 from the pixel block 200 (hereinafter referred to as the image signal of the pixel block 200) and outputs it to the external system.

[0328] When additional information is set to the image signal of the pixel block 200, the amount of data transmitted to the external system increases by the amount of additional information set, resulting in a decrease in communication speed and an increase in power consumption. Furthermore, as the size of the pixel block 200 decreases due to miniaturization of exposure control (the fewer pixels there are in one pixel block 200), the impact of decreased communication speed and increased power consumption becomes greater. The following describes a method for reading the exposure value for each control block 400 in order to suppress the decrease in communication speed and the increase in power consumption.

[0329] Figure 51 is an explanatory diagram showing an example 1 of reading the exposure value for each control block 400. The pixel portion 101 of the first semiconductor substrate 110 has an effective pixel region 5111 that receives subject light and an optical black pixel region 5112 formed around the effective pixel region 5111. The effective pixel region 5111 is composed of a plurality of pixel blocks 200 as described above.

[0330] The optical black pixel region 5112 is a collection of optical black pixels. An optical black pixel is a pixel 201 in which the light-receiving area that the photoelectric conversion unit 300 can receive light is shielded. Since no light is incident on an optical black pixel, the exposure time of an optical black pixel is uniquely determined by the incident time and does not depend on the amount of incident light. Also, like the effective pixel region 5111, the optical black pixel region 5112 is composed of multiple pixel blocks 200. The pixel blocks 200 within the optical black pixel region 5112 are referred to as OB pixel blocks 5120.

[0331] The shift register 4102 of the exposure control unit 412 of the control block 400 (hereinafter referred to as OB control block 5140) corresponding to one or more OB pixel blocks 5120 out of the total OB pixel blocks 5120 has an exposure value set as the set exposure value, which corresponds to the exposure time (for example, one of 1ms, 2ms, 4ms, ..., 100ms). The OB control block 5140 is connected to the control block 400 in a communication manner.

[0332] Furthermore, at least one reference pixel 5101 is provided within at least one pixel block 200 of all pixel blocks 200 within the effective pixel area 5111. The reference pixel 5101 is a pixel 201 in which the light-receiving area that the photoelectric conversion unit 300 can receive light is shielded, similar to an optical black pixel. Also, similar to an optical black pixel, no light is incident on the reference pixel 5101, so the exposure time of the optical black pixel does not depend on the amount of incident light and is uniquely determined by the incident time.

[0333] In the pixel block 200, each pixel 201 outputs a pixel signal to the control block 400. The preprocessing unit 2311 of the control block 400 calculates statistical values ​​of the pixel signal of the reference pixel 5101 (for example, mean, median, maximum, or minimum values; referred to as the reference pixel preprocessing result) and outputs them to the exposure value calculation unit 2313.

[0334] In each OB pixel block 5120, each optical black pixel outputs a pixel signal to the OB control block 5140. The pre-processing unit 2311 of each OB control block 5140 calculates the statistical value of the pixel signal of each optical black pixel (hereinafter referred to as the black pixel pre-processing result).

[0335] The exposure value calculation unit 2313 of the control block 400 acquires the black pixel preprocessing results from the preprocessing unit 2311 of each OB control block 5140. The exposure value calculation unit 2313 of the control block 400 then compares the reference pixel calculation result with each black pixel preprocessing result. The exposure value calculation unit 2313 of the control block 400 identifies the black pixel preprocessing result with the smallest difference from the reference pixel calculation result.

[0336] Then, the exposure value calculation unit 2313 of the control block 400 obtains the exposure value held by the OB control block 5140, which is the source of the calculation of the identified black pixel preprocessing result. The exposure value calculation unit 2313 of the control block 400 outputs the obtained exposure value to the exposure control unit 412.

[0337] In this way, by comparing the pixel signals from the reference pixel 5101 and the optical black pixel for each control block 400, the exposure value, which is uniquely determined by the incident time and independent of the amount of incident light, can be read. The control block 400 also includes the read exposure value in the digital pixel signal of each pixel 201 in the corresponding pixel block 200 and outputs it to an external system. This suppresses a decrease in communication speed and an increase in power consumption.

[0338] Furthermore, by arranging multiple reference pixels 5101 in a single pixel block 200, even if a reference pixel 5101 has a pixel defect, it can be compensated for by other reference pixels 5101. Also, the multiple reference pixels 5101 may be arranged in different rows or columns. This makes it possible to avoid pixel defects in multiple reference pixels 5101 arranged in the same row or column due to line defects within the pixel block 200. Additionally, the multiple reference pixels 5101 may be spaced apart. This allows the reference pixels 5101 to be compensated for by the digital pixel signals of their surrounding pixels.

[0339] Figure 52 is an explanatory diagram showing Example 2 of reading exposure values ​​for each control block 400. Unlike Example 1 shown in Figure 51, Example 2 is an example of reading exposure values ​​using control block 400.

[0340] Pixel block 200 has one or more reference pixels 5202. When multiple reference pixels 5202 are arranged, the exposure value (for example, Tv0 to Tv8) is set differently for each reference pixel 5202. In reading example 2, the exposure value of the pixel region 5200 excluding the reference pixels 5202 in pixel block 200 is determined by the exposure value obtained for the reference pixels 5202. Note that the reference pixels 5202 are not shielded from light, as shown in reference pixel 5101 in Figure 51.

[0341] In the control block 400, the autonomous exposure processing unit 411 obtains the digital pixel signal values ​​S0 to S8 from the reference pixel 5202 and the digital pixel signal value SP of the target pixel area 5200. The digital pixel signal value SP of the target pixel area 5200 is, for example, a statistical value of the digital pixel signals of all pixels 201 in the target pixel area 5200 excluding the reference pixel 5202.

[0342] Figure 53 is a block diagram showing a detailed block configuration example of control block 400 in Example 2 of reading exposure values ​​for each control block 400. In Figure 53, control block 400A is used as an example for explanation, but control block 400B can also be implemented by arranging the same configuration as the signal processing unit 402 in the signal processing unit 1602. Control block 400A includes a signal processing unit 402 (signal input unit 421, signal conversion unit 422, signal output unit 423), an autonomous exposure processing unit 411, an exposure control unit 412, a pixel driving unit 413, and a setting unit 5300.

[0343] The setting unit 5300 generates and outputs a reset signal (TX2) for each of the reference pixels 5202, which starts exposure at a different reset timing. Each of the reference pixels 5202 starts (or ends) exposure (accumulation in the photoelectric conversion unit 300) at the timing when it receives the reset signal from the setting unit 5300.

[0344] The autonomous exposure processing unit 411 identifies the digital pixel signal value of the reference pixel 5202 that has the smallest difference from the digital pixel signal value SP of the target pixel area 5200, from among S0 to S8. The autonomous exposure processing unit 411 sets the exposure value (for example, Tv0 to Tv8) set for the reference pixel 5202 that outputs the identified digital pixel signal value to the exposure value of the target pixel area 5200.

[0345] Each pixel 201 within the target pixel region 5200 will be reset according to the exposure value set by the autonomous exposure processing unit 411, as described above, for example, by starting exposure.

[0346] In this way, by reading the exposure value for each control block 400, the exposure value can be included in the digital pixel signal of each pixel 201 in the corresponding pixel block 200 and output to an external system. Therefore, a decrease in communication speed and an increase in power consumption can be suppressed.

[0347] Furthermore, multiple reference pixels 5202 set to the same exposure value may be placed in a single pixel block 200. This allows other reference pixels 5202 to compensate for any pixel defects in one reference pixel 5202. Additionally, multiple reference pixels 5202 may be placed in different rows or columns. This makes it possible to avoid pixel defects in multiple reference pixels 5202 placed in the same row or column due to line defects within the pixel block 200.

[0348] <Reduction of color shift in autonomous exposure control every 400 control blocks> In the image sensor 100, if any of the R, G, or B pixels become saturated, a color shift occurs during demosaicing and subsequent color image processing. For example, even if the average value of the digital pixel signals of all pixels 201 within a pixel block 200 is not saturated, the average value of any of the RGB single colors may be saturated. On the other hand, detecting saturation by separating the RGB single colors increases the complexity of the circuitry.

[0349] The image sensor 100 performs autonomous exposure control for each pixel block 200, but it is necessary to avoid image quality problems such as color shift. Here, we will describe an example of reducing color shift by setting an appropriate exposure time for each pixel block 200 so that each RGB color does not become saturated.

[0350] [Example of color shift reduction 1] Figure 54 is a block diagram showing an example of the internal configuration of the preprocessor 2311 in color shift reduction example 1. The preprocessor 2311 includes a comparator 5401 and a latch circuit 5402. The comparator 5401 receives the digital pixel signal from the pixel block 200 (hereinafter referred to as the first pixel signal) and the digital pixel signal latched by the latch circuit 5402 (hereinafter referred to as the second pixel signal), without distinguishing between R pixels, G pixels, and B pixels.

[0351] The comparator 5401 compares the first pixel signal and the second pixel signal, and outputs the pixel signal with the larger value to the latch circuit 5402.

[0352] The latch circuit 5402 resets itself internally with a reset pulse from the controller 2312, and then begins overwriting and saving the digital pixel signals from the comparator 5401. Before the next reset pulse is input, the latch circuit 5402 receives a timing signal from the controller 2312 indicating that all 200 minutes of digital pixel signals for a 1-pixel block have been input, and finally outputs the held digital pixel signal to the exposure value calculation unit 2313.

[0353] The digital pixel signal output to the exposure value calculation unit 2313 is a digital pixel signal that takes the maximum value in the pixel block 200 for each frame. This allows the control block 400 to calculate an appropriate exposure value for each pixel block 200 in which it is responsible, so that each RGB color does not become saturated for each frame. Therefore, color shift in the output image data from the image sensor 100 can be suppressed for each pixel block 200.

[0354] [Example of color shift reduction 2] Example 2 of color shift reduction is an example in which one or more white pixels are placed in pixel block 200. The white pixels are pixels 201 that have a transparent filter instead of a color filter 703.

[0355] Figure 55 is an explanatory diagram showing an example of a pixel block 200 in color shift reduction example 2. In Figure 55, R in pixel 201 indicates a red (R) pixel, B indicates a blue (B) pixel, Ga and Gb indicate green (G) pixels, and W indicates a white pixel. Pixel 201 with the left half black is an AF pixel. Since the letter within the AF pixel is W, that pixel 201 is both an AF pixel and a white pixel. There are also pixel blocks 200 that do not have AF pixels.

[0356] The preprocessor 2311 discards the digital pixel signals of R pixels, B pixels, Ga pixels, and Gb pixels. If only one white pixel is located in the pixel block 200, the preprocessor 2311 outputs the digital pixel signal of the white pixel to the exposure value calculation unit 2313. If two or more white pixels are located in the pixel block 200, the preprocessor 2311 calculates the maximum or average value of the digital pixel signals of the two or more white pixels and outputs it to the exposure value calculation unit 2313.

[0357] Since white pixels are not affected by color like R pixels, B pixels, Ga pixels, and Gb pixels, using the digital pixel signal of a white pixel for exposure control can suppress saturation of RGB monochromatic pixels in pixel block 200.

[0358] Furthermore, if AF pixels are included in the pixel block 200, the number of RGB pixels that need to be replaced with white pixels can be reduced by using AF pixels in conjunction with white pixels. In addition, multiple white pixels may be discretely arranged in the pixel block 200. In this case, multiple white pixels may be arranged in different rows or columns. This makes it possible to avoid pixel defects in multiple white pixels arranged in the same row or column due to line defects within the pixel block 200. Also, multiple white pixels may be spaced apart. This allows white pixels to be compensated for by the digital pixel signals of their surrounding pixels.

[0359] Furthermore, multiple white pixels may be pixels 201 with sensitivity adjusted by multiple stops. Specifically, for example, an ND filter or light-shielding metal may be used for the white pixels. When adjusting sensitivity with light-shielding metal, it may be set as an AF pixel. In this case, the width of the light-shielding metal in the row direction may be set wider as the principal ray angle of the lens increases. This improves the phase-detection accuracy of the AF pixels.

[0360] [Example 3 of reducing color shift] Since defective pixels within the pixel block 200 become saturated, if the preprocessing unit 2311 uses the digital pixel signal of the defective pixel for preprocessing, the exposure time will be set to a shorter duration. Therefore, in color shift reduction example 3, we will describe an example in which the preprocessing unit 2311 removes the digital pixel signal of the defective pixel.

[0361] Figure 56 is a block diagram showing an example of the internal configuration of the pre-processing unit 2311 in color shift reduction example 3. The pre-processing unit 2311 connects (d+1) data holding units in series, where d (d is an integer of 1 or more) is the number of defective pixels expected at the time of shipment. In Figure 56, an example is shown where d=2, and it has three stages of data holding units 5601, 5602, and 5603.

[0362] The data holding units 5601, 5602, and 5603 each have comparators 5611, 5621, and 5631, and latch circuits 5612, 5622, and 5632.

[0363] In the data holding unit 5601, the comparator 5611 receives the digital pixel signal from the pixel block 200 (hereinafter referred to as the first pixel signal) and the digital pixel signal latched by the latch circuit 5612 (hereinafter referred to as the second pixel signal), without distinguishing between R pixels, G pixels, and B pixels.

[0364] The comparator 5611 compares the first pixel signal and the second pixel signal and outputs the value of the pixel signal with the larger value to the latch circuit 5612. The latch circuit 5612 resets itself with a reset pulse from the controller 2312 and then starts overwriting and saving the digital pixel signals from the comparator 5611. Before the next reset pulse is input, the latch circuit 5402 receives a timing signal from the controller 2312 indicating that all 200 minutes of digital pixel signals for one pixel block have been input, and finally outputs the held digital pixel signal to the exposure value calculation unit 2313.

[0365] In other words, for a given frame, when the digital pixel signals of all pixels 201 within the pixel block 200 are input to the comparator 5611 as the first pixel signal, the digital pixel signal with the maximum value among the digital pixel signals of all pixels 201 is held in the latch circuit 5612.

[0366] In the data holding unit 5602, the comparator 5621 and the latch circuit 5622 perform the same operations as the comparator 5611 and the latch circuit 5612 for digital pixel signals that were not held by the latch circuit 5612.

[0367] As a result, when a digital pixel signal that was not held by the latch circuit 5612 in the pixel block 200 for a given frame is input to the comparator 5621 as the first pixel signal, the digital pixel signal with the maximum value among the digital pixel signals that were not held by the latch circuit 5612 will be held by the latch circuit 5622.

[0368] For the data holding unit 5603, the comparator 5631 and latch circuit 5632 perform the same operations as the comparator 5611 and latch circuit 5612 for digital pixel signals that were not held by the latch circuits 5612 and 5622.

[0369] As a result, when a digital pixel signal that was not held by the latch circuits 5612 and 5622 within the pixel block 200 for a given frame is input to the comparator 5631 as the first pixel signal, the digital pixel signal with the maximum value among the digital pixel signals that were not held by the latch circuits 5612 and 5622 will be held by the latch circuit 5632.

[0370] For a given frame, the maximum value of the digital pixel signal values ​​of all pixels 201 within the pixel block 200 is held in latch circuit 5612, the second largest value is held in latch circuit 5622, and the third largest value is held in latch circuit 5632.

[0371] Therefore, if the preprocessing unit 2311 wants to output the maximum value excluding d (=2) defective pixels, it will output the value of the digital pixel signal held in the latch circuit 5632 to the exposure value calculation unit 2313.

[0372] Furthermore, the output terminal of comparator 5621 is switchably connected to the input / output terminal of comparator 5631 and the average value calculation unit 5600 via switch 5610. Switch 5610 is controlled by controller 2312. When comparators 5621 and 5631 are connected via switch 5610, the value of the digital pixel signal held in the latch circuit 5632 is output to the exposure value calculation unit 2313 as described above.

[0373] When the comparator 5621 and the average value calculation unit 5600 are connected by the switch 5610, the average value calculation unit 5600 calculates the average value of the digital pixel signals that were not held by the latch circuits 5612, 5622, and 5632, and outputs the calculated average value to the exposure value calculation unit 2313.

[0374] This enables preprocessing that takes into account the number of defective pixels d, allowing for the removal of the digital pixel signals of defective pixels. Therefore, color shift in the output image data from the image sensor 100 can be suppressed for each pixel block 200.

[0375] [Example 4 of reducing color shift] Color shift reduction example 4 is a modification of color shift reduction example 3. In color shift reduction example 3, the circuit configuration of the pre-processing unit 2311 took into account the number of defective pixels d at the time of shipment, but in color shift reduction example 4, the configuration takes into account the number of defective pixels d not only at the time of shipment but also during calibration in use.

[0376] Figure 57 is a block diagram showing an example of the internal configuration of the image sensor 100 in color shift reduction example 4. In Figure 57, control block 400a controls pixel block 200a, control block 400b controls pixel block 200b, and control block 400c controls pixel block 200c. Control blocks 400a, 400b, and 400c are communicated together on the second semiconductor substrate 120.

[0377] Each control block 400a, 400b, and 400c comprises an autonomous exposure processing unit 411a, 411b, and 411c, an exposure control unit 412a, 412b, and 412c, and a storage unit 5700a, 5700b, and 5700c, respectively.

[0378] Here, pixel blocks 200a and 200c are assumed to have a number of defective pixels less than or equal to the allowable number t (where t is a non-negative integer), and pixel block 200b is assumed to have a number of defective pixels exceeding the allowable number. The allowable number t is a preset value. The memory units 5700a, 5700b, and 5700c store the number of defective pixels in pixel blocks 200a, 200b, and 200c. The initial value of the number of defective pixels is the value at the time of shipment and is set for each pixel block 200a, 200b, and 200c, but it can be updated by calibration during use.

[0379] Since pixel block 200b contains a number of defective pixels exceeding the allowable number t, control block 400b does not calculate the exposure value from the digital pixel signal from pixel block 200b, but instead obtains the exposure value calculated by one of the control blocks 400 of the adjacent pixel blocks 200a or 200c. For example, control block 400b obtains the exposure value calculated by the control block 400 that controls the adjacent pixel block 200 with the fewer defective pixels. In this way, by reusing the exposure values ​​of adjacent pixel blocks 200a and 200c, which have a number of defective pixels equal to or less than the allowable number, color shift in pixel block 200b can be suppressed.

[0380] In Figure 57, adjacent pixel blocks 200 refer to the pixel blocks 200a and 200c to the left and right of pixel block 200b, but may also include the pixel blocks 200 above and below, which are not shown. Alternatively, they may refer to the eight pixel blocks surrounding pixel block 200b.

[0381] Furthermore, if the number of defective pixels in any of the adjacent pixel blocks 200 exceeds the allowable number t, the control block 400b only needs to obtain the exposure value calculated by the control block 400 that controls the closest pixel block 200 among the pixel block groups separated by two or more pixel blocks and whose number of defective pixels is less than or equal to the allowable number t.

[0382] <Analysis of defects in the junction 610 between semiconductor substrates> Next, we will explain the defect analysis of bonding pads between semiconductor substrates. As a way to avoid yield reduction due to bonding defects at the bonding portions 610 between semiconductor substrates, there is a method of providing multiple bonding portions 610 for a single signal path passing through the semiconductor substrates. However, it is difficult to detect the bonding quality of each individual bonding portion 610.

[0383] In this example, a control switch is provided for each joint 610 that connects semiconductor substrates, and by switching the control switch, it is possible to verify the operation, thereby enabling failure analysis of the joint 610 between semiconductor substrates.

[0384] [Example of failure analysis of bonding pad 714 between semiconductor substrates in a pixel drive signal line] Figure 58 is a circuit diagram showing an example of failure analysis of a bonding pad 714 between semiconductor substrates in a pixel drive signal line. Multiple pixels 201 in the row direction of the first semiconductor substrate 110 and the pixel drive unit 413 of the second semiconductor substrate 120 are connected by a pixel drive signal line 5803. Multiple bonding portions 610A, 610B are provided at the interface 720 between the first semiconductor substrate 110 and the second semiconductor substrate 120.

[0385] The bonding portions 610A and 610B are each composed of a pair of bonding pads 714a and 714b. Bonding pad 714a is provided on the first semiconductor substrate 110, and bonding pad 714b is provided on the second semiconductor substrate 120. The pixel drive signal line 5803 has a signal path passing through bonding portion 610A and a signal path passing through bonding portion 610B.

[0386] On the second semiconductor substrate 120, a test circuit 5800 is provided between the two bonding pads 714b and the pixel driving unit 413. The test circuit 5800 has two switches 5801A and 5801B. Because the pixel control signal from the pixel driving unit 413 has a large amplitude, switches 5801A and 5801B are composed of CMOS switches. Furthermore, since the first semiconductor substrate 110 is composed of a pixel-dedicated process using only NMOS, switches 5801A and 5801B, which are composed of CMOS switches, are provided on the second semiconductor substrate 120.

[0387] Switch 5801A is provided between the pixel drive unit 413 and the junction unit 610A and is connected by the pixel drive signal line 5803. Switch 5801B is provided between the pixel drive unit 413 and the junction unit 610B and is connected by the pixel drive signal line 5803. In addition, the gate terminals of switches 5801A and 5801B are each connected to the pixel drive unit 413 by the switch control line 5802.

[0388] When a control signal is input from the pixel drive unit 413 to the gate terminal of switch 5801A, switch 5801A outputs the pixel drive signal from the pixel drive unit 413 to the junction unit 610A. When a control signal is input from the pixel drive unit 413 to the gate terminal of switch 5801B, switch 5801B outputs the pixel drive signal from the pixel drive unit 413 to the junction unit 610B.

[0389] During pre-shipment operational checks, a control signal is applied from the pixel drive unit 413 to the gate terminal of switch 5801A via the switch control line 5802, and it is confirmed that the pixel drive signal from the pixel drive unit 413 passes through the junction 610A and reaches multiple pixels 201 in the row direction. Similarly, a control signal is applied from the pixel drive unit 413 to the gate terminal of switch 5801B via the switch control line 5802, and it is confirmed that the pixel drive signal from the pixel drive unit 413 passes through the junction 610B and reaches multiple pixels 201 in the row direction.

[0390] If continuity is detected in at least one of the two signal paths passing through the junctions 610A and 610B of the pixel drive signal line 5803, the connection between the pixel drive unit 413 and the row of pixels 201 is determined to be good.

[0391] [Example of failure analysis of bonding pad 714 between semiconductor substrates on signal line 202] Figure 59 is a circuit diagram showing example 1 of failure analysis of a bonding pad 714 between semiconductor substrates in the signal line 202. The pixels 201 of the first semiconductor substrate 110 and the pixel driving unit 413 of the second semiconductor substrate 120 are connected by the signal line 202. The signal line 202 is shared by m pixels 201 in the column direction.

[0392] Similar to Figure 58, a plurality of bonding portions 610A and 610B are provided at the interface 720 between the first semiconductor substrate 110 and the second semiconductor substrate 120. Each bonding portion 610A and 610B is composed of a pair of bonding pads 714a and 714b. Bonding pad 714a is provided on the first semiconductor substrate 110, and bonding pad 714b is provided on the second semiconductor substrate 120. The signal line 202 has a signal path passing through bonding portion 610A and a signal path passing through bonding portion 610B.

[0393] The test circuit 5800 is provided, for example, in the signal input section 421. Considering the symmetry of the pixel structure and the number of transistors, it is preferable to provide the test circuit 5800 on the second semiconductor substrate 120. This is because if the test circuit 5800 is provided on the first semiconductor substrate 110, the pixel structure layout and the number of transistors will differ between the pixels 201 closest to the second semiconductor substrate 120 and the other pixels 201 in the column direction, resulting in a decrease in manufacturing yield.

[0394] Switch 5801A is located between the pixel drive unit 413 and the junction unit 610A and is connected by a signal line 202. Switch 5801B is located between the pixel drive unit 413 and the junction unit 610B and is connected by a signal line 202. The gate terminals of switches 5801A and 5801B are each connected to the pixel drive unit 413 by a switch control line 5802.

[0395] When a control signal is input from the pixel drive unit 413 to the gate terminal of switch 5801A, switch 5801A outputs the analog pixel signal from pixel 201 to the signal conversion unit 422 via the junction unit 610A. When a control signal is input from the pixel drive unit 413 to the gate terminal of switch 5801B, switch 5801B outputs the analog pixel signal from pixel 201 to the signal conversion unit 422 via the junction unit 610B.

[0396] During pre-shipment operational checks, a control signal is applied from the pixel drive unit 413 to the gate terminal of switch 5801A via the switch control line 5802, and it is confirmed that the analog pixel signal from pixel 201 passes through the junction 610A and reaches the signal conversion unit 422. Similarly, a control signal is applied from the pixel drive unit 413 to the gate terminal of switch 5801B via the switch control line 5802, and it is confirmed that the analog pixel signal from pixel 201 passes through the junction 610B and reaches the signal conversion unit 422.

[0397] If continuity is detected in at least one of the two signal paths passing through the junctions 610A and 610B of the signal line 202, the connection between the pixel 201 and the signal conversion unit 422 is determined to be good.

[0398] Figure 60 is a circuit diagram showing failure analysis example 2-1 of the bonding pad 714 between semiconductor substrates in the signal line 202. In failure analysis example 1 in Figure 59, the test circuit 5800 was provided on the second semiconductor substrate 120, but in failure analysis example 2-1 in Figure 60, the test circuit 5800 is provided on the first semiconductor substrate 110. This is effective when the circuit size of the second semiconductor substrate 120 increases. Specifically, for example, the first semiconductor substrate 110 has an FD shared pixel group 6000. The FD shared pixel group 6000 shares the FD 303 and the pixel output unit 305 with multiple (four in Figure 60) photoelectric conversion units 300.

[0399] The pixel output section 305 has an amplification section 351 and selection sections 352A and 352B, and constitutes the test circuit 5800. The selection sections 352A and 352B act as switches in the test circuit 5800. The junction section 610A connects the selection section 352A to the signal input section 421. The junction section 610B connects the selection section 352B to the signal input section 421.

[0400] When the selection control signal φSEL is input to the gate terminal of the selection unit 352A, the selection unit 352A outputs the analog pixel signal from the FD shared pixel group 6000 to the signal conversion unit 422 via the junction unit 610A. When the selection control signal φSEL is input to the gate terminal of the selection unit 352B, the selection unit 352B outputs the analog pixel signal from the FD shared pixel group 6000 to the signal conversion unit 422 via the junction unit 610B.

[0401] During pre-shipment operational checks, a selection control signal φSEL is applied only to the gate terminal of selection unit 352A, and it is confirmed that the analog pixel signal from the FD shared pixel group 6000 passes through the junction unit 610A and reaches the signal conversion unit 422. Similarly, a selection control signal φSEL is applied only to the gate terminal of selection unit 352B and it is confirmed that the analog pixel signal from the FD shared pixel group 6000 passes through the junction unit 610B and reaches the signal conversion unit 422.

[0402] If continuity is detected in at least one of the two signal paths passing through the junctions 610A and 610B of the signal line 202, the connection between the FD shared pixel group 6000 and the signal conversion unit 422 is determined to be good.

[0403] Figure 61 is a circuit diagram showing failure analysis example 2-2 of the bonding pad 714 between semiconductor substrates in the signal line 202. While failure analysis example 2-1 in Figure 60 described the case of the FD shared pixel group 6000, failure analysis example 2-2 in Figure 61 is an example where each pixel 201 has an ADC 500. In this case as well, if continuity is detected in at least one of the two signal paths passing through the bonding portions 610A and 610B of the signal line 202, the bonding between the pixel 201 and the signal conversion unit 422 is judged to be good.

[0404] [Example of failure analysis of bonding pads between semiconductor substrates when signal paths are shared between multiple circuits] Figure 62 is a circuit diagram showing an example of failure analysis of bonding pads between semiconductor substrates when signal paths are shared between multiple circuits. Figure 62 shows an example of failure analysis of bonding pads between semiconductor substrates 6200A and 6200B. If semiconductor substrate 6200A is the first semiconductor substrate 110, then semiconductor substrate 6200B is the second semiconductor substrate 120, and if semiconductor substrate 6200A is the second semiconductor substrate 120, then semiconductor substrate 6200B is the third semiconductor substrate 130.

[0405] The semiconductor substrate 6200A has circuits A1 and A2. If the semiconductor substrate 6200A is the first semiconductor substrate 110, then circuits A1 and A2 are, for example, pixels 201. If the semiconductor substrate 6200A is the second semiconductor substrate 120, then circuits A1 and A2 are, for example, ADC 500.

[0406] The semiconductor substrate 6200B has circuits B1 and B2. If the semiconductor substrate 6200B is the first semiconductor substrate 110, then circuits B1 and B2 are, for example, ADC 500. If the semiconductor substrate 6200B is the third semiconductor substrate 130, then circuits B1 and B2 are, for example, digital circuits within the data processing unit 103.

[0407] Bonding portions 6201P, 6201Q, 6202P, and 6202Q are provided at the interface 6210 between the first semiconductor substrate 110 and the second semiconductor substrate 120. Each of the bonding portions 6201P, 6201Q, 6202P, and 6202Q is composed of a pair of bonding pads 714a and 714b. Bonding pad 714a is provided on semiconductor substrate 6200A, and bonding pad 714b is provided on semiconductor substrate 6200B.

[0408] A test circuit 6220 is provided between semiconductor substrates 6200A and 6200B, separated by the interface surface 6210. The test circuit 6220 includes a first test circuit 6221 for performing failure analysis of a pair of bonding pads 714a and 714b between circuits A1 and B1, a second test circuit 6222 for performing failure analysis of a pair of bonding pads 714a and 714b between circuits A2 and B2, and a connecting wire 6223 that connects the first test circuit 6221 and the second test circuit 6222.

[0409] The first test circuit 6221 is a circuit in which switches SW1A1 and SW1B1, which are connected in series between circuits A1 and B1 via junction 6201P, and switches SW1A2 and SW1B2, which are connected in series between circuits A1 and B1 via junction 6201Q, are connected in parallel.

[0410] The second test circuit 6222 is a circuit in which switches SW2A1 and SW2B1, which are connected in series between circuits A2 and B2 via junction 6202P, and switches SW2A2 and SW2B2, which are connected in series between circuits A2 and B2 via junction 6202Q, are connected in parallel.

[0411] The connection wiring 6223 connects switch SW1A2 of the first test circuit 6221 to switch SW2A1 of the second test circuit 6222 on semiconductor substrate 6200A, and connects switch SW1B2 of the first test circuit 6221 to switch SW2B1 of the second test circuit 6222 on semiconductor substrate 6200B.

[0412] In Figures 62 and 63, the path following circuit A1, switch SW1A1, junction 6201P, switch SW1B1, and circuit B1 is referred to as the first wiring. The path following circuit A1, switch SW1A1, junction 6201Q, switch SW1B1, and circuit B1 is referred to as the second wiring. The path following circuit A2, switch SW2A1, junction 6202P, switch SW2B1, and circuit B2 is referred to as the third wiring. The path following circuit A2, switch SW2A2, junction 6202Q, switch SW2B2, and circuit B2 is referred to as the fourth wiring.

[0413] In the first test circuit 6221, by turning ON the gates of switches SW1A1 and SW1B1, and turning OFF the gates of switches SW1A2 and SW1B2, a fault analysis of the junction 6201P is performed to determine whether or not there is continuity between circuits A1 and B1 of the first wiring.

[0414] Similarly, by turning ON the gates of switches SW1A2 and SW1B2, and OFF the gates of switches SW1A1 and SW1B1, a fault analysis of junction 6201Q is performed to determine whether or not there is continuity between circuits A1 and B1 of the second wiring.

[0415] In the second test circuit 6222, by turning ON the gates of switches SW2A1 and SW2B1, and turning OFF the gates of switches SW2A2 and SW2B2, a fault analysis of the junction 6202P is performed to determine whether or not there is continuity between circuits A2 and B2 of the third wiring.

[0416] Similarly, by turning ON the gates of switches SW2A2 and SW2B2, and OFF the gates of switches SW2A1 and SW2B1, a fault analysis of junction 6202Q is performed to determine whether or not there is continuity between circuits A2 and B2 of the fourth wiring.

[0417] Figure 63 is a circuit diagram showing an example of settings after failure analysis of junction pads between semiconductor substrates when multiple circuits share a signal path. Suppose that, for example, a junction failure is detected at junctions 6202P and 6202Q based on the failure analysis in Figure 62. In this case, signal transmission between circuits A2 and B2 is not possible in the third and fourth wirings of the second test circuit 6222. Therefore, in the first test circuit 6221, switches SW1A1 and SW1B1 are turned ON to enable transmission between circuits A1 and B1 via the first wiring 6301.

[0418] Furthermore, the first test circuit 6221 turns off switches SW1A2 and SW1B2, the second test circuit 6222 turns on switches SW2A1 and SW2B1 and turns off switches SW2A2 and SW2B2, and the connecting wiring 6223 turns on switches SW3A and SW3B. This allows transmission between circuits A2 and B2 via a detour path 6302 that passes through the junction 6001Q which passed the failure analysis. In this way, by reusing the paths of adjacent circuits, it is possible to avoid poor conductivity when the junction pad 714 is faulty.

[0419] [Example of failure analysis of bonding pads between semiconductor substrates when multiple circuits share a bonding area] Figure 64 is a circuit diagram showing example 1 of failure analysis of bonding pads between semiconductor substrates when multiple circuits share a bonding point, and Figure 65 is a circuit diagram showing example 2 of failure analysis of bonding pads between semiconductor substrates when multiple circuits share a bonding point. Figures 64 and 65 have the same circuit configuration, but the bonding points where defects were detected are different. First, the circuit configurations of Figures 64 and 65 will be explained.

[0420] The test circuit 6400 has switches SW1, SW2, and SW3 on semiconductor substrate 6200A, and switches SW4, SW5, and SW6 on semiconductor substrate 6200B. Bonding portions 6401 to 6403 are provided on the interface surface 6210.

[0421] Switch SW1 switches between the connection between circuit A1 and the junction pad 714a of junction 6401, and the connection between another circuit (not shown) and the junction pad 714a of junction 6401.

[0422] Switch SW2 switches between the connection between circuit A1 and the bonding pad 714a of junction 6403, and the connection between circuit A2 and the bonding pad 714a of junction 6403.

[0423] Switch SW3 switches between the connection between circuit A2 and the junction pad 714a of junction 6402, and the connection between another circuit (not shown) and the junction pad 714a of junction 6402. do.

[0424] Switch SW4 switches between the connection between circuit B1 and the junction pad 714a of junction 6401, and the connection between another circuit (not shown) and the junction pad 714b of junction 6401.

[0425] Switch SW5 switches between the connection between circuit B1 and the junction pad 714b of junction 6403, and the connection between circuit B2 and the junction pad 714b of junction 6403.

[0426] Switch SW6 switches between the connection between circuit B2 and the junction pad 714b of junction 6402, and the connection between another circuit (not shown) and the junction pad 714b of junction 6402.

[0427] In Figures 64 and 65, the path following circuit A1, switch SW1, junction 6401, switch SW4, and circuit B1 is referred to as the first wiring. The path following circuit A2, switch SW3, junction 6402, switch SW6, and circuit B2 is referred to as the second wiring.

[0428] The path following circuit A1, switch SW2, junction 6403, switch SW5, and circuit B1 is referred to as the third wiring. The path following circuit A1, switch SW2, junction 6403, switch SW5, and circuit B2 is referred to as the fourth wiring.

[0429] The path following circuit A2, switch SW2, junction 6403, switch SW5, and circuit B1 is referred to as the fifth wiring. The path following circuit A2, switch SW2, junction 6403, switch SW5, and circuit B2 is referred to as the sixth wiring.

[0430] In Figure 64, assume that a faulty connection is detected at junction 6401 by fault analysis using test circuit 6400. In this case, switches SW1 and SW4 are left unconnected, and switch SW2 is used to connect circuit A1 to junction pad 714a of junction 6403, and switch SW5 is used to connect circuit B1 to junction pad 714b of junction 6403, thereby forming a third wiring.

[0431] Furthermore, a second wiring is formed by connecting circuit A2 to the junction pad 714a of junction 6402 with switch SW3, and connecting circuit B2 to the junction pad 714b of junction 6402 with switch SW6.

[0432] As a result, signals are transmitted between circuits A1 and B1 via the third wiring through junction 6403, and between circuits A2 and B2 via the second wiring through junction 6402.

[0433] In Figure 65, assume that a faulty connection is detected at junction 6403 by fault analysis using test circuit 6400. In this case, switches SW2 and SW5 are left unconnected, and the first wiring is formed by connecting circuit A1 to junction pad 714a of junction 6401 with switch SW1, and connecting circuit B1 to junction pad 714b of junction 6401 with switch SW4.

[0434] Furthermore, a second wiring is formed by connecting circuit A2 to the junction pad 714a of junction 6402 with switch SW3, and connecting circuit B2 to the junction pad 714b of junction 6402 with switch SW6.

[0435] As a result, signals are transmitted between circuits A1 and B1 via the junction 6401 through the first wiring, and between circuits A2 and B2 via the junction 6403 through the second wiring.

[0436] In this way, faulty connections at the junctions 6401 to 6403 between semiconductor substrates 6200A and 6200B can be detected, and signal transmission can be performed using the approved junctions.

[0437] Figure 66 is a block diagram showing an example configuration of an imaging device 6600 according to an embodiment. The imaging device 6600 comprises an image sensor 100, a system control unit 6601, a drive unit 6602, a photometering unit 6603, a work memory 6604, a recording unit 6605, a display unit 6606, an operation unit 6608, a drive unit 6614, and a photographic lens 6620.

[0438] The imaging lens 6620 guides the subject light beam incident along the optical axis OA to the image sensor 100. The imaging lens 6620 is composed of multiple optical lens groups and forms an image of the subject light beam from the scene near its focal plane. The imaging lens 6620 may be an interchangeable lens that can be attached to and detached from the imaging device 6600. In Figure 66, the imaging lens 6620 is represented by a single hypothetical lens positioned near the pupil.

[0439] The drive unit 6614 drives the photographic lens 6620. For example, the drive unit 6614 moves the optical lens group of the photographic lens 6620 to change the focus position. The drive unit 6614 may also drive the iris diaphragm within the photographic lens 6620 to control the amount of light beam incident on the image sensor 100.

[0440] The drive unit 6602 has a control circuit that performs charge accumulation control such as timing control and area control of the image sensor 100 according to instructions from the system control unit 6601. The operation unit 6608 receives instructions from the imager via a release button or the like.

[0441] The image sensor 100 passes pixel signals to the image processing unit 6611 of the system control unit 6601. The image processing unit 6611 uses the work memory 6604 as a workspace to generate image data after performing various image processing steps. For example, when generating image data in JPEG file format, it generates a color video signal from the signal obtained by the Bayer array and then performs compression processing. The generated image data is recorded in the recording unit 6605 and converted into a display signal, which is then displayed in the display unit 6606 for a preset time.

[0442] The photometering unit 6603 detects the brightness distribution of the scene prior to a series of shooting sequences that generate image data. The photometering unit 6603 includes, for example, an AE sensor of about 1 million pixels. The calculation unit 6612 of the system control unit 6601 receives the output of the photometering unit 6603 and calculates the brightness of each region of the scene.

[0443] The calculation unit 6612 determines the shutter speed, aperture value, and ISO sensitivity according to the calculated luminance distribution. The photometering unit 6603 may also be integrated into the image sensor 100. The calculation unit 6612 also performs various calculations for operating the imaging device 6600. The drive unit 6602 may be partially or entirely mounted on the image sensor 100. Part of the system control unit 6601 may also be mounted on the image sensor 100.

[0444] It should be noted that the present invention is not limited to the above, and may be combined in any way. Furthermore, other embodiments that can be conceivable within the scope of the technical idea of ​​the present invention are also included in the scope of the present invention. [Explanation of Symbols]

[0445] 100, 100A, 100B Image sensor, 101 Pixel section, 102 Control circuit section, 103 Data processing section, 110 First semiconductor substrate, 120 Second semiconductor substrate, 121 Peripheral circuit section, 130 Third semiconductor substrate, 200 Pixel block, 201 Pixel, 202 Signal line, 210 Pixel group, 300 Photoelectric conversion section, 301 Transfer section, 302 Output section, 304 Reset section, 305 Pixel output section, 306 Load current source, 310 Readout section, 351 Amplification section, 352 Selection section, 400, 400A, 400B Control block, 401 Pixel control section, 402 Signal transfer section, 411 Autonomous exposure processing section, 412 Exposure control section, 413 Pixel drive section, 421 Signal input section, 422 Signal processing section, 423 Signal output section< / m>

Claims

[Claim 1] A first semiconductor substrate having a pixel section including: a first photoelectric conversion unit that converts light into electric charge; a second photoelectric conversion unit that converts light into electric charge and is arranged in the row direction alongside the first photoelectric conversion unit; a first transfer unit that transfers the charge converted by the first photoelectric conversion unit; a second transfer unit that transfers the charge converted by the second photoelectric conversion unit; a first storage unit that stores the charge transferred from the first photoelectric conversion unit by the first transfer unit; a second storage unit that stores the charge transferred from the second photoelectric conversion unit by the second transfer unit; a first output unit that outputs a first signal based on the charge transferred to the first storage unit to a first signal line and has a first selection unit electrically connected to the first signal line; and a second output unit that outputs a second signal based on the charge transferred to the second storage unit to a second signal line and has a second selection unit electrically connected to the second signal line. A semiconductor substrate laminated with the first semiconductor substrate, comprising: a first exposure processing unit that uses the first signal to calculate a first evaluation value relating to the storage time for storing the charge converted by the first photoelectric conversion unit; a second exposure processing unit that uses the second signal to calculate a second evaluation value relating to the storage time for storing the charge converted by the second photoelectric conversion unit; a first pixel driving unit that outputs a first transfer control signal for controlling the first transfer unit based on the first evaluation value; a second pixel driving unit that outputs a second transfer control signal for controlling the second transfer unit based on the second evaluation value; and a driving unit that outputs a selection control signal for controlling the first selection unit and the second selection unit, The first transfer unit is electrically connected to the first transfer control line from which the first transfer control signal is output. The second transfer unit is electrically connected to the second transfer control line from which the second transfer control signal is output. The first selection unit and the second selection unit are electrically connected to the selection control line on which the selection control signal is output. Image sensor.

Images