Non-oxide dielectric spacers for resistive random access memory

Abstract

This prevents the lower electrode sidewall from being exposed to oxygen after the formation of a resistive random-access memory (RRAM) cell. [Solution] In the integrated circuit device 200, the RRAM cell 143A is surrounded by a non-oxide dielectric layer 111A that protects the lower electrode 131 from oxygen-induced damage during the formation of the interlayer dielectric 107. The non-oxide dielectric layer may also function as a second spacer positioned on a first spacer 117 surrounding the upper electrode 137. The first spacer may provide a lateral offset between the sidewall of the lower electrode and the sidewall of the upper electrode. The non-oxide dielectric layer is particularly beneficial in embodiments in which the resistive switching structure 205 is sensitive to oxygen intrusion originating from the lower electrode.

Description

[Background technology]

[0001] Many modern electronic devices include electronic memory configured to store data. Electronic memory can be volatile or non-volatile. Volatile memory stores data while power is supplied, while non-volatile memory can retain data when power is off. Resistive random-access memory (RRAM) is one of the promising candidates for next-generation non-volatile memory due to its simple structure and compatibility with complementary metal-oxide-semiconductor (CMOS) processes. RRAM cells include a resistive switching structure with variable resistance. The resistive switching structure is typically located between two electrodes placed within a metal interconnect structure. [Overview of the project] [Problems that the invention aims to solve]

[0002] The integrated circuit may include a resistive random-access memory (RRAM) cell having a resistive switching structure positioned between an upper electrode and a lower electrode. The resistive switching structure can be reversibly switched between a high-resistance state (HRS) and a low-resistance state (LRS) using current pulses. The distinction between HRS and LRS provides the basis for data coding. Read operations can use a voltage lower than the programming voltage, allowing detection without changing the state of the RRAM cell.

[0003] Before an RRAM cell is used to store data, initial conductive filaments are typically formed across the resistive switching structure. The formation of these initial conductive filaments facilitates subsequent programming operations. The initial conductive filaments are formed by pulsed forming voltage between the upper and lower electrodes.

[0004] In some types of RRAM cells, the resistive switching structure contains a metal oxide, and the conductive filament is formed by oxygen vacancies within the metal oxide structure. In these types of RRAM cells, a forming voltage pulse can break the metal oxide bonds, releasing oxygen ions. The released oxygen ions move toward the upper electrode, where some are absorbed. The movement of oxygen ions leaves behind oxygen vacancies. Since new oxygen vacancies form more easily adjacent to existing ones, the oxygen vacancies tend to align, forming conductive filaments that continuously extend the resistive switching structure.

[0005] After the initial conductive filaments are formed, the RRAM cell can be switched between HRS and LRS using a voltage lower than the forming voltage. During the reset operation, oxygen ions are driven to return roughly to their original positions, preventing the conductive filaments from moving anymore. During the set operation, oxygen ions are again driven towards and into the upper electrode, re-establishing the conductive filaments.

[0006] The driving force behind increasing integrated circuit device density has led to a long-standing need to make RRAM cells smaller. One approach to achieving this involves providing them with a non-planar structure by forming RRAM cell stacks on holes or recesses within a dielectric layer. The resulting lower electrodes, resistive switching structures, and upper electrodes of the RRAM cell may each have a central recess on the hole or recess. This structure increases the electric field strength in the central region, helps to better confine the area where the conductive filament is formed, and allows the edges of the RRAM cell to be closer to its center. Providing tapered profiles on the sidewalls enhances these benefits by reducing the electric field strength at the edges of the cell.

[0007] The inventors have found that, under certain circumstances, such as when the RRAM cell is very small and has tapered sidewalls, exposure of the lower electrode sidewall to oxygen after RRAM cell formation can cause significant damage. This damage can occur by altering the shape of the lower electrode edge or by incorporating oxygen into its composition, which adversely affects the performance of the RRAM cell. [Means for solving the problem]

[0008] The present invention provides an integrated circuit device in several embodiments. The integrated circuit device is A metal interconnect structure comprising a plurality of metallization layers disposed on a semiconductor substrate and separated by via layers, wherein each metallization layer includes a conductive trace surrounded by an interlayer dielectric (ILD), and each via layer includes conductive vias that interconnect the conductive traces and are surrounded by the interlayer dielectric, and A resistive random access memory (RRAM) cell comprising a lower electrode, an upper electrode, and a resistive switching structure located between the lower electrode and the upper electrode, integrated within the metal interconnect structure, The device includes a non-oxide dielectric layer that surrounds the lower electrode and provides a physical barrier between the lower electrode and the interlayer dielectric.

[0009] The present invention provides an integrated circuit device in several embodiments. The integrated circuit device is A metal interconnect structure disposed on a semiconductor substrate, wherein the metal interconnect structure includes a plurality of metallization layers separated by via layers, each metallization layer includes a conductive trace surrounded by an interlayer dielectric (ILD), and each via layer includes conductive vias that interconnect the conductive traces and are surrounded by the interlayer dielectric, and the metal interconnect structure, A resistive random access memory (RRAM) cell comprising a lower electrode, an upper electrode, and a resistive switching structure located between the lower electrode and the upper electrode, wherein the RRAM cell is integrated within the metal interconnect structure, and the upper surface of the upper electrode includes a tapered recess, A first spacer is positioned on the upper surface of the resistive switching structure and along the outer side wall of the upper electrode, The system includes a second dielectric layer that surrounds the lower electrode, provides a physical barrier between the lower electrode and the interlayer dielectric, and is of a type that can be formed by an oxygen-free deposition process.

[0010] In some embodiments, the present invention provides a method for manufacturing an integrated circuit device. The method is as follows: Forming a metallization layer containing conductive traces on the surface of a semiconductor substrate, Depositing a dielectric layer on the metallization layer, To form the holes penetrating the dielectric layer so that the conductive traces are exposed through the holes, The lower electrode layer, the resistive switching structure, and the upper electrode layer are deposited on the dielectric layer and the holes, such that each of them has a central recess above the holes. Forming a hard mask on the upper electrode layer, A first etching process is performed to define the upper electrode by etching through the upper electrode layer, By forming a side wall spacer around the upper electrode, Using a second etching process to etch through the lower electrode layer to define the lower electrode and expose the lower electrode sidewall, wherein either the first etching process or the second etching process etches through the resistive switching structure to define the resistive switching structure, and the lower electrode, the upper electrode, and the resistive switching structure together provide a resistive random access memory (RRAM) cell, The process involves depositing a non-oxide dielectric layer on the lower electrode sidewall using a substantially oxygen-free deposition process, The non-oxide dielectric layer is deposited in such a way as to protect the lower electrode from oxidation during the deposition of the interlayer dielectric (ILD), Includes. [Effects of the Invention]

[0011] According to the present invention, by forming a non-oxide dielectric layer on the sidewall before subsequent processing in an oxidizing environment, such as the process of forming an interlayer dielectric, damage that adversely affects the performance of the RRAM cell is prevented. [Brief explanation of the drawing]

[0012] Aspects of the present invention are best understood from the following detailed description, which is to be read together with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not depicted to scale. In fact, the dimensions of various features may be arbitrarily enlarged or reduced for clarity of discussion.

[0013] [Figure 1] This is a cross-sectional view of an integrated circuit device according to various embodiments. The device includes a resistive random-access memory (RRAM) cell having a lower electrode protected by a non-oxide dielectric layer, as taught by the present invention. [Figure 2]A cross-sectional view of an integrated circuit device according to various embodiments. The device includes a resistive random access memory (RRAM) cell having a lower electrode protected by a non-oxide dielectric layer, as taught by the present invention. [Figure 3] A cross-sectional view showing a larger portion of the integrated circuit device of FIG. 2, according to various embodiments. [Figure 4] A cross-sectional view showing a larger portion of the integrated circuit device of FIG. 2, according to various embodiments. [Figure 5] An enlarged view of a portion of the RRAM cell of FIG. 2, according to one embodiment. [Figure 6] A cross-sectional view of an additional integrated circuit device according to another embodiment. This device includes a resistive random access memory (RRAM) cell having a lower electrode protected by a non-oxide dielectric layer, as taught by the present invention. [Figure 7] A cross-sectional view of an additional integrated circuit device according to another embodiment. This device includes a resistive random access memory (RRAM) cell having a lower electrode protected by a non-oxide dielectric layer, as taught by the present invention. [Figure 8] A cross-sectional view of an integrated circuit device being manufactured according to one embodiment of the present invention. [Figure 9] A cross-sectional view of an integrated circuit device being manufactured according to one embodiment of the present invention. [Figure 10] A cross-sectional view of an integrated circuit device being manufactured according to one embodiment of the present invention. [Figure 11] A cross-sectional view of an integrated circuit device being manufactured according to one embodiment of the present invention. [Figure 12] A cross-sectional view of an integrated circuit device being manufactured according to one embodiment of the present invention. [Figure 13] A cross-sectional view of an integrated circuit device being manufactured according to one embodiment of the present invention. [Figure 14] A cross-sectional view of an integrated circuit device being manufactured according to one embodiment of the present invention. [Figure 15] This is a cross-sectional view of an integrated circuit device being manufactured according to one embodiment of the present invention. [Figure 16] This is a cross-sectional view of an integrated circuit device being manufactured according to one embodiment of the present invention. [Figure 17] This is a cross-sectional view of an integrated circuit device being manufactured according to one embodiment of the present invention. [Figure 18] This is a cross-sectional view of an integrated circuit device during the manufacturing stage according to another embodiment. [Figure 19] This is a cross-sectional view of an integrated circuit device during the manufacturing stage according to another embodiment. [Figure 20] This is a cross-sectional view of an integrated circuit device during the manufacturing stage according to another embodiment. [Figure 21] This is a cross-sectional view of an integrated circuit device during the manufacturing stage according to another embodiment. [Figure 22] This is a cross-sectional view of an integrated circuit device during the manufacturing stage according to another embodiment. [Figure 23] This is a cross-sectional view of an integrated circuit device during the manufacturing stage according to another embodiment. [Figure 24] This is a cross-sectional view showing a modified version of the process shown in Figures 18-23, according to another embodiment. [Figure 25] This is a cross-sectional view showing a modified version of the process shown in Figures 18-23, according to another embodiment. [Figure 26] This is a cross-sectional view of an integrated circuit device during the manufacturing stage according to another embodiment. [Figure 27] This is a cross-sectional view of an integrated circuit device during the manufacturing stage according to another embodiment. [Figure 28] This is a cross-sectional view of an integrated circuit device during the manufacturing stage according to another embodiment. [Figure 29] This is a cross-sectional view of an integrated circuit device during the manufacturing stage according to another embodiment. [Figure 30] This is a cross-sectional view of an integrated circuit device during the manufacturing stage according to another embodiment. [Figure 31]This is a cross-sectional view of an integrated circuit device during the manufacturing stage according to another embodiment. [Figure 32] This flowchart shows a method for forming and protecting an RRAM cell according to several embodiments. [Modes for carrying out the invention]

[0014] The present invention provides many different embodiments or examples for implementing different features of the invention. Specific examples of components and arrangements are described below for the sake of brevity of the invention. These are, of course, merely examples and are not intended to be limiting. For example, forming a first feature on or above a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, or it may include embodiments in which an additional feature is formed between the first and second features so that the first and second features are not in direct contact. Furthermore, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity and does not in itself determine the relationships between the various embodiments and / or configurations discussed.

[0015] Furthermore, spatial relative terms such as "below," "downward," "lower," "above," and "higher" may be used herein for ease of description to describe the relationship between one element or feature and another, as shown in the figures. Spatial relative terms are intended to encompass different orientations of the apparatus in use or operation, in addition to the orientation depicted in the figures. The apparatus may be in other orientations (90-degree rotation or other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0016] In some embodiments, the RRAM cell is formed by a process that includes forming an RRAM cell stack and performing a two-step etching. The RRAM cell stack includes a lower electrode layer, an RRAM switching layer, an upper electrode layer, and often a hard mask layer. Any of these layers may include multiple sublayers. The first step of etching patterns the upper electrode layer to define the upper electrode and stops on, within, or on the RRAM switching layer or the lower electrode layer. Next, sidewall spacers are formed around the upper electrode. The second step of etching, if not completed during the first etching process, patterns the RRAM switching layer to define the RRAM switching structure and patterns the lower electrode layer aligned with the sidewall spacers to define the lower electrode. The sidewall spacers prevent damage to the working portion of the RRAM switching layer during patterning of the lower electrode. Conventionally, it was thought that no additional spacers were necessary, and the interlayer dielectric was formed directly on top of the resulting structure. However, according to the present invention, a non-oxide dielectric layer is provided as a second spacer formed outside the sidewall spacers.

[0017] During the RRAM cell patterning process, the edges of the upper electrodes may be exposed. This is especially true when the RRAM cell stack is formed on holes or recesses, and the edges of the upper electrodes are sloped upward and have a higher elevation than the central region of the upper electrodes. These exposed edges are vulnerable to oxidation during the formation of the interlayer dielectric. In some embodiments, a non-oxide dielectric layer extends over the upper electrode layer to protect these edges.

[0018] Interlayer dielectrics are generally low-k dielectric layers or very low-k dielectric layers. These types of layers may not adhere well to non-oxide dielectric layers. Therefore, in some embodiments, a silicon dioxide layer is formed on the non-oxide dielectric layer to act as an interface layer between the non-oxide dielectric layer and the interlayer dielectric.

[0019] Figure 1 shows the first metallization layer M, which is part of the metal interconnection structure on a semiconductor substrate (not shown). X and the second metallization layer M X+1 A cross-sectional view of an integrated circuit device 100 including a resistive random access memory (RRAM) cell 143 positioned between the two is shown. According to the present invention, the RRAM cell 143 is surrounded by a non-oxide dielectric layer 111.

[0020] The RRAM cell 143 includes a lower electrode 131, a resistive switching structure 205, and an upper electrode 137. The lower electrode 131 may include a barrier layer 125 and a lower electrode metal layer 123. The barrier layer 125 is composed of the lower electrode metal layer 123 and a first metallization layer M X It provides a barrier between itself and the conductive trace 135 inside. The upper electrode 137 may include a capping structure 119 and an upper electrode metal layer 115. The capping structure 119 facilitates the absorption of oxygen ions from the resistive switching structure 205.

[0021] The RRAM cell 143 is positioned on an opening defined by the sidewall 139 of the dielectric layer 127. In this configuration, the lower electrode 131, the resistive switching structure 205, and the upper electrode 137 have a central recess. These layers taper upward from their central recess to their outer edges at an angle similar to the angle θ1 formed by the sidewall 139 with respect to the horizontal axis.

[0022] The sidewall spacer 117, located on the lower electrode 131, surrounds the upper electrode 137. The lower electrode metal layer 123 has sidewalls 122 aligned with the sidewall spacer 117. The sidewall spacer 117 is entirely above the lower electrode metal layer 123 in the sense that its bottom surface is vertically higher than the top surface of the lower electrode metal layer 123. The sidewall spacer 117 may extend to the same height as or below the top surface of the upper electrode 137 as a result of the forming process. The hard mask 113 may be positioned on the upper electrode 137. The corners 141 of the upper electrode 137 may protrude from between the sidewall spacer 117 and the hard mask 113.

[0023] The non-oxide dielectric layer 111 surrounds the sidewall spacer 117, covers the sidewall 122 of the lower electrode metal layer 123, and provides a physical barrier between the lower electrode 131 and the interlayer dielectric 107. The non-oxide dielectric layer 111 is in direct contact with the sidewall 122, but may be separated from the interlayer dielectric 107 by the interface layer 109. The non-oxide dielectric layer 111 extends over the upper electrode 137 and the hard mask 113, covering the corner 141. The non-oxide dielectric layer 111 may be in direct contact with the corner 141.

[0024] Via 105 extends through the interlayer dielectric 107, interface layer 109, non-oxide dielectric layer 111, and hard mask 113, and connects to the upper electrode 137 and the second metallization layer M X+1 A connection is formed between the via 105 and the conductive trace 103 inside. The via 105 and the conductive trace 103 may be separated from the interlayer dielectric 107 by the diffusion barrier layer 101. Similarly, the conductive trace 135 may be separated from the lower interlayer dielectric 129 by the diffusion barrier layer 133.

[0025] The upper electrode 137 has a side wall 140 that tapers at an angle θ2 with respect to the vertical axis 138. In some embodiments, the angle θ2 is in the range of about 10° to about 60°. In some embodiments, the angle θ2 is in the range of about 15° to about 45°. By tilting the side wall 140 instead of making it vertical, the electric field strength at the ends of the RRAM cell 143 is reduced, but the corners 141 may be more easily exposed during the formation and subsequent processing of the side wall spacer 117.

[0026] The sidewalls 122 of the lower electrode metal layer 123 are tapered at an angle θ3 with respect to the vertical axis. In some embodiments, the angle θ3 is in the range of approximately 15° to approximately 75°. In some embodiments, the angle θ3 is in the range of approximately 30° to approximately 60°. By tilting the sidewalls 122 instead of making them vertical, the electric field strength at the ends of the RRAM cell 143 is reduced, but the lower electrode metal layer 123 is made more sensitive to damage by increasing the exposed surface area and thus increasing exposure to damage from high-energy particles projected along the vertical axis 138.

[0027] Figure 2 shows a cross-sectional view of the integrated circuit device 200, which includes an RRAM cell 143A. The RRAM cell 143A has an upper electrode 137A, a resistive switching structure 205A, a lower electrode 131A, a planarized hard mask 113A, and a non-oxide dielectric layer 111A having a sidewall spacer profile. The RRAM cell 143A is similar to the RRAM cell 143 in Figure 1, but differs in shape. The difference in shape includes the upper electrode 137A and lower electrode 131A having vertical sidewalls. Furthermore, these sidewalls are displaced from the sidewall 139 that defines the opening in the dielectric layer 127, and the upper electrode 137A, resistive switching structure 205A, and lower electrode 131A are flat in their peripheral regions.

[0028] The upper electrode 137A has a capping structure 119A which includes a capping metal layer 201 and a diffusion barrier layer 203. The diffusion barrier layer 203 is part of the capping structure 119A which is provided to limit or delay the transport of oxygen ions from the capping structure 119A to the resistive switching structure 205A, thereby mitigating the spontaneous diffusion of oxygen ions which could adversely affect the stability of the RRAM cell 143A.

[0029] The resistive switching structure 205A has a multilayer structure that reduces the forming voltage. As transistors are made smaller, their safe operating voltage decreases. Therefore, the driving force behind increasing integrated circuit device density has led to a long-standing demand to reduce the forming voltage of RRAM cells. One approach to reducing the forming voltage is to reduce the thickness of the resistive switching structure, but as the resistive switching structure becomes very thin (e.g., less than 10 angstroms), leakage current tends to become excessive. Furthermore, as the resistive switching structure becomes thinner, there is an increased tendency for oxygen ions to spontaneously diffuse from the upper electrode into the resistive switching structure, which can negatively impact the reliability of the RRAM cell.

[0030] The resistive switching structure 205A solves this problem with a structure that includes a high oxygen affinity metal oxide layer 205_1 and a low oxygen affinity metal oxide layer 205_2. The high oxygen affinity metal oxide layer 205_1 is close to the upper electrode 137A, and the low oxygen affinity metal oxide layer 205_2 is close to the lower electrode 131A. Due to the difference in oxygen affinity, some oxygen ions spontaneously move from the low oxygen affinity metal oxide layer 205_2 to the high oxygen affinity metal oxide layer 205_1, thereby creating intrinsic oxygen vacancies within the low oxygen affinity metal oxide layer 205_2. If the difference in oxygen affinity is sufficiently large and the thicknesses of the low oxygen affinity metal oxide layer 205_1 and the high oxygen affinity metal oxide layer 205_2 are appropriately selected, the forming voltage will decrease. To facilitate this mechanism, the lower electrode 131A is designed to resist oxygen uptake or release.

[0031] The inventors observed that, without the non-oxide dielectric layer 111A, the time required for switching from LRS to HRS depended on the thickness of the lower electrode 131A. The inventors found evidence of oxidative damage at the edges of the lower electrode 131A and hypothesized that this damage was related to the variation in switching time due to the thickness of the lower electrode layer. This hypothesis was confirmed by experiments showing that the addition of the non-oxide dielectric layer 111A eliminates the dependence of the switching time on the thickness of the lower electrode 131A, thereby allowing the RRAM cell 143A to be made smaller without incurring a switching time penalty.

[0032] Figure 3 provides a cross-sectional view 300 showing a larger portion of the integrated circuit device 200 of Figure 2. The cross-sectional view 300 shows that the RRAM cell 143A is located within a metal interconnect structure 321 on a semiconductor substrate 309. A semiconductor device 313 on the surface of the semiconductor substrate 309 may provide an access control device for the RRAM cell 143A. The semiconductor device 313 is depicted as a metal oxide semiconductor field-effect transistor (MOSFET), but may alternatively be a bipolar junction transistor (BTJ), a high electron mobility transistor (HEMT), similar, or any other type of access control device.

[0033] The semiconductor device 313 includes a gate dielectric layer 310, a gate electrode 312, and a pair of source / drain regions 311a to 311b. An isolation structure 307 is located within the semiconductor substrate 309 and is configured to electrically isolate the semiconductor device 313 from other devices (not shown) located within and / or on the semiconductor substrate 309. The source / drain regions may be referred to as source or drain, individually or collectively, depending on the context.

[0034] The metal interconnection structure 321 consists of multiple metallization layers M1, M, separated by via layers V1, V2, etc. X M X+1 This includes, for example, each metallization layer includes a conductive trace 303 surrounded by an interlayer dielectric (ILD) 129. Each via layer includes conductive vias 305 interconnecting the conductive traces 303 and surrounded by an interlayer dielectric (ILD) 129. The conductive traces 303 and conductive vias 305 are electrically coupled in a predefined manner and configured to provide electrical connections between various devices arranged throughout the integrated circuit device 200.

[0035] A first conductive trace 303b electrically coupled to the gate electrode 312 may provide a word line. A second conductive trace 303a electrically coupled to the source / drain region 311a may provide a source line. A third conductive trace 303c may provide a bit line. The RRAM cell 143A may be electrically coupled to the source / drain region 311b via a metal interconnect structure 321. Thus, in some embodiments, an appropriate voltage applied to the word line electrically couples the RRAM cell 143A between the bit line and the source line. Thus, by providing appropriate bias conditions, the RRAM cell 143A can be read or switched between one of two different data states. The current passing through the RRAM cell 143A also passes through the semiconductor device 313. By designing the RRAM cell 143A to operate at lower voltages, it becomes possible to scale down the semiconductor device 313.

[0036] Figure 4 provides a cross-sectional view 400 showing a larger portion of the integrated circuit device 200 of Figure 2, which shows that the RRAM cell 143A is one of an array of similar cells. The RRAM cell 143A may be located within a memory region 401 of the semiconductor substrate 309 (see Figure 3). The semiconductor substrate 309 may have a logic region 403 laterally relative to the memory region 401. The RRAM cell 143A is located within a via layer V containing vias 405. X It may be located inside or elsewhere within the metal interconnect structure 321 (see Figure 3).

[0037] Figure 5 provides a cross-sectional view 500 (see Figure 3) that provides a more detailed view of the central region 301 of the RRAM cell 143A after the conductive filament 503 has been formed within the resistive switching structure 205A. In some embodiments, the conductive filament 503 includes oxygen vacancies 501 and is formed and dissolved through oxidation-reduction reactions. Typically, initially forming the conductive filament 503 involves applying a forming voltage pulse between the lower electrode 131A and the upper electrode 137A. Subsequently, a set voltage or reset voltage can be applied between the lower electrode 131A and the upper electrode 137A to change the resistivity between the HRS and LRS of the resistive switching structure 205A. The conductive filament 503 extends from the lower electrode 131A to the capping structure 119A. By forming the conductive filament 503, the LRS is generated. By dissolving at least a portion of the conductive filament 503, the HRS is generated.

[0038] The forming voltage pulse can knock out oxygen atoms from the lattice within the resistive switching structure 205A, thereby creating localized oxygen vacancies that tend to align and form conductive filaments 503. The capping structure 119A may be configured to absorb oxygen ions from the resistive switching structure 205A during the forming and setting operations and release oxygen ions to the resistive switching structure 205A during the reset operation. This role as an oxygen ion reservoir facilitates the formation and dissolution of the conductive filaments 503. A diffusion barrier layer 203 located between the capping metal layer 201 and the high oxygen affinity metal oxide layer 205_1 helps to regulate the exchange of oxygen ions between them. The lower electrode metal layer 123 is designed to avoid the release of oxygen ions, as these fill oxygen vacancies and inhibit the filament formation process.

[0039] Figure 6 shows a cross-sectional view of the integrated circuit device 600, which includes an RRAM cell 143B. The RRAM cell 143B is similar to the RRAM cell 143A in Figure 2, but has an upper electrode 137B with a side wall 601 aligned with the side wall 603 of the resistive switching structure 205A and the side wall 122 of the lower electrode metal layer 123. The side walls 601, 603, and 122 may be vertical or may have a taper away from the vertical axis. A non-oxide dielectric layer 111B covers and abuts against the side walls 601, 603, and 122. In some embodiments, the non-oxide dielectric layer 111B has a side wall spacer profile.

[0040] Figure 7 shows a cross-sectional view of the integrated circuit device 700, which includes an RRAM cell 143C. The RRAM cell 143C is similar to the RRAM cell 143A in Figure 2, but has a planar lower electrode 131C, a resistive switching structure 205C, and an upper electrode 137C. The lower electrode 131C may be electrically coupled to a conductive trace 135 by a lower electrode via 701. The lower electrode via 701 is narrower than the lower electrode 131C and may function as a diffusion barrier between the conductive trace 135 and the lower electrode 131C. The non-oxide dielectric layer 111C covers and abuts the sidewall 122 of the lower electrode metal layer 123, surrounds the sidewall spacer 117, and extends over the upper electrode 137C and the hard mask 113C.

[0041] In embodiments including the sidewall spacer 117, the sidewall spacer 117 may be positioned on top of the resistive switching structure 205, 205A, or 205C as shown in Figures 1 and 2, or it may extend downward to the lower electrode metal layer 123 to cover the sidewall 603 of the resistive switching structure 205, 205A, or 205C as shown in Figure 7. In either configuration, the sidewall spacer 117 can prevent damage to the operating portion of the resistive switching structure 205 during etching of the lower electrode metal layer 123.

[0042] Figures 8-17 show a series of cross-sectional views 800-1700 of an integrated circuit device including an RRAM cell at various stages of manufacturing according to the process of the present invention. Although Figures 8-17 are described in relation to a series of operations, the order of operations may be changed in some cases, and it will be understood that this series of operations is applicable to structures other than those shown. In some embodiments, some of these operations may be omitted in whole or in part. Furthermore, it will be understood that the structures shown in Figures 8-17 are not limited to the manufacturing method, but may rather exist as structures separated from the method.

[0043] As shown in the cross-sectional view 800 of Figure 8, the process begins with front-end-of-line (FEOL) processing of the semiconductor substrate 309, followed by the metallization layer M X Backend obline processing may be performed to generate the metal interconnect structure 321 up to this point. The semiconductor substrate 309 may be, for example, silicon, single-crystal silicon, silicon-germanium, silicon-on-insulator (SOI) substrate, one or more epitaxial layers, other suitable substrates, or any combination thereof, or may include these. FOEL processing provides the isolation structure 307, doped substrate regions such as source / drain regions 311a-311b, and semiconductor devices such as semiconductor devices 313.

[0044] BEOL processing includes forming layers of interlayer dielectric 129 and optionally an etch stop layer (not shown) between the layers. The interlayer dielectric 129 may be silicon dioxide (SiO2), a low-k dielectric, or an extremely low-k dielectric, or may include these. A low-k dielectric has a dielectric constant lower than that of silicon dioxide (SiO2). SiO2 has a dielectric constant of about 3.9. Examples of low-k dielectrics include organosilicate glasses (OSG) such as carbon-doped silicon dioxide and fluorine-doped silicon dioxide (also called fluorinated silica glass (FSG)), organic polymer low-k dielectrics, and porous silicate glasses. An extremely low-k dielectric is a material with a dielectric constant of about 2.1 or less. Extremely low-k dielectric materials are generally low-k dielectric materials formed in a porous structure. Porosity reduces the effective dielectric constant. The interlayer dielectric 129 may be deposited by atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), similar methods, or other suitable processes.

[0045] Conductive vias 305 and conductive traces 303 may be formed within the interlayer dielectric 129 by a damascene or dual damascene process. The conductive vias 305 and conductive traces 303 may be, for example, copper (Cu), aluminum (Al), tungsten (W), ruthenium (Ru), a combination thereof, or similar, or may contain these. In some embodiments, a diffusion barrier layer 133 (see Figure 1) separates the conductive vias 305 and conductive traces 303 from the interlayer dielectric 129. The diffusion barrier layer 133 may be, for example, titanium nitride (TiN), tantalum nitride (TaN), or similar, or may contain these. The damascene or dual damascene process may include masking and etching to form trenches and holes, deposition to fill the trenches and holes, followed by planarization to remove excess material, such as chemical mechanical polishing (CMP). The deposition process may be, for example, ALD, CVD, electroplating, electroless plating, or similar.

[0046] As shown in the cross-sectional view 900 of FIG. 9, the dielectric layer 127 may be formed on the metallization layer M X A mask 901 may be formed, and the dielectric layer 127 may be etched to form a hole 903 having sidewalls 139. The dielectric layer 127 may be, for example, silicon dioxide (SiO2), silicon carbide (SiC), silicon oxycarbide (SiOC), silicon nitride (SiN), silicon oxynitride (SiON), boron nitride (BN), aluminum nitride (AlN), the like, other dielectric materials, or any combination thereof, or may include them. In some embodiments, the dielectric layer 127 is a non-oxide dielectric such as silicon carbide (SiC), silicon nitride (SiN), silicon carbonitride (SiCN), boron nitride (BN), aluminum nitride (AlN), or the like. The use of a non-oxide dielectric may help protect the lower electrode 131 (see FIG. 1) from oxygen. In some embodiments, the dielectric layer 127 is a carbide-based dielectric such as silicon carbide (SiC), or another dielectric that provides an effective barrier against copper diffusion.

[0047] The mask 901 may include a photoresist, a hard mask, or a similar material, similar to other masks used in the processes described herein. The mask 901 and other masks used in these processes may be patterned using photolithography, ion beam lithography, or other suitable patterning techniques. The etching process may be dry etching such as plasma etching, or other suitable etching methods. The etching process may be configured to form a hole 903 having sidewalls 139 at an angle θ1 by adjusting parameters such as the etchant gas composition, pressure, power, incident angle, and etching time. After the etching process, the mask 901 may be removed.

[0048] The width 905 of the hole 903, the thickness of the dielectric layer 127, and the angle θ1 at which the sidewall 139 tapers each affect the resulting shape of the RRAM cell 143 (see Figure 1). In some embodiments, the thickness of the dielectric layer 127 ranges from about 50 Å to about 1000 Å. In some embodiments, the thickness of the dielectric layer 127 ranges from about 100 Å to about 400 Å. In some embodiments, the width 905 ranges from about 5 nm to about 200 nm. In some embodiments, the width 905 ranges from about 10 nm to about 100 nm. In some embodiments, the aspect ratio of the hole 903 (ratio of width 905 to thickness of dielectric layer 127) ranges from about 1:1 to about 5:1.

[0049] The angle θ1 may be relatively small, reflecting the shallow taper of the sidewall 139. In some embodiments, the angle θ1 is in the range of approximately 10° to approximately 80°. In some embodiments, the angle θ1 is in the range of approximately 30° to approximately 60°. If the angle θ1 is too small or too large, the RRAM cell whose shape is determined by the hole 903 may be unreliable.

[0050] As shown in the cross-sectional view 1000 of Figure 10, the RRAM cell stack 1001 is formed on top of the hole 903. The RRAM cell stack 1001 is formed using a conformal or partially conformal deposition process, resulting in a central recess 1007 on top of the hole 903 and a tapered region 1005 extending from the central recess 1007 to the outer region 1003. In some embodiments, the tapered region 1005 has a slope similar to the side wall 139 of the hole 903.

[0051] The RRAM cell stack 1001 includes a lower electrode layer 1013, a resistive switching layer 1011, and an upper electrode layer 1009. The lower electrode layer 1013 may include a barrier layer 125 and a lower electrode metal layer 123. In some embodiments, the lower electrode metal layer 123 has a composition selected so as not to significantly absorb oxygen ions from or release oxygen ions to the resistive switching layer 1011. In some embodiments, the barrier layer 125 is selected as a conductive material that prevents copper diffusion. The barrier layer 125 may be, for example, a conductive oxide, nitride, or oxynitride of aluminum (Al), manganese (Mn), cobalt (Co), titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), tin (Sn), or magnesium (Mg), a combination thereof, or similar. The lower electrode metal layer 123 may be copper (Cu), ruthenium (Ru), aluminum (Al), tungsten (W), tantalum (Ta), titanium (Ti), compounds or mixtures thereof, or similar materials. The composition of the lower electrode metal layer 123 may be selected to provide good work function matching with the adjacent resistive switching layer 1011. In some embodiments, the thickness of the lower electrode metal layer 123 ranges from about 3 angstroms to about 500 angstroms. In some embodiments, the thickness ranges from about 50 angstroms to about 100 angstroms.

[0052] The resistive switching layer 1011 may be one or more layers of a suitable dielectric. Suitable dielectrics include hafnium oxide (HfO), zirconium oxide (ZrO), aluminum oxide (AlO), silicon nitride (SiN), aluminum nitride (AlN), other high-k dielectrics, and similar materials. In some embodiments, the resistive switching layer 1011 is a metal oxide. In some embodiments, the resistive switching layer 1011 includes a high oxygen affinity metal oxide layer 205_1 and a low oxygen affinity metal oxide layer 205_2.

[0053] The high oxygen affinity metal oxide layer 205_1 and the low oxygen affinity metal oxide layer 205_2 have different oxygen affinities of their metals. One measure of a metal's oxygen affinity is the standard Gibbs free energy for oxygen vacancy formation for the largest oxide (the oxide with the highest oxygen content) of that metal. A higher standard Gibbs free energy for oxygen vacancy formation indicates greater oxygen affinity. A more practically equivalent and manageable measure is the standard Gibbs free energy for the formation of the largest oxide on a per mole of oxygen basis. A lower (more negative) standard Gibbs free energy for metal oxide formation indicates greater oxygen affinity. In some embodiments, the difference between the standard Gibbs free energy for metal oxide formation of the first metal, which is the metal in the low oxygen affinity metal oxide layer 205_2, and the standard Gibbs free energy for metal oxide formation of the second metal, which is the metal in the high oxygen affinity metal oxide layer 205_1, is at least about 100 kJ / mol oxygen (O2). In some embodiments, this difference is at least about 200 kJ / mol oxygen (O2).

[0054] In some embodiments, the thickness ratio between the low oxygen affinity metal oxide layer 205_2 and the high oxygen affinity metal oxide layer 205_1 is in the range of about 0.5 to about 1.3. In some embodiments, the thickness ratio is in the range of about 0.8 to about 1.0. In some embodiments, the thickness of the resistive switching layer 1011 is in the range of about 20 angstroms to about 45 angstroms. In some embodiments, each of the low oxygen affinity metal oxide layer 205_2 and the high oxygen affinity metal oxide layer 205_1 has a thickness of at least about 10 angstroms. If the high oxygen affinity metal oxide layer 205_1 is too thin, or too thin relative to the low oxygen affinity metal oxide layer 205_2, it may not have the ability to generate a sufficient number of oxygen vacancies in the low oxygen affinity metal oxide layer 205_2 to significantly reduce the formation voltage. If the high oxygen affinity metal oxide layer 205_1 is too thick, it may increase the formation voltage. If the low oxygen affinity metal oxide layer 205_2 is too thin, it may not be able to hold enough oxygen vacancies to significantly reduce the formation voltage. If the combined thickness of the low oxygen affinity metal oxide layer 205_2 and the high oxygen affinity metal oxide layer 205_1 is too thin, the leakage current may become excessive.

[0055] In some embodiments, the high oxygen affinity metal oxide layer 205_1 is or comprises an oxide of a metal whose standard Gibbs free energy for oxide formation is -1000 kJ / molO2 or less. In some embodiments, the high oxygen affinity metal oxide layer 205_1 is or comprises one of the following: zirconium oxide (ZrO), lanthanum oxide (LaO), hafnium oxide (HfO), gadolinium oxide (GdO), yttrium oxide (YO), or similar. In some embodiments, the high oxygen affinity metal oxide layer 205_1 has a thickness ranging from about 10 angstroms to about 25 angstroms.

[0056] In some embodiments, the low oxygen affinity metal oxide layer 205_2 includes an oxide of a metal whose standard Gibbs free energy for oxide formation is approximately -900 kJ / molO2 or higher. In some embodiments, the low oxygen affinity metal oxide layer 205_2 includes an oxide of a metal whose standard Gibbs free energy for oxide formation is in the range of approximately -750 kJ / molO2 (for tantalum) to approximately -500 kJ / molO2. If the oxygen affinity of the low oxygen affinity metal oxide layer 205_2 is too high, it may not be able to form intrinsic oxygen defects and reduce the formation voltage. If the oxygen affinity of the low oxygen affinity metal oxide layer 205_2 is too low, the leakage current may be excessive. In some embodiments, the low oxygen affinity metal oxide layer 205_2 comprises one of the following: zinc oxide (ZnO), tantalum oxide (TaO), silicon oxide (SiO), germanium oxide (GeO), indium tin oxide (ITO), indium gallium zinc oxide (IGZO), ruthenium oxide (RuO), or similar. Indium tin oxide (ITO) has a standard Gibbs free energy of about -550 kJ / mol O2 for formation. Indium gallium zinc oxide (IGZO) has a standard Gibbs free energy of about -620 kJ / mol O2 for formation.

[0057] In some embodiments, the low oxygen affinity metal oxide layer 205_2 has a thickness ranging from about 10 angstroms to about 25 angstroms. The difference in oxygen affinity between the low oxygen affinity metal oxide layer 205_2 and the high oxygen affinity metal oxide layer 205_1 is sufficient for oxygen ions to spontaneously move from the low oxygen affinity metal oxide layer 205_2 to the high oxygen affinity metal oxide layer 205_1, generating oxygen defects inherent in the low oxygen affinity metal oxide layer 205_2 to the extent that it reduces the formation voltage of the RRAM cell 143.

[0058] The number of intrinsic oxygen vacancies in the low oxygen affinity metal oxide layer 205_2 depends on the relative thickness of the high oxygen affinity metal oxide layer 205_1. In some embodiments, the ratio of the thickness of the high oxygen affinity metal oxide layer 205_1 to the thickness of the low oxygen affinity metal oxide layer 205_2 is 0.85 or greater. In some embodiments, this ratio is 1:1 or greater. These ratios provide the high oxygen affinity metal oxide layer 205_1 with the capacity to receive a sufficient number of oxygen ions from the low oxygen affinity metal oxide layer 205_2 and generate a sufficient number of oxygen vacancies to achieve the desired reduction in the formation voltage.

[0059] In some embodiments, the low oxygen affinity metal oxide layer 205_2 further contains a dopant metal oxide. The dopant metal oxide improves durability by limiting the dispersion of oxygen vacancies that may occur over many cycles of formation and fracture of the conductive filament 503 (see Figure 5). The metal having a higher concentration in the low oxygen affinity metal oxide layer 205_2 may be called the bulk metal. The concentration of the dopant metal may be low enough that the overall oxygen affinity of the low oxygen affinity metal oxide layer 205_2 is not substantially altered by the dopant metal. The dopant metal has a higher oxygen affinity than the bulk metal. In some embodiments, the dopant metal has a standard Gibbs free energy for oxide formation of less than approximately -750 kJ / molO2 (less than that of tantalum).

[0060] For the purposes of the present invention, the following standard Gibbs free energies for oxide formation, expressed in kJ / mol oxygen (O2), may be used, including determining which is the bulk metal and which is the dopant metal in the embodiments described above: ruthenium (Ru, -274), zinc (Zn, -640), tantalum (Ta, -750), silicon (Si, -860), titanium (Ti, -889), hafnium (Hf, -1000), aluminum (Al, -1055), zirconium (Zr, -1100), lanthanum (La, -1140), neodymium (Nd, -1150), gadolinium (Gd, -1160), and yttrium (Y, -1270).

[0061] In some embodiments, the low oxygen affinity metal oxide layer 205_2 has an oxygen amount less than the stoichiometric amount relative to the maximum oxide of its metal constituent. In some embodiments, the oxygen amount is in the range of about 80 to about 99.5% of the stoichiometric amount. In some embodiments, the oxygen amount is in the range of about 90 to about 95% of the stoichiometric amount. An oxygen amount less than the stoichiometric amount reduces the formation voltage. If the oxygen amount is too high, the formation voltage may be too high. If the oxygen amount is too low, the leakage current may be too high.

[0062] In some embodiments, the low oxygen affinity metal oxide layer 205_2 has a dopant concentration ranging from 0.1% to about 10% on an atomic basis. If the dopant amount is too low, the benefit of improved durability may not be realized. If the dopant amount is too high, the formation voltage may increase excessively.

[0063] In some embodiments, the high oxygen affinity metal oxide layer 205_1 has a substoichiometric amount of oxygen relative to the maximum oxide of its metal constituent. In some embodiments, the oxygen amount is in the range of about 80 to about 99.5% of the stoichiometric amount. In some embodiments, the oxygen amount is in the range of about 90 to about 95% of the stoichiometric amount. A substoichiometric amount of oxygen in the high oxygen affinity metal oxide layer 205_1 also contributes to achieving a lower formation voltage. If the oxygen amount in the high oxygen affinity metal oxide layer 205_1 is too high, the formation voltage may be too high. If the oxygen amount in the high oxygen affinity metal oxide layer 205_1 is too low, the leakage current may be excessive.

[0064] The resistive switching layer 1011 may be formed by CVD, PVD, ALD, or any other process. In some embodiments, these layers are formed by ALD. In some embodiments, the low oxygen affinity metal oxide layer 205_2 contains a dopant metal oxide, which is deposited in a separate cycle from the bulk metal oxide. The low oxygen affinity metal oxide layer has been found to perform better when the dopant metal is deposited in a separate cycle, as opposed to when the dopant metal precursor is combined with the bulk metal precursor and both metal oxides are deposited simultaneously. In some embodiments, the bulk metal oxide to dopant metal oxide deposition cycle ratio is in the range of 3:1 to 15:1. In some embodiments, the bulk metal oxide to dopant metal oxide deposition cycle ratio is in the range of 5:1 to 10:1. In some embodiments, the bulk metal oxide to dopant metal oxide deposition cycle ratio is at least 6:1. If the ratio is too low, the formation voltage may increase. If the ratio is too high, there may not be enough dopant metal to improve durability.

[0065] The upper electrode layer 1009 includes a capping structure 119 and an upper electrode metal layer 115. In some embodiments, the capping structure 119 includes one or more layers of metals having high oxygen ion solubility, such as tantalum (Ta), titanium (Ti), platinum (Pt), aluminum (Al), hafnium (Hf), zirconium (Zr), nickel (Ni), iridium (Ir), or others. In some embodiments, a diffusion barrier layer 203 (see Figure 2) is provided to reduce the spontaneous diffusion of oxygen ions from the capping structure 119 to the resistive switching layer 1011. The diffusion barrier layer 203 may include, for example, tantalum nitride (TaN), titanium nitride (TiN), or others. In some embodiments, the diffusion barrier layer 203 is a metal nitride of the capping structure 119. The thickness of the diffusion barrier layer 203 may range from about 20 angstroms to about 30 angstroms. If the diffusion barrier layer 203 is too thin, it may allow excessive spontaneous diffusion of oxygen ions. If the diffusion barrier layer 203 is too thick, it may excessively increase the formation voltage.

[0066] The thickness of the capping structure 119 may be in the range of approximately 10 angstroms to approximately 50 angstroms, or other appropriate values. If the capping structure 119 is too thin, it may not be able to properly absorb oxygen ions during the set operation. If the capping structure 119 is too thick, oxygen ions may disperse within the capping structure 119 and not return to the resistive switching layer 1011 during the reset operation.

[0067] The upper electrode metal layer 115 has good conductivity but does not need to absorb oxygen significantly. The upper electrode metal layer 115 may be, for example, tantalum nitride (TaN), titanium nitride (TiN), ruthenium (Ru), platinum (Pt), a combination thereof, or other materials. The thickness of the upper electrode metal layer 115 may be, for example, in the range of about 80 angstroms to about 200 angstroms, or other appropriate values. The upper electrode layer 1009 may be formed by CVD, PVD, ALD, electroplating, electroless plating, a combination thereof, or other methods.

[0068] As shown in the cross-sectional view 1100 of Figure 11, a hard mask 113 is formed and used to pattern the upper electrode metal layer 115 and the capping structure 119 to define the upper electrode 137. Optionally, etching is continued through the high oxygen affinity metal oxide layer 205_1 and the low oxygen affinity metal oxide layer 205_2 to form sidewalls 140 that define the resistive switching structure. In some embodiments, the sidewalls 140 are formed in tapered regions 1005, and the upper electrode 115 has a taper corresponding to the sidewalls 139. The etching process may be dry etching such as plasma etching or other suitable etching methods. The etching process may be configured to form sidewalls 140 at an angle θ2 by adjusting parameters such as etchant gas composition, pressure, power, and etching time.

[0069] As shown in the cross-sectional view 1200 of Figure 12, the sidewall spacer 117 is positioned on the lower electrode layer 1013 and is formed to cover the sidewall 140 of the upper electrode 137. The width 1201 of the sidewall spacer 117 may range, for example, from about 10 angstroms to about 200 angstroms. The sidewall spacer 117 may be, or include, silicon dioxide (SiO2), silicon carbide (SiC), silicon oxycarbide (SiOC), silicon nitride (SiN), silicon oxynitride (SiON), or other materials. In some embodiments, the sidewall spacer 117 is a non-oxide dielectric such as silicon carbide (SiC), silicon nitride (SiN), silicon carbonitride (SiCN), or other materials. The sidewall spacer 117 may be manufactured through deposition and etching. The deposition process may be, for example, CVD, PVD, ALD, or other. Etching may remove the spacer material on top of the upper electrode 137. The etching process may be anisotropic plasma etching, or other suitable etching processes.

[0070] As shown in the cross-sectional view 1300 of Figure 13, a second etching process is performed, which is aligned by the sidewall spacers 117 and the hard mask 113. The second etching process defines the resistive switching structure 1301 if it has not yet been defined by the first etching process, and defines the lower electrode 131. The etching process may be dry etching such as plasma etching, or other suitable etching method. The etching process may be configured to form the sidewall 122 at an angle θ3 by adjusting parameters such as etchant gas composition, pressure, power, and etching time. In some embodiments, the second etching process recesses the hard mask 113 or otherwise exposes the corner 141. In some embodiments, the second etching process recesses the dielectric layer 127, creating an undercut 1303 at the end of the lower electrode 131. The second etching process completes the definition of the RRAM cell 143 from the RRAM cell stack 1001 (see Figure 10).

[0071] As shown in the cross-sectional view 1400 of Figure 14, the non-oxide dielectric material 1401 is deposited on the RRAM cell 143 so as to cover the sidewalls 122 and corners 141. In some embodiments, the partially fabricated device shown in the cross-sectional view 1300 of Figure 13 is maintained in a substantially oxygen-free environment until and throughout the deposition of the non-oxide dielectric material 1401 so as not to form native oxides on the exposed metal. The non-oxide dielectric material 1401 may be deposited by CVD, PVD, ALD, or other suitable process. In some embodiments, the film deposition process is carried out in an oxygen-free environment.

[0072] As shown in the cross-sectional view 1500 of Figure 15, the non-oxide dielectric material 1401 may be etched to define the non-oxide dielectric layer 111. In some embodiments, the non-oxide dielectric material 1401 is deposited only to its final thickness, and this etching process may be omitted, although the combination of deposition and etching has advantages such as gap filling. The etching process may be dry etching, wet etching, or other suitable etching process. In some embodiments, etching leaves the non-oxide dielectric layer 111 extending over the RRAM cell 143.

[0073] As shown in the cross-sectional view 1600 of Figure 16, the interlayer dielectric 107 may be deposited on the RRAM cell 143. In some embodiments, an interface layer 109 is deposited before the interlayer dielectric 107 is deposited. Each layer may be deposited by CVD, PVD, ALD, or other suitable deposition or growth process. In some embodiments, the interlayer dielectric 107 is deposited via plasma-enhanced CVD utilizing a supply gas containing tetraethyl orthosilicate (TEOS) and oxygen (O2). In such embodiments, oxygen is usually introduced before the introduction of TEOS to prepare the surface. However, this step may be omitted if the interface layer 109 is deposited beforehand. In some embodiments, the interlayer dielectric 107 is a low-k dielectric. In some embodiments, the interlayer dielectric 107 is an extremely low-k dielectric. To achieve the desired low-k or extremely low-k dielectric properties, deposition parameters may be adjusted and / or additional supply gases may be introduced. A non-oxide dielectric layer 111 protects the lower electrode 131 from oxidative damage during these deposition processes.

[0074] As shown in the cross-sectional view 1700 of Figure 17, openings may be formed in the interlayer dielectric 107. These openings may include trenches 1701 and holes 1703. Holes 1703 extend through the interlayer dielectric 107, through the interface layer 109, and through the hard mask 113, thereby exposing the upper electrode 137. The openings may be formed using a masking and etching process, which may be either a trench-first or via-first process. The trenches 1701 and holes 1703 may be lined with a diffusion barrier layer 101 and then filled with a conductive material to provide conductive traces 103 and vias 105 as shown in Figure 1. The conductive material may be deposited by CVD, PVD, ALD, electroless plating, electroplating, or other suitable deposition process. After deposition, excess material may be removed using a planarization process such as CMP.

[0075] Figures 18-23 show a series of cross-sectional views 1800-2300 of an integrated circuit device containing RRAM cells at various stages of manufacturing according to another process of the present invention. Although Figures 18-23 are described in relation to a series of operations, the order of operations may be changed in some cases, and it will be understood that this series of operations is applicable to structures other than those illustrated. In some embodiments, some of these operations may be omitted whole or in part. Furthermore, it will be understood that the structures shown in Figures 18-23 are not limited to the manufacturing method, but may rather exist as structures separate from the method.

[0076] The processes shown in Figures 18-23 are similar in many respects to the processes shown in Figures 8-17. The processes in Figures 18-23 may have the same steps as the processes in Figures 8-17 up to the formation of the RRAM cell stack 1801 shown in the cross-sectional view 1800 of Figure 18. The RRAM cell stack 1801 may be substantially the same as the RRAM cell stack 1001 in Figure 10, although the RRAM cell stack 1801 is depicted as having a slightly different shape.

[0077] As shown in the cross-sectional view 1900 of Figure 19, a hard mask 113A is formed and a first etching process is performed to define the upper electrode 137A. This process is similar to that shown in the cross-sectional view 1100 of Figure 11, except that the hard mask 113A is fabricated to have a flat top surface 1901 and the upper electrode 137A is etched to have vertical sidewalls. The first etching process may be stopped on or within the resistive switch layer 1903 or on the lower electrode metal layer 123.

[0078] As shown in the cross-sectional view 2000 of Figure 20, the sidewall spacer 117 is formed around the sidewalls of the upper electrode 137A and the hard mask 113A. This process may be similar to that shown in the cross-sectional view 1200 of Figure 12.

[0079] As shown in the cross-sectional view 2100 of Figure 21, a second etching process is performed to define the lower electrode 131A, define the resistive switching structure 205A, and complete the formation of the RRAM cell 143A. This process may be similar to that shown in the cross-sectional view 1300 of Figure 13, but differs in that the etching process is designed to provide sidewalls perpendicular to the lower electrode 131A and the resistive switching structure 205A.

[0080] As shown by the cross-sectional view 2200 in Figure 22, the non-oxide dielectric material 2201 may be deposited on the RRAM cell 143A. This process may be similar to that shown by the cross-sectional view 1400 in Figure 14.

[0081] As shown by the cross-sectional view 2300 in Figure 23, an etching process may be performed to define the non-oxide dielectric layer 111A from the non-oxide dielectric material 2201. This process may be similar to that shown by the cross-sectional view 1500 in Figure 15, except that the etching process removes the non-oxide dielectric material 2201 from above the hard mask 113A and the upper electrode 137A. The etching process may leave the non-oxide dielectric layer 111A in the tapered profile of the sidewall spacer. The process then proceeds as depicted in the cross-sectional views 1600 and 1700 in Figures 16 and 17 to provide an integrated circuit device as shown in Figure 2.

[0082] Sectional views 2400 and 2500 in Figures 24 and 25 show a variation of the aforementioned process that may be employed to form the integrated circuit device 600 of Figure 6. This variation begins with a second etching process. As shown by sectional view 2400 in Figure 24, the first etching process previously shown in sectional view 1900 in Figure 19 may be combined with the second etching process and extend through the lower electrode metal layer 123 to define the RRAM cell 143B. In this embodiment, the sidewall 601 of the upper electrode 137B, the sidewall 603 of the resistive switching structure 205A, and the sidewall 122 of the lower electrode metal layer 123 are aligned. The second etching process may extend to the dielectric layer 127, as depicted in Figure 24, or terminate at the barrier layer 125. Terminating the second etching process at the barrier layer 125 may mitigate damage to the sidewall 122 of the lower electrode metal layer 123. The barrier layer 125 may be relatively thin and have relatively low conductivity, eliminating the need for etching through this layer.

[0083] As shown in the cross-sectional view 2500 of Figure 25, the non-oxide dielectric layer 111B may be formed around the RRAM cell 143B and may take the form of a sidewall spacer. This process may correspond to that described in relation to the cross-sectional views 2200 and 2300 of Figures 22 and 23. In this modification, the formation of the sidewall spacer 117 shown in the cross-sectional view 2000 of Figure 20 may be omitted, allowing the non-oxide dielectric layer 111B to directly contact both the sidewall 601 of the upper electrode 137B and the sidewall 122 of the lower electrode metal layer 123.

[0084] Cross-sectional views 2600 to 3100 in Figures 26 to 31 illustrate a process according to another embodiment that may be employed to form the integrated circuit device 700 of Figure 7. This process may begin with the structure shown by cross-sectional view 900 in Figure 9. As shown in cross-sectional view 2600 in Figure 26, a conductive material is deposited to fill the holes 903 and then planarized to form the lower electrode vias 701. The deposition process may be CVD, PVD, ALD, electroless plating, electroplating, or similar. The planarization process may be CMP or similar.

[0085] As shown in the cross-sectional view 2700 of Figure 27, the RRAM cell stack 2701 may be deposited on the lower electrode via 701. The RRAM cell stack 2701 may be similar to the RRAM cell stack 1001 in Figure 10 and may be formed by a similar process, but the RRAM cell stack 2701 differs in that it has a planar layer and lacks the barrier layer 125 (see Figure 10). The lower electrode via 701 may provide the barrier layer.

[0086] As shown in the cross-sectional view 2800 of Figure 28, a hard mask 113C may be formed and a first etching process may be performed to define the upper electrode 137C. The etching process may stop at one of the resistive switching layers, or it may continue through the resistive switching layers as depicted in Figure 28 to define the resistive switching structure 205C.

[0087] As shown in the cross-sectional view 2900 of Figure 29, the sidewall spacer 117 may be formed around the sidewall of the upper electrode 137C and the resistive switching structure 205C. This process may be similar to that described in relation to the cross-sectional view 2000 of Figure 20.

[0088] As shown in the cross-sectional view 3000 of Figure 30, a second etching process may be employed to define the lower electrode 131C and the RRAM cell 143C. In this embodiment, the second etching process may be stopped at the dielectric layer 127.

[0089] As shown in the cross-sectional view 3100 of Figure 31, a non-oxide dielectric layer 111C may be formed on the RRAM cell 143C. The non-oxide dielectric layer 111C may be formed by deposition and etching, or by deposition alone. The non-oxide dielectric layer 111C may be left extending on the RRAM cell 143C as depicted in Figure 31, or it may be etched into the shape of a spacer as depicted in the cross-sectional view 2300 of Figure 23.

[0090] Figure 32 provides a flowchart of a method 3200 for forming an RRAM cell according to some embodiments of the present invention. Although method 3200 is illustrated and / or described as a series of operations or events, it will be understood that these methods are not limited to the illustrated order or operations. Thus, in some embodiments, the operations may be performed in a different order than those illustrated and / or simultaneously. Furthermore, in some embodiments, the illustrated operations or events may be subdivided into multiple operations or events, which may be performed at separate times or simultaneously with other operations or sub-operations. In some embodiments, some of the illustrated operations or events may be omitted, and other operations or events not illustrated may be included.

[0091] Method 3200 begins with the FEOL process of operation 3201 and the formation of multiple metallization layers alternating with via layers of operation 3203. A cross-sectional view 800 in Figure 8 provides an example. While the example of the present invention shows RRAM cells formed directly above the metallization layers and RRAM cells contained within a single via layer, the RRAM cells may be located anywhere within the metal interconnect structure or elsewhere within the integrated circuit device. The RRAM cells may be offset above the metallization layers and connected to them by vias.

[0092] Operation 3205 is to form a dielectric barrier layer. Operation 3207 is to etch holes through that layer. Conductive structures, such as conductive traces, are exposed through the holes. Cross-sectional view 900 in Figure 9 provides an example.

[0093] Operation 3209 is to form an RRAM cell stack on top of the holes. Cross-sectional views 1000, 1800, and 2700 in Figures 10, 18, and 27 provide examples. In some embodiments, a conformal deposition process is employed, resulting in each layer having a central recess on top of the holes.

[0094] Operation 3211 is patterning to define the upper electrodes from the RRAM cell stack. This is called the first etching process. Cross-sectional views 1100, 1900, 2400, and 2800 in Figures 11, 19, 24, and 28 provide examples. The first etching process may also define a resistive switching structure from the RRAM cell stack.

[0095] Operation 3213 is an optional step of forming a sidewall spacer around the upper electrode. Cross-sectional views 1200, 2000, and 2900 in Figures 12, 20, and 29 provide examples.

[0096] Operation 3215 is patterning to define the lower electrode from the RRAM cell stack. This is called the second etching process. Cross-sectional views 1300, 2100, 2400, and 3000 in Figures 13, 21, 24, and 30 provide examples. The second etching process defines the resistive switching structure from the RRAM cell stack if this was not achieved by operation 3211. If operation 3213 was used to form the sidewall spacers, the lower electrode is patterned to align with the sidewall spacers.

[0097] Operation 3217 is to form a non-oxide dielectric layer. The non-oxide dielectric layer covers and protects the sidewalls of the lower electrode. In some embodiments, the non-oxide dielectric layer is etched into the shape of a spacer. In some embodiments, the non-oxide dielectric layer extends over the RRAM cell. In some embodiments, the extent of the non-oxide dielectric layer is limited to the sides of the RRAM cell. Sectional views 1400 and 1500 in Figures 14 and 15 provide one example, sectional views 2200 and 2300 in Figures 22 and 23 provide another example, sectional view 2500 in Figure 25 provides a third example, and sectional view 3000 in Figure 30 provides a fourth example.

[0098] Operation 3219 is an optional step of forming an interface layer, and operation 3221 is the deposition of the interlayer dielectric. The non-oxide dielectric layer protects the lower electrode during these process steps. A cross-sectional view 1600 in Figure 16 provides an example. In some embodiments, the interface layer bonds the interlayer dielectric to the non-oxide dielectric layer. In some embodiments, the interface layer is omitted, and the interlayer dielectric layer is in direct contact with the non-oxide dielectric layer.

[0099] Operation 3223 is to form upper electrode vias. The upper electrode vias pass through the interlayer dielectric and contact the upper electrode. Cross-sectional view 1700 in Figure 17 provides an example illustrating the first stage of this process.

[0100] Some aspects of the present invention relate to a semiconductor device comprising an RRAM cell within a metal interconnect structure disposed on a semiconductor substrate. The metal interconnect structure comprises a plurality of metallization layers separated by via layers, each metallization layer comprising conductive traces surrounded by interlayer dielectrics (ILDs), and each via layer comprising conductive vias interconnecting the conductive traces and surrounded by interlayer dielectrics. The RRAM cell comprises a lower electrode, an upper electrode, and a resistive switching structure located between the lower electrode and the upper electrode. A non-oxide dielectric layer surrounds the lower electrode, the non-oxide dielectric layer providing a physical barrier between the lower electrode and the interlayer dielectric.

[0101] In some embodiments, the sidewall spacer is positioned along the outer sidewall of the upper electrode and positioned entirely above the lower electrode. In some embodiments, the sidewall spacer is a non-oxide dielectric. In some embodiments, the non-oxide dielectric layer is positioned along the outer sidewall of the sidewall spacer. In some embodiments, the non-oxide dielectric layer on the sidewall spacer contacts the upper electrode in the region above the sidewall spacer.

[0102] In some embodiments, a hard mask is present on the RRAM cell, and the non-oxide dielectric layer extends on the hard mask. In some embodiments, the hard mask on the sidewall spacer is positioned between the non-oxide dielectric layer and the central recess of the upper electrode. In some embodiments, the hard mask is limited to a height below the peak height of the upper surface of the upper electrode. In some embodiments, a silicon dioxide layer is present between the non-oxide dielectric layer and the ILD, and the ILD is a low-k dielectric. In some embodiments, the non-oxide dielectric layer includes silicon carbide (SiC), silicon nitride (SiN), or silicon carbonitride (SiCN).

[0103] In some embodiments, the lower electrode includes a central recess and an inclined sidewall, and the lower electrode is continuously inclined upward from the central recess to the inclined sidewall. In some embodiments, the non-oxide dielectric layer abuts against the inclined sidewall.

[0104] In some embodiments, the lower electrode includes a first layer on a second layer, the second layer being at least the same thickness as the first layer, and the second layer being in contact with one of the conductive traces. In some embodiments, the conductive traces include copper. In some embodiments, the second layer is an oxide, nitride, or oxynitride of a metal or metal alloy.

[0105] In some embodiments, the resistive switching structure comprises one or more metal oxides, and the RRAM cell is of a type in which conductive filaments are formed by oxygen vacancies within the resistive switching structure. In some embodiments, the resistive switching structure comprises a first layer adjacent to the lower electrode and a second layer adjacent to the upper electrode. The majority of the first layer is an oxide of a first metal, and the majority of the second layer is an oxide of a second metal, the second metal having a higher oxygen affinity than the first metal.

[0106] In some embodiments, the lower electrode layer is located on a dielectric barrier layer and has a central portion located on a hole penetrating the dielectric barrier layer, a peripheral portion located on the inclined sidewall of the dielectric barrier layer surrounding the hole, and a tapered surface connecting the surface of the peripheral portion to the surface of the central portion. In some embodiments, the dielectric barrier layer is a non-oxide dielectric.

[0107] Some aspects of the present invention relate to a semiconductor device comprising an RRAM cell within a metal interconnect structure disposed on a semiconductor substrate. The metal interconnect structure comprises a plurality of metallization layers separated by via layers, each metallization layer comprising conductive traces surrounded by interlayer dielectrics (ILDs), and each via layer comprising conductive vias interconnecting the conductive traces and surrounded by interlayer dielectrics. The RRAM cell comprises a lower electrode, an upper electrode, and a resistive switching structure located between the lower and upper electrodes. A first spacer is disposed on the upper surface of the resistive switching structure and along the outer sidewall of the upper electrode. A second spacer surrounds the lower electrode, the second spacer providing a physical barrier between the lower electrode and the interlayer dielectric, and is of a type that may be formed by an oxygen-free deposition process. In some embodiments, there is an interface layer between the second spacer and the interlayer dielectric. The interface layer may be an oxide layer.

[0108] Some aspects of the present invention relate to a method for manufacturing an integrated circuit device. The method includes forming a metallization layer on the surface of a semiconductor substrate, depositing a dielectric layer on the metallization layer, forming holes through the dielectric layer so that conductive traces within the metallization layer are exposed through the holes, depositing the lower electrode layer, the resistive switching layer, and the upper electrode layer on the dielectric layer and the holes such that each of the lower electrode layer, the resistive switching layer, and the upper electrode layer has a central recess on the holes, forming a hard mask on the upper electrode layer, performing a first etching process to define the upper electrode by etching through the upper electrode layer, forming a sidewall spacer around the upper electrode, and using a second etching process to define the lower electrode and expose the lower electrode sidewall by etching through the lower electrode layer. Either the first or second etching process etches the resistive switching layer to define the resistive switching structure, and the lower electrode, upper electrode, and resistive switching structure together provide an RRAM cell. This method further involves depositing a non-oxide dielectric layer on the lower electrode sidewall using a substantially oxygen-free deposition process, and depositing an interlayer dielectric (ILD), the non-oxide dielectric layer protecting the lower electrode from oxidation during ILD deposition.

[0109] In some embodiments, a second etching process provides a sidewall having an inclination that tapers at an angle with respect to the surface of the semiconductor substrate to the lower electrode. In some embodiments, a first etching process provides a sidewall having an inclination that tapers at an angle with respect to the surface of the semiconductor substrate to the upper electrode. In some embodiments, the bottom of the sidewall spacer slopes upward from a central recess. In some embodiments, a portion of the upper electrode is exposed by etching a portion of the hard mask in the second etching process. Non-oxide dielectric layer but Upper electrode The exposed portion is covered. In some embodiments, the hole has a tapered sidewall, and the lower electrode sidewall extends from the tapered sidewall. In some embodiments, this method is further covered by a silicon dioxide layer Non-oxide dielectric layerThis includes depositing a silicon dioxide layer to ensure close adhesion.

[0110] In some embodiments, depositing a resistive switching layer involves depositing a first layer containing an oxide of a first metal, followed by depositing a second layer containing an oxide of a second metal, where the first metal has a lower standard Gibbs free energy for oxygen vacancy formation for its maximum oxide than the second metal. In some embodiments, depositing the first layer involves depositing an oxide of a first metal and an oxide of a third metal, where the oxides of the first and third metals are deposited in different atomic layer deposition cycles, where the first metal has a lower standard Gibbs free energy for oxygen vacancy formation for its maximum oxide than the third metal.

[0111] The foregoing outlines the features of several embodiments so that those skilled in the art may better understand aspects of the present invention. Those skilled in the art should understand that the present invention can be readily used as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages as the embodiments presented herein. Those skilled in the art should also understand that such equivalent configurations do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the present invention. [Industrial applicability]

[0112] This invention provides a new integrated circuit device and a method for manufacturing an integrated circuit device. [Explanation of Symbols]

[0113] 100, 200, 600, 700: Integrated circuit devices 101, 133, 203: Diffusion barrier layer 103, 135, 303, 303a, 303b, 303c: Conductive traces 105, 405: Beer 107: Interlayer Dielectrics 109:Interfacial layer 111, 111A, 111B, 111C: Non-oxide dielectric layer 113, 113A, 113C: Hard mask 115: Upper electrode metal layer 117: Side wall spacer 119, 119A: Capping structure 122, 139, 140, 601, 603: Side wall 123: Lower electrode metal layer 125: Barrier layer 127: Dielectric layer 129: Interlayer Dielectrics (ILDs) 131, 131A, 131C: Lower electrode 137, 137A, 137B, 137C: Upper electrode 138: Vertical axis 141: Corner 143, 143A, 143B, 143C: Resistive Random-Access Memory (RRAM) cells 201: Capping metal layer 205, 205A, 205C, 1301: Resistive switching structure 205_1: High oxygen affinity metal oxide layer 205_2: Low oxygen affinity metal oxide layer 300, 400, 500, 800, 900, 1000, 1100, 1200, 1300, 1400, 1500, 1600, 1700, 1800, 1900, 2000, 2100, 2200, 2300, 2400, 2500, 2600, 2700, 2800, 2900, 3000, 3100: Cross-sectional view 301: Central area 305: Conductive via 307: Separate structure 309: Semiconductor substrate 310: Gate dielectric layer 311a, 311b: Source / drain area 312: Grid gate 313: Semiconductor devices 321: Metal interconnection structure 401: Memory area 403: Logical Domain 501: Oxygen deficiency 503: Conductive filament 701: Lower electrode via 901: Mask 903, 1703: Hall 905, 1201: width 1001, 1801, 2701: RRAM cell stack 1003: External area 1005: Tapered region 1007: Central recess 1009: Upper electrode layer 1011: Resistive switching layer 1013: Lower electrode layer 1303: Undercut 1401, 2201: Non-oxide dielectric materials 1701: Trench 1901:Top surface 1903: Resistive switch layer 3200: Method 3201, 3203, 3205, 3207, 3209, 3211, 3213, 3215, 3217, 3219, 3221, 3223: Operation M1, MX, MX+1: Metallization layer V1, V2: Via layer θ1, θ2, θ3: angles

Claims

1. A metal interconnect structure comprising a plurality of metallization layers disposed on a semiconductor substrate and separated by via layers, wherein each metallization layer includes a conductive trace surrounded by an interlayer dielectric (ILD), and each via layer includes conductive vias that interconnect the conductive traces and are surrounded by the interlayer dielectric, and A resistive random access memory (RRAM) cell comprising a lower electrode, an upper electrode, and a resistive switching structure located between the lower electrode and the upper electrode, integrated within the metal interconnect structure, A non-oxide dielectric layer surrounds the lower electrode and provides a physical barrier between the lower electrode and the interlayer dielectric, Integrated circuit devices, including those mentioned above.

2. The integrated circuit device according to claim 1, further comprising a side wall spacer positioned along the outer side wall of the upper electrode and positioned entirely above the lower electrode.

3. The integrated circuit device according to claim 2, wherein the side wall spacer is a non-oxide dielectric.

4. The integrated circuit device according to claim 2, wherein the non-oxide dielectric layer is arranged along the outer side wall of the side wall spacer.

5. The integrated circuit device according to claim 4, wherein the non-oxide dielectric layer abuts the upper electrode in a region above the side wall spacer.

6. The integrated circuit device according to claim 1, further comprising a silicon dioxide layer between the non-oxide dielectric layer and the ILD, wherein the ILD is a low-k dielectric.

7. The integrated circuit device according to claim 6, wherein the non-oxide dielectric layer comprises silicon carbide (SiC), silicon nitride (SiN), or silicon carbonitride (SiCN).

8. The lower electrode includes a central recess and inclined side walls. The integrated circuit device according to claim 1, wherein the lower electrode is continuously inclined upward from the central recess to the inclined side wall.

9. The lower electrode includes a first layer on top of the second layer, The second layer has at least the same thickness as the first layer. The second layer is in contact with one of the conductive traces. The conductive trace contains copper. The integrated circuit device according to claim 8.

10. The integrated circuit device according to claim 9, wherein the second layer is an oxide, nitride, or oxynitride of a metal or metal alloy.

11. The integrated circuit device according to claim 1, wherein the resistive switching structure includes a first layer adjacent to the lower electrode and a second layer adjacent to the upper electrode, the majority of which of the first layer is an oxide of a first metal, the majority of which of the second layer is an oxide of a second metal, and the second metal has a higher oxygen affinity than the first metal.

12. A metal interconnect structure disposed on a semiconductor substrate, wherein the metal interconnect structure includes a plurality of metallization layers separated by via layers, each metallization layer includes a conductive trace surrounded by an interlayer dielectric (ILD), and each via layer includes conductive vias that interconnect the conductive traces and are surrounded by the interlayer dielectric, and the metal interconnect structure, A resistive random access memory (RRAM) cell comprising a lower electrode, an upper electrode, and a resistive switching structure located between the lower electrode and the upper electrode, wherein the RRAM cell is integrated within the metal interconnect structure, and the upper surface of the upper electrode includes a tapered recess, A first spacer is positioned on the upper surface of the resistive switching structure and along the outer side wall of the upper electrode, A second dielectric layer surrounds the lower electrode, provides a physical barrier between the lower electrode and the interlayer dielectric, and is of a type that can be formed by an oxygen-free deposition process, Integrated circuit devices, including those mentioned above.

13. The integrated circuit device according to claim 12, further comprising an interface layer provided between the second dielectric layer and the interlayer dielectric, wherein the interface layer is an oxide.

14. Forming a metallization layer containing conductive traces on the surface of a semiconductor substrate, Depositing a dielectric layer on the metallization layer, To form the holes penetrating the dielectric layer so that the conductive traces are exposed through the holes, The lower electrode layer, the resistive switching structure, and the upper electrode layer are deposited on the dielectric layer and the holes, such that each of them has a central recess above the holes. Forming a hard mask on the upper electrode layer, A first etching process is performed to define the upper electrode by etching through the upper electrode layer, By forming a side wall spacer around the upper electrode, The second etching process is used to etch through the lower electrode layer to define the lower electrode and expose the lower electrode sidewall, wherein either the first etching process or the second etching process etches through the resistive switching structure to define the resistive switching structure, and the lower electrode, the upper electrode, and the resistive switching structure together provide a resistive random access memory (RRAM) cell. The process involves depositing a non-oxide dielectric layer on the lower electrode sidewall using a substantially oxygen-free deposition process, The non-oxide dielectric layer is deposited in such a way as to protect the lower electrode from oxidation during the deposition of the interlayer dielectric (ILD), A method for manufacturing an integrated circuit device, including [a specific component].

15. The method according to claim 14, wherein the second etching process provides the lower electrode with a side wall having an angle tapered slope with respect to the surface of the semiconductor substrate.

16. The method according to claim 14, wherein the first etching process provides the upper electrode with a side wall having an angle tapered slope with respect to the surface of the semiconductor substrate.

17. The method according to claim 16, wherein the bottom of the side wall spacer is inclined upward from the central recess.

18. The method according to claim 14, wherein the second etching process penetrates and etches a portion of the hard mask to expose a portion of the upper electrode, and the oxide-free dielectric covers the exposed portion.

19. The method according to claim 14, further comprising depositing a silicon dioxide layer, wherein the ILD is in close contact with the oxide-free dielectric by the silicon dioxide layer.

20. The method according to claim 14, wherein the deposition of the resistive switching structure comprises depositing a first layer containing an oxide of a first metal, followed by depositing a second layer containing an oxide of a second metal, wherein the first metal has a lower standard Gibbs free energy for oxygen defect formation for its maximum oxide than the second metal.

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