Semiconductor equipment

Abstract

The present invention provides a semiconductor device that can suppress differences in gate wiring resistance between multiple transistors. [Solution] The semiconductor device includes a gate terminal, a gate wiring electrically connected to the gate terminal, a first transistor having a first gate pad electrically connected to the gate wiring, a second transistor having a second gate pad electrically connected in parallel with the first transistor to the gate wiring, a first wire connecting the gate wiring and the first gate pad, and a second wire connecting the gate wiring and the second gate pad, wherein the gate wiring has a first connection point to which the first wire is connected and a second connection point to which the second wire is connected, the first signal path length between the first connection point and the gate terminal is shorter than the second signal path length between the second connection point and the gate terminal, and the first length of the first wire between the first connection point and the first gate pad is longer than the second length of the second wire between the second connection point and the second gate pad.

Description

Technical Field

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[0001] This disclosure relates to a semiconductor device.

Background Art

[0002] A semiconductor device in which a plurality of transistors are provided on an insulating substrate is known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a conventional semiconductor device, there is a possibility that the difference in gate wiring resistance between a plurality of transistors becomes large.

[0005] An object of this disclosure is to provide a semiconductor device capable of suppressing the difference in gate wiring resistance between a plurality of transistors.

Means for Solving the Problems

[0006] The semiconductor device of the present disclosure includes a gate terminal, a gate wiring electrically connected to the gate terminal, a first transistor having a first gate pad electrically connected to the gate wiring, a second transistor having a second gate pad electrically connected in parallel with the first transistor to the gate wiring, a first wire connecting the gate wiring and the first gate pad, and a second wire connecting the gate wiring and the second gate pad, wherein the gate wiring has a first connection point to which the first wire is connected and a second connection point to which the second wire is connected, the first signal path length between the first connection point and the gate terminal is shorter than the second signal path length between the second connection point and the gate terminal, and the first length of the first wire between the first connection point and the first gate pad is longer than the second length of the second wire between the second connection point and the second gate pad. [Effects of the Invention]

[0007] According to this disclosure, differences in gate wiring resistance between multiple transistors can be suppressed. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a plan view showing a semiconductor device according to the first embodiment. [Figure 2] Figure 2 is a schematic diagram showing the signal path length of the control signal in the semiconductor device according to the first embodiment. [Figure 3] Figure 3 is a plan view showing a semiconductor device according to the second embodiment. [Figure 4] Figure 4 is a schematic diagram showing the relationship of wire heights in a semiconductor device according to the second embodiment. [Figure 5] Figure 5 is a plan view showing a semiconductor device according to the third embodiment. [Figure 6] Figure 6 is a schematic diagram showing the signal path length of the control signal in the semiconductor device according to the third embodiment. [Figure 7] Figure 7 is a plan view showing a device according to the fourth embodiment. [Figure 8] Figure 8 is a schematic diagram showing the signal path length of the control signal in the semiconductor device according to the fourth embodiment. [Modes for carrying out the invention]

[0009] The implementation methods are described below.

[0010] [Description of Embodiments in this Disclosure] The embodiments of this disclosure are listed and described below. In the following description, the same or corresponding elements are denoted by the same reference numerals, and the same description will not be repeated. In the following description, the XYZ Cartesian coordinate system is used, but this coordinate system is defined for illustrative purposes and is not limited to the orientation of the semiconductor device. Also, from any point, the +Z side may be referred to as up, upper, or top, and the -Z side may be referred to as down, lower, or bottom. In this disclosure, "planar view" means viewing an object from above, and "planar shape" means the shape of an object as viewed from above.

[0011] [1] A semiconductor device according to one aspect of the present disclosure includes a gate terminal, a gate wiring electrically connected to the gate terminal, a first transistor having a first gate pad electrically connected to the gate wiring, a second transistor having a second gate pad electrically connected in parallel with the first transistor to the gate wiring, a first wire connecting the gate wiring and the first gate pad, and a second wire connecting the gate wiring and the second gate pad, wherein the gate wiring has a first connection point to which the first wire is connected, and a second connection point to which the second wire is connected, the first signal path length between the first connection point and the gate terminal is shorter than the second signal path length between the second connection point and the gate terminal, and the first length of the first wire between the first connection point and the first gate pad is longer than the second length of the second wire between the second connection point and the second gate pad.

[0012] Since the length of the first signal path between the first connection point and the gate terminal is shorter than the length of the second signal path between the second connection point and the gate terminal, the resistance between the first connection point and the gate terminal is lower than the resistance between the second connection point and the gate terminal. Also, since the first length of the first wire between the first connection point and the first gate pad is longer than the second length of the second wire between the second connection point and the second gate pad, the resistance of the first wire is higher than the resistance of the second wire. Therefore, the difference between the sum of the resistance between the first connection point and the gate terminal and the resistance of the first wire, and the sum of the resistance between the second connection point and the gate terminal and the resistance of the second wire is kept small and suppressed. As a result, the difference in gate wiring resistance between the first transistor and the second transistor can be suppressed.

[0013] [2] In [1], the gate wiring includes a third transistor having a third gate pad electrically connected in parallel with the first transistor, and a third wire connecting the gate wiring and the third gate pad, wherein the gate wiring has a third connection point to which the third wire is connected, the length of the third signal path between the third connection point and the gate terminal is longer than the length of the first signal path and shorter than the length of the second signal path, and the third length of the third wire between the third connection point and the third gate pad may be shorter than the first length and longer than the second length. In this case, the difference in gate wiring resistance between the first transistor and the third transistor can be suppressed, and the difference in gate wiring resistance between the third transistor and the second transistor can be suppressed.

[0014] [3] The present invention provides a plurality of transistors having gate pads electrically connected to the gate wiring, and a plurality of wires connecting the gate wiring to each of the plurality of gate pads, wherein the gate wiring has a plurality of connection points to which each of the plurality of wires is connected, the first signal path length is the shortest of the plurality of signal path lengths between the plurality of connection points and the gate terminal, the second signal path length is the longest of the plurality of signal path lengths between the plurality of connection points and the gate terminal, the first length is the longest of the plurality of wire lengths between each of the plurality of connection points and each of the plurality of gate pads, and the second length is the shortest of the plurality of wire lengths between each of the plurality of connection points and each of the plurality of gate pads. In this case, differences in gate wiring resistance between the plurality of transistors can be suppressed.

[0015] [4] In any of [1] to [3], there is an insulating substrate having a first main surface, the gate wiring is provided on the first main surface, the first transistor is positioned between the gate terminal and the second transistor in a direction along the gate wiring, and in a plan view from a direction perpendicular to the first main surface, the first distance between the first gate pad and the gate wiring may be longer than the second distance between the second gate pad and the gate wiring. In this case, the lengths of the first wire and the second wire can be adjusted according to the arrangement of the first transistor and the second transistor, and the difference in gate wiring resistance between the first transistor and the second transistor can be suppressed.

[0016] [5] In any of [1] to [3], there is an insulating substrate having a first main surface, the gate wiring is provided on the first main surface, and the third distance between the first point of the first wire furthest from the first main surface and the first main surface may be greater than the fourth distance between the second point of the second wire furthest from the first main surface and the first main surface. In this case, the lengths of the first wire and the second wire can be adjusted during wire bonding, and differences in gate wiring resistance between the first transistor and the second transistor can be suppressed.

[0017] 〔6〕 In any one of 〔1〕 to 〔3〕, it has an insulating substrate having a first main surface, the gate wiring is provided on the first main surface, and in a plan view from a direction perpendicular to the first main surface, a first angle formed by the short side direction of the gate wiring and the first wire may be larger than a second angle formed by the short side direction and the second wire. In this case, the lengths of the first wire and the second wire can be adjusted during wire bonding, and a difference in gate wiring resistance between the first transistor and the second transistor can be suppressed.

[0018] 〔7〕 In any one of 〔1〕 to 〔6〕, the first transistor and the second transistor may include at least one selected from the group consisting of silicon carbide, silicon, gallium nitride, and gallium oxide. In this case, it is easy to use the semiconductor device for a power module or the like.

[0019] 〔8〕 In any one of 〔1〕 to 〔7〕, it may have a fourth wire connecting the gate terminal and the gate wiring. In this case, the semiconductor device is easy to assemble.

[0020] [Embodiments of the Present Disclosure] (First Embodiment) The first embodiment will be described. The first embodiment relates to a semiconductor device. FIG. 1 is a plan view showing the semiconductor device according to the first embodiment. FIG. 2 is a schematic diagram showing the signal path length of the control signal in the semiconductor device according to the first embodiment.

[0021] As shown in FIG. 1, the semiconductor device 1 according to the first embodiment includes an insulating substrate 10, a gate pattern 11, a source pattern 12, a drain pattern 13, transistors 20A, 20B, 20C, and 20D, a gate terminal 51, a source terminal 52, and a drain terminal 53. The semiconductor device 1 further includes wires 31A, 31B, 31C, 31D, 41, 42, and 43. The transistors 20A, 20B, 20C, and 20D are, for example, field effect transistors (FETs).

[0022] The insulating substrate 10 has a bottom surface (-Z side) and an upper surface 10A (+Z side) opposite to the bottom surface, and the gate pattern 11, source pattern 12, and drain pattern 13 are provided on the upper surface 10A of the insulating substrate 10. The material of the insulating substrate 10 is, for example, silicon nitride (SiN), aluminum oxide (Al2O3), or aluminum nitride (AlN). The material of the gate pattern 11, source pattern 12, and drain pattern 13 is, for example, copper (Cu). The upper surface 10A is an example of a first main surface.

[0023] The gate pattern 11 has a rectangular planar shape with a longitudinal direction along the X-axis. The drain pattern 13 has a rectangular planar shape with a longitudinal direction along the X-axis. The drain pattern 13 is on the -Y side of the gate pattern 11. The source pattern 12 has an L-shaped planar shape and has a portion on the -Y side of the drain pattern 13 and a portion on the -X side of the drain pattern 13. The portion on the -Y side of the drain pattern 13 has a rectangular planar shape with a longitudinal direction along the X-axis, and the portion on the -X side of the drain pattern 13 has a rectangular planar shape with a longitudinal direction along the Y-axis. The gate pattern 11 is an example of gate wiring.

[0024] Transistor 20A mainly comprises a silicon carbide substrate, a gate pad 21A, a source pad 22A, a drain pad (not shown), and a passivation film 23A. Transistor 20A includes one or more transistor cells, and each transistor cell is provided with a gate electrode. The silicon carbide substrate of transistor 20A has a bottom surface and an upper surface opposite to the bottom surface. The gate pad 21A and source pad 22A are provided on the upper surface, and the drain pad is provided on the bottom surface. The silicon carbide substrate includes a silicon carbide single crystal substrate and a silicon carbide epitaxial layer formed on the silicon carbide single crystal substrate. The passivation film 23A covers the silicon carbide substrate, the gate pad 21A, and the source pad 22A. The passivation film 23A has a gate opening in which the gate pad 21A is exposed and a source opening in which the source pad 22A is exposed. Transistor 20A is an example of a first transistor, and gate pad 21A is an example of a first gate pad.

[0025] Transistor 20B mainly comprises a silicon carbide substrate, a gate pad 21B, a source pad 22B, a drain pad (not shown), and a passivation film 23B. Transistor 20B includes one or more transistor cells, each of which is provided with a gate electrode. The silicon carbide substrate of transistor 20B has a bottom surface and an upper surface opposite to the bottom surface. The gate pad 21B and source pad 22B are provided on the upper surface, and the drain pad is provided on the bottom surface. The silicon carbide substrate includes a silicon carbide single crystal substrate and a silicon carbide epitaxial layer formed on the silicon carbide single crystal substrate. The passivation film 23B covers the silicon carbide substrate, the gate pad 21B, and the source pad 22B. The passivation film 23B has a gate opening through which the gate pad 21B is exposed and a source opening through which the source pad 22B is exposed. Transistor 20B is an example of a third transistor, and gate pad 21B is an example of a third gate pad.

[0026] Transistor 20C mainly comprises a silicon carbide substrate, a gate pad 21C, a source pad 22C, a drain pad (not shown), and a passivation film 23C. Transistor 20C includes one or more transistor cells, each of which is provided with a gate electrode. The silicon carbide substrate of transistor 20C has a bottom surface and an upper surface opposite to the bottom surface. The gate pad 21C and source pad 22C are provided on the upper surface, and the drain pad is provided on the bottom surface. The silicon carbide substrate includes a silicon carbide single crystal substrate and a silicon carbide epitaxial layer formed on the silicon carbide single crystal substrate. The passivation film 23C covers the silicon carbide substrate, the gate pad 21C, and the source pad 22C. The passivation film 23C has a gate opening through which the gate pad 21C is exposed and a source opening through which the source pad 22C is exposed. Transistor 20C is another example of a third transistor, and gate pad 21C is another example of a third gate pad.

[0027] The transistor 20D mainly comprises a silicon carbide substrate, a gate pad 21D, a source pad 22D, a drain pad (not shown), and a passivation film 23D. The transistor 20D includes one or more transistor cells, each of which is provided with a gate electrode. The silicon carbide substrate of the transistor 20D has a bottom surface and an upper surface opposite to the bottom surface. The gate pad 21D and source pad 22D are provided on the upper surface, and the drain pad is provided on the bottom surface. The silicon carbide substrate includes a silicon carbide single crystal substrate and a silicon carbide epitaxial layer formed on the silicon carbide single crystal substrate. The passivation film 23D covers the silicon carbide substrate, the gate pad 21D, and the source pad 22D. The passivation film 23D has a gate opening through which the gate pad 21D is exposed and a source opening through which the source pad 22D is exposed. Transistor 20D is an example of a second transistor, and gate pad 21D is an example of a second gate pad.

[0028] Excluding manufacturing tolerances, the internal gate resistances of transistors 20A, 20B, 20C, and 20D are equal to each other. Internal gate resistance is the electrical resistance between the gate pad and the gate electrode of the transistor cell. The internal gate resistance primarily depends on the electrical resistance of the gate electrode material, such as polycrystalline silicon.

[0029] Transistors 20A, 20B, 20C, and 20D are located on the drain pattern 13. Transistor 20B is on the +X side of transistor 20A, transistor 20C is on the +X side of transistor 20B, and transistor 20D is on the +X side of transistor 20C. Transistor 20A is further from the gate pattern 11 than transistor 20B. Transistor 20B is further from the gate pattern 11 than transistor 20C. Transistor 20C is further from the gate pattern 11 than transistor 20D. Transistors 20B and 20C are located between transistors 20A and 20D, transistor 20B is located between transistors 20A and 20C, and transistor 20C is located between transistors 20B and 20D. The drain pads of transistors 20A, 20B, 20C, and 20D are bonded to the drain pattern 13 by a conductive bonding material. The conductive bonding material is, for example, solder such as lead-free solder containing tin (Sn).

[0030] In a plan view from a direction perpendicular to the top surface 10A, distance D1A is greater than distance D1B, distance D1B is greater than distance D1C, and distance D1C is greater than distance D1D. Distance D1A is the distance between gate pad 21A and gate pattern 11. Distance D1B is the distance between gate pad 21B and gate pattern 11. Distance D1C is the distance between gate pad 21C and gate pattern 11. Distance D1D is the distance between gate pad 21D and gate pattern 11. Distance D1A is an example of a first distance, and distance D1D is an example of a second distance.

[0031] Gate pads 21A, 21B, 21C, and 21D are connected to the gate pattern 11 by wires 31A, 31B, 31C, and 31D, respectively. In other words, gate pads 21A, 21B, 21C, and 21D are electrically connected to the gate pattern 11. The number of wires 31A, 31B, 31C, and 31D may be one each. Wire 31B is connected to the gate pattern 11 on the +X side of wire 31A, wire 31C is connected to the gate pattern 11 on the +X side of wire 31B, and wire 31D is connected to the gate pattern 11 on the +X side of wire 31C. In other words, wires 31B and 31C are connected to the gate pattern 11 between wire 31A and wire 31D, wire 31B is connected to the gate pattern 11 between wire 31A and wire 31C, and wire 31C is connected to the gate pattern 11 between wire 31B and wire 31D. Wire 31A is longer than wire 31B, wire 31B is longer than wire 31C, and wire 31C is longer than wire 31D. The material of wires 31A, 31B, 31C, and 31D is, for example, aluminum (Al) or gold (Au). Wire 31A is an example of a first wire, and wire 31D is an example of a second wire. Wire 31B is an example of a third wire, and wire 31C is another example of a third wire.

[0032] The gate pattern 11 has a connection point 61A to which wire 31A is connected, a connection point 61B to which wire 31B is connected, a connection point 61C to which wire 31C is connected, a connection point 61D to which wire 31D is connected, and a connection point 62 to which wire 41 is connected. Connection point 61A is closer to connection point 62 than connection point 61B, connection point 61B is closer to connection point 62 than connection point 61C, and connection point 61C is closer to connection point 62 than connection point 61D. Gate pad 21A has a connection point 60A to which wire 31A is connected. Gate pad 21B has a connection point 60B to which wire 31B is connected. Gate pad 21C has a connection point 60C to which wire 31C is connected. Gate pad 21D has a connection point 60D to which wire 31D is connected. Connection point 61A is an example of a first connection point, connection point 61B is an example of a third connection point, connection point 61C is another example of a third connection point, and connection point 61D is an example of a second connection point.

[0033] In the longitudinal direction of the gate pattern 11, connection points 60A and 61A may be at the same position as each other. In the longitudinal direction (X-axis direction) of the gate pattern 11, connection points 60B and 61B may be at the same position (coordinates) as each other. In the longitudinal direction of the gate pattern 11, connection points 60C and 61C may be at the same position (coordinates) as each other. In the longitudinal direction of the gate pattern 11, connection points 60D and 61D may be at the same position (coordinates) as each other. In a side view from the short direction perpendicular to the longitudinal direction of the gate pattern 11, connection point 61A may overlap with connection point 60A, connection point 61B may overlap with connection point 60B, connection point 61C may overlap with connection point 60C, and connection point 61D may overlap with connection point 60D.

[0034] Source pads 22A, 22B, 22C, and 22D are connected to source pattern 12 by wires 32A, 32B, 32C, and 32D, respectively. In other words, source pads 22A, 22B, 22C, and 22D are electrically connected to source pattern 12. There may be multiple wires 32A, 32B, 32C, and 32D. Wire 32B is connected to source pattern 12 on the +X side of wire 32A, wire 32C is connected to source pattern 12 on the +X side of wire 32B, and wire 32D is connected to source pattern 12 on the +X side of wire 32C. In other words, wires 32B and 32C are connected to source pattern 12 between wire 32A and wire 32D, wire 32B is connected to source pattern 12 between wire 32A and wire 32C, and wire 32C is connected to source pattern 12 between wire 32B and wire 32D. The material of wires 32A, 32B, 32C, and 32D is, for example, aluminum (Al) or gold (Au).

[0035] The gate terminal 51, source terminal 52, and drain terminal 53 are provided, for example, on the upper surface of the insulating substrate 10. The gate terminal 51 is provided near the gate pattern 11 on the +Y side of the gate pattern 11. The gate terminal 51 is connected to the gate pattern 11 by wire 41. In other words, the gate terminal 51 is electrically connected to the gate pattern 11. Wire 41 is connected to the gate pattern 11 on the -X side of wires 31A, 31B, 31C, and 31D. The source terminal 52 is provided near the source pattern 12 on the -X side of the source pattern 12. The source terminal 52 is connected to the source pattern 12 by wire 42. In other words, the source terminal 52 is electrically connected to the source pattern 12. The drain terminal 53 is provided near the drain pattern 13 on the +X side of the drain pattern 13. The drain terminal 53 is connected to the drain pattern 13 by wire 43. In other words, the drain terminal 53 is electrically connected to the drain pattern 13. The number of wires 41 may be one. The number of wires 42 and 43 may be multiple. The material of wires 41, 42, and 43 is, for example, aluminum (Al) or gold (Au). Wire 41 is an example of a fourth wire.

[0036] Control signals from transistors 20A, 20B, 20C, and 20D are input to gate terminal 51. The control signals input to gate terminal 51 are transmitted to gate pads 21A, 21B, 21C, and 21D through wire 41, gate pattern 11, and wires 31A, 31B, 31C, or 31D. The signal path length of the control signals will now be described.

[0037] As shown in Figure 2, the length of wire 41 is L0, and the lengths of wires 31A, 31B, 31C, and 31D are L2A, L2B, L2C, and L2D, respectively. Length L2A is longer than length L2B, length L2B is longer than length L2C, and length L2C is longer than length L2D.

[0038] Therefore, the resistance R1A between connection point 60A and connection point 61A of wire 31A is higher than the resistance R1B between connection point 60B and connection point 61B of wire 31B. Also, resistance R1B is higher than the resistance R1C between connection point 60C and connection point 61C of wire 31C, and resistance R1C is higher than the resistance R1D between connection point 60D and connection point 61D of wire 31D. The heights of wires 31A, 31B, 31C, and 31D, i.e., the distance between the point furthest from the top surface 10A and the top surface 10A, may be equal to each other.

[0039] Furthermore, on the gate pattern 11, the distance between connection point 62 and connection point 61A is L1A, the distance between connection point 62 and connection point 61B is L1B, the distance between connection point 62 and connection point 61C is L1C, and the distance between connection point 62 and connection point 61D is L1D. Length L1B is longer than length L1A, length L1C is longer than length L1B, and length L1D is longer than length L1C.

[0040] Therefore, the signal path length (L0+L1A) between connection point 61A and gate terminal 51 is shorter than the signal path length (L0+L1B) between connection point 61B and gate terminal 51. Consequently, the resistance R2A between gate terminal 51 and connection point 61A is lower than the resistance R2B between gate terminal 51 and connection point 61B. The signal path length (L0+L1A) between connection point 61A and gate terminal 51 is an example of a first signal path length. The signal path length (L0+L1B) between connection point 61B and gate terminal 51 is an example of a third signal path length.

[0041] Furthermore, the signal path length (L0+L1B) between connection point 61B and gate terminal 51 is shorter than the signal path length (L0+L1C) between connection point 61C and gate terminal 51. Therefore, the resistance R2B between gate terminal 51 and connection point 61B is lower than the resistance R2C between gate terminal 51 and connection point 61C. The signal path length (L0+L1C) between connection point 61C and gate terminal 51 is another example of a third signal path length.

[0042] Furthermore, the signal path length (L0+L1C) between connection point 61C and gate terminal 51 is shorter than the signal path length (L0+L1D) between connection point 61D and gate terminal 51. Therefore, the resistance R2C between gate terminal 51 and connection point 61C is lower than the resistance R2D between gate terminal 51 and connection point 61D. The signal path length (L0+L1D) between connection point 61D and gate terminal 51 is an example of a second signal path length.

[0043] In the first embodiment, as described above, the resistance R1A of wire 31A is higher than the resistance R1B of wire 31B, the resistance R1B of wire 31B is higher than the resistance R1C of wire 31C, and the resistance R1C of wire 31C is higher than the resistance R1D of wire 31D. In other words, among the resistances R1A, R1B, R1C, and R1D, resistance R1A is the highest and resistance R1D is the lowest. Also, resistance R2A is lower than resistance R2B, resistance R2B is lower than resistance R2C, and resistance R2C is lower than resistance R2D. Therefore, the difference between the gate wiring resistance (R1A + R2A) between the gate terminal 51 and the gate pad 21A of transistor 20A and the gate wiring resistance (R1B + R2B) between the gate terminal 51 and the gate pad 21B of transistor 20B is kept small and suppressed. Furthermore, the difference between the gate wiring resistance (R1B+R2B) between gate terminal 51 and gate pad 21B of transistor 20B and the gate wiring resistance (R1C+R2C) between gate terminal 51 and gate pad 21C of transistor 20C is suppressed to a small extent. Also, the difference between the gate wiring resistance (R1C+R2C) between gate terminal 51 and gate pad 21C of transistor 20C and the gate wiring resistance (R1D+R2D) between gate terminal 51 and gate pad 21D of transistor 20D is suppressed to a small extent.

[0044] Therefore, according to the first embodiment, it is possible to suppress the timing difference in operation caused by differences in gate wiring resistance between transistors 20A, 20B, 20C, and 20D. For example, it is possible to suppress the timing difference in turn-on and turn-off between transistors 20A, 20B, 20C, and 20D. By suppressing the timing difference in operation, it is possible to suppress differences in the current flowing through transistors 20A, 20B, 20C, and 20D. Furthermore, oscillation of the circuit including transistors 20A, 20B, 20C, and 20D can also be suppressed.

[0045] In the first embodiment, for example, the lengths of wires 31A, 31B, 31C, and 31D can be adjusted according to the arrangement of transistors 20A, 20B, 20C, and 20D.

[0046] Here, we will explain the effect in a specific example. In this example, we assume that the planar shape of transistors 20A, 20B, 20C, and 20D is a square with a side length of 4 mm. We assume that the distance between transistors 20A and 20B, the distance between transistors 20B and 20C, and the distance between transistors 20C and 20D in the X-axis direction is 1 mm. We assume that the distance between connection point 62 and connection point 61A, the distance between connection point 61A and connection point 61B, the distance between connection point 61B and connection point 61C, and the distance between connection point 61C and connection point 61D is 5 mm. We assume that the width (Y-axis dimension) of the gate pattern 11 is 1 mm and the thickness (Z-axis dimension) is 0.5 mm, and that the resistances between connection point 62 and connection points 61A, 61B, 61C, and 61D are 0.2 mΩ, 0.4 mΩ, 0.6 mΩ, and 0.8 mΩ, respectively.

[0047] Furthermore, assume that the lengths of wires 31A, 31B, 31C, and 31D are 10.0 mm, 9.9 mm, 9.8 mm, and 9.6 mm, respectively. Assume that the diameter of wires 31A, 31B, 31C, and 31D is 150 μm and the resistivity is 2.7 μΩ·cm. In this case, the resistances of wires 31A, 31B, 31C, and 31D are 15.3 mΩ, 15.1 mΩ, 14.9 mΩ, and 14.7 mΩ.

[0048] Therefore, in this specific example, the resistance between connection point 62 and gate pads 21A, 21B, 21C, and 21D is 15.5 mΩ in all cases. This indicates that, for example, if wire 31D is 0.4 mm shorter than wire 31A, the resistance between connection point 62 and gate pads 21A and 21D becomes equal.

[0049] (Second Embodiment) A second embodiment will now be described. The second embodiment differs from the first embodiment mainly in the arrangement of transistors and the height of the wires. Figure 3 is a plan view showing a semiconductor device according to the second embodiment. Figure 4 is a schematic diagram showing the relationship of wire heights in the semiconductor device according to the second embodiment.

[0050] As shown in Figure 3, in the semiconductor device 2 according to the second embodiment, transistors 20A, 20B, 20C, and 20D are arranged along the X-axis, and excluding manufacturing tolerances, the distances between each of the transistors 20A, 20B, 20C, and 20D and the gate pattern 11 are equal to each other. Also, excluding manufacturing tolerances, the distances D1A, D1B, D1C, and D1D are equal to each other in a plan view from a direction perpendicular to the top surface 10A.

[0051] As shown in Figure 4, the distances between the points P1A, P1B, P1C, and P1D, which are furthest from the top surface 10A of each of the wires 31A, 31B, 31C, and 31D, and the top surface 10A are D2A, D2B, D2C, and D2D, respectively. Distance D2A is greater than distance D2B, distance D2B is greater than distance D2C, and distance D2C is greater than distance D2D. That is, wire 31A is formed higher than wire 31B, wire 31B is formed higher than wire 31C, and wire 31C is formed higher than wire 31D. The length L2A of wire 31A is longer than the length L2B of wire 31B, the length L2B of wire 31B is longer than the length L2C of wire 31C, and the length L2C of wire 31C is longer than the length L2D of wire 31D. Therefore, as in the first embodiment, resistance R1A is higher than resistance R1B, resistance R1B is higher than resistance R1C, and resistance R1C is higher than resistance R1D. Point P1A is an example of a first point, and point P1D is an example of a second point. Distance D2A is an example of a third distance, and distance D2D is an example of a fourth distance.

[0052] Other configurations of the second embodiment are the same as those of the first embodiment.

[0053] In the second embodiment as well, the difference between the gate wiring resistance (R1A+R2A) between the gate terminal 51 and the gate pad 21A of transistor 20A and the gate wiring resistance (R1B+R2B) between the gate terminal 51 and the gate pad 21B of transistor 20B is suppressed to a small extent. Furthermore, the difference between the gate wiring resistance (R1B+R2B) between the gate terminal 51 and the gate pad 21B of transistor 20B and the gate wiring resistance (R1C+R2C) between the gate terminal 51 and the gate pad 21C of transistor 20C is suppressed to a small extent. Furthermore, the difference between the gate wiring resistance (R1C+R2C) between the gate terminal 51 and the gate pad 21C of transistor 20C and the gate wiring resistance (R1D+R2D) between the gate terminal 51 and the gate pad 21D of transistor 20D is suppressed to a small extent.

[0054] Therefore, the second embodiment can also suppress timing differences in operation between transistors 20A, 20B, 20C, and 20D caused by differences in gate wiring resistance. For example, timing differences in turn-on and turn-off between transistors 20A, 20B, 20C, and 20D can be suppressed. By suppressing the timing differences in operation, differences in the current flowing through transistors 20A, 20B, 20C, and 20D can be suppressed. Furthermore, oscillation of the circuit including transistors 20A, 20B, 20C, and 20D can also be suppressed.

[0055] In the second embodiment, for example, the lengths of wires 31A, 31B, 31C, and 31D can be adjusted during wire bonding.

[0056] In Figure 3, for convenience, the relationship between the lengths of wires 31A, 31B, 31C, and 31D is illustrated as follows: in the XY plane, wire 31A is curved more than wire 31B, wire 31B is curved more than wire 31C, and wire 31C is curved more than wire 31D, making it easier to visually understand the length relationship between wires 31A, 31B, 31C, and 31D.

[0057] (Third embodiment) A third embodiment will now be described. The third embodiment differs from the first embodiment mainly in the arrangement of transistors and wires. Figure 5 is a plan view showing a semiconductor device according to the third embodiment. Figure 6 is a schematic diagram showing the signal path length of a control signal in the semiconductor device according to the third embodiment.

[0058] As shown in Figure 5, in the semiconductor device 3 according to the third embodiment, transistors 20A, 20B, 20C, and 20D are arranged along the X-axis, and excluding manufacturing tolerances, the distances between each of the transistors 20A, 20B, 20C, and 20D and the gate pattern 11 are equal to each other. Also, excluding manufacturing tolerances, the distances D1A, D1B, D1C, and D1D are equal to each other in a plan view from a direction perpendicular to the top surface 10A.

[0059] As shown in Figure 6, in the X-axis direction (the longitudinal direction of the gate pattern 11), connection point 61A is located between connection points 60A and 60B. That is, the X-coordinate of connection point 61A is greater than the X-coordinate of connection point 60A and smaller than the X-coordinate of connection point 60B. In the X-axis direction, connection point 61B is located between connection points 60B and 60C. That is, the X-coordinate of connection point 61B is greater than the X-coordinate of connection point 60B and smaller than the X-coordinate of connection point 60C. In the X-axis direction, connection point 61C is located between connection points 60C and 60D. That is, the X-coordinate of connection point 61C is greater than the X-coordinate of connection point 60C and smaller than the X-coordinate of connection point 60D. Alternatively, in a side view from the short direction (Y-axis direction) perpendicular to the longitudinal direction of the gate pattern 11, connection point 61A is between connection point 60A and connection point 60B, connection point 61B is between connection point 60B and connection point 60C, and connection point 61C is between connection point 60C and connection point 60D. In the X-axis direction, connection points 60D and 61D may be at the same position (coordinates) as each other.

[0060] Furthermore, as shown in Figure 6, in a plan view from a direction perpendicular to the top surface 10A, the angle θA between the short side of the gate pattern 11 and wire 31A is greater than the angle θB between the short side of the gate pattern 11 and wire 31B. In a plan view from a direction perpendicular to the top surface 10A, the angle θB between the short side of the gate pattern 11 and wire 31B is greater than the angle θC between the short side of the gate pattern 11 and wire 31C. In a plan view from a direction perpendicular to the top surface 10A, the angle θC between the short side of the gate pattern 11 and wire 31C is greater than the angle θD between the short side of the gate pattern 11 and wire 31D. The length L2A of wire 31A is longer than the length L2B of wire 31B, the length L2B of wire 31B is longer than the length L2C of wire 31C, and the length L2C of wire 31C is longer than the length L2D of wire 31D. Therefore, as in the first embodiment, resistance R1A is higher than resistance R1B, resistance R1B is higher than resistance R1C, and resistance R1C is higher than resistance R1D. Angle θA is an example of a first angle, and angle θD is an example of a second angle. Angle θD may be 0 degrees.

[0061] The other configurations of the third embodiment are the same as those of the first embodiment.

[0062] In the third embodiment as well, the difference between the gate wiring resistance (R1A+R2A) between the gate terminal 51 and the gate pad 21A of transistor 20A and the gate wiring resistance (R1B+R2B) between the gate terminal 51 and the gate pad 21B of transistor 20B is suppressed to a small extent. Furthermore, the difference between the gate wiring resistance (R1B+R2B) between the gate terminal 51 and the gate pad 21B of transistor 20B and the gate wiring resistance (R1C+R2C) between the gate terminal 51 and the gate pad 21C of transistor 20C is suppressed to a small extent. Furthermore, the difference between the gate wiring resistance (R1C+R2C) between the gate terminal 51 and the gate pad 21C of transistor 20C and the gate wiring resistance (R1D+R2D) between the gate terminal 51 and the gate pad 21D of transistor 20D is suppressed to a small extent.

[0063] Therefore, the third embodiment can also suppress the timing difference in operation caused by differences in gate wiring resistance between transistors 20A, 20B, 20C, and 20D. For example, it can suppress the timing difference in turn-on and turn-off between transistors 20A, 20B, 20C, and 20D. By suppressing the timing difference in operation, it can suppress differences in the current flowing through transistors 20A, 20B, 20C, and 20D. Furthermore, it can also suppress oscillation of the circuit including transistors 20A, 20B, 20C, and 20D.

[0064] In the third embodiment, for example, the lengths of wires 31A, 31B, 31C, and 31D can be adjusted during wire bonding.

[0065] Furthermore, assuming the same change in signal path length, the increase in electrical resistance due to the extension of the signal path length in wires 31A, 31B, 31C, and 31D is greater than the decrease in electrical resistance due to the shortening of the signal path length in the gate pattern 11. This is because the area of ​​the cross-section of wires 31A, 31B, 31C, and 31D perpendicular to the signal propagation direction is smaller than the area of ​​the cross-section of the gate pattern 11 perpendicular to the signal propagation direction. Therefore, in the X-axis direction (longitudinal direction of the gate pattern 11), connection point 61A may be between connection point 62 and connection point 60A, connection point 61B may be between connection point 60A and connection point 60B, and connection point 61C may be between connection point 60B and connection point 60C.

[0066] (Fourth Embodiment) A fourth embodiment will now be described. The third embodiment differs from the first embodiment mainly in the arrangement of gate terminals, transistors, and wires. Figure 7 is a plan view showing a semiconductor device according to the fourth embodiment. Figure 8 is a schematic diagram showing the signal path length of the control signal in the semiconductor device according to the fourth embodiment.

[0067] As shown in Figures 7 and 8, in the semiconductor device 4 according to the fourth embodiment, in the longitudinal direction (X-axis direction) of the gate pattern 11, connection point 62 is located between connection point 61B and connection point 61C. Excluding manufacturing tolerances, the distances between transistors 20A and 20D and the gate pattern 11 are equal to each other, and the distances between transistors 20B and 20C and the gate pattern 11 are equal to each other. Also, excluding manufacturing tolerances, in a plan view from a direction perpendicular to the top surface 10A, distances D1A and D1D are equal to each other, and distances D1B and D1C are equal to each other. Transistor 20B is further from the gate pattern 11 than transistor 20A, and transistor 20C is further from the gate pattern 11 than transistor 20D. In a plan view from a direction perpendicular to the top surface 10A, distance D1B is greater than distance D1A, and distance D1C is greater than distance D1D.

[0068] Furthermore, the length L2B of wire 31B is longer than the length L2A of wire 31A, the length L2B of wire 31B is equal to the length L2C of wire 31C, and the length L2C of wire 31C is longer than the length L2D of wire 31D. Therefore, resistance R1B is higher than resistance R1A, resistance R1B and resistance R1C are equal, and resistance R1C is higher than resistance R1D.

[0069] Furthermore, on the gate pattern 11, length L1A is longer than length L1B, length L1B and length L1C are equal, and length L1D is longer than length L1C.

[0070] Therefore, the resistance R2B between gate terminal 51 and connection point 61B is lower than the resistance R2A between gate terminal 51 and connection point 61A. Also, the resistance R2B between gate terminal 51 and connection point 61B is equal to the resistance R2C between gate terminal 51 and connection point 61C. Furthermore, the resistance R2C between gate terminal 51 and connection point 61C is lower than the resistance R2D between gate terminal 51 and connection point 61D.

[0071] The other configurations of the fourth embodiment are the same as those of the first embodiment.

[0072] The fourth embodiment also suppresses timing differences in operation between transistors 20A, 20B, 20C, and 20D caused by differences in gate wiring resistance. For example, it can suppress timing differences in turn-on and turn-off between transistors 20A, 20B, 20C, and 20D. By suppressing timing differences, differences in current flowing through transistors 20A, 20B, 20C, and 20D can be suppressed. Furthermore, oscillation of the circuit including transistors 20A, 20B, 20C, and 20D can also be suppressed.

[0073] Transistors 20A, 20B, 20C, and 20D may contain at least one selected from the group consisting of silicon carbide, silicon, gallium nitride, and gallium oxide. In this case, the semiconductor device 1 is easy to use in power modules and the like. In particular, when high-voltage materials are used, the semiconductor device 1 is suitable for power modules. Transistors 20A, 20B, 20C, and 20D may contain the same material as each other, or be composed of the same material as each other. Also, some of transistors 20A, 20B, 20C, and 20D may contain a different material than the other parts, or be composed of a different material than the other parts. For example, two of transistors 20A, 20B, 20C, and 20D may contain silicon carbide, and the other two may contain gallium nitride.

[0074] The semiconductor device 1 is easy to assemble because it includes an insulating substrate 10, wires 31A, 31B, 31C, and 31D, and wire 41.

[0075] The number of transistors included in a semiconductor device is not particularly limited, as long as it is two or more. For example, when focusing on transistors 20A and 20B, transistor 20B may be considered an example of a second transistor. For another example, when focusing on transistors 20B and 20C, transistor 20B may be considered an example of a first transistor and transistor 20C may be considered an example of a second transistor. For yet another example, when focusing on transistors 20A, 20B, and 20C, transistor 20C may be considered an example of a second transistor. For yet another example, when focusing on transistors 20B, 20C, and 20D, transistor 20B may be considered an example of a first transistor.

[0076] In this disclosure, an insulated gate bipolar transistor (IGBT) may be used as the transistor.

[0077] Although embodiments have been described in detail above, this disclosure is not limited to any particular embodiment, and various modifications and changes are possible within the scope of the claims. [Explanation of symbols]

[0078] 1, 2, 3, 4: Semiconductor devices 10: Insulating substrate 10A: Top surface (first surface) 11: Gate Pattern (Gate Wiring) 12: Source Patterns 13: Drain Pattern 20A: Transistor (First Transistor) 20B: Transistor (3rd transistor) 20C: Transistor (3rd transistor) 20D: Transistor (2nd transistor) 21A: Gate pad (1st gate pad) 21B: Gate pad (3rd gate pad) 21C: Gate pad (3rd gate pad) 21D: Gate pad (2nd gate pad) 22A, 22B, 22C, 22D: Source pad 23A, 23B, 23C, 23D: Passivation membrane 31A: Wire (First Wire) 31B: Wire (3rd wire) 31C: Wire (3rd wire) 31D: Wire (Second Wire) 32A, 32B, 32C, 32D: Wire 41: Wire (4th wire) 42, 43: Wire 51: Gate terminal 52: Source terminal 53: Drain terminal 60A, 60B, 60C, 60D: Connection point 61A: Connection point (First connection point) 61B: Connection point (Third connection point) 61C: Connection point (Third connection point) 61D: Connecting point (2nd connecting point) 62:Connection point D1A: Distance (First Distance) D1B, D1C: Distance D1D: Distance (Second Distance) D2A: Distance (3rd distance) D2B, D2C: Distance D2D: Distance (4th Distance) L0, L1A, L1B, L1C, L1D, L2A, L2B, L2C, L2D: Distance P1A: Point (Point 1) P1B, P1C: Points P1D: Point (2nd point) θA: Angle (first angle) θB, θC: Angles θD: Angle (2nd one)

Claims

1. Gate terminal and A gate wiring electrically connected to the gate terminal, A first transistor having a first gate pad electrically connected to the gate wiring, The gate wiring includes a second transistor having a second gate pad electrically connected in parallel with the first transistor, A first wire connecting the gate wiring and the first gate pad, A second wire connecting the gate wiring and the second gate pad, It has, The aforementioned gate wiring is The first connection point to which the first wire is connected, The second connection point to which the second wire is connected, It has, The length of the first signal path between the first connection point and the gate terminal is shorter than the length of the second signal path between the second connection point and the gate terminal. The first length of the first wire between the first connection point and the first gate pad is longer than the second length of the second wire between the second connection point and the second gate pad. Semiconductor equipment.

2. The gate wiring includes a third transistor having a third gate pad electrically connected in parallel with the first transistor, A third wire connecting the gate wiring and the third gate pad, It has, The gate wiring has a third connection point to which the third wire is connected. The length of the third signal path between the third connection point and the gate terminal is longer than the length of the first signal path and shorter than the length of the second signal path. The third length of the third wire between the third connection point and the third gate pad is shorter than the first length and longer than the second length. The semiconductor device according to claim 1.

3. Multiple transistors having gate pads electrically connected to the gate wiring, Multiple wires connecting the gate wiring to each of the multiple gate pads, It has, The gate wiring has multiple connection points to which each of the multiple wires is connected. The first signal path length is the shortest of the multiple signal path lengths between the multiple connection points and the gate terminal. The second signal path length is the longest of the plurality of signal path lengths between the plurality of connection points and the gate terminal. The first length is the longest of the lengths of the plurality of wires between each of the plurality of connection points and each of the plurality of gate pads, The second length is the shortest of the lengths of the plurality of wires between each of the plurality of connection points and each of the plurality of gate pads. The semiconductor device according to claim 1 or claim 2.

4. Having an insulating substrate having a first main surface, The gate wiring is provided on the first main surface, In the direction along the gate wiring, the first transistor is positioned between the gate terminal and the second transistor. In a plan view from a direction perpendicular to the first main surface, the first distance between the first gate pad and the gate wiring is longer than the second distance between the second gate pad and the gate wiring. The semiconductor device according to claim 1 or claim 2.

5. Having an insulating substrate having a first main surface, The gate wiring is provided on the first main surface, The third distance between the first point of the first wire furthest from the first main surface and the first main surface is greater than the fourth distance between the second point of the second wire furthest from the first main surface and the first main surface. The semiconductor device according to claim 1 or claim 2.

6. Having an insulating substrate having a first main surface, The gate wiring is provided on the first main surface, In a plan view from a direction perpendicular to the first main surface, the first angle formed by the short side of the gate wiring and the first wire is greater than the second angle formed by the short side of the gate wiring and the second wire. The semiconductor device according to claim 1 or claim 2.

7. The first transistor and the second transistor each include at least one selected from the group consisting of silicon carbide, silicon, gallium nitride, and gallium oxide. The semiconductor device according to claim 1 or claim 2.

8. A fourth wire is provided to connect the gate terminal and the gate wiring. The semiconductor device according to claim 1 or claim 2.

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