Semiconductor die and method for manufacturing a semiconductor die

Abstract

The present invention provides a semiconductor die having metallization on a semiconductor body. [Solution] The semiconductor die 100 comprises a semiconductor body 10, an insulating layer 20, and a metallization 30. A conductor line 31 is formed within the metallization 30 and located outside the active area 101 of the semiconductor die. A first contact opening 21 is formed within the insulating layer below the conductor line. The conductor line is electrically connected to the semiconductor body in a first contact area 41 within the first contact opening. The first contact opening is divided into a plurality of first contact opening sections 21.1 to 21.3 along the longitudinal extension 110 of the conductor line. The first contact area is provided with first interruption sections 51, 51.1, and 51.2 between adjacent first contact opening sections.

Description

Technical Field

[0005] ,

[0001] The present disclosure relates to a semiconductor die including a semiconductor body.

Background Art

[0002] In embodiments of this application, the semiconductor body is made of silicon carbide (SiC) having a relatively wide bandgap (compared to, for example, silicon). This can be of interest, for example, as a power semiconductor device in high voltage and / or high current applications. In the semiconductor body, a device structure with one or more load terminals (for example, a transistor structure having a source terminal and a drain terminal) can be formed. For wiring and contact of the device structure, metallization can be formed on the semiconductor body.

Summary of the Invention

[0003] Examples of this application are directed to advantageous semiconductor dies.

[0004] The semiconductor die can include a semiconductor body, an insulating layer on a first side of the semiconductor body, and a metallization on the insulating layer. Conductor lines can be formed and arranged outside the active area of the die within the metallization. The conductor lines are connected to the semiconductor body (for example, to an entity formed within the semiconductor body or to the semiconductor body itself) through a first contact opening formed in the underlying insulating layer. Specifically, electrical contact can be formed through a first contact area within the first contact opening. In one embodiment, the first contact opening is divided into a plurality of first contact opening sections along the longitudinal extension of the conductor line, and the insulating layer is not interrupted, for example, between adjacent first contact opening sections. Conversely, the first contact area can be interrupted respectively between adjacent first contact opening sections (that is, provided with each of the first interruptions).

[0005] In other words, the first contact area beneath the conductor line is accompanied by a first interruption (for example, in a dashed line pattern as detailed below) rather than extending continuously. The interruption(s) may be advantageous, for example, in terms of manufacturing (e.g., with respect to structuring the metallization). The metallization or sublayer of the metallization may be structured by a lift-off process (i.e., deposited on a structured mask, followed by mask removal). This lift-off process may be improved if a small undercut is formed in the insulating layer beneath the mask (e.g., a slight over-etching at the lateral edge of the insulating layer, without which the lateral edge of the insulating layer would be essentially coplanar with each of the lateral edges of the mask), as shown in Figures 4a-f. By segmenting the contact opening, the formation of undercuts may be improved, for example, compared to a continuous (uninterrupted) contact opening. Such segmentation or interruption may allow for improved solvent erosion for lifting off the mask.

[0006] Further embodiments and features are provided in the claims and throughout this disclosure. In this document, individual features will be disclosed independently of the specific claim category and / or embodiment. This disclosure relates not only to the aspects of apparatus and devices but also to the methods and aspects of use. For example, where a die manufactured in a particular manner is described, this is also a disclosure of the corresponding manufacturing process, and vice versa. Broadly speaking, the approach of this application is to divide an opening in an insulating layer into multiple opening sections (e.g., contact openings under a conductor line or pad).

[0007] As described above, the conductor lines or pads are located outside the active area (e.g., the edge termination area between the active area and the lateral edge of the die). In the active area, a device structure can be formed within the semiconductor body. The semiconductor body may be made of silicon carbide (SiC), but this can be substituted with, for example, silicon (Si), gallium nitride (GaN), or aluminum oxide (Al2O3). The device structure may include, for example, a first load terminal located on the first side of the semiconductor body. In addition, the device structure may include a second load terminal, for example, on the second side opposite the semiconductor body in the perpendicular direction. The device structure may be an FET having a source terminal / region and a drain terminal / region within the semiconductor body (e.g., having the source region on the first side of the semiconductor body and the drain region on the second side of the semiconductor body).

[0008] The device may include a body region in addition to a source region and a drain region, to which a gate electrode is capacitively coupled. In addition, a drift region may be located between the body region and the drain region, and this drift region is configured such that, for example, it has the same doping type as the drain region but has a lower concentration than the drain region. The source region, the drain region, and (if present) the drift region may be configured with a first doping type, and the body region may be configured with a second doping type. In one embodiment, the first doping type is n-type and the second doping type is p-type.

[0009] Generally, each contact area (through which the metallization connects to the semiconductor body) may be formed by a separate contact plug beneath the metallization. However, in one embodiment, the metallization itself forms each contact area and extends downward, for example, within each contact opening, down to the semiconductor body. More specifically, each contact area may be formed between the lowest layer of the metallization (e.g., the sputtered deposition layer) and the semiconductor body (i.e., where the lowest metallization layer is in contact with the semiconductor body). To improve electrical contact, a highly doped contact region may be formed within the semiconductor body beneath the conductor line. Generally, the highly doped contact region within the semiconductor body may also have interruptions (e.g., coinciding with interruptions in the contact area). However, in one embodiment, the highly doped contact region extends uninterrupted (e.g., as a continuous line) beneath the conductor line.

[0010] As detailed below, the conductor lines may, for example, form a runner extending alongside or along the active area, or be part of such a runner. The conductor lines may extend along one or more of the lateral edges of the die and may, for example, have an L-shape or a U-shape, or form a closed line around the active area. Regardless of the above details, the conductor lines may also, for example, be the gate runner or source runner of the device.

[0011] In one embodiment, each of the first contact opening sections beneath the conductor line has a length of at least 0.5 μm and / or a maximum of 50 μm. Further lower limits may be, for example, at least 0.7 μm, 0.8 μm, 0.9 μm, 1 μm, 1.1 μm, or 1.2 μm, although larger lower limits (e.g., at least 2 μm) are also conceivable. Further upper limits may be 20 μm, 10 μm, or 5 μm. This length, regardless of the specific value, may be measured along the longitudinal extension of the conductor line, for example, along the centerline of the first contact opening as viewed in a vertical top view. In detail, the length may be measured at the bottom of the corresponding contact opening section (where the contact area is formed).

[0012] In one embodiment, each interruption in the contact area (or conversely, each uninterrupted portion of the insulating layer) has a length of at least 0.5 μm and / or a maximum of 50 μm. Further lower limits may be, for example, at least 0.7 μm, 0.8 μm, 0.9 μm, 1 μm, 1.1 μm, or 1.2 μm, although larger lower limits (e.g., at least 2 μm) are also possible. Further upper limits may be, for example, a maximum of 20 μm, 10 μm, or 5 μm. As above, this length may be measured along the longitudinal extension of the conductor line, for example, along the centerline of the first contact opening as viewed in a vertical top view.

[0013] In one embodiment, the first contact opening section forms a dashed pattern along at least a portion of the conductor line. Here, the “dashed pattern” may be characterized by the number of contact opening sections provided per unit length (e.g., at least five contact opening sections along a conductor line length of 100 μm). Here, the portion of the conductor line with the dashed pattern may extend further (e.g., it may have a length of several hundred micrometers or may extend in the range of millimeters).

[0014] Furthermore, the lower limit of the number of first contact opening sections per 100 μm unit length could be, for example, at least 10, 15, or 20 first contact opening sections. The feasible upper limit could be, for example, up to 100, 80, 60, or 50 first contact opening sections per 100 μm unit length. This “dashed line pattern” may be irregular, regardless of the specific number (i.e., contact opening sections of different lengths and / or distances between them may be provided). Alternatively, the dashed line pattern may be regular, with each contact opening section having the same length and being arranged with the same distance between them.

[0015] In one embodiment, the conductor line extends along the lateral edge of the die, and the dashed pattern is provided along at least 25% of the total length of the conductor line along the corresponding lateral edge. The conductor line may extend parallel to the lateral edge when viewed in a vertical top view, and the total length may be measured over the length over which the conductor line extends parallel (for example, ignoring curved portions at corners). In other words, the total length may be measured over the length over which the conductor line extends as a straight line. Regardless of the above details, in this embodiment, the dashed pattern may extend over a portion (≥25%) of the total length (100%) or over the total length.

[0016] In one embodiment, the conductor line has a curved shape at the corner of the semiconductor die (i.e., the transition between two adjacent lateral edges of the die). The dashed line pattern may be provided along at least one segment of the curved shape (for example, across a portion of the curved shape or across the entire curved shape). This curved shape at the corner may increase the area between the conductor line and the lateral edge of the die, and for example, the corresponding mask area in the lift-off process may also increase. This may make the aforementioned over-etching (i.e., solvent erosion that may occur in the lift-off process) advantageous.

[0017] In one embodiment, the conductor line is or belongs to a runner, and a second contact opening is formed below the runner. The second contact opening is positioned laterally offset from the first contact opening in the transverse direction (i.e., in a direction perpendicular to the longitudinal extension of the runner). The contact openings below the runner may be arranged parallel to each other, for example, and the centerlines of each contact opening are at a certain distance from each other when viewed, for example, in a vertical top view. As described above, the runner may be, for example, a gate runner or a source runner, i.e., it may be connected to a gate terminal (e.g., a gate electrode) or to a source region of a device structure formed within an active area.

[0018] Generally, the division of a (first) contact opening into multiple (first) contact opening sections is done with respect to the longitudinal direction of the runner. Conversely, the division of contact openings (such as the first and second) with different reference numbers is done with respect to the transverse direction, which is perpendicular to the longitudinal direction.

[0019] In other words, a contact region beneath the runner, having a certain width transversely, is divided into multiple contact openings, which are arranged adjacent to each other (and separated from each other by corresponding portions of the insulating layer). As described above with respect to the division of the first contact opening along the longitudinal direction, division in the transverse direction can also improve the formation of undercuts (and the lift-off process) (compared, for example, to the case where the contact opening extends uninterrupted across the entire width of the runner). Conductor lines of the runner, even if divided into multiple contact openings, can be electrically connected to the same entity within the semiconductor body, such as a doped region (source region) or a polysilicon structure (gate electrode).

[0020] In one embodiment, the first contact opening, which is provided with a segmented first contact area (e.g., a dashed pattern), is the innermost or outermost contact opening in the lateral direction below the runner. The innermost contact opening in the lateral direction may be located closer to the active area than the other contact openings below the runner, while the outermost contact opening may be located closer to the lateral edge than the other contact openings on the runner. Areas without metallization may be located on the inner and / or outer sides of the runner in the lateral direction, so that the mask used in the lift-off process may have a relatively large area in these corresponding areas. (Also, as mentioned above, segmentation is advantageous).

[0021] In one embodiment, the second contact opening forms a second contact area (which is also segmented) with respect to the semiconductor body. In other words, the second contact opening below the conductor line is divided into a plurality of second contact opening sections along the longitudinal extension of the conductor line, similar to how the first contact opening is described above. All embodiments described above for the first contact opening and first contact area are similarly disclosed for the second contact opening / second contact area. For example, the second contact opening may also form a dashed pattern. The first and second contact openings may be, for example, the innermost and outermost contact openings of the runner in the transverse direction. In general, further contact openings that may be located transversely between the first and second contact openings in the transverse direction may also be provided with a dashed pattern. For example, all contact openings located below the conductor line may be provided with a dashed pattern along the longitudinal extension.

[0022] In one embodiment, at least one additional contact opening is formed beneath the runner, and this additional contact opening is positioned transversely between the first and second contact openings. This at least one additional contact opening connects the conductor line to the semiconductor body via a corresponding contact area below. Here, the at least one additional contact area beneath the runner may be continuous along the length of the runner (i.e., not interrupted / divided). In other words, the at least one additional contact area / contact opening beneath the runner may extend as a continuous line when viewed in a vertical top view. One or more additional contact openings having corresponding continuous contact areas along the length can be combined with the first and / or second contact openings that form a divided contact area along the length, which may enable optimization of both lift-off and electrical contact characteristics, for example.

[0023] In one embodiment, the width of each contact opening under the runner (e.g., a first, second, or additional contact opening) and / or the distance between adjacent contact openings is at least 0.5 μm and / or at most 3 μm. Such width and distance are measured transversely.

[0024] As described above, a device (e.g., a transistor device) may be formed in the active area. More specifically, such a device may include a plurality of device cells, which are arranged in a row within the active area with a certain cell pitch. The device cells may, for example, be electrically connected in parallel and / or arranged translationally symmetrically with respect to each other (each offset by a certain cell pitch).

[0025] Regardless of these details, in one embodiment, the distance between adjacent contact openings under the runner, measured in the transverse direction, may not differ by more than ±80% from the cell pitch within the active area. In other words, the distance between adjacent contact openings may be at most 80% lower or higher compared to the cell pitch. Further upper limits may be, for example, 60%, 50%, 40%, 30%, or 20%, and this distance may also be equal to the cell pitch. By adapting the dimensions of the runner to the dimensions within the active area, it may be possible to reduce differences in, for example, lift-off behavior.

[0026] In one embodiment, a plurality of device contact openings are formed within the insulating layer of the active area, and each device contact opening belongs to a corresponding device cell. Each device contact opening may form an electrical contact to an element (e.g., source region and / or body region) of the corresponding device cell. The device contact openings within the active area may have a length extension in a first transverse direction, and the device cells may have translational symmetry in a second transverse direction perpendicular to the first transverse direction.

[0027] In one embodiment, the width of each contact opening of the runner does not differ by more than ±80% from the width of the device contact openings in the active area, and the widths of the contact openings are measured transversely / perpendicular to the length extension, respectively. In other words, the width of the contact openings in the runner may be at most 80% lower or higher compared to the width of the contact openings in the active area, and further upper limits may be 60%, 50%, 40%, 30%, or 20% (the width in the runner may also be equal to the width in the active area).

[0028] In one embodiment, a method of manufacturing a semiconductor die is i) forming an insulating layer on a first side of a semiconductor body, and ii) forming a mask on the insulating layer, the mask defining an opening that is - disposed outside the active area of the semiconductor die and - forming a mask that is divided into a plurality of opening sections along a lengthwise extending portion; iii) etching an opening defined by the mask in the insulating layer; iv) depositing at least one sub-layer of metallization in the opening etched in the mask and in the insulating layer; v) removing the mask from the insulating layer.

[0029] The mask in step ii) may be formed, for example, by depositing and structuring a photoresist layer, and this mask may be, for example, an organic layer. For example, the mask may define further openings within (and also outside) the active area. The mask that defines the opening in the insulating layer causes the opening to be formed in step iii) (i.e., where contact to the semiconductor body is to be formed).

[0030] After the opening for forming the contact is etched in the insulating layer in step iii), at least one sub-layer of metallization is deposited in step iv) (where the mask is still in place at this time). In other words, at least one sub-layer of metallization can contact the semiconductor body where the insulating layer has been opened, and can cover the mask in other parts. When the mask is removed in step v), the part of the sub-layer that contacts the semiconductor body within the opening remains, while the other parts are removed together with the mask.

[0031] At least one sublayer of the metallization may be, for example, a sputter-deposited metal layer (such as a metal layer containing nickel and / or aluminum). In subsequent processing, the sublayer may function as a seed layer (for the bath deposition of further layers or layer stacks, such as one or more copper layers). Regardless of these details, at least one sublayer deposited in step iv) may have a thickness of, for example, at least 30 nm (e.g., at least 40 nm) and / or up to 90 nm (e.g., up to 70 nm).

[0032] In one embodiment, step iii) includes an isotropic etching step and a subsequent anisotropic etching step. The anisotropic etching step can form a contact opening, and the preceding isotropic etching step can form an undercut under the mask described above. Both the anisotropic etching step and the isotropic etching step can be performed, for example, by dry etching.

[0033] In one embodiment, step v) includes adding a solvent to the mask and at least one sublayer. This solvent, which dissolves or peels off the mask, can more strongly erode the mask where undercuts are formed, because at least one sublayer may be interrupted there. This lift-off process can also be improved because segmented contact areas / contact openings can improve undercut formation.

[0034] As mentioned above, all the characteristics described regarding the die are also disclosed regarding the manufacturing method, and vice versa.

[0035] Hereafter, semiconductor dies and methods for manufacturing them will be described in more detail using exemplary embodiments. Here, individual features may be relevant in different combinations. [Brief explanation of the drawing]

[0036] [Figure 1]This shows a cross-sectional view of a conductor line on a semiconductor body. [Figure 2] This shows the contact opening below the runner at the corner of the semiconductor die in a vertical top view. [Figure 3] A vertical cross-sectional view passing through the runner is shown. [Figure 4a-c] Various steps for forming a contact opening are shown. [Figure 4d-f] This shows various steps for forming a metallization sublayer within the contact opening. [Figure 5] A flowchart summarizes some of the manufacturing steps. [Figure 6] This shows a vertical cross-section of a device that may be formed in the active area of ​​the die. [Modes for carrying out the invention]

[0037] Figure 1 is a vertical cross-sectional view of a portion of a semiconductor die 100, showing a semiconductor body 10. In the illustrated example, the semiconductor body 10 is a silicon carbide (SiC) semiconductor body 11. An insulating layer 20 is located on the first side 10.1 of the semiconductor body 10, and this insulating layer 20 may be, for example, a layer or stack of silicon oxide (e.g., including a PSG layer or BPSG layer). A metallization 30 is formed on the insulating layer 20, and the cross-section in Figure 1 shows a conductor line 31 formed within the metallization 30. This cross-sectional plane is parallel to the longitudinal direction 111 and the vertical direction 113. In other words, the cross-section in Figure 1 extends along the longitudinally extending portion 110 of the conductor line 31 (Figure 2). BB reference).

[0038] The conductor line 31 is electrically connected to the semiconductor body 10 through a first contact opening 21 etched within the insulating layer 20. Here, as shown in Figure 1, the first contact opening 21 does not extend continuously along the longitudinally extending portion 110, but is divided into a plurality of first contact opening sections 21.1 to 21.3. As a result, a first interruption 51 is provided in the first contact area 41 (through which the conductor line path 31 is electrically connected to the semiconductor body 10) (i.e., there are first interruptions 51.1 and 51.2, respectively, between adjacent first contact opening sections 21.1 to 21.3). Conversely, the first contact area 41 is divided into first contact area sections 41.1 to 41.3.

[0039] Viewed along the longitudinally extending portion 110 (i.e., in the longitudinal direction 111), each of the first contact opening sections 21.1 to 21.3 may have a length l1 of 0.5 μm to 50 μm (for example, about 3 μm in the illustrated example). Each of the interrupted portions 51.1 and 51.2 of the contact area 41 may have a length l2 of 0.5 μm to 50 μm (for example, about 3 μm in the illustrated example).

[0040] Figure 2 shows a portion of the semiconductor die 100 in a vertical top view (i.e., as viewed from the vertical direction 113). The illustrated portion is located at the corner 106 of the die 100, where two lateral edges 105 and 107 of the die 100 extend adjacent to each other. As shown in the lower left of the figure, the conductor line forms the runner 70. Below the runner 70, a second contact opening 22 and at least one additional contact opening 23 are formed, which will be described in detail later.

[0041] The first and second contact openings 21 and 22 are shown as hatched lines indicating interruptions / divisions in the longitudinal direction. The interruptions (i.e., the contact opening sections shown in Figure 1) form a dashed line pattern 60. Here, for example, 5 to 100 contact opening sections (i.e., about 8 contact opening sections in the illustrated example) may be provided over a conductor line length l3 of 100 μm ("unit length").

[0042] With respect to the total length l4 that the conductor line 31 has along the lateral edge 105, the dashed line pattern 60 may extend over at least 25% of the total length l4 (i.e., over the entire total length l4 in the illustrated example). At the corner 106, the conductor line 31 has a curved shape 120, and the dashed line pattern 60 is also provided on the curved shape 120 (this also applies to the second contact opening 22).

[0043] Figure 2 also shows the active area 101 of the die 100. In the active area 101, a semiconductor transistor device 200 is formed, which includes a plurality of device cells 201 to 203 (see Figure 5 for details). Each device contact opening 210 belongs to one of the device cells 201 to 203, and each of these device contact openings 210 has a width comparable to the width of each contact opening 21 to 23 of the runner 70 in the illustrated example.

[0044] Figure 3 shows the width w in a vertical cross-section through the runner 70 (see cross-sectional plane AA shown in Figure 2). Generally, in this disclosure, similar reference numerals indicate similar elements having similar functions. See also the descriptions of the other figures. The runner 70 is provided as a single conductor line in the transverse direction 112, with separate contact areas 41-43 formed below it, which are spaced apart from each other by a distance d (comparable to the distance between device contact openings in the active area).

[0045] As described above, the second contact area 42 is similarly divided (i.e., like the first contact area 41). At least one additional contact opening 23 (i.e., two additional contact openings 23 in the illustrated example, but other numbers are possible as shown in Figure 2) is located between the first contact opening 21 and the second contact opening 22. Here, each contact area 43 extends without interruption (as shown by continuous lines in Figure 2).

[0046] Similar to Figure 1, Figure 3 also shows a highly doped region 12 formed within the semiconductor body 10, which can improve electrical contact with the semiconductor body 10. As shown in Figure 3, the highly doped region 12 extends uninterrupted between the contact openings 21-23. This also applies to the portion of the highly doped region 12 extending in the longitudinal direction 111 below the first and second contact openings 21 and 22 (see the example in Figure 1).

[0047] Figures 4a-4f show some of the manufacturing steps for the formation of contact openings and subsequent metallization or deposition of a metallization sublayer. In Figure 4a, a highly doped region 12 is formed within the semiconductor body 10, and an insulating layer 20 is deposited on the semiconductor body 10. Furthermore, a mask 250 is formed on the insulating layer 20. The mask 250 is structured (i.e., defining openings 251 for the subsequent etching step).

[0048] Figure 4b shows the isotropic etching step 302.1, in which an undercut 25 is etched into the insulating layer 20. In the subsequent anisotropic etching step 302.2, the entire contact opening section 21 is etched through the insulating layer 20, as shown in Figure 4c.

[0049] Figure 4d shows the subsequent deposition 303 of sublayer 230, which is the bottom layer of the metallization. Within the opening 21, sublayer 230 forms a contact area 41 with respect to the semiconductor body 10. Outside the opening on the side of the opening, sublayer 230 is deposited on the mask 250 and removed along with the mask 250 in a lift-off process. As shown in Figure 4d, the undercut 25 locally interrupts the sublayer 230, allowing for improved solvent erosion of the mask 250 against the resist.

[0050] Figure 4e shows the state after the mask has been removed, with the sublayer 230 remaining at the bottom of the contact opening 21. The entire metallization 30 is formed in subsequent steps (see the example in Figure 4f).

[0051] Figure 5 is a flow chart summarizing some of the manufacturing steps. After forming the insulating layer 300, a mask 301 may be formed on the insulating layer. Openings may then be etched into the insulating layer 302 (i.e., etching is performed in the isotropic etching step 302.1 and the subsequent anisotropic etching step 302.2, as described above). Sublayers may then be deposited 303 before the mask is removed 304, for example by adding a solvent 305.

[0052] Figure 6 shows a semiconductor transistor device 200 having a device cell 201. A source region 221 is located on a first side 10.1 of the semiconductor body 10, and a drain region 222 is formed on a second side 10.2 opposite the semiconductor body 10 in the vertical direction. In addition, the device 200 includes a body region 223, and a gate region 225 is located in a gate trench 226 adjacent to the body region 223. The gate region 225 includes a gate electrode 225.1 and a gate insulating film 225.2, the gate electrode 225.1 is capacitively coupled to the body region 223 via the gate insulating film 225.2. By applying a voltage to the gate electrode 225.1, the flow of vertical current through the device 200 can be controlled.

[0053] The illustrated device 200 further comprises a drift region 224, which is configured with the same doping type as the drain region 222, but has a lower doping concentration than the drain region 222. In the illustrated example, the source region 221, drain region 222, and drift region 224 are n-type doped, and the body region 223 is p-type doped.

Claims

1. A semiconductor die (100), Semiconductor body (10) and The insulating layer (20) on the first side (10.1) of the semiconductor body (10), Metallization (30) on the insulating layer (20), Equipped with, The conductor line (31) is formed within the metallization (30) and is located outside the active area (101) of the semiconductor die (100). A first contact opening (21) is formed in the insulating layer (20) below the conductor line (31), and the conductor line (31) is electrically connected to the semiconductor body (10) in a first contact area (41) within the contact opening (21). The first contact opening (21) is divided into a plurality of first contact opening sections (21.1 to 21.3) along the longitudinally extending portion (110) of the conductor line (31), The first contact area (41) is provided with first interruption sections (51, 51.1, 51.2) between adjacent first contact opening sections (21.1 to 21.3). Semiconductor die (100).

2. Each of the first contact opening sections (21.1 to 21.3) has a length of at least 0.5 μm and / or up to 50 μm (l) measured along the longitudinal extension (110) of the conductor line (31). １ A semiconductor die (100) according to claim 1, having ).

3. Each of the first interrupted portions (51, 51.1, 51.2) of the first contact area (41) has a length of at least 0.5 μm and / or up to 50 μm (l) measured along the longitudinally extending portion (110) of the conductor line (31). ２ A semiconductor die (100) according to claim 1 or 2, having ).

4. The first contact opening sections (21.1 to 21.3) form a dashed line pattern (60) along at least a portion of the conductor line (31), and in the dashed line pattern (60), there are conductor line lengths of 100 μm (l) such that each of the first interrupted portions (51, 51.1, 51.2) of the contact area (41) is located between adjacent first contact opening sections (21.1 to 21.3). ３ The semiconductor die (100) according to claim 1, wherein at least five first contact opening sections (21.1 to 21.3) are provided along the )

5. The conductor line (31) extends along the lateral edge (105) of the semiconductor die (100), and the total length (l) of the conductor line (31) along the lateral edge (105) is ４ Regarding the dashed line pattern (60), the total length (l ４ The semiconductor die (100) according to claim 4, provided along at least 25% of the )

6. The semiconductor die (100) according to claim 4 or 5, wherein the conductor line (31) has a curved shape (120) at the corner (106) of the semiconductor die (100), and the dashed line pattern (60) is provided along at least one segment of the curved shape (120).

7. The semiconductor die (100) according to claim 1, wherein the conductor line (31) is a runner (70) extending along the active area (101) or belongs to the runner (70), and a second contact opening (22) is formed in the insulating layer (20) below the runner (70), and the second contact opening (22) is laterally offset from the first contact opening (21) in a transverse direction (112) perpendicular to the longitudinally extending portion (110) of the runner (70).

8. The semiconductor die (100) according to claim 7, wherein the first contact opening (21) is the innermost or outermost contact opening of the runner (70) in the lateral direction.

9. The semiconductor die (100) according to claim 7 or 8, wherein the runner (70) is electrically connected to the semiconductor body (10) via a second contact area (42) in the second contact opening (22), the second contact opening (22) is divided into a plurality of second contact opening sections along the longitudinally extending portion (110) of the conductor line (31), and the second contact area (42) is provided with a second interruption between adjacent second contact opening sections.

10. A semiconductor die (100) according to claim 8, wherein a third contact opening (23) is formed in the insulating layer (20) below the runner, the third contact opening (23) is positioned laterally between the first contact opening (21) and the second contact opening (22), the runner (70) is electrically connected to the semiconductor body (10) via a third contact area (43) in the third contact opening (23), and the third contact area (43) is continuous along the longitudinally extending portion (110) of the runner (70).

11. The semiconductor die (100) according to claim 7 or 8, wherein the width (w) of each contact opening (21, 22, 23) and / or the distance (d) between adjacent contact openings (21, 22, 23) below the runner (70), as measured in the transverse direction (112), is at least 0.5 μm and / or at most 3 μm.

12. A semiconductor die (100) according to claim 7 or 8, wherein a plurality of device cells (201-203) are arranged in the active area (101) with a certain cell pitch, and the distance (d) between adjacent contact openings (21, 22, 23) below the runner (70) does not differ by more than ±80% from the cell pitch in the active area (101).

13. The semiconductor die (100) according to claim 12, wherein in the active area (101), a plurality of device contact openings (210) are formed within the insulating layer (20), each device contact opening (210) belongs to a corresponding device cell (201-203), and the width (w) of each contact opening (21, 22, 23) below the runner (70) does not differ from the device contact opening width in the active area (101) by more than ±80%.

14. A method for manufacturing a semiconductor die (100), i) The step (300) of forming an insulating layer (20) on the first side (10.1) of the semiconductor body (10), ii) A step (301) of forming a mask (200) defining an opening (201) on the insulating layer (20), wherein the opening (201) is It is located outside the active area (101) of the semiconductor die, and The longitudinally extending portion (110) is divided into multiple opening sections. Step (301) of forming a mask (200), iii) The step (302) of etching the opening (201) defined by the mask (200) into the insulating layer (20), iv) A step (303) of depositing at least one sublayer (230) of metallization (30) on the mask and in the etched opening (201) within the insulating layer (20), v) Step (304) of removing the mask (230) from the insulating layer (20), Methods that include...

15. Step III) Isotropic etching step (302.1), The subsequent anisotropic etching step (302.2), The method according to claim 14, including the method described in claim 14.

16. Step v) is, The method according to claim 14 or 15, comprising adding a solvent (305) to the mask (200) and the at least one sublayer (230).

17. A method according to claim 14 or 15 for manufacturing the semiconductor die (100) described in claim 1, The method according to claim 14 or 15, wherein the opening (201) etched in step iii) is a first contact opening (21), and the at least one sublayer (230) deposited in step iv) forms a first contact area (41) with respect to the semiconductor body (10).

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