Gradient doping epitaxy in superjunctions for improved voltage resistance
By employing epitaxial growth with tapered sidewalls and dopant concentration gradients, the method addresses void formation and charge imbalance in super-junction MOSFETs, improving breakdown voltage and reducing interference.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- APPLIED MATERIALS INC
- Filing Date
- 2025-12-26
- Publication Date
- 2026-04-21
AI Technical Summary
As the size of vertical pn junctions in super-junction MOSFETs decreases, it becomes difficult to fill trenches without voids while maintaining charge balance between p- and n-regions, leading to potential electromagnetic interference and dielectric strength degradation.
A method involving epitaxial growth processes to form n-type and p-type doped layers with tapered sidewalls and controlled dopant concentration gradients to reduce void formation and improve charge balance, using a multi-chamber processing tool for efficient substrate processing.
The method effectively reduces void formation and improves charge balance, enhancing breakdown voltage and reducing electromagnetic interference in super-junction MOSFETs.
Smart Images
Figure 2026067876000001_ABST
Abstract
Description
Technical Field
[0001]
[0001] Embodiments of the present disclosure generally relate to substrate processing and equipment for processing substrates.
Background Art
[0002]
[0002] A metal-oxide-semiconductor field-effect transistor (MOSFET) is a field-effect transistor (FET) having an insulating gate, in which voltage determines the conductivity of the device. MOSFETs are generally used for signal switching or amplification. The ability to vary conductivity depending on the amount of voltage applied can be used for amplification or switching of electronic signals. A MOSFET having a planar structure has a drawback that as the rated voltage increases, the drift layer becomes thicker and the resistance (on-resistance) between the drain and source of the MOSFET during operation increases. A super-junction MOSFET has a non-planar structure in which a plurality of vertical pn junctions are arranged, thereby reducing the on-resistance while maintaining a high voltage, and reducing the amount of charge that needs to be injected into the gate electrode to turn on the MOSFET. However, as the size of the plurality of vertical pn junctions decreases, it becomes difficult to fill the trenches of the vertical pn junctions without voids while maintaining the charge balance between the p-region and n-region of pn.
[0003]
[0003] Based on the above, the inventors present in this document an improved semiconductor device and a method for forming an improved semiconductor device.
Summary of the Invention
[0004]
[0004] Embodiments of substrate processing are presented in this document. In some embodiments, a method for processing a substrate involves: first epitaxial growth process to deposit n-type doped silicon material onto the substrate to form an n-type doped layer, adjusting the ratio of dopant precursor to silicon precursor so that the dopant concentration of the n-type doped layer increases from the bottom to the top of the n-type doped layer; etching the n-type doped layer to form a plurality of trenches having tapered sidewalls and a plurality of n-type doped pillars between the plurality of trenches; and second epitaxial growth process to fill the plurality of trenches with p-type doped material to form a plurality of p-type doped pillars. Includes.
[0005]
[0005] In some embodiments, a non-transient computer-readable medium, when executed by one or more processors, is performed by a first epitaxial growth process which involves depositing n-type doped silicon material onto a substrate to form an n-type doped layer, adjusting the ratio of dopant precursor to silicon precursor such that the dopant concentration of the n-type doped layer increases from the bottom to the top of the n-type doped layer, etching the n-type doped layer to form a plurality of trenches having tapered sidewalls and a plurality of n-type doped pillars between the plurality of trenches, and a second epitaxial growth process which involves filling the plurality of trenches with p-type doped material to form a plurality of p-type doped pillars. A method for processing a substrate is implemented, which includes the following:
[0006]
[0006] In some embodiments, the semiconductor device includes an N-type doped layer, the n-type doped layer having a dopant concentration that increases from the bottom of the n-type doped layer to the top of the n-type doped layer, and includes a plurality of trenches having sidewalls tapered inward, with a plurality of n-type doped pillars defined between the plurality of trenches, and the semiconductor device further includes a plurality of p-type doped pillars arranged corresponding to each of the plurality of trenches.
[0007]
[0007] Other embodiments and further embodiments of the present disclosure will be described later.
[0008]
[0008] The embodiments of the present disclosure, which are briefly summarized above and described in detail below, can be understood by referring to the exemplary embodiments of the present disclosure shown in the accompanying drawings. However, the accompanying drawings show only typical embodiments of the present disclosure and should not be considered limiting in scope, for the present disclosure may also permit other equally valid embodiments. [Brief explanation of the drawing]
[0009] [Figure 1] A flowchart of a method for processing a substrate according to at least a portion of the embodiments of this disclosure is shown. [Figure 2A] This document shows a semiconductor device after depositing n-type doped silicon material, according to at least a portion of the embodiments of this disclosure. [Figure 2B] Figure 2A shows a semiconductor device having a plurality of trenches, according to at least a part of the embodiments of this disclosure. [Figure 2C] Figure 2B shows a semiconductor device according to at least a portion of the embodiments of this disclosure, in which a plurality of trenches are filled with p-type doped material. [Figure 3] This shows a cross-sectional view of a portion of a semiconductor device according to at least a part of the embodiments of this disclosure. [Figure 4] This shows a cross-sectional view of a portion of a semiconductor device according to at least a part of the embodiments of this disclosure. [Figure 5] A schematic diagram of an epitaxy chamber according to at least a part of the embodiments of this disclosure is shown. [Modes for carrying out the invention]
[0010]
[0016] For ease of understanding, the same reference numerals were used to indicate identical elements common to multiple figures where possible. The figures are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be usefully incorporated into other embodiments without further description.
[0011]
[0017] This book presents embodiments for processing a substrate to form a field-effect transistor (FET). A superjunction metal-oxide-semiconductor field-effect transistor (MOSFET) is a type of "FET" device having a non-planar structure in which multiple vertical pn junctions are arranged. For example, an n-type doped layer may contain multiple features (such as trenches) to accommodate p-type doped material and form alternating pn junctions. For example, an n-type doped layer may contain multiple features (such as trenches) to accommodate p-type doped material and form a pn junction (e.g., a p-channel MOSFET). As mentioned above, an n-type doped layer has multiple features for accommodating p-type doped material, but alternatively, a p-type doped layer may also contain multiple features to accommodate n-type doped material and form a pn junction (e.g., an n-channel MOSFET). However, as the size of the multiple vertical pn junctions decreases, it becomes difficult to fill the multiple trenches of the vertical pn junctions without voids.
[0012]
[0018] The inventors have confirmed that tapered sidewalls in multiple trenches advantageously reduce or prevent void formation within these trenches. However, tapered sidewalls can cause charge imbalance between n-type doped and p-type doped regions, potentially leading to electromagnetic interference and degradation of dielectric strength. To address this, the inventors have confirmed that adjusting the dopant concentration in at least one of the n-type doped layer (or region) or p-type doped layer (or region) of the device advantageously improves the charge balance between the p- and n-regions of the pn junction. The method presented here can be implemented in a multi-chamber processing tool or in multiple standalone chambers.
[0013]
[0019] Figure 1 shows a flowchart of a method 100 for processing a substrate according to at least a portion of embodiments of the present disclosure. Method 100 includes, in 102, depositing n-type doped silicon material onto a substrate (e.g., substrate 210) by a first epitaxial growth process to form an n-type doped layer (e.g., n-type doped layer 220), while adjusting the ratio of dopant precursor to silicon precursor such that the dopant concentration of the n-type doped layer increases from the bottom (e.g., bottom 212) to the top (e.g., top 214) of the n-type doped layer. For example, Figure 2A shows a semiconductor device 200 including the substrate 210 after the n-type doped silicon material has been deposited, according to at least a portion of embodiments of the present disclosure. In some embodiments, the thickness of the n-type doped layer 220 is about 30 to about 50 micrometers. In some embodiments, the n-type doped layer 220 comprises a doped silicon material (such as doped silicon or doped silicon carbide). The n-type doped layer 220 may be doped with any suitable dopant (e.g., phosphorus or arsenic).
[0014]
[0020] In some embodiments, the thickness 204 of the n-type doped layer 220 is about 30 to about 50 micrometers. In some embodiments, the thickness 206 of the substrate 210 is about 0.5 to about 5 micrometers. In some embodiments, the substrate 210 contains an n-type doped material having positively charged ions (i.e., n + (a type of semiconductor substrate) On the other hand, the n-type doped layer 220 contains n-type doped material having negatively charged ions (i.e., n ー (A type of semiconductor substrate). In some embodiments, the substrate 210 includes an n-type doped material having negatively charged ions, while the n-type doped layer 220 includes an n-type doped material having positively charged ions. In some embodiments, the substrate 210 may be pre-cleaned before the first epitaxial growth process. The substrate 210 may be coupled to a drain region (such as a drain) 208 of the semiconductor device 200. For example, the drain region may be coupled to the substrate on the side opposite to the n-type doped layer.
[0015]
[0021] Method 100 includes etching an n-type doped layer in 104 to form a plurality of trenches (e.g., a plurality of trenches 228) having tapered sidewalls (e.g., sidewalls 230). In some embodiments, Method 100 includes depositing a mask (such as an oxide hard mask) on the n-type doped layer 220. The mask may be used to pattern the plurality of trenches 228 before etching the n-type doped layer 220 to form the plurality of trenches 228.
[0016]
[0022] Figure 2B shows the semiconductor device 200 of Figure 2A after the multiple trenches 228 have been etched, according to at least some embodiments of the present disclosure. The multiple trenches 228 may be of uniform size and may be arranged along a constant interval. The multiple trenches 228 generally include side walls 230 that are tapered downward and inward such that the upper part 218 of each of the multiple trenches 228 is wider than the lower part 216 of each of the multiple trenches 228. In some embodiments, the upper part 218 of each of the multiple trenches 228 is arranged along a horizontal plane substantially common with the upper part 214 of the n-type doped layer 220. The multiple trenches 228 define a multiple n-type doped pillar 250 between the multiple trenches 228. In some embodiments, the multiple trenches 228 are etched to a depth of about 30 to about 50 micrometers. In some embodiments, the trenches 228 have a bottom width of about 0.5 to about 1.5 micrometers and a top width of about 1.0 to about 2.0 micrometers. In some embodiments, the trenches 228 have an aspect ratio of 1:1 to about 1:40, or about 1:1 to about 1:20. In some embodiments, the sidewalls 230 are tapered at an angle 232 of about 1 to about 4 degrees from the normal to the top 214 of the n-type doped layer 220.
[0017]
[0023] Figure 3 shows a partial cross-sectional view of a semiconductor device 200 according to at least a portion of embodiments of the present disclosure. Figure 4 shows a partial cross-sectional view of a semiconductor device according to at least a portion of embodiments of the present disclosure. In some embodiments, as shown in Figure 3, the side walls 230 of a plurality of trenches 228 are continuously tapered from the top 218 of the plurality of trenches 228 to the bottom 216 of the plurality of trenches. In some embodiments, etching an n-type doped layer involves forming a plurality of trenches having side walls 230 including substantially vertical upper side walls 404 and tapered lower side walls 406, as shown in Figure 4.
[0018]
[0024] By epitaxially depositing on the sidewalls 230 of the plurality of trenches 228, the sidewalls 230 are tapered inwardly so that voids are less likely to be formed in the plurality of trenches 228 during the formation of the p-type doped pillars 240. The inventors have confirmed that by the sidewalls 230 being continuously tapered (as in FIG. 3) or partially tapered (as in FIG. 4), void formation during the formation of the plurality of p-type doped pillars 240 is reduced or prevented. The inventors have also confirmed that by the sidewalls 230 being partially tapered, the width of the plurality of n-type doped pillars 250 is widened, which is advantageous in improving the breakdown voltage (since the current may only pass through the n-type doped pillars 250). In some embodiments, the depth 408 of the lower sidewall 406 is from about 1 to about 10 percent of the depth 410 of the plurality of trenches 228 of the sidewall 230, which includes the substantially vertical upper sidewall 404 and the tapered lower sidewall 406.
[0019]
[0025] In some embodiments, the dopant concentration of the n-type doped layer 220 includes a first dopant concentration at the bottom 212 of the n-type doped layer 220 and a second dopant concentration at the upper portion 214 of the n-type doped layer 220. In some embodiments, the first dopant concentration at the bottom of the n-type doped layer 220 is from about 5e15 to about 8e15 per cubic centimeter. In some embodiments, the second dopant concentration at the upper portion 214 of the n-type doped layer 220 is from about 1e16 to about 2e16 per cubic centimeter.
[0020]
[0026] In some embodiments, the n-type doped layer 220 is doped based on a certain calibration method. In some embodiments, this calibration method includes tuning the n-type doped layer 220 by defining a first dopant concentration and a second dopant concentration based on certain parameters (such as the expected breakdown voltage, the shape and size of the plurality of trenches 228, etc.). The calibration method may include adjusting the dopant concentration from the first dopant concentration to the second dopant concentration in any suitable manner during the epitaxial deposition of the n-type doped layer. For example, the dopant concentration may be adjusted linearly, parabolically, piecewise, or in another manner, from the first dopant concentration to the second dopant concentration.
[0021]
[0027] Referring back to FIG. 1, method 100 includes, at 106, filling a plurality of trenches with a p-type doped material by a second epitaxial growth process. For example, FIG. 2C shows the semiconductor device 200 of FIG. 2B in which a plurality of trenches 228 are filled with a p-type doped material to form a plurality of P-type doped pillars 240, according to at least some embodiments of the present disclosure. The inventors have confirmed that the tapered sidewalls advantageously reduce void formation in the plurality of trenches 228. However, the tapered sidewalls 230 have a first width 242 between adjacent p-type doped pillars 240 near the upper portion 218 of the plurality of trenches 228, and this first width 242 is narrower than a second width 244 between adjacent p-type doped pillars 240 near the bottom 216 of the plurality of trenches 228. Such a difference in width causes a charge imbalance between the plurality of p-type doped pillars 240 and the plurality of n-type doped pillars 250. In some embodiments, after the formation of the p-type doped pillars 240, a planarization process (such as a chemical mechanical polishing (CMP) process) may be performed on the upper portion (such as the upper portion 214) of the n-type doped layer 220.
[0022]
[0028] The doping gradient of the n-type doped layer 220 advantageously improves the charge imbalance caused by the tapered sidewall 230. For example, the n-type doped layer 220 has a higher dopant concentration in the narrower first width 242 than in the wider second width 244. In some embodiments, the dopant concentration of the p-type doped pillar 240 is between the first and second dopant concentrations of the n-type doped layer 220. In some embodiments, multiple p-type doped pillars 240 have substantially uniform dopant concentrations. In some embodiments, the p-type doped material includes silicon or silicon carbide doped with any suitable p-type dopant (such as boron, aluminum, or gallium).
[0023]
[0029] Referring again to Figures 3 and 4, the semiconductor device 200 is positioned on or embedded on top of each of the multiple p-type doped pillars 240, n + The present invention may further include a doped well 308. In some embodiments, the n-type doped layer 220 includes a recess 302 on each of a plurality of p-type doped pillars 240, the recess 302 being wider than the plurality of trenches 228. The recess 302 is filled with a p-type doped body 318. In some embodiments, the well 308 is at least partially located within the p-type doped body 318.
[0024]
[0030] In some embodiments, the semiconductor device 200 includes a metal oxide layer 304. The metal oxide layer 304 is positioned on a plurality of n-doped pillars 250 of an n-doped layer 220, and partially on adjacent p-doped bodies 318, or partially on adjacent p-doped pillars 240. In some embodiments, a gate electrode 310 is positioned on the metal oxide layer. The gate electrode may be made of polycrystalline silicon, a silicon compound material, or a metal composite (e.g., tungsten nitride (WN), titanium nitride (TiN), tantalum nitride (TaN), etc.). To encapsulate the gate electrode 310, an insulating film 312 comprising at least one of the nitride layer or oxide layer may be positioned on the top and sides of the gate electrode 310. A source electrode 314 may be positioned on the insulating film 312 and the plurality of p-doped pillars 240. The source electrode 314 may be positioned on a well 308 and may be connected to the well 308. The source electrode 314 can be, for example, an aluminum-based electrode.
[0025]
[0031] During use, when a positive voltage is applied to the drain, a depletion region is formed between the multiple n-type doped pillars 250 and the multiple p-type doped pillars 240. When a gate voltage higher than the threshold voltage is applied to the semiconductor device 200, an inversion layer is formed between the metal oxide layer 304 and the n-type doped layer 220. The inversion layer facilitates the flow of current from the drain 208 to the source electrode 314. In some embodiments, the current flows from the drain 208 through the n-type doped layer 220 and the well 308 to the source electrode 314.
[0026]
[0032] Figure 5 shows a schematic diagram of a multi-chamber processing tool 500 suitable for carrying out a method for processing a substrate according to at least some embodiments of the present disclosure. Examples of multi-chamber processing tools 500 may include the CENTURA® and ENDURA® tools, commercially available from Applied Materials, Inc. in Santa Clara, California. The methods described herein may be practiced using another multi-chamber processing tool to which suitable process chambers are connected, or in other suitable standalone process chambers. For example, in some embodiments, the creative methods described herein above may be advantageously carried out in a multi-chamber processing tool such that vacuum breaks between processing steps are limited or eliminated entirely. For example, reduced vacuum breaks make it possible to limit or prevent contamination of the substrate being processed in the multi-chamber processing tool. Other process chambers (including those available from other manufacturers) may also be suitably used in connection with the teachings presented herein.
[0027]
[0033] The multi-chamber processing tool 500 includes a vacuum-sealed processing platform 501, a factory interface (FI) 504, and a system controller 502. The processing platform 501 includes a plurality of processing chambers (e.g., 514A, 514B, 514C, and 514D) operably connected to a transfer chamber 503 under vacuum. The factory interface 504 is selectively operably connected to the transfer chamber 503 by one or more load-lock chambers (e.g., 506A and 506B in Figure 5).
[0028]
[0034] In some embodiments, the factory interface 504 includes at least one docking station 507 and at least one factory interface robot 538 to facilitate the transfer of substrates. At least one docking station 507 is configured to receive one or more forward-opening unified pods (FOUPs). Figure 5 illustrates four FOUPs, numbered 505A, 505B, 505C, and 505D. At least one factory interface robot 538 is configured to transfer substrates from the factory interface 504 to the processing platform 501 through load lock chambers 506A and 506B. Each of the load lock chambers 506A and 506B has a first port connected to the factory interface 504 and a second port connected to the transfer chamber 503. The load lock chambers 506A and 506B are connected to a pressure control system (not shown) which pumps down and evacuates the load lock chambers 506A and 506B to facilitate the passage of the substrate between the vacuum environment of the transfer chamber 503 and the substantially ambient environment (e.g., atmospheric environment) of the factory interface 504.
[0029]
[0035] A vacuum robot 542 is positioned inside the transfer chamber 503. The vacuum robot 542 is capable of transferring the substrate 521 between the load lock chambers 506A and 506B and the processing chambers 514A, 514B, 514C, and 514D. In some embodiments, the substrate 521 may be substrate 210. In some embodiments, the vacuum robot 542 is capable of extending into and retracting from any processing chamber connected to the transfer chamber 203.
[0030]
[0036] Each of the processing chambers 514A, 514B, 514C, and 514D may include an epitaxy chamber, a chemical vapor deposition (CVD) chamber, an atomic layer deposition (ALD) chamber, a physical vapor deposition (PVD) chamber, a plasma atomic layer deposition (PEALD) chamber, an etching chamber (i.e., a dry etching chamber), a pre-cleaning / annealing chamber, a masking chamber, and the like. In some embodiments, at least one of the processing chambers 514A, 514B, 514C, and 514D is an epitaxy chamber configured to carry out at least one of a first epitaxy process or a second epitaxy process.
[0031]
[0037] The system controller 502 controls the operation of the multi-chamber processing tool 500 by using direct control of at least one epitaxy chamber, or alternatively by controlling a computer (or controller) associated with the epitaxy chambers and process chambers 514A, 514B, 514C, and 514D. The system controller 502 generally includes a central processing unit (CPU) 530, memory 534, and support circuitry 532. The CPU 530 may be one of any form of general-purpose computers having one or more processors that can be used in an industrial setting. The support circuitry 532 is conventionally connected to the CPU 130 and may include a cache, clock circuitry, input / output subsystems, power supply, etc. Software routines (such as the processing methods described above) may be stored in memory 534 and, when executed by the CPU 530, can translate the CPU 530 to the system controller 502. Software routines may also be stored and / or executed by a second controller (not shown) located remotely from the multi-chamber processing tool 500.
[0032]
[0038] During operation, the system controller 502 optimizes the performance of the multi-chamber processing tool 500 by enabling data collection and feedback from each chamber and system, and by instructing system components to carry out the methods described herein. For example, memory 534 may be a non-transient computer-readable storage medium having instructions, which, when executed by the CPU 530 (or system controller 502), carry out the methods described herein.
[0033]
[0039] Referring again to Figure 1, in some embodiments, method 100 further includes forming the gate and source regions of a semiconductor device 200 on a plurality of n-doped pillars 250 and a plurality of p-doped pillars 240 in 108. For example, in some embodiments, the upper part 214 of the n-doped layer 220 may be etched to form a recess (such as a recess 302), which allows a plurality of p-doped bodies (such as a p-doped body 318) to be deposited in the recess and coupled to a subsequently formed source electrode (such as a source electrode 314). Each of the p-doped bodies 318 may extend vertically beneath a subsequently formed gate oxide (such as a metal oxide layer 304) and gate electrode (such as a gate electrode 310). For example, the gate oxide is deposited on each of the n-type doped pillars 250 of the n-type doped layer 220, and partially on multiple p-type doped pillars 240 after the formation of the p-type doped pillars 240.
[0034]
[0040] In some embodiments, method 100 further includes depositing a gate electrode on a metal oxide layer. An insulating film (such as insulating film 312) comprising at least one of a nitride layer or an oxide layer may be deposited on the gate electrode 310. A source electrode 314 may be deposited on the insulating film 312 and a plurality of p-doped pillars 240, with the insulating film insulating the gate electrode from the source electrode. The source electrode 314 is electrically coupled to a well 308 and, in some embodiments, a p-doped body 318. The source electrode 314 short-circuits the p-doped body 318 with the plurality of p-doped pillars 240 to prevent latch-up or the formation of a parasitic diode structure.
[0035]
[0041] While the above applies to embodiments of the present disclosure, other embodiments and further embodiments of the present disclosure can be devised without departing from the basic scope of the present disclosure.
Claims
1. A method for processing a substrate, The first epitaxial growth process involves depositing n-type doped silicon material onto a substrate to form an n-type doped layer, while adjusting the ratio of dopant precursor to silicon precursor so that the dopant concentration of the n-type doped layer increases from the bottom to the top of the n-type doped layer. Etching the n-type doped layer to form a plurality of trenches having tapered sidewalls and a plurality of n-type doped pillars between the plurality of trenches, The second epitaxial growth process involves filling the multiple trenches with p-doped material to form multiple p-doped pillars, Methods that include...
2. The method according to claim 1, further comprising forming a gate region and a source region on the plurality of n-type doped pillars and the plurality of p-type doped pillars, wherein a drain region is connected to the substrate on the opposite side of the n-type doped layer.
3. The method according to claim 1, wherein the thickness of the n-type doped layer is about 30 to about 50 micrometers.
4. The method according to claim 1, wherein the n-type doped layer is doped with phosphorus or arsenic.
5. The method according to claim 1, wherein the p-type doped material includes silicon or silicon carbide doped with boron, aluminum, or gallium.
6. The method according to any one of claims 1 to 5, wherein the dopant concentration comprises a first dopant concentration of about 5e15 to about 8e15 per cubic centimeter at the bottom of the n-type doped layer and a second dopant concentration of about 1e16 to about 2e16 per cubic centimeter at the top of the n-type doped layer.
7. The method according to any one of claims 1 to 5, wherein etching the n-type doped layer comprises forming a plurality of trenches having substantially vertical upper sidewalls and tapered lower sidewalls.
8. The method according to any one of claims 1 to 5, further comprising depositing an oxide hard mask on the n-type doped layer before etching the n-type doped layer to form the plurality of trenches.
9. The method according to any one of claims 1 to 5, wherein the plurality of p-doped pillars have a bottom width of about 0.5 to about 1.5 micrometers and a top width of about 1.0 to about 2.0 micrometers.
10. A non-transient computer-readable medium that, when executed by one or more processors, performs the method according to any one of claims 1 to 5.
11. The non-transient computer-readable medium according to claim 10, wherein the dopant concentration comprises a first dopant concentration of about 5e15 to about 8e15 per cubic centimeter at the bottom of the n-type doped layer and a second dopant concentration of about 1e16 to about 2e16 per cubic centimeter at the top of the n-type doped layer.
12. The non-transient computer-readable medium according to claim 10, wherein etching the n-type doped layer comprises forming a plurality of trenches having substantially vertical upper sidewalls and inwardly tapered lower sidewalls.
13. The non-transient computer-readable medium according to claim 10, further comprising depositing an oxide hard mask on the n-type doped layer before etching the n-type doped layer to form the plurality of trenches.
14. The non-transient computer-readable medium according to claim 10, wherein the plurality of p-type doped pillars have a bottom width of about 0.5 to about 1.5 micrometers and a top width of about 1.0 to about 2.0 micrometers.
15. It is a semiconductor device, The semiconductor device comprises an n-type doped layer, the n-type doped layer having a dopant concentration that increases from the bottom to the top of the n-type doped layer, and includes a plurality of trenches having side walls tapered inward, with a plurality of n-type doped pillars defined between the plurality of trenches, and the semiconductor device further comprises Each of the aforementioned trenches is equipped with a plurality of p-shaped doped pillars, Semiconductor devices.
16. The semiconductor device according to claim 15, wherein the side walls of the plurality of trenches include a substantially vertical upper side wall and a lower side wall tapered inward.
17. The semiconductor device according to claim 15, wherein the side walls of the plurality of trenches are continuously tapered from the top of the plurality of trenches to the bottom of the plurality of trenches.
18. The semiconductor device according to any one of claims 15 to 17, wherein the plurality of p-type doped pillars have substantially uniform dopant concentrations.
19. A metal oxide layer is disposed on the plurality of n-type doped pillars of the n-type doped layer, and partially disposed on adjacent p-type doped pillars of the plurality of p-type doped pillars, A gate electrode disposed on the metal oxide layer, The semiconductor device according to any one of claims 15 to 17, further comprising an insulating film disposed on the gate electrode.
20. The n-type doped pillars are positioned on or embedded on top of each of the aforementioned plurality of p-type doped pillars. ＋ Doped Well and The semiconductor device according to claim 19, further comprising the insulating film and a source electrode disposed on the well.