Semiconductor equipment

Abstract

A semiconductor device using an oxide semiconductor, which provides a highly reliable semiconductor device. . [Solution] A first electrode layer, and a first conductive layer and a second conductive layer located on the first electrode layer. A second electrode layer comprising a laminated structure, and between the first electrode layer and the second electrode layer in the thickness direction. The device has an oxide semiconductor film and an insulating film located at the first electrode, and the first conductive layer and insulating film are the first electrode The oxide semiconductor film has a first opening in the region overlapping with the layer, and in the region overlapping with the first opening It has a second opening, and the second conductive layer is exposed from the first opening and the second opening. A semiconductor device is provided that is in contact with the electrode layer.

Description

Technical Field

[0001] The present invention relates to an article, a method, or a manufacturing method. Alternatively, the present invention relates to a process, a machine, a manu facture, or a composition of matter. Also, one aspect of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a storage device, a driving method thereof, or a manufacturing method thereof. In particular, one aspect of the present invention relates to a semiconductor device, a display device, or a light-emitting device including an oxide semiconductor.

[0002] Note that in this specification, the semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. An electro-optical device, an image display device, a semiconductor circuit, and an electronic device may include a semiconductor device.

Background Art

[0003] Techniques for constructing a transistor using a semiconductor layer have attracted attention. The transistor is widely applied to electronic devices such as an integrated circuit (IC) and an image display device (also simply referred to as a display device). Silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors, but oxide semiconductors are attracting attention as other materials. In a transistor in which a channel is formed in an oxide semiconductor, it is known that a part of hydrogen contained in the oxide semiconductor forms a donor level and increases the carrier density. Therefore, in order to obtain stable electrical characteristics in a transistor using an oxide semiconductor, measures to reduce the hydrogen concentration contained in the oxide semiconductor are required. For example, in Patent Document 1, an oxide semiconductor layer and an insulating layer in contact therewith are made to have a reduced impurity concentration such as hydrogen.

[0004] ​​​​​​​​ A method to reduce the hydrogen concentration that may be contained in an oxide semiconductor layer by depositing the film in a deposition chamber. It is disclosed. Furthermore, Patent Document 2 describes a resist mask used for processing an oxide semiconductor layer. By removing it by ashing instead of chemical treatment, water is removed from the oxide semiconductor layer. Methods for preventing contamination with elements, hydrocarbons, etc. are disclosed. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2011-091381 [Patent Document 2] Japanese Patent Publication No. 2012-160717 [Overview of the Initiative] [Problems that the invention aims to solve]

[0006] As mentioned above, the chemical removal process of the resist mask used in the processing of oxide semiconductor layers is This is undesirable from the viewpoint of suppressing the inclusion of impurities in the oxide semiconductor layer. On the other hand, oxide semiconductor The removal of the resist mask used for processing the layer by ashing process is part of the processing of the oxide semiconductor layer. Depending on the shape, it may be undesirable. For example, an electric field provided in the lower layer of an oxide semiconductor layer The resist mask, which forms openings that reach the polar layer, is removed by ashing. As a result, the surface of the electrode layer exposed through the opening oxidizes, causing electrical contact at the opening. Defects may occur in the future.

[0007] Therefore, in one aspect of the present invention, electrode layers provided above and below an oxide semiconductor layer are provided above the oxide semiconductor layer. A method for manufacturing a semiconductor device that can be stably connected at an opening provided in a body layer, and One of the objectives is to provide a semiconductor device manufactured by the same manufacturing method.

[0008] Alternatively, one aspect of the present invention is a semiconductor device using an oxide semiconductor, wherein a highly reliable semiconductor... One objective of this invention is to provide a conductive device. Alternatively, one aspect of this invention relates to a novel semiconductor device. One of the objectives is to provide a suitable location.

[0009] Alternatively, one aspect of the present invention relates to a semiconductor device using an oxide semiconductor that achieves miniaturization. One of the objectives is to provide semiconductor devices. This includes increasing the speed of transistor operation, and... In order to achieve lower power consumption, lower cost of semiconductor devices, and higher integration of semiconductor devices, Therefore, miniaturization of transistors is essential.

[0010] Furthermore, the description of these problems does not preclude the existence of other problems. One aspect of the present invention is: It is not necessary to solve all of these issues. Furthermore, any issues other than those mentioned above are addressed in the specification. This becomes clear from the descriptions, and we will extract any issues other than those mentioned above from the descriptions in the specifications, etc. It is possible to do so. [Means for solving the problem]

[0011] One aspect of the present invention comprises a first electrode layer and a first conductive layer and a second electrode layer located on the first electrode layer. A second electrode layer including a laminated structure of conductive layers, and the first electrode layer and the second electrode layer in the thickness direction The device has an oxide semiconductor film and an insulating film located between the two, and the first conductive layer and the insulating film are first The oxide semiconductor film has a first opening in the region overlapping with the electrode layer, and the oxide semiconductor film overlaps with the first opening The region has a second opening, and the second conductive layer is exposed from the first opening and the second opening. This is a semiconductor device that is in contact with the first electrode layer.

[0012] Alternatively, one aspect of the present invention provides an island-shaped oxide semiconductor layer and an island-shaped oxide semiconductor layer electrically A source electrode layer and a drain electrode layer to be connected, and provided on the source electrode layer and the drain electrode layer An oxide semiconductor film in contact with an island-shaped oxide semiconductor layer, and provided on the oxide semiconductor film A gate insulating film and a gate electrode layer that overlaps with an island-shaped oxide semiconductor layer on the gate insulating film. And, on the gate insulating film, a first electrode overlaps with one of the source electrode layer and the drain electrode layer. The electrode layer comprises a polar layer, and the first electrode layer includes a laminated structure of a first conductive layer and a second conductive layer, The conductive layer and gate insulating film of 1 overlap with either the source electrode layer or the drain electrode layer in the region where they meet. The oxide semiconductor film has a first opening, and the oxide semiconductor film has a second opening in a region overlapping with the first opening. Furthermore, the second conductive layer is the source electrode layer and the drain exposed from the first and second openings. This is a semiconductor device that is in contact with one of the in-electrode layers.

[0013] In the semiconductor device described above, the gate electrode layer is composed of a first conductive layer and a second conductive layer, respectively It may also include a laminated structure of a third conductive layer and a fourth conductive layer formed in the same manufacturing process. stomach.

[0014] Alternatively, one aspect of the present invention includes a first transistor and a second transistor adjacent to the first transistor. The transistor has an island-shaped oxide semiconductor layer and an island-shaped acid A source electrode layer and a drain electrode layer electrically connected to a semiconductor alloy layer, and the source electrode layer and An oxide semiconductor film provided on the drain electrode layer and in contact with an island-shaped oxide semiconductor layer, and an oxide A gate insulating film provided on a semiconductor film, and island-shaped oxide semiconductors on the gate insulating film. The second transistor has a first gate electrode layer that overlaps with the first conductive layer and It has at least a second gate electrode layer which includes a laminated structure of two conductive layers, and the first conductive layer and the gate electrode layer The insulating film overlaps with either the source electrode layer or the drain electrode layer of the first transistor. The oxide semiconductor film has an opening, and the oxide semiconductor film has a second opening in a region that overlaps with the first opening. The conductive layer is exposed from the first and second openings of the source power of the first transistor. This is a semiconductor device in contact with either the polar layer or the drain electrode layer.

[0015] Alternatively, in one aspect of the present invention, an oxide semiconductor film, an insulating film and A first conductive film is formed in sequence, and a resist mask is formed on the first conductive film. Using this method, the first conductive film and insulating film are processed to reach an oxide semiconductor film at a position overlapping with the electrode layer. A first opening is formed, the resist mask is removed, and the first conductive having the first opening Using the film as a mask, the oxide semiconductor film is processed to form a second opening that reaches the electrode layer. A second conductive layer is in contact with the electrode layer exposed from the first opening and the second opening on the first conductive film. This is a method for fabricating semiconductor devices that form an electrical film.

[0016] In the above semiconductor device fabrication method, the resist mask is assembled using oxygen plasma. It is preferable to remove it by a polishing process. Also, after the removal of the resist mask, Before forming the second conductive film, the first conductive film is subjected to an ashing treatment using oxygen plasma. It is preferable to perform a process to remove the oxide film formed on the upper surface. [Effects of the Invention]

[0017] According to one aspect of the present invention, a semiconductor device using an oxide semiconductor, which is a highly reliable semiconductor We can provide a body device.

[0018] Alternatively, according to one aspect of the present invention, a semiconductor device using an oxide semiconductor, wherein miniaturization is performed A semiconductor device that achieves these effects can be provided. However, one aspect of the present invention is not limited to these effects. It is not fixed. For example, one aspect of the present invention may, depending on the circumstances, Furthermore, it may have effects other than those listed above. Or, for example, one aspect of the present invention is However, in some cases, or depending on the circumstances, these effects may not be present. [Brief explanation of the drawing]

[0019] [Figure 1] A plan view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 2] A cross-sectional diagram illustrating the method for manufacturing semiconductor devices. [Figure 3] A cross-sectional diagram illustrating the method for manufacturing semiconductor devices. [Figure 4] A cross-sectional diagram illustrating the method for manufacturing semiconductor devices. [Figure 5] A cross-sectional view illustrating one aspect of a semiconductor device. [Figure 6] A plan view, cross-sectional view, and circuit diagram illustrating one aspect of a semiconductor device. [Figure 7] An example of the configuration of an RFIC tag according to an embodiment. [Figure 8] An example of a CPU configuration according to an embodiment. [Figure 9] Circuit diagram of a memory element according to an embodiment. [Figure 10] An electronic device according to an embodiment. [Figure 11] An example of RFIC usage according to the embodiment. [Figure 12] Cross-sectional STEM image of the sample prepared in the example. [Figure 13]A cross-sectional view illustrating one aspect of a semiconductor device. [Figure 14] A block diagram and a circuit diagram of a display device according to an embodiment. [Modes for carrying out the invention]

[0020] The embodiments of the disclosed invention will be described in detail below with reference to the drawings. However, this The invention disclosed in this specification is not limited to the following description, and its form and details may be modified in various ways. This will be easily understood by those skilled in the art. Furthermore, the inventions disclosed herein are as follows: The present invention is not limited to the descriptions of the embodiments shown below. In one embodiment of the configuration, the same part or a part having a similar function is given the same reference numeral. This information is used consistently across drawings, and its repetition will be omitted. Also, parts with similar functions are described. When referring to this, the hatch pattern is the same, and sometimes no specific designation is assigned.

[0021] Furthermore, in this specification, ordinal numbers such as "the first," "the second," etc., are used to avoid confusion of constituent elements. This is meant to be noticed, and is not limited to a specific number.

[0022] Furthermore, in this specification, the terms "above" and "below" refer to the positional relationship of the constituent elements, meaning "directly above" or This does not necessarily mean "directly below". For example, "gate electrode on gate insulating film" If the expression is "layer," then it refers to a layer that includes other components between the gate insulating film and the gate electrode layer. They are not excluded. The same applies to "below".

[0023] Furthermore, in this specification, the upper surface of the film refers to the surface that is substantially parallel to the substrate surface, from the substrate surface. This indicates the side that is further away from the substrate surface, and the bottom surface of the film is the side that is approximately parallel to the substrate surface. This shows the side that is closer.

[0024] In this specification, "parallel" means that two straight lines are positioned at an angle of -10° or more and 10° or less. This refers to a state in which something is positioned. Therefore, it also includes cases where the angle is between -5° and 5°. Also, "perpendicular" This refers to a state in which two straight lines are positioned at an angle of 80° to 100°. Therefore This also includes cases where the angle is between 85° and 95°.

[0025] Furthermore, in this specification and other documents, when the crystal is trigonal or rhombohedral, it is listed as hexagonal. vinegar.

[0026] Furthermore, in this specification, the functions of "source" and "drain" refer to transients of different polarities. The positions are swapped when using a standard or when the direction of current changes during circuit operation. This may occur. For this reason, in this specification, the terms "source" and "drain" are used in the following contexts: It may be used as a substitute.

[0027] In this specification, etc., "electrically connected" means "having some kind of electrical effect." This includes cases where the connection is made via ". Here, "something that has some electrical effect" The term "connection" is not particularly limited as long as it enables the exchange of electrical signals between connected objects. For example, "things that have some kind of electrical effect" include electrodes and wiring, as well as transistors. These include switching elements, resistive elements, inductors, capacitors, and various other functional elements. This includes elements such as [specific components].

[0028] (Embodiment 1) In this embodiment, a semiconductor device and a method for manufacturing a semiconductor device according to one aspect of the present invention are shown in Figures 1 to 1. This will be explained with reference to Figure 4. In this embodiment, as an example of a semiconductor device, an oxide semiconductor is used. This shows a semiconductor device containing a transistor with a top-gate structure in which a channel is formed.

[0029] <Example 1 of semiconductor device configuration> Figures 1(A) and 1(B) show examples of semiconductor device configurations including transistor 300. (A) is a plan view of the semiconductor device, and Figure 1(B) is a view of A1-A2 and A3 of Figure 1(A). -This is a cross-sectional view in A4 size. Note that in Figure 1(A), to avoid complexity, tra Some components of the inverter 300 (for example, the gate insulating film 410, etc.) are omitted from the illustration. Yes, they are.

[0030] The semiconductor device shown in Figures 1(A) and 1(B) includes transistor 300 and transistor 3 It comprises an electrode layer 416b that is electrically connected to a source electrode layer 406a. Furthermore, the electrode layer 416b replaces the source electrode layer 406a with the drain electrode layer 406b. It's okay if they're connected electrically.

[0031] The electrode layer 416b consists of a first conductive layer 412b and a second conductive layer 414b, which are stacked in order. It has. The transistor 300 is provided on the substrate 400 via the underlying insulating film 402. Island-shaped oxide semiconductor layer 404 and source electrode layer electrically connected to oxide semiconductor layer 404 406a and drain electrode layer 406b, and source electrode layer 406a and drain electrode layer 40 The oxide semiconductor film 408 on 6b, the gate insulating film 410 on the oxide semiconductor film 408, and The gate electrode layer 416a overlaps with the island-shaped oxide semiconductor layer 404 via the insulating film 410. , has. In this embodiment, the gate electrode layer 416a is sequentially stacked with the first conductive It has a layer 412a and a second conductive layer 414a. The protective insulating film 418 and / or the insulating film 420 formed on the protective insulating film 418 It may be included as a component of the Rangista 300.

[0032] As shown in the cross-sectional view of Figure 1(B), the source electrode layer 406a and electrode layer of transistor 300 An oxide semiconductor film 408 and a gate insulating film 410 are provided between 416b and the other element. The first conductive layer 412b and gate insulating film 410 of the electrode layer 416b are connected to the source electrode layer 406 The region overlapping with a has an opening 417, and the gate insulating film 410 and the source electrode layer 406a The oxide semiconductor film 408 located in between has an opening 415 that overlaps with the opening 417. The second conductive layer 414b of the pole layer 416b covers the openings 417 and 415 and the first Source electrode layer provided on conductive layer 412b and exposed from openings 417 and 415 It comes into contact with 406a. This makes contact between the source electrode layer 406a of transistor 300 and the electrode. It is electrically connected to layer 416b.

[0033] The oxide semiconductor film 408 is an oxide semiconductor in which channels are formed (which become the main paths for current). Located between layer 404 and gate insulating film 410, impurities are introduced into the oxide semiconductor layer 404. It has the function of suppressing and stabilizing the interface of the oxide semiconductor layer 404. The oxide semiconductor film 408 in contact with the oxide semiconductor layer 404 contains as much water, hydrogen, etc. as possible. It is preferable that it does not contain impurities. Oxide semiconductor film 40 in contact with oxide semiconductor layer 404 If hydrogen is present in 8, there is a risk that the hydrogen may penetrate the oxide semiconductor layer 404, or that the water This is because the element may extract oxygen from the oxide semiconductor layer 404.

[0034] In the semiconductor device manufacturing process shown in Figures 1(A) and 1(B), the gate insulating film 410 and After forming an opening in the oxide semiconductor film 408, a resist mask for forming the opening is used. When these are removed by chemical treatment, impurities such as water and hydrogen enter the oxide semiconductor from the inside of the opening. It may become mixed into film 408. Therefore, chemical treatment is used to remove the resist mask. It is undesirable for it to be present. Also, depending on the composition of the oxide semiconductor film 408, the resist mass It is soluble in the chemical solution applied to the stripping of the coating, and the use of this chemical solution removes the shape defects of the opening 415. This may occur. On the other hand, a resist mask is formed on the gate insulating film 410, source After forming an opening that reaches the electrode layer 406a, ashing using oxygen plasma or the like When the resist mask is removed, the surface of the exposed source electrode layer 406a is oxidized, and A defect occurs in the electrical connection with the electrode layer 416b formed thereon.

[0035] Therefore, in the semiconductor device of this embodiment, the electrode layer 416b is in contact with the source electrode layer 406a. As such, a first conductive layer 412b is formed on the gate insulating film 410, and the first conductive layer 412b And after forming an opening 417 in the gate insulating film 410, the first conductive layer 412b is used as a mask. Then an opening 415 is formed in the oxide semiconductor film 408, and a second conductive layer 414b is formed. Electrode layers provided above and below the semiconductor film 408 (here, source electrode layer 406a and electrode) By forming the connection portion of layer 416b) using this manufacturing method, water is removed during chemical treatment. This includes the inclusion of impurities such as those listed above, the formation of shape defects, and oxides caused by ashing of the resist mask. Both oxidation of the surface of the electrode layer (in this case, the source electrode layer 406a) beneath the semiconductor film 408. This can prevent problems and make it possible to form semiconductor devices with good electrical characteristics. .

[0036] However, the present invention is not limited to this embodiment. For example, as a cross-sectional view, Figure 1(B) is Other configurations may be used. For example, a conductive layer 422 may be provided below the oxide semiconductor layer 404. A cross-sectional view of the case is shown in Figure 13(A). Note that, as shown in Figure 13(B), through the opening The conductive layer 422 may be connected to the gate electrode layer 416a. This can function as a gate electrode (back gate electrode). (See Figure 13(A)) In this case, the conductive layer 422 may be supplied with a different potential from the gate electrode layer 416a, and A constant potential may be supplied. For example, a constant potential may be supplied to the conductive layer 422 to enable the transient The threshold voltage of TA300 may be controlled.

[0037] Details of each element included in the semiconductor device of this embodiment are described below.

[0038] Circuit board The substrate 400 is not merely a support, but also forms other elements such as transistors and capacitors. It may also be a substrate. In this case, the gate electrode layer 416a of transistor 300, At least one of the - electrode layer 406a or the drain electrode layer 406b is electrically connected to the other element. It may be connected electrically.

[0039] <<Underlying insulating film>> The underlying insulating film 402 has the role of preventing the diffusion of impurities from the substrate 400, as well as It can play a role in supplying oxygen to the oxide semiconductor layer 404 on which the filament is formed. Therefore, the underlying insulating film 402 is preferably an insulating film containing oxygen, and has a stoichiometric composition. It is more preferable that the insulating film contains a larger amount of oxygen. Also, as mentioned above, substrate 400 If the substrate has other elements formed on it, the underlying insulating film 402 functions as an interlayer insulating film. It also has. In that case, the surface of the substrate insulating film 402 may be flattened. For example, the substrate CMP (Chemical Mechanical Polishing) on ​​insulating film 402 The surface can be leveled using methods such as the ) method.

[0040] ≪Oxide Semiconductor Layer≫ The oxide semiconductor layer 404 is an oxide semiconductor containing indium. The presence of um is preferable because it increases carrier mobility (electron mobility). Furthermore, oxides are also preferable. The semiconductor layer 404 is made of, for example, aluminum, gallium, germanium, yttrium, and It is preferable that it contains element M such as tungsten, tin, lanthanum, cerium, or hafnium. i. Such an element M is an element with a high bonding energy with oxygen. Or such an element Element M is an element that has the function of increasing the energy gap of oxides. The material semiconductor layer 404 preferably contains zinc. When the oxide semiconductor contains zinc, the oxide The semiconductor layer 404 becomes easier to crystallize. Alternatively, the energy at the top of the valence band of the oxide semiconductor. This can be controlled, for example, by the atomic ratio of zinc. However, the oxide semiconductor layer 40 4 is not limited to indium-containing oxide semiconductors. The oxide semiconductor layer 404 is, for example, Zn-Sn oxide or Ga-Sn oxide may also be used.

[0041] Furthermore, the oxide semiconductor layer 404 is formed using an oxide semiconductor with a large energy gap. The energy gap of the oxide semiconductor layer 404 is, for example, 2.5 eV or more, preferably The voltage shall be 2.8 eV or higher, more preferably 3.0 eV or higher. However, the semiconductor layer shall function as such. To achieve this, the energy gap of the oxide semiconductor layer 404 is preferably 4.2 eV or less. The voltage shall be 3.8 eV or less, more preferably 3.5 eV or less.

[0042] Furthermore, when depositing the oxide semiconductor layer 404 by sputtering, reducing the number of particles Therefore, it is preferable to use a target containing indium. Also, the atoms of element M mentioned above When using an oxide target with a high number ratio, the conductivity of the target may decrease. When using a target containing indium in addition to element M, the target's conductivity decreases. This can suppress or enhance the conductivity of the target, and facilitate DC discharge and AC discharge. This makes it possible to deposit films on large-area substrates, which is effective for that purpose. By forming the oxide semiconductor layer 404 using a target, the productivity of semiconductor devices can be increased. It is possible to do so.

[0043] When depositing an oxide semiconductor layer 404 by sputtering, the atomic ratio of the target used The ratios of In:M:Zn are 3:1:1, 3:1:2, 3:1:4, 1:1:0.5, and 1:1: A ratio such as 1, 1:1:2 would suffice. Furthermore, the oxide semiconductor layer 404 is formed by sputtering. When forming a film, the atomic ratio of the deposited oxide semiconductor layer 404 is equal to the atomic number of the target used. The ratio does not necessarily match. In particular, the atomic ratio of zinc in the oxide semiconductor layer 404 after film formation is In some cases, the atomic ratio may be smaller than that of the target. Specifically, the target contains There may be cases where it is about 40 atomic% or more and about 90 atomic% or less of the atomic ratio of zinc. .

[0044] In order to stabilize the electrical characteristics of the transistor 300, it is effective to reduce the impurity concentration in the oxide semiconductor layer 404 where the channel is formed and to reduce the carrier density and achieve high purity intrinsic properties. . The carrier density contained in the oxide semiconductor layer 404 is preferably less than 1×10 / cm 3 , less than 1×10 15 / cm 3 , or less than 1×10 13 / cm 3 . Impurities that can be factors for carrier generation in the oxide semiconductor include, for example, silicon, hydrogen, nitrogen, etc. Also, when there is an oxygen deficiency in the oxide semiconductor layer 404, a part of it becomes a donor and releases electrons as carriers.

[0045] For example, when silicon is contained in the oxide semiconductor layer 404, the impurity levels formed by silicon may become carrier traps. Therefore, the silicon concentration between the oxide semiconductor layer 404 and the underlying insulating film 402 is less than 1×10 in secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry), preferably less than 5×10 1 9 / cm 3 , more preferably less than 2×10 18 / cm 3 . Furthermore, it is more preferably less than 2×10 18 / cm 3 .

[0046] Also, when hydrogen is contained in the oxide semiconductor layer 404, the carrier density will increase.​​​​​​ There is a match. Therefore, the hydrogen concentration of the oxide semiconductor layer 404 is 2 × 10 in SIMS. 2 0 atoms / cm 3 The following is preferably 5 × 10 19 atoms / cm 3 The following are more preferred Or 1 x 10 19 atoms / cm 3 More preferably 5 × 10 18 atoms / cm 3 The following applies. Furthermore, if nitrogen is present in the oxide semiconductor layer 404, the carrier density This can increase the nitrogen concentration in the oxide semiconductor layer 404 in SIMS. , 5×10 19 atoms / cm 3 Less than 5 × 10 18 atoms / cm 3 Below Below, fer 1 × 10 18 atoms / cm 3 More preferably 5 × 10 1 7 atoms / cm 3 The following applies:

[0047] Furthermore, in order to reduce the hydrogen concentration of the oxide semiconductor layer 404, the hydrogen concentration of the underlying insulating film 402 It is preferable to reduce the hydrogen concentration of the underlying insulating film 402, which is 2 × 10 in SIMS. 20 atoms / cm 3 The following is preferably 5 × 10 19 atoms / cm 3 The following are better Mashiku is 1 x 10 19 atoms / cm 3 More preferably 5 × 10 18 Atom s / cm 3 The following applies. In addition, in order to reduce the nitrogen concentration of the oxide semiconductor layer 404, the substrate It is preferable to reduce the nitrogen concentration of the insulating film 402. The nitrogen concentration of the underlying insulating film 402 is determined by SIM In S, 5 × 10 19 atoms / cm 3 Less than 5 × 10 18 atoms / cm 3 More preferably 1 × 10 18 atoms / cm 3 More preferably, 5 x 10 17 atoms / cm 3 The following applies:

[0048] <Source electrode layer and drain electrode layer> Oxygen is released from the oxide semiconductor layer 404 into the source electrode layer 406a and the drain electrode layer 406b. It is preferable to use a conductive layer that has the property of extracting. Examples include aluminum, titanium, chromium, nickel, molybdenum, tantalum, and tungsten. Examples include conductive layers containing materials such as fluorine.

[0049] Due to the action of the conductive layer which has the property of extracting oxygen from the oxide semiconductor layer 404, Oxygen may be desorbed from the body layer 404, forming an oxygen vacancy in the oxide semiconductor layer 404. Oxygen abstraction is more likely to occur at higher temperatures. Because there are several heating steps, the source electrode layer 406a of the oxide semiconductor layer 404 Alternatively, there is a high possibility that an oxygen deficiency will be formed in the region near the drain electrode layer 406b that is in contact with it. Furthermore, the regions where oxygen deficiencies are formed become n-type. Also, heating causes water to form at the sites of the oxygen deficiencies. In some cases, elements may enter, causing the oxide semiconductor layer 404 to become n-type. Therefore, the source electrode Due to the action of layer 406a and drain electrode layer 406b, the oxide semiconductor layer 404 and the source The region in contact with the electrode layer 406a or the drain electrode layer 406b is made less resistive, and the transient This can reduce the on-resistance of the STA300.

[0050] Note that transistors with small channel lengths (e.g., 200nm or less, or 100nm or less) When fabricating this, the formation of the n-type region can cause a short circuit between the source and drain. Yes. Therefore, when forming a transistor with a small channel length, the source electrode layer 40 6a and the drain electrode layer 406b have the property of moderately extracting oxygen from the oxide semiconductor layer 404. A conductive layer having the property of moderately extracting oxygen can be used. Examples include conductive layers containing nickel, molybdenum, or tungsten.

[0051] Furthermore, transistors with very small channel lengths (40nm or less, or 30nm or less) were fabricated. In this case, the source electrode layer 406a and the drain electrode layer 406b are oxide semiconductor layers 4 A conductive layer that does not extract much oxygen from 04 should be used. Oxide semiconductor layer 40 Examples of conductive layers that do not extract much oxygen from 4 include tantalum nitride and nitride. This includes conductive layers containing titanium or ruthenium. Multiple types of conductive layers may be laminated. No.

[0052] Furthermore, transistors with very small channel lengths (40nm or less, or 30nm or less) can be fabricated. If so, use a resist mask processing method suitable for fine line processing, such as electron beam lithography. The etching process is performed to ensure the conductivity between the source electrode layer 406a and the drain electrode layer 406b. The film should be etched. Note that a positive-type resist should be used as the resist mask. This allows for minimizing the exposure area and improving throughput. Using methods such as these, it is possible to form transistors with a channel length of 30 nm or less. It is possible.

[0053] In this embodiment, the side surfaces of the source electrode layer 406a and the drain electrode layer 406b are shown in Figure As shown in 1(B), it is in contact with the side surface of the oxide semiconductor layer 404. Also, gate electrode layer 41 The electric field of 6a can electrically surround the oxide semiconductor layer 404 (gate electric field The structure of a transistor, in which the oxide semiconductor layer is electrically surrounded by the polar electric field, This is called a rounded channel (s-channel) structure. Therefore, acid A channel is formed throughout the entire (bulk) of the ionized semiconductor layer 404. (s-channel structure) Therefore, a large current can be passed between the source and drain of the transistor, and a high on-current can be obtained. It is possible.

[0054] Because it provides a high on-current, the s-channel structure is used in miniaturized transistors. It can be said to be a suitable structure. Because the transistor can be miniaturized, it is a semiconductor having the transistor. The device can be made into a highly integrated, high-density semiconductor device. For example, The channel length of the lampistor is preferably 40 nm or less, more preferably 30 nm or less. More preferably, the wavelength should be 20 nm or less, and the channel width of the transistor should preferably be 40 The wavelength should be less than or equal to nm, more preferably less than or equal to 30 nm, and more preferably less than or equal to 20 nm.

[0055] The channel length is the region in the top view where the semiconductor layer and the gate electrode layer overlap. The source (source region or source electrode layer) and the drain (drain region or drain electrode) This refers to the distance from the layer. That is, in Figures 1(A) and 1(B), the channel length is the oxide. Source electrode layer 406a in the region where semiconductor layer 404 and gate electrode layer 416a overlap This is the distance between the semiconductor layer and the drain electrode layer 406b. The channel width is the distance between the semiconductor layer and the gate electrode. This refers to the length of the parallel relationship between the source and drain in the region where layers overlap. In other words, in Figures 1(A) and 1(B), the channel width is between the oxide semiconductor layer 404 and the gate. In the region where the source electrode layer 406a and the drain electrode layer 40 overlap, This refers to the length between 6b and the other parallel line.

[0056] ≪Oxide Semiconductor Films≫ Acids that form channels are formed on the source electrode layer 406a and the drain electrode layer 406b. The oxide semiconductor film 408 in contact with the oxide semiconductor layer 404 is composed of the oxide semiconductor layer 404. An oxide semiconductor film containing at least one of the constituent metal elements as a constituent element is suitable. It is used in contact with the oxide semiconductor layer 404, and is different from the elements that make up the oxide semiconductor layer 404. When forming an insulating layer containing an element (for example, silicon), the oxide semiconductor layer 404 and the insulating layer Trap levels may form at the interface with the marginal layer. However, in this implementation In this state, the oxide semiconductor film 408 provided in contact with the oxide semiconductor layer 404 is an oxide semiconductor film. Because the conductive layer 404 is composed of one or more metal elements, the oxide semiconductor layer 40 Carrier scattering at the interface with 4 is less likely to occur. By using this configuration, the transient The field-effect mobility of the material can be increased. Furthermore, by including the oxide semiconductor film 408, As the gate insulating film 410, a different element (e.g., silicon) from the oxide semiconductor layer 404 is used. Even if an insulating layer is used, a shape may form at the interface between the oxide semiconductor film 408 and the gate insulating film 410. The influence of the trap levels that may be formed extends to the oxide semiconductor layer 404 where the channel is formed. This can prevent that from happening.

[0057] Furthermore, the oxide semiconductor layer 404 contains indium, zinc, and element M (where M is aluminum). Gallium, germanium, yttrium, zirconium, tin, lanthanum, cerium or When using an oxide semiconductor material represented by an In-M-Zn oxide containing hafnium, The oxide semiconductor film 408 is denoted as In-M-Zn oxide, and the oxide semiconductor layer 404 It is preferable to use oxide semiconductor materials with a higher atomic ratio of element M to indium. More preferably, when the oxide semiconductor layer 404 is In-M-Zn oxide, oxidation The monocrystalline semiconductor layer 404 is In:M:Zn=x1:y1:z1 [atomic ratio], and the oxide semiconductor film 4 If we represent 08 as In:M:Zn=x2:y2:z2 [atomic ratio], then y2 / x2 is y1 / x The value should be 1.5 times or more than 1, preferably 2 times or more, and more preferably 3 times or more. At this time, if y1 is greater than or equal to x1 in the oxide semiconductor layer 404, the electrical current of the transistor The characteristics can be stabilized. However, if y1 is more than 3 times x1, the transistor Since the field effect mobility decreases, it is preferable that y1 is less than three times x1.

[0058] When depositing an oxide semiconductor film 408 by sputtering, the atomic ratio of the target used This is when In:M:Zn is 1:3:2, 1:4:4, 1:6:4, or 1:9:6, etc. Yes.

[0059] Furthermore, element M is an element that has the function of increasing the energy gap of oxides. The oxide semiconductor film 408 has a larger energy gap compared to the oxide semiconductor layer 404. It is a film. Here, if the atomic ratio of element M to indium is too high, it becomes an oxide semiconductor. Because the energy gap of film 408 becomes larger, it can function as an insulating layer, thus it is an oxide semiconductor. The atomic ratio of M to indium is adjusted so that film 408 can function as a semiconductor layer. This is preferable. However, depending on the atomic ratio of M to indium, the oxide semiconductor film 40 8 can also function as an insulating film (for example, as part of the gate insulating film).

[0060] Furthermore, as mentioned above, element M is an element with a high bonding energy with oxygen, therefore Oxide semiconductor film 40 has a higher atomic ratio of element M to zinc than oxide semiconductor layer 404. Layer 8 is a film that is less prone to oxygen vacancies compared to the oxide semiconductor layer 404. Channels are formed. In contact with the oxide semiconductor layer 404, an oxide semiconductor film 408 that is less prone to oxygen vacancies is formed. This reduces oxygen vacancies in the oxide semiconductor layer 404. By providing an oxide semiconductor film 408 between the insulating film 410 and the oxide semiconductor layer 404, acid A trap level caused by oxygen vacancy exists at the interface of the ionized semiconductor layer 404 on the gate insulating film 410 side. This can suppress the formation of [the compound].

[0061] Furthermore, when an electric field is applied to the gate electrode layer 416a, a channel is formed in the oxide semiconductor layer 404. For it to be formed, an energy difference must be found at the lower end of the conduction band between the oxide semiconductor film and the oxide semiconductor layer. It is necessary to have. Specifically, the oxide semiconductor film 408 has more oxide semiconductor layer 404 than the oxide semiconductor layer 404. In addition, an oxide is applied where the lower end of the conduction band is close to the vacuum level. In other words, the oxide semiconductor film 408 and Therefore, the electron affinity (energy difference between the vacuum level and the lower end of the conduction band) is greater than that of the oxide semiconductor layer 404. A small oxide is applied. For example, an oxide semiconductor layer 404 is used as the oxide semiconductor film 408. Rather than electron affinity of 0.07 eV to 1.3 eV, preferably 0.1 eV to 0.7 eV Use an oxide with a low eV of 0.15eV or less, more preferably 0.4eV or more. It is preferable.

[0062] Between the oxide semiconductor layer 404 and the oxide semiconductor film 408, the oxide semiconductor layer 404 and the oxide It may have a mixed region with the monocrystalline semiconductor film 408. In the mixed region, the interface state density is low. Therefore, the stacked structure of the oxide semiconductor layer 404 and the oxide semiconductor film 408 is such that the interfaces In the vicinity, a band structure is formed where the energy changes continuously (also called a continuous junction). .

[0063] Furthermore, in order to improve the on-current of the transistor, the thickness of the oxide semiconductor film 408 should be small. The more preferable. For example, the oxide semiconductor film 408 is less than 10 nm, preferably 5 nm. Hereafter, it is more preferably 3 nm or less. On the other hand, the oxide semiconductor film 408 has a channel The oxide semiconductor layer 404 is formed, and elements other than oxygen that constitute the gate insulating film 410 (C It has a function to block the entry of (such as reconstituted material). 408 preferably has a certain thickness. For example, the thickness of the oxide semiconductor film 408 The wavelength is 0.3 nm or more, preferably 1 nm or more, and more preferably 2 nm or more.

[0064] Furthermore, to improve reliability, it is preferable to reduce the impurity concentration of the oxide semiconductor film 408. For example, silicon between the oxide semiconductor layer 404 and the oxide semiconductor film 408. The concentration in SIMS is 1 × 10 19 atoms / cm 3 Less than 5 × 10 18 atoms / cm 3 Less than 2 × 10 18 atoms / cm 3 Less than and Furthermore, the hydrogen concentration of the oxide semiconductor film 408 is 2 × 10⁻⁶ in SIMS. 20 ato ms / cm 3 The following is preferably 5 × 10 19 atoms / cm 3 More convenient 1 ×10 19 atoms / cm 3 More preferably 5 × 10 18 atoms / cm 3 The following applies. Furthermore, the nitrogen concentration of the oxide semiconductor film 408 is 5 × 10 in SIMS. 1 9 atoms / cm 3 Less than 5 × 10 18 atoms / cm 3 The following are more preferred Or 1 x 10 18 atoms / cm 3 More preferably 5 × 10 17 atoms / cm 3 The following applies:

[0065] ≪Gate Insulating Film≫ The gate insulating film 410 is, for example, silicon oxide, silicon oxide nitride, silicon oxide nitride, and nitrogen Silicon oxide, aluminum oxide, hafnium oxide, gallium oxide, or Ga-Zn metals Oxides, silicon nitride, etc., can be used, and they can be provided in a laminated or single layer configuration. Also, gate insulation. As film 410, hafnium silicate (HfSiO x ), nitrogen-added hafnium Silicate (HfSi x O y N z ), nitrogen-added hafnium aluminate (HfA l x O y N z ), using high-k materials such as hafnium oxide and yttrium oxide. This reduces gate leakage in transistors.

[0066] ≪Electrode layer≫ The electrode layer 416b forms an opening 415 in the oxide semiconductor film 408 and the gate insulating film 410. A first conductive layer 412b that functions as a hard mask during the process, and on the first conductive layer 412b It has a laminated structure with the first conductive layer 412b and the second conductive layer 414b. The materials for 414b are molybdenum, titanium, tantalum, tungsten, aluminum, copper, A metal film containing elements selected from chromium, neodymium, and scandium, or the above elements The components are metal nitride films (tantalum nitride film, titanium nitride film, molybdenum nitride film, tan nitride). A suitable material can be selected from a gusten film, etc. Also, the first conductive layer 412b or The second conductive layer 414b is a polycrystalline silicon film doped with impurity elements such as phosphorus. The semiconductor film shown may be a silicide film such as nickel silicide. Alternatively, Indium oxide containing tungsten oxide, tungsten oxide, and other materials containing tungsten oxide Indium zinc oxide, indium oxide containing titanium oxide, indium oxide containing titanium oxide Conductive materials such as tin oxide, indium zinc oxide, and indium tin oxide with added silicon oxide. It is also possible to apply synthetic materials.

[0067] ≪Gateway Layer≫ The gate electrode layer 416a can be fabricated using the same process as the electrode layer 416b described above. Therefore, the gate electrode layer 416a is in contact with the gate insulating film 410, and the first conductive layer 4 A first conductive layer 412a formed of the same material as 12b, and provided on the first conductive layer 412a The second conductive layer 414a, which is formed of the same material as the second conductive layer 414b, is formed by the product of the second conductive layer 414a. It has a layered structure. In addition, the gate electrode layer 416a is in contact with the gate insulating film 410. As the conductive layer 412a, a nitrogen-containing metal oxide, specifically, nitrogen-containing In-Ga- Zn-O film, nitrogen-containing In-Sn-O film, nitrogen-containing In-Ga-O film, nitrogen In-Zn-O films containing nitrogen, Sn-O films containing nitrogen, In-O films containing nitrogen, and metal nitrides. Using a film (such as indium nitride film, tin nitride film, tantalum nitride film, or titanium nitride film) These films are preferable. The voltage of these films is 5 eV (electron volts) or higher, preferably 5.5 eV (electron volts). (t) Having a work function of the above, when used as a gate electrode layer, the threshold voltage of the transistor This allows the pressure to be shifted to the positive side, realizing a so-called normally-off switching element. Cut.

[0068] In this embodiment, the first conductive layers 412a and 412b are tantalum nitride films or nitride films. A tungsten film is applied, and a tungsten film is applied as the second conductive layer 414a, 414b. Let's assume that.

[0069] In the semiconductor device of this embodiment, the gate electrode layer 416a of transistor 300 and Electrode layer connected to the source electrode layer 406a or drain electrode layer 406b of the lampistor 300 By manufacturing 416b and 416b in the same process, the number of masks required to manufacture semiconductor devices can be reduced. This is preferable because it can reduce the gate electric current. However, this embodiment is not limited to this, and the gate electric current is also preferable. The polar layer 416a and the electrode layer 416b may be fabricated by separate processes. For example, After forming the gate electrode layer 416a of the transistor 300, an insulating film covering the transistor 300 is formed. The insulating film is electrically connected to the source electrode layer 406a or the drain electrode layer 406b. An electrode layer 416b may be formed. In that case, the gate electrode layer 416a will have a single-layer structure. That's fine.

[0070] ≪Protective Insulating Film≫ The protective insulating film 418 provided on the transistor 300 is an oxide semiconductor film 408 and It has lower permeability to oxygen than the gate insulating film 410 (it has barrier properties against oxygen). ) An insulating film is provided. A protective insulating film having barrier properties against oxygen is provided in contact with the gate insulating film 410. By providing the film 418, the gate insulating film 410 and the oxide semiconductor film 408 in contact with it The desorption of oxygen can be suppressed. Oxide semiconductor film 408 and gate insulating film 410 By suppressing the desorption of oxygen from the film, the oxide semiconductor containing oxygen vacancies in the film is prevented. This can suppress oxygen abstraction from layer 404, resulting in the acidity of the channel-forming region. Elementary defects can be suppressed. As such a protective insulating layer, for example, aluminum oxide A film, silicon nitride film, or silicon nitride oxide film can be provided.

[0071] Furthermore, in oxide semiconductors, hydrogen, in addition to oxygen vacancies, serves as a carrier source. When hydrogen is present, donors are generated in levels close to the conduction band (shallow levels), resulting in lower resistance (n (It becomes molded.) Therefore, it is preferable to reduce the hydrogen concentration contained in the protective insulating film 418. Specifically, the hydrogen concentration contained in the protective insulating film 418 is 5 × 10⁻⁶. 19 cm -3 less than It is preferable to do so, 5 × 10 18 cm -3 It is more preferable to set it to less than [value].

[0072] Furthermore, aluminum oxide films possess not only barrier properties against oxygen but also barrier properties against hydrogen. It is a film that does so. Therefore, it is preferable to apply an aluminum oxide film as the protective insulating film 418. It is suitable.

[0073] <Insulating film> The insulating film 420 is provided stacked on the protective insulating film 418, thereby protecting the transistor 300 The dielectric breakdown voltage can be improved. The insulating film 420 is formed using an inorganic insulating material. This is possible, and the film thickness can be at least greater than the film thickness of the protective insulating film 418. preferable.

[0074] <Example of semiconductor device configuration 2> The semiconductor device of this embodiment is not limited to the configuration shown above. For example, Other configuration examples of the oxide semiconductor layer 404 applicable to semiconductor devices of the form are described below. explain.

[0075] <<Modifications of oxide semiconductor layers>> The oxide semiconductor layer 404 may be a stacked film of oxide semiconductor layers. For example, Figure 1(C) As shown, an oxide semiconductor layer 404a and an oxide semiconductor layer 404 in which a channel is formed A layered structure of b is also acceptable.

[0076] The oxide semiconductor layer 404b (middle layer) where the channel is formed is the oxide semiconductor layer 4 up to this point Refer to the description for 04. The oxide semiconductor layer 404b in which the channel is formed, and the substrate The oxide semiconductor layer 404a provided between the insulating film 402 and the oxide semiconductor layer 404b An oxide semiconductor layer containing at least one of the constituent metal elements as a constituent element Apply. By providing the oxide semiconductor layer 404a, the interface of the oxide semiconductor layer 404b The formation of lap levels is suppressed, and the oxide semiconductor layer 404a and the underlying insulating film 40 The influence of trap levels that may form at the interface with 2 affects the oxide semiconductor layer where the channel is formed. This prevents the process from extending to 404b. Details of the oxide semiconductor layer 404a This can be the same as the oxide semiconductor film 408 shown earlier.

[0077] Furthermore, in order to improve reliability, the oxide semiconductor layer 404a is thicker, and the oxide semiconductor film 408 It is preferable that it be thin. Specifically, the thickness of the oxide semiconductor layer 404a is 20 nm or more. Preferably 30 nm or more, more preferably 40 nm or more, and more preferably 60 nm or more. The thickness of the oxide semiconductor layer 404a is set to 20 nm or more, preferably 30 nm or more. Furthermore, by making the wavelength 4 more preferably 40 nm or more, and more preferably 60 nm or more, the underlying insulating film 4 A channel is formed in the oxide semiconductor layer 404 at the interface between 02 and the oxide semiconductor layer 404a. Up to b, 20 nm or more, preferably 30 nm or more, more preferably 40 nm or more, Preferably, the distance can be 60 nm or more. However, if the productivity of the semiconductor device decreases. Therefore, the thickness of the oxide semiconductor layer 404a is 200 nm or less, preferably 120 nm. Further, the wavelength is preferably 80 nm or less.

[0078] <Method for fabricating semiconductor devices> The method for fabricating the semiconductor device shown in Figures 1(A) and 1(B) can be described by referring to Figures 2 to 4. I will explain.

[0079] A base insulating film 402 is formed on the substrate 400 (see Figure 2(A)). The base insulating film 402 is Sputtering method, chemical vapor deposition (CVD) (Situation) method (Organometallic Chemical Deposition (MOCVD) method, Plasma Chemical Vapor Deposition (PEC) method) (Including VD method), Molecular Beam Epitaxy (MBE) itaxy) method, Atomic Layer Deposition (ALD) method n) Method or pulsed laser deposition (PLD) The film should be deposited using method n). To reduce plasma damage to the deposited film, For this purpose, it is preferable to use the MOCVD method or the ALD method.

[0080] After forming the underlayer insulating film 402, a CMP treatment is performed to flatten the surface of the underlayer insulating film 402. It is permissible to perform this. By performing CMP treatment, the average surface roughness (Ra) of the underlying insulating film 402 can be increased to 1n The number of m or less, preferably 0.3 nm or less, and more preferably 0.1 nm or less. Setting Ra below a certain value may increase the crystallinity of the oxide semiconductor layer 404. This was measured using an atomic force microscope (AFM). It is possible to determine this.

[0081] Next, by adding oxygen to the underlying insulating film 402, an insulating layer containing excess oxygen is formed. That's fine too. Oxygen can be added by plasma treatment or ion implantation. When adding by ion implantation, for example, the acceleration voltage is set to 2kV or more and 100kV or less. Dosage 5 × 10 14 ions / cm 2 The above 5 x 10 16 ions / cm 2 The following Yes.

[0082] Next, an oxide semiconductor film which will become the oxide semiconductor layer 404 is sputtered onto the underlying insulating film 402. Formed using the galvanic acid method, CVD method, MBE method, ALD method, or PLD method. Subsequently, the acid The ionized semiconductor film is processed into island-like structures by etching using photolithography, and then oxidized. A material semiconductor layer 404 is formed (see Figure 2(B)). The underlying insulating film is then etched. By simultaneously etching 402, the film thickness of the region exposed from the oxide semiconductor layer 404 is reduced. It is also permissible to do so. However, etching of the underlying insulating film 402 is not permitted on the surface of the substrate 400 (or the underlying The acid should be applied appropriately so as not to expose the film surface (which is located beneath the insulating film 402). By reducing the thickness of the underlying insulating film 402 in the region exposed from the semiconductor layer 404, The gate electrode layer formed thereon faces the lower end or its vicinity in the thickness direction of the oxide semiconductor layer. This makes it possible to apply a voltage to the entire oxide semiconductor layer 404.

[0083] Furthermore, the oxide semiconductor layer 404 consists of oxide semiconductor layer 404a and oxide semiconductor layer 404 When forming a laminated structure including b, the laminated films that form each layer are exposed to the atmosphere. It is preferable to form them continuously without interruption.

[0084] In order to reduce the inclusion of impurities and form a highly crystalline oxide semiconductor layer 404, The oxide semiconductor film that forms the conductive layer 404 is prepared at a substrate temperature of 100°C or higher, preferably 150°C or higher. Furthermore, the film is formed at a temperature of 200°C or higher. Also, the oxygen gas used as the film-forming gas The dew point of the gases, such as argon, is -40°C or lower, preferably -80°C or lower, more preferably - A gas purified to below 100°C is used. Furthermore, the impurity concentration is low, and the defect level density is low. A low oxygen deficiency (low oxygen loss) is referred to as high-purity genuine or substantially high-purity genuine.

[0085] A first heat treatment may be performed after the formation of the oxide semiconductor layer 404. The first heat treatment is At a temperature of 250°C to 650°C, preferably 300°C to 500°C, an inert gas The procedure can be carried out in an atmosphere containing 10 ppm or more of an oxidizing gas, or under reduced pressure. The atmosphere for the heat treatment in step 1 is an inert gas atmosphere, followed by replenishing the desorbed oxygen. For this purpose, the process may be carried out in an atmosphere containing 10 ppm or more of an oxidizing gas. The first heat treatment is performed as follows: The crystallinity of the oxide semiconductor layer 404 is enhanced, and impurities such as hydrogen and water are removed from the underlying insulating film 402. It can remove objects.

[0086] Next, a source electrode layer 406a and a drain electrode layer 406b are formed on the oxide semiconductor layer 404. A conductive film is formed. The conductive film is formed by sputtering, CVD, MBE, ALD, or The film can be deposited using the PLD method. After that, the conductive film is etched to break it apart, and then... - An electrode layer 406a and a drain electrode layer 406b are formed (see Figure 2(C)). When etching the conductive film, the edges of the source electrode layer 406a and the drain electrode layer 406b They may be rounded (have curved surfaces). Also, when etching the conductive film, the source electric Exposed underlayment insulation from electrode layer 406a, drain electrode layer 406b, and oxide semiconductor layer 404 The film 402 may be etched, reducing the thickness of the underlying insulating film 402 in that region.

[0087] Furthermore, the conductive films that form the source electrode layer 406a and the drain electrode layer 406b are acidic as residue. If the residue remains on the oxide semiconductor layer 404, the residue will remain in the oxide semiconductor layer 404 or at the interface. This may form impurity levels. Alternatively, the residue may cause the oxide semiconductor layer 404 Oxygen can be drawn out from the source electrode, potentially leading to an oxygen deficiency. After forming layer 406a and drain electrode layer 406b, the residue is removed from the surface of the oxide semiconductor layer 404. Removal treatment may be performed. Residue removal treatment may involve etching (for example, wet etching). This can be done by treatment using ) or by plasma treatment using oxygen or nitrous oxide. This can be done. The residue removal process removes the source electrode layer 406a and the drain electrode layer 40 The thickness of the oxide semiconductor layer 404 exposed between 6b layers decreases by approximately 1 nm to 3 nm. There is.

[0088] Next, an oxide semiconductor film 408 and The gate insulating film 410 is formed by stacking them (see Figure 2(D)). Note that the oxide semiconductor film 4 When 08 and the gate insulating film 410 are formed continuously without being exposed to the atmosphere, an oxide semiconductor film 4 08 Because it can prevent impurities such as hydrogen and moisture from adsorbing onto the surface, it is preferable. stomach.

[0089] The oxide semiconductor film 408 is produced by sputtering, CVD, MBE, ALD, or PL. It can be formed using the D method. Note that the oxide semiconductor film that becomes the oxide semiconductor layer 404 Similar to that, in order to reduce the incorporation of impurities and form an oxide semiconductor film 408 with high crystallinity , the substrate temperature is set to 100 °C or higher, preferably 150 °C or higher, and more preferably 200 °C or higher and film formation is carried out. Also, the oxygen gas and argon gas used as the film formation gas have a dew point of -40 °C or lower, preferably -80 °C or lower, and more preferably -100 °C or lower, and a highly purified gas is used.

[0090] The gate insulating film 410 can be formed by sputtering, MBE, CVD, pulsed laser deposition, ALD, etc. using the above materials. Note that the gate insulating film 4 10 is preferably formed by high-density plasma CVD using microwaves (for example, a frequency of 2.45 GHz) so that a dense film with high breakdown voltage can be obtained. .

[0091] ​​​​​​​​​​​​​​​​​​ Part 417 is formed (see Figure 3(B)).

[0093] Furthermore, by providing the organic coating film 429, the adhesion of the resist mask 430 is improved. This is possible. However, if the adhesion of the resist mask 430 is sufficient, the organic coating film 4 29 does not need to be provided. The organic coating film 429 is an anti-reflective film (BARC:Bottom Anti-reflective coating), for example, SWK-T7 (Tokyo Ohka) (Manufactured by) or adhesion enhancers, for example, AZ AD promoter (AZ ELECTRONIC M (ATERIALS products, etc.) can be used.

[0094] The light used for exposure to process the resist mask 430 is, for example, the i-line (wavelength 365 nm). Using light from the g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture thereof. The resist film is irradiated via a photomask to form the resist mask 430. This is possible. Alternatively, exposure may be performed using immersion lithography. Furthermore, extreme purple light may be used for exposure. External light (EUV: Extreme Ultra-violet) or X-rays may also be used. Alternatively, an electron beam can be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or Using an electron beam is preferable because it enables extremely fine processing. When exposure is performed by scanning a beam such as a luminaire, a photomask is not required. Furthermore, in order to miniaturize the semiconductor device, it is preferable to reduce the area of ​​the aperture 417. To miniaturize the aperture 417, a method suitable for fine wire processing, such as electron beam lithography, is required. The resist mask 430 can be processed using this method.

[0095] Next, the resist mask 430 is removed (see Fig. 3(C)). For the removal of the resist mask 430, it is preferable to apply an ashing process using oxygen plasma treatment or the like. By performing the ashing process of the resist mask 430 in a state where the oxide semiconductor film 408 is exposed from the opening 417, damage to the gate insulating film 410 by plasma can be prevented, and oxidation of the surface of the source electrode layer 406a located under the oxide semiconductor film 408 can be prevented. In addition, by applying an ashing process to the removal process of the resist mask 430, damage to the surface of the oxide semiconductor film 408 due to chemical solution treatment when peeling the resist mask (contamination by impurities, reduction in film thickness, oxygen deficiency, etc.) can be prevented. Note that an oxide film 431 may be formed on the surface of the conductive film 412 by the ashing process here. (contamination by impurities, reduction in film thickness, oxygen deficiency, etc.) can be prevented. Note that an oxide film 431 may be formed on the surface of the conductive film 412 by the ashing process here.

[0096] Next, the oxide semiconductor film 408 is etched using the conductive film 412 having the opening 417 as a mask. By the etching process here, an opening 415 that overlaps the opening 417 and reaches the source electrode layer 406a is formed in the oxide semiconductor film 408.

[0097] <� Also, by subjecting the conductive film 412 to reverse sputtering treatment, the oxide film 431 formed on the surface of the conductive film 412 is removed (see Fig. 3(D)). The reverse sputtering treatment is a method of forming plasma near the substrate using an RF power source on the substrate side in an atmosphere of an inert gas (for example, argon) without applying a voltage to the target side and modifying the surface. The reverse sputtering treatment also has the effect of planarizing the film formation surface of the conductive film 414 to be formed later.

[0098] Next, so that it comes into contact with the source electrode layer 406a exposed through openings 415 and 417 A conductive film 414 is formed on the conductive film 412 (see Figure 4(A)). The conductive film 414 is spa The film can be deposited using the tarting method, CVD method, MBE method, ALD method, or PLD method. In this embodiment, a tungsten film is formed as the conductive film 414.

[0099] Subsequently, conductive film 412 and conductive film 41 are etched using photolithography. 4 is processed to form a gate electrode layer 416 including a first conductive layer 412a and a second conductive layer 414a. a and an electrode layer 416b including a first conductive layer 412b and a second conductive layer 414b are formed. (See Figure 4(B)). The etching process here removes the transistor 300 and the transistor An electrode layer 416b is formed which is electrically connected to the source electrode layer 406a of the inverter 300. It can be done.

[0100] Next, a protective insulating film 418 is formed on the transistor 300 and the electrode layer 416b. Then, an insulating film 420 is formed on the protective insulating film 418 (see Figure 4(C)).

[0101] As described above, the protective insulating film 418 is an oxide semiconductor film 408 and a gate insulating film 4 Provide an insulating film that has lower oxygen permeability than 10 (has oxygen barrier properties). For example, the protective insulating film 418 may be an aluminum oxide film, a silicon nitride film, or an acid nitride film. A silicon dioxide film can be provided. Furthermore, the protective insulating film 418 has a low hydrogen concentration. Since it is preferable to reduce the amount of particles, it is preferable to deposit the film by sputtering.

[0102] For example, when forming an aluminum oxide film as the protective insulating film 418, An aluminum oxide film may be formed using a sputtering target containing [unclear], or [unclear] Using a titanium target, sputtering is performed in an oxygen atmosphere, or in an oxygen and noble gas atmosphere. An aluminum oxide film may be formed by performing a polishing method.

[0103] The insulating film 420 is provided stacked on the protective insulating film 418, thereby protecting the transistor 300 The dielectric breakdown voltage can be improved. The insulating film 420 is formed using an inorganic insulating material. This is possible, and it is preferable that the film thickness be at least greater than that of the protective insulating film 418. For example, an insulating film 420 can be oxidized and nitrided to a thickness of 300 nm by plasma CVD. A silicon film can be formed.

[0104] It is preferable to perform a heat treatment after forming the protective insulating film 418 and the insulating film 420. The temperature is preferably between 300°C and 450°C. This heat treatment will improve the substrate This makes it easier for oxygen to be released from the insulating film 402, reducing oxygen vacancies in the oxide semiconductor layer 404. It is possible.

[0105] Furthermore, the conductive films that will form the source electrode layer 406a and the drain electrode layer 406b are sputtered. When a film is deposited by this method, plasma damage occurs to the surface of the oxide semiconductor layer 404 during film deposition. This can occur, and an oxygen deficiency may form. Furthermore, hydrogen can enter the oxygen deficiency that has formed. This may occur. Therefore, the conductive films that form the source electrode layer 406a and the drain electrode layer 406b After formation, the entire surface of the oxide semiconductor layer 404 in contact with the conductive film may be converted to n-type. Therefore, An oxide semiconductor film 408 is formed in contact with a portion of the n-type oxide semiconductor layer 404, and After forming a protective insulating film 418 on the upper layer of the oxide semiconductor film 408 to suppress oxygen desorption, Therefore, it is effective to perform a heat treatment that supplies oxygen. By performing this heat treatment, the oxide semiconductor layer 40 By supplying oxygen to 4, even if the region where the channel is formed becomes n-type, It becomes possible to convert it to an i-type.

[0106] Furthermore, by appropriately adjusting the temperature and time of the heat treatment here, the source electrode layer 406a and In the region in contact with the drain electrode layer 406b, an n-type region remains due to oxygen deficiency. Furthermore, i-type conversion can be achieved in the region where the channel is formed. In this case, source It includes an n-type region that functions as a region or drain region, and is intrinsically or substantially An oxide semiconductor layer 404 having an intrinsically modified channel region can be formed.

[0107] As described above, the semiconductor device of this embodiment can be manufactured.

[0108] <Example 3 of semiconductor device configuration> Figure 5 shows an example of the configuration of a semiconductor device including transistor 360. Figure 5 shows an oxide semiconductor film 4 08 and the gate insulating film 410 mask the gate electrode layer 416a and the electrode layer 416b In that it is manufactured in a self-aligning manner, it has a different configuration from the semiconductor device described earlier. This is a semiconductor device. In the configuration shown in Figure 5, the oxide semiconductor film 408 and the gate insulating film 4 Since 10 is processed in a self-aligning manner, the mask can be increased from the semiconductor device fabrication method shown earlier. The configuration shown in Figure 5 can be formed without causing any problems. By using the configuration shown in Figure 5, The sides of the oxide semiconductor film 408 and the gate insulating film 410 can be covered with a protective insulating film 418. Because it is capable of suppressing the detachment of oxygen from the sides and / or the incorporation of impurities such as hydrogen. Yes, it is possible. On the other hand, by using the configuration shown in Figures 1(A) and 1(B), the protective insulating film 418 Because the flatness of the film-forming surface can be improved, protective insulating film 418 and protective insulating film 4 This makes it possible to improve the coverage of the insulating film 420 provided on 18.

[0109] As described above, the configuration of this embodiment allows the electrode layers provided above and below the oxide semiconductor layer to , a semiconductor device that can be stably connected at an opening provided in the oxide semiconductor layer It becomes possible to provide a suitable location. Furthermore, the semiconductor device having the configuration of this embodiment has a shape This is a highly reliable semiconductor device with suppressed defects and connection problems.

[0110] The configurations and methods described in this embodiment are compatible with the configurations and methods described in other embodiments. They can be used in any combination.

[0111] (Embodiment 2) The following describes an acid applicable to the oxide semiconductor layer 404 included in a semiconductor device according to one aspect of the present invention. The structure of the ionized semiconductor layer will be explained.

[0112] Oxide semiconductor layers are broadly classified into non-single-crystal oxide semiconductor layers and single-crystal oxide semiconductor layers. A single-crystal oxide semiconductor layer is a CAAC-OS (C Axis Aligned Crystals Polycrystalline oxide semiconductor layer This refers to microcrystalline oxide semiconductor layers, amorphous oxide semiconductor layers, and so on.

[0113] First, let's explain the CAAC-OS layer.

[0114] The CAAC-OS layer is one of the oxide semiconductor layers having multiple crystalline regions, and most of the bonds The crystal portion is small enough to fit within a cube with sides less than 100 nm. Therefore, CAAC -The crystalline portion contained in the OS layer is a cube with sides of less than 10 nm, less than 5 nm, or less than 3 nm. This also includes cases where the item fits inside.

[0115] CAAC-OS layer is examined using a transmission electron microscope (TEM). When observed with a microscope, clear boundaries between crystalline regions, i.e., bonds, can be seen. It is difficult to identify grain boundaries (also called grain boundaries). Therefore, C The AAC-OS layer is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0116] The CAAC-OS layer was observed by TEM from a direction roughly parallel to the sample surface (cross-sectional TEM observation). ) This confirms that metal atoms are arranged in layers in the crystalline region. Each layer reflects the surface (also called the formed surface) or the top surface that forms the CAAC-OS layer. It has this shape and is arranged parallel to the surface or top surface of the CAAC-OS layer.

[0117] On the other hand, the CAAC-OS layer was observed by TEM from a direction roughly perpendicular to the sample surface (planar TEM). (M observation) reveals that in the crystalline region, metal atoms are arranged in a triangular or hexagonal shape. This can be confirmed. However, no regularity is observed in the arrangement of metal atoms between different crystalline regions. .

[0118] Cross-sectional TEM observation and planar TEM observation revealed that the crystalline portion of the CAAC-OS layer exhibits orientation. It becomes clear that...

[0119] X-ray diffraction (XRD) was applied to the CAAC-OS layer. When structural analysis is performed using this method, for example, a CAAC-OS layer having InGaZnO4 crystals is found. In the out-of-plane analysis, the diffraction angle (2θ) shows a peak near 31°. This peak may appear. This peak is attributed to the (009) plane of the InGaZnO4 crystal. Therefore, the crystals of the CAAC-OS layer have c-axis orientation, and the c-axis is roughly aligned with the surface to be formed or the upper surface. It can be confirmed that it is facing vertically.

[0120] On the other hand, in-pl X-rays are incident on the CAAC-OS layer from a direction approximately perpendicular to the c-axis. In analysis using the ANE method, a peak may appear when 2θ is around 56°. This peak is It is attributed to the (110) plane of the InGaZnO4 crystal. Single crystal oxidation of InGaZnO4 For a solid semiconductor layer, fix 2θ to around 56°, and use the normal vector of the sample surface as the axis (φ axis). When the sample is rotated while the analysis (φ scan) is performed, the crystal plane equivalent to the (110) plane is found. Six attributed peaks are observed. In contrast, in the case of the CAAC-OS layer, 2θ is set to 5 Even when fixed at approximately 6° and scanned using the φ scan function, no clear peak appears.

[0121] From the above, it can be concluded that in the CAAC-OS layer, the orientation of the a-axis and b-axis is irregular between different crystalline regions. However, the c-axis orientation is important, and the c-axis is parallel to the normal vector of the surface to be formed or the upper surface. It can be seen that it is facing in the direction. Therefore, it is arranged in layers as confirmed by the aforementioned cross-sectional TEM observation. Each layer of arranged metal atoms is a plane parallel to the ab-plane of the crystal.

[0122] The crystalline portion is formed when the CAAC-OS layer is deposited, or when crystallization treatment such as heat treatment is performed. It is formed when this occurs. As described above, the c-axis of the crystal is on the surface or above where the CAAC-OS layer is formed. It is oriented in a direction parallel to the surface normal vector. Therefore, for example, the shape of the CAAC-OS layer When the shape is altered by etching or other means, the c-axis of the crystal becomes the surface on which the CAAC-OS layer is formed. Alternatively, it may not be parallel to the normal vector of the top surface.

[0123] Furthermore, the degree of crystallinity within the CAAC-OS layer does not need to be uniform. For example, the CAAC-OS layer When the crystalline portion is formed by crystal growth from near the upper surface of the CAAC-OS layer, the upper surface The nearby region may have a higher degree of crystallinity than the region near the surface being formed. Also, CAA When impurities are added to the C-OS layer, the degree of crystallinity in the region where the impurities are added changes, and some areas Regions with different degrees of crystallinity may also be formed.

[0124] Furthermore, the out-of-plane method for CAAC-OS layers containing InGaZnO4 crystals. Analysis revealed that in addition to a peak near 2θ = 31°, a peak also appeared near 2θ = 36°. In some cases, the peak near 36° 2θ indicates c-axis orientation in a portion of the CAAC-OS layer. This indicates that it contains crystals that do not have [the specified property]. The CAAC-OS layer has 2θ near 31°. It is preferable that a peak is observed, and that no peak is observed near 36° for 2θ.

[0125] The CAAC-OS layer is an oxide semiconductor layer with a low impurity concentration. The impurities are hydrogen, carbon, These are elements other than the main components of oxide semiconductor layers, such as silicon and transition metal elements. In particular, silicon Elements such as ions, which have a stronger bonding force with oxygen than the metal elements that make up the oxide semiconductor layer, By removing oxygen from the material semiconductor layer, the atomic arrangement of the oxide semiconductor layer is disrupted, reducing its crystallinity. This is a contributing factor. Also, heavy metals such as iron and nickel, argon, and carbon dioxide have atomic radii. Because of its large molecular radius, when it is contained within the oxide semiconductor layer, it contributes to the formation of the oxide semiconductor layer. This disrupts the arrangement of particles and reduces crystallinity. Note that these are impurities contained in the oxide semiconductor layer. These can sometimes act as carrier traps or carrier sources.

[0126] Furthermore, the CAAC-OS layer is an oxide semiconductor layer with a low defect level density. For example, oxide Oxygen vacancies in semiconductor layers can act as carrier traps or capture hydrogen. It can be a source of carrier activity.

[0127] A low impurity concentration and low defect level density (few oxygen vacancies) are referred to as high-purity intrinsic or actual. This is qualitatively referred to as high-purity intrinsic. An oxide semiconductor layer that is high-purity intrinsic or substantially high-purity intrinsic is Because there are few carrier sources, the carrier density can be kept low. Therefore, Transistors using oxide semiconductor layers exhibit electrical characteristics where the threshold voltage is negative (no Also called Marion.) It rarely becomes high-purity genuine or substantially high-purity genuine. The oxide semiconductor layer has few carrier traps. Therefore, the oxide semiconductor layer The transistors used exhibit minimal fluctuations in electrical characteristics, resulting in highly reliable transistors. Oh, the time it takes for the charge trapped in the carrier trap of the oxide semiconductor layer to be released. It can last for a long time and behave as if it were a fixed charge. Therefore, when the impurity concentration is high, Transistors using oxide semiconductor layers with a high defect level density exhibit unstable electrical properties. There is a match.

[0128] Furthermore, transistors using the CAAC-OS layer exhibit electrical characteristics under irradiation with visible light and ultraviolet light. The fluctuations are small.

[0129] Next, we will explain the microcrystalline oxide semiconductor layer.

[0130] In microcrystalline oxide semiconductor layers, it is difficult to clearly identify the crystalline structure using TEM observation. In some cases, the crystalline portion contained in the microcrystalline oxide semiconductor layer is between 1 nm and 100 nm. Or they are often between 1 nm and 10 nm in size. In particular, between 1 nm and 10 nm , or nanocrystals (nc: nanocrystal) which are microcrystalline particles between 1 nm and 3 nm in size. An oxide semiconductor layer having nc-OS (nanocrystalline oxide It is called the Semiconductor layer. Also, the nc-OS layer is, for example, TEM In some observational images, it can be difficult to clearly identify grain boundaries.

[0131] The nc-OS layer is a very small region (for example, a region between 1 nm and 10 nm, especially one larger than 1 nm). The atomic arrangement has periodicity in the region of 3 nm or less. Also, the nc-OS layer is different No regularity in crystal orientation is observed between the crystalline regions. Therefore, no overall orientation is observed. Therefore, the nc-OS layer is indistinguishable from the amorphous oxide semiconductor layer depending on the analysis method. There are cases where this occurs. For example, XRD using X-rays with a larger diameter than the crystalline region on an nc-OS layer. When structural analysis is performed using the apparatus, the out-of-plane method analyzes the crystal planes. The peak shown is not detected. Also, the nc-OS layer has a larger probe diameter than the crystalline portion (e.g. For example, electron diffraction (also called limited-field electron diffraction) is performed using an electron beam with a wavelength of 50 nm or more. Then, a diffraction pattern resembling a halo pattern is observed. On the other hand, for the nc-OS layer, Probe diameter close to or smaller than the size of the crystal (for example, between 1 nm and 30 nm) When electron diffraction using an electron beam (also called nanobeam electron diffraction) is performed, the spot is It is observed. Furthermore, when nanobeam electron diffraction is performed on the nc-OS layer, it traces a circular pattern. In some cases, a ring-shaped region of high brightness may be observed. Also, nano- When beam electron diffraction is performed, multiple spots may be observed within a ring-shaped region. .

[0132] The nc-OS layer is an oxide semiconductor layer with higher orderliness than an amorphous oxide semiconductor layer. Therefore, the nc-OS layer has a lower defect level density than the amorphous oxide semiconductor layer. However, The nc-OS layer shows no regularity in crystal orientation between different crystalline regions. Therefore, nc-O The S layer has a higher defect level density compared to the CAAC-OS layer.

[0133] The oxide semiconductor layer can be, for example, an amorphous oxide semiconductor layer, a microcrystalline oxide semiconductor layer, or CA. The AC-OS layer may have two or more types. Furthermore, it may be provided in contact with the oxide semiconductor layer 404. The oxide semiconductor film 408 that is applied also has a structure similar to that of the oxide semiconductor layer described above. can.

[0134] The configurations and methods described in this embodiment are compatible with the configurations and methods described in other embodiments. They can be used in any combination.

[0135] (Embodiment 3) In this embodiment, as an example of the semiconductor device shown in Embodiment 1, a state in which power is not supplied is described. Moreover, a semiconductor device (semiconductor) that can retain its stored contents and has no limit on the number of write cycles. The memory device will be explained using diagrams.

[0136] Figure 6 shows an example of the configuration of a semiconductor device. Figure 6(A) shows a plan view of the semiconductor device, and Figure 6( Figure B) shows a cross-sectional view of X1-Y1 in Figure 6(A), and Figure 6(C) shows a circuit diagram of the semiconductor device. They will each be shown.

[0137] The semiconductor device of this embodiment shown in Figures 6(A) and 6(B) includes a transistor 300, It has a transistor 300 adjacent to a transistor 310 and a capacitive element 320, Transistor 300 has the same configuration as transistor 300 shown in Embodiment 1. The transistor 310 was manufactured using the same process as the transistor 300, and the base film 402 was used to create the base Island-shaped oxide semiconductor layers 405 provided on the plate 400, and the oxide semiconductor layer 405 and electrical The source electrode layer 406c and drain electrode layer 406d are connected to the source electrode layer 406c and the oxide semiconductor film 408 on the drain electrode layer 406d, and the oxide semiconductor film 408 on the oxide semiconductor film 408 A gate insulating film 410 and an island-shaped oxide semiconductor layer 405 are superimposed via the gate insulating film 410. It has a gate electrode layer 416d and a first layer which is stacked in order. It has a conductive layer 412d and a second conductive layer 414d. In the transistor 310, the oxide semiconductor film 408 and the gate insulating film 410 are common to both. .

[0138] The gate electrode layer 416d of transistor 310 is the source electrode layer 40 of transistor 300 It has a region in contact with 6a and corresponds to the electrode layer 416b of Embodiment 1. More specifically, The first conductive layer 412d and gate insulating film 410 of the gate electrode layer 416d are transistors The oxide semiconductor film 40 has an opening 417 at a position overlapping with the source electrode layer 406a 300. 8 has an opening 415 that overlaps with the opening 417. And opening 417 and opening 41 The second lead of the gate electrode layer 416d is in contact with the source electrode layer 406a exposed from 5. The electrode layer 414d is formed. This forms the source electrode layer 40 of the transistor 300. 6a and the gate electrode layer 416d of transistor 310 are electrically connected.

[0139] Furthermore, the source electrode layer 406a of transistor 300 is one electrode of capacitive element 320. It also functions. The other electrode 416c of the capacitive element 320 is connected to the first conductive layer 412c and the second It has a laminated structure of conductive layer 414c, and the gate electrode layer 416a of the transistor 300 and It is fabricated using the same process as the gate electrode layer 416d of the transistor 310. Note that capacitance is not required. In some cases, a configuration without the capacitive element 320 is also possible. Alternatively, it may be provided above transistor 300.

[0140] The transistor 300 shown in Figure 6(A) is a transistor that uses an oxide semiconductor as the channel formation region. It is a transistor. Transistors that use oxide semiconductors in the channel formation region are extremely small. A low off-current characteristic can be achieved. Transistor 300 has a low off-current, so By using this in semiconductor memory devices, it is possible to retain the contents of the memory for a long period of time. In other words, it does not require a refresh operation, or the frequency of refresh operations is extremely low. This makes it possible to use fewer semiconductor memory devices, thus significantly reducing power consumption. Yes, it is possible. Furthermore, the oxide semiconductor layer contained in transistor 300 is made of highly purified material. It is desirable to have this. Using highly purified oxide semiconductors provides better off-stop characteristics. A transistor 300 can be obtained.

[0141] Figure 6(C) shows an example of a circuit configuration corresponding to Figures 6(A) and 6(B).

[0142] In Figure 6(C), the first wiring (1st Line) and the source power of transistor 310 The polar layer is electrically connected to the second line and transistor 310. The drain electrode layer is electrically connected. Also, the third wiring (3rd Line) The source electrode layer or drain electrode layer of transistor 300 is electrically connected to it. The fourth wire (4th Line) and the gate electrode layer of transistor 300 are electrically connected. They are precisely connected. And the gate electrode layer of transistor 310 and transistor 30 The other of the source electrode layer or drain electrode layer of 0 is electrically connected to one of the electrodes of the capacitive element 320. It is connected to the fifth line and the other electrode of the capacitive element 320, which is electrically Connected.

[0143] In the semiconductor device shown in Figure 6(C), the potential of the gate electrode layer of transistor 310 can be maintained. By taking advantage of these characteristics, it is possible to write, store, and read information as follows: .

[0144] This section will explain how to write and retain information. First, the potential of the fourth wire is set to the transistor. The potential is set so that transistor 300 is ON, thereby turning on transistor 300. The potential of the third wiring is supplied to the gate electrode layer of transistor 310 and the capacitive element 320. It is obtained. That is, a predetermined charge is given to the gate electrode layer of transistor 310. (Writing). Here, assume that either of two different potential level charges (hereinafter referred to as Low level charge , High level charge) is given. Then, the potential of the fourth wiring is set to a potential at which the transistor 300 is in the off state, and the transistor 300 is turned off so that the charge applied to the gate electrode layer of the transistor 310 is retained (held).

[0145] Since the off-current of the transistor 300 is extremely small, the charge in the gate electrode layer of the transistor 310 is retained for a long time.

[0146] Next, information reading will be described. When a predetermined potential (constant potential) is applied to the first wiring and an appropriate potential (read potential) is applied to the fifth wiring, the second wiring takes different potentials according to the amount of charge retained in the gate electrode layer of the transistor 310. Generally, when the transistor 310 is an n-channel type, the apparent threshold voltage V when a High level charge is applied to the gate electrode layer of the transistor 310 is lower than the apparent threshold voltage V th_H when a Low level charge is applied to the gate electrode layer of the transistor 310. Here, the apparent threshold voltage means the potential of the fifth wiring required to turn the transistor 310 into the "on th_L state". Therefore, by setting the potential of the fifth wiring to a potential V0 between V th_H and V th_L , the charge applied to the gate electrode layer of the transistor 310 can be discriminated. For example, in writing, when a High level th_H charge was applied, if the potential of the fifth wiring becomes V0 (> V th_L ), then ​​​Transistor 310 turns "on" when a low-level charge is applied. The potential of the fifth wire is V0( <V th_L Even if this happens, transistor 310 will be "off" The state remains the same. Therefore, by looking at the potential of the second wire, the information that is being held can be determined. It can be read.

[0147] When memory cells are arranged in an array, only the information of the desired memory cell is read. It is necessary to be able to output the information. In memory cells that do not read information, the state of the gate electrode layer Regardless of the state, the potential at which transistor 310 is in the "off state" is, that is, V th_ H A smaller potential can be applied to the fifth wire. Alternatively, regardless of the state of the gate electrode layer, The potential at which transistor 310 is in the "on state" is, that is, V th_L bigger We just need to apply potential to the fifth wire.

[0148] In the semiconductor device shown in this embodiment, an oxide semiconductor is used in the channel formation region for off-current By applying extremely small transistors, it is possible to retain memory contents for extremely long periods of time. This is possible. In other words, the refresh operation becomes unnecessary, or the refresh operation is eliminated. Because the frequency of operation can be made extremely low, power consumption can be significantly reduced. Furthermore, in the absence of power supply (however, it is desirable that the potential be fixed), However, it is possible to retain the memory contents over a long period of time. Here, transistor 3 By making 00 a normally-off transistor, in the absence of power supply, the transistor... The gate (gate electrode layer 416a) of the inverter 300 is configured to receive the ground potential. This is possible. In this way, when there is no power supply, transistor 300 is in the OFF state. It can maintain its state and retain its memory contents.

[0149] Furthermore, the semiconductor device shown in this embodiment does not require a high voltage for writing information, and There are no issues with degradation of the child. For example, unlike conventional non-volatile memory, it does not use floating gates. Because there is no need to inject electrons into it or extract electrons from the floating gate, Problems such as degradation of the gate insulating film do not occur at all. In other words, the semiconductor according to the disclosed invention. The device does not have the limitations on the number of rewrite cycles that are a problem with conventional non-volatile memory, and Reliability improves dramatically. Furthermore, the on and off states of the transistors allow information to be transmitted. Because writing is performed, high-speed operation can be easily achieved.

[0150] Furthermore, the semiconductor device shown in this embodiment is manufactured using the manufacturing method shown in Embodiment 1, and adjacent to By improving the connection of electrodes in the transistor, a miniaturized structure is achieved, and reliability is improved. It is possible to create high-performance semiconductor devices.

[0151] As described above, a semiconductor device that achieves miniaturization and high integration, and is given high electrical characteristics. The invention provides a method for setting up and manufacturing such a semiconductor device.

[0152] The configurations and methods described in this embodiment are compatible with the configurations and methods described in other embodiments. They can be used in any combination.

[0153] (Embodiment 4) This embodiment includes the transistor or semiconductor memory device described in the previous embodiment. The RFIC tag will be explained with reference to Figure 7.

[0154] The RFIC tag in this embodiment has a memory circuit inside, and the memory circuit stores the necessary information. It stores information and exchanges it with the outside world using contactless means, such as wireless communication. Due to these characteristics, RFIC tags can identify items by reading individual information about those items. It can be used in individual authentication systems and the like. This requires extremely high reliability.

[0155] The configuration of an RFIC tag will be explained using Figure 7. Figure 7 shows an example of an RFIC tag configuration. This is a block diagram.

[0156] As shown in Figure 7, the RFIC tag 800 is connected to the communicator 801 (interrogator, reader / writer, etc.) An antenna that receives a radio signal 803 transmitted from antenna 802 connected to (also known as) It has 804. The RFIC tag 800 also has a rectifier circuit 805, a constant voltage circuit 806, and demodulation It has a circuit 807, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. It is present. Furthermore, sufficient reverse current is supplied to the rectifying transistor included in the demodulation circuit 807. A configuration using a material capable of suppressing this, such as an oxide semiconductor, may also be used. This suppresses the decrease in rectification due to reverse current and prevents the output of the demodulation circuit from saturating. This prevents the output of the demodulation circuit from becoming more linear with respect to the input of the demodulation circuit. This is possible. The data transmission method involves placing a pair of coils opposite each other and using mutual induction. Electromagnetic coupling methods for communication, electromagnetic induction methods for communication using induced electromagnetic fields, and communication using radio waves. They can be broadly classified into three types of radio wave transmission methods. The RFIC tag 800 shown in this embodiment is one of them. It can also be used in the offset method.

[0157] Next, the configuration of each circuit will be explained. Antenna 804 is connected to the communication device 801. This is for transmitting and receiving wireless signals 803 with Tenor 802. Also, a rectifier circuit 8 05 rectifies the input AC signal generated by receiving a wireless signal with antenna 804. For example, half-wave voltage doubling rectification is performed, and the rectified signal is smoothed by a capacitive element provided in the subsequent stage. This is a circuit for generating input potential by converting it. Furthermore, the input side of the rectifier circuit 805 is also A limiter circuit may be provided on the output side. A limiter circuit is a circuit that limits the amplitude of the input AC signal. When the internally generated voltage is large, do not input power exceeding a certain level to the subsequent circuit. This is a circuit for controlling sea urchins.

[0158] The constant voltage circuit 806 generates a stable power supply voltage from the input potential and supplies it to each circuit. This is a circuit. Note that the constant voltage circuit 806 may also have an internal reset signal generation circuit. The reset signal generation circuit utilizes the stable rise of the power supply voltage to generate the logic circuit 80. This is a circuit for generating a reset signal for number 9.

[0159] The demodulation circuit 807 demodulates the input AC signal by detecting its envelope and generates a demodulated signal. This is a circuit for that purpose. Furthermore, the modulation circuit 808 responds to the data output from the antenna 804. This is a circuit for performing modulation.

[0160] Logic circuit 809 is a circuit for analyzing and processing demodulated signals. Memory circuit 810 is This is a circuit that holds the input information, and includes a row decoder, column decoder, memory area, etc. It has. Furthermore, ROM811 stores unique numbers (IDs), etc., and outputs them according to the processing. This is a circuit for that purpose.

[0161] Furthermore, the circuits described above can be selected or omitted as needed.

[0162] Here, the semiconductor memory device described in the previous embodiment can be used in the memory circuit 810. A semiconductor memory device according to one aspect of the present invention can retain information even when the power supply is cut off. Therefore, it can be suitably used in RFIC tags. Furthermore, one embodiment of the present invention is a semiconductor The storage device requires significantly less power (voltage) to write data compared to conventional non-volatile memory. Because it is extremely small, it should not cause a difference in the maximum communication distance between data reading and writing. This is also possible. Furthermore, insufficient power during data writing can cause malfunctions or incorrect writing. It can suppress the urge to squirm.

[0163] Furthermore, a semiconductor memory device according to one aspect of the present invention can be used as a non-volatile memory. Therefore, it can also be applied to ROM811. In that case, the manufacturer will be responsible for ROM811 A separate command is provided for writing data to it, preventing users from freely overwriting it. It is preferable to leave it as is. The producer writes a unique number on the product before shipping it. Therefore, instead of assigning a unique number to every RFIC tag produced, the tags are shipped... This makes it possible to assign a unique number only to good products, and prevents discontinuity in the unique numbers of products after shipment. This eliminates the need for post-shipment product management, making customer support easier.

[0164] The configurations and methods described in this embodiment are compatible with the configurations and methods described in other embodiments. They can be used in any combination.

[0165] (Embodiment 5) In this embodiment, at least the transistors described in the embodiments can be used. Next, we will describe a CPU including the semiconductor memory device described in the previous embodiment.

[0166] Figure 8 shows an example of a CPU that uses at least some of the transistors described in the previous embodiment. This is a block diagram showing the structure.

[0167] The CPU shown in Figure 8 is an ALU1191 (ALU: Arithmetic) mounted on board 1190. c logic unit, arithmetic circuit, ALU controller 1192, instruction Decoder 1193, interrupt controller 1194, timing controller 1 195, Register 1196, Register Controller 1197, Bus Interface 11 98 (Bus I / F), rewritable ROM1199, and ROM interface It has a ROM I / F (S1189). The substrate 1190 is a semiconductor substrate, SOI substrate , a glass substrate is used. ROM1199 and ROM interface1189 are, It may also be placed on a separate chip. Of course, the CPU shown in Figure 8 is a simplified representation of its configuration. This is just one example; actual CPUs have a wide variety of configurations depending on their application. For example, A configuration including the CPU or arithmetic circuit shown in Figure 8 is considered one core, and a configuration including multiple such cores is also considered. The configuration may also be such that each core operates in parallel. The number of bits that can be handled by a data bus is, for example, 8 bits, 16 bits, 32 bits, or 64 bits. This can be done as follows.

[0168] Instructions input to the CPU via the bus interface 1198 are instructions The signal is input to decoder 1193, decoded, and then processed by ALU controller 1192, interface Raptor controller 1194, register controller 1197, timing controller It is entered into 1195.

[0169] ALU controller 1192, interrupt controller 1194, register controller R1197 and timing controller 1195 control various commands based on the decoded instructions. To perform the operation. Specifically, the ALU controller 1192 controls the operation of the ALU 1191. It generates a signal for that purpose. Also, the interrupt controller 1194 is the CPU programmer. During execution, interrupt requests from external input / output devices and peripheral circuits are prioritized and masked. The state is judged and processed. The register controller 1197 adds register 1196 It generates a response and reads or writes to register 1196 depending on the CPU state.

[0170] Furthermore, the timing controller 1195 is connected to the ALU 1191 and the ALU controller 119 2. Instruction decoder 1193, interrupt controller 1194, and It generates signals to control the timing of the operation of the register controller 1197. For example, The timing controller 1195 uses the reference clock signal CLK1 to determine the internal clock signal It is equipped with an internal clock generation unit that generates CLK2, and the internal clock signal CLK2 is the above It supplies power to various circuits.

[0171] In the CPU shown in Figure 8, a memory cell is located in register 1196. Register 1 The transistors shown in the previous embodiment can be used as the 196 memory cells. .

[0172] In the CPU shown in Figure 8, the register controller 1197 receives the registers from the ALU 1191. Following the instructions, select the hold operation in register 1196. That is, register 119 In the memory cell of 6, data is retained by a flip-flop, or the capacity element Choose whether to retain data using a child. If data retention using a flip-flop is selected... If selected, power voltage is supplied to the memory cell in register 1196. If data retention in the capacitive element is selected, then data rewriting to the capacitive element is This can be done to stop the supply of power voltage to the memory cell in register 1196.

[0173] Figure 9 shows an example of a circuit diagram of a memory element that can be used as register 1196. The memory element 1200 has a circuit 1201 in which the stored data volatilizes when the power is cut off, and when the power is cut off the stored data Circuit 1202 that prevents data from volatilizing, switch 1203, switch 1204, and logic element Circuit 1 includes 1206, a capacitive element 1207, and a circuit 1220 having a selection function. 202 consists of the capacitive element 1208, transistor 1209, and transistor 1210. It has. Furthermore, the memory element 1200 may include diodes, resistors, and inductors as needed. It may also have other elements such as the following.

[0174] Here, the circuit 1202 can use the semiconductor memory device described in the previous embodiment. When the power supply voltage to the memory element 1200 is stopped, the transistor of circuit 1202 The gate of transistor 1209 is at ground potential (0V), or at the potential that turns off transistor 1209. The configuration is designed to continuously receive input. For example, the gate of transistor 1209 is connected via a load such as a resistor. The configuration is such that it is grounded.

[0175] Switch 1203 uses a single-conductivity (e.g., n-channel) transistor 1213. The switch 1204 is configured to have a conductivity type opposite to that of a single-conductivity type (for example, a p-channel type). An example using transistor 1214 is shown. Here, the first terminal of switch 1203 The child corresponds to one of the source and drain of transistor 1213, and the second of switch 1203. The terminals correspond to the source and drain of transistor 1213, and switch 1203 is The control signal RD input to the gate of transistor 1213 controls the first terminal and the second terminal. Continuity or non-conductivity between terminals (i.e., the on or off state of transistor 1213) ) is selected. The first terminal of switch 1204 is the source and drain of transistor 1214. Corresponding to one side of the input, the second terminal of switch 1204 is the source of transistor 1214. Corresponding to the other side of the drain, switch 1204 is input to the gate of transistor 1214. The control signal RD determines whether the first terminal and the second terminal are conductive or non-conductive (i.e., The ON or OFF state of the Rangista 1214 is selected.

[0176] One of the sources and drains of transistor 1209 is connected to the pair of electrodes of capacitive element 1208. One side of this is electrically connected to the gate of transistor 1210. Here, the connection part Let the minute be node M2. One of the sources and drains of transistor 1210 is at a low power supply potential. It is electrically connected to a wire (e.g., a GND wire) that can supply power, and the other is a switch. The first terminal of 1203 (one of the source and drain of transistor 1213) is electrically connected. The second terminal of switch 1203 (source and drain of transistor 1213) On the other hand, the first terminal of switch 1204 (the source and drain of transistor 1214) is the first terminal of switch 1204. It is electrically connected to the second terminal of switch 1204 (the terminal of transistor 1214). The other end of the drain is electrically connected to wiring that can supply the power potential VDD. The second terminal of switch 1203 (the other terminal of the source and drain of transistor 1213) ) and the first terminal of switch 1204 (one of the source and drain of transistor 1214) ) and the input terminal of logic element 1206 and one of the pair of electrodes of capacitive element 1207, These are electrically connected. Here, the connection point is called node M1. A pair of capacitive elements 1207. The other electrode can be configured to receive a constant potential. For example, a low potential The system can be configured to receive either a source potential (such as GND) or a high power supply potential (such as VDD) as input. The other of the pair of electrodes of the capacitive element 1207 is a distribution capable of supplying a low power supply potential. It is electrically connected to a wire (for example, a GND wire). This configuration allows for a constant potential to be input. For example, a low power supply potential (such as GND). ) or a high power supply potential (VDD, etc.) can be input. Capacitive element 120 The other of the pair of electrodes (8) is connected to a wire capable of supplying a low power potential (e.g., GND). It is electrically connected to a wire.

[0177] Capacitive elements 1207 and 1208 are used to absorb parasitic capacitance from transistors and wiring. It was possible to omit it by actively using it.

[0178] The control signal WE is input to the first gate (first gate electrode) of transistor 1209. Switches 1203 and 1204 use a different control signal RD than control signal WE. The conduction or non-conduction state between the first terminal and the second terminal is selected by this, and one of the terminals When there is continuity between the first and second terminals of one switch, the first terminal of the other switch and the second terminal The area between terminals 2 becomes non-conductive.

[0179] The source and drain of transistor 1209 are connected to the data held in circuit 1201. A signal corresponding to this is input. In Figure 9, the signal output from circuit 1201 is a transient An example is shown where the source and drain of switch 1209 are input to the other. The signal output from terminal 2 (the other of the source and drain of transistor 1213) is, The logic value of element 1206 is inverted, becoming an inverted signal, and then through circuit 1220 This is input to circuit 1201.

[0180] Note that in Figure 9, the second terminal of switch 1203 (source and drain of transistor 1213) The signal output from the other side of the input is sent through logic element 1206 and circuit 1220 to the circuit An example of inputting to 1201 is shown, but it is not limited to this. The second terminal of switch 1203 ( The signals output from the source and drain (the other side) of transistor 1213 invert the logic value. It may be input to circuit 1201 without being forced to do so. For example, input into circuit 1201 If there is a node that holds a signal inverted from the logical value of the signal input from the power terminal, , the second terminal of switch 1203 (the other of the source and drain of transistor 1213) The signal output from can be input to the node in question.

[0181] Furthermore, in Figure 9, among the transistors used in the memory element 1200, Transistors other than 1209 are made of a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. A transistor can be formed in which a channel is formed in a silicon layer or a silicon layer. A transistor can be used to form a channel on a recon substrate. Also, memory element 1 All transistors used in the 200 are transistors whose channels are formed by an oxide semiconductor layer. It can also be a zista. Alternatively, the memory element 1200 may be a transistor other than the transistor 1209. The transistor may also include a channel formed by an oxide semiconductor layer, and the remaining The lunger is formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor, with a channel formed in it. It can also be used as a transistor.

[0182] In Figure 9, circuit 1201 can, for example, use a flip-flop circuit. Furthermore, logic elements 1206 can be, for example, inverters or clocked inverters. It is possible.

[0183] In one aspect of the present invention, in a semiconductor device, when the power supply voltage is not supplied to the memory element 1200 The data stored in circuit 1201 is transferred to the capacitive element 120 provided in circuit 1202. It can be held by 8.

[0184] Furthermore, transistors in which channels are formed in the oxide semiconductor layer exhibit extremely low off-current. For example, the off-current of a transistor in which a channel is formed in an oxide semiconductor layer has crystalline properties. It is significantly lower than the off-current of a transistor in which a channel is formed in silicon. Therefore, by using the transistor as transistor 1209, memory element 1 Even when no power voltage is supplied to 200, the signal held by the capacitive element 1208 will persist for a long period of time. The memory element 1200 is thus preserved. It is possible to hold data.

[0185] Furthermore, by providing switches 1203 and 1204, pre-charge action Since it is a memory element characterized by performing an operation, after the power supply voltage is restored, the circuit 1201 This can shorten the time it takes to restore the original data.

[0186] Furthermore, in circuit 1202, the signal held by the capacitive element 1208 is transmitted to the transistor The signal is input to gate 1210. As a result, the power supply voltage to memory element 1200 is restored. After that, the signal held by the capacitive element 1208 is controlled by the state of transistor 1210 ( It can be converted to an ON state or an OFF state and read from circuit 1202. Therefore, even if the potential corresponding to the signal held in the capacitive element 1208 fluctuates slightly, the original signal It is possible to read it accurately.

[0187] Such memory elements 1200 are stored in registers and cache memory of the processor. By using it in a storage device, it prevents the loss of data in the storage device due to a power supply interruption. This is possible. Furthermore, after the power supply voltage is restored, the system will quickly return to the state it was in before the power supply was interrupted. Therefore, the entire processor, or one of the components of the processor, This allows for power-off even for short periods in multiple logic circuits, thus reducing power consumption. It can be suppressed.

[0188] In this embodiment, although the memory element 1200 was described as an example of being used in a CPU, the memory element 1 200 is a DSP (Digital Signal Processor), custom L LSIs such as SIs and PLDs (Programmable Logic Devices), R It can also be applied to F-ID (Radio Frequency Identification). It is possible.

[0189] The configurations and methods described in this embodiment are compatible with the configurations and methods described in other embodiments. They can be used in any combination.

[0190] (Embodiment 6) This embodiment describes an example of the configuration of a display panel according to one aspect of the present invention.

[0191] [Example Configuration] Figure 14(A) is a top view of a display panel according to one embodiment of the present invention, and Figure 14(B) is a top view of the present invention. A pixel circuit that can be used when applying liquid crystal elements to the pixels of a display panel in one embodiment of the present invention. This is a circuit diagram for illustrative purposes. Figure 14(C) is a diagram of a display panel according to one embodiment of the present invention. A circuit diagram illustrating a pixel circuit that can be used when applying organic EL elements as a base. That is the case.

[0192] The transistors placed in the pixel area can be formed according to the above embodiment. Since the transistor can easily be made into an n-channel type, the n-channel transistor is used in the drive circuit. A portion of the drive circuit, which can be constructed using a single-type transistor, is identical to the transistors in the pixel section. It is formed on a substrate. In this way, the pixel portion and the driving circuit are formed with the transistors shown in the above embodiment. By using this, a highly reliable display device can be provided.

[0193] An example of a block diagram of an active-matrix display device is shown in Figure 14(A). On the substrate 700 are a pixel unit 701, a first scan line drive circuit 702, and a second scan line drive circuit It has 703 and a signal line driving circuit 704. Multiple signal lines are driven in the pixel section 701. Extending from circuit 704, multiple scan lines are arranged to the first scan line drive circuit 702, and It is arranged as an extension from the scan line drive circuit 703. Note that the intersection area of ​​the scan line and signal line Each region has pixels, each containing a display element, arranged in a matrix. The 700 board is used for connections such as FPC (Flexible Printed Circuit). It is connected to the timing control circuit (also called a controller or control IC) via a component. .

[0194] Figure 14(A) shows the first scan line drive circuit 702, the second scan line drive circuit 703, and the signal line The drive circuit 704 is formed on the same substrate 700 as the pixel unit 701. Therefore, it is not externally installed. Since the number of components such as drive circuits is reduced, costs can be reduced. Also, the circuit board 7 00If an external drive circuit is installed, it becomes necessary to extend the wiring, and the number of connections between wires increases. When the drive circuit is placed on the same circuit board 700, the number of connections between the wires can be reduced. This can lead to improved reliability or increased yield.

[0195] [LCD panel] Furthermore, an example of the pixel circuit configuration is shown in Figure 14(B). Here, a VA-type liquid crystal display panel... This shows a pixel circuit that can be applied to a pixel.

[0196] This pixel circuit can be applied to configurations in which a single pixel has multiple pixel electrode layers. The pixel electrode layer is connected to different transistors, and each transistor is driven by a different gate signal. It is configured to allow this to happen. This allows for the individual pixels of a multi-domain designed pixel to be... The signals applied to the electrode layer can be controlled independently.

[0197] The gate wiring 712 of transistor 716 and the gate wiring 713 of transistor 717 are They are separated so that different gate signals can be applied. On the other hand, as data lines The functioning source electrode layer or drain electrode layer 714 is connected to transistor 716 and transistor It is commonly used in 717. Transistors 716 and 717 are used in the above implementation. Transistors described by their form can be used as appropriate. This allows for highly reliable liquid crystals. A display panel can be provided.

[0198] A first pixel electrode layer electrically connected to transistor 716, and an electrical connection between transistor 717 and transistor 717. The shape of the second pixel electrode layer that connects to the first pixel electrode layer will be described. The shape of the electrode layers is separated by slits. The first pixel electrode layer spreads out in a V-shape. The second pixel electrode layer has a shape, and is formed to surround the outside of the first pixel electrode layer.

[0199] The gate electrode of transistor 716 is connected to the gate wiring 712, and the gate electrode of transistor 717 The gate electrode is connected to gate wiring 713. Gate wiring 712 and gate wiring 713 By applying different gate signals, the operating timing of transistors 716 and 717 is determined. By varying the parameters, the alignment of the liquid crystals can be controlled.

[0200] Furthermore, the capacitive wiring 710, the gate insulating film which functions as a dielectric, and the first pixel electrode layer A retention capacitance may be formed by a capacitive electrode electrically connected to a second pixel electrode layer.

[0201] The multi-domain structure includes a first liquid crystal element 718 and a second liquid crystal element 719 in each pixel. The first liquid crystal element 718 is composed of a first pixel electrode layer, a counter electrode layer, and a liquid crystal layer between them. The second liquid crystal element 719 is composed of a second pixel electrode layer, a counter electrode layer, and a liquid crystal layer between them. ru.

[0202] Note that the pixel circuit shown in Figure 14(B) is not limited to this. For example, as shown in Figure 14(B) A new switch, resistor, capacitive element, transistor, sensor, or logic circuit may be added to the pixel. You can add any of these.

[0203] [OLED panel] Another example of a pixel circuit configuration is shown in Figure 14(C). Here, a display using an organic EL element is shown. This shows the pixel structure of the panel.

[0204] Organic EL elements emit electrons from one of a pair of electrodes when a voltage is applied to the light-emitting element. On the other hand, holes are injected into layers containing luminescent organic compounds, and an electric current flows. Through the recombination of electrons and holes, the luminescent organic compound forms an excited state, It emits light when the excited state returns to the ground state. This mechanism explains why such light emission occurs. The device is called a current-excited light-emitting element.

[0205] Figure 14(C) shows an example of an applicable pixel circuit. Here, an n-channel type An example is shown in which two lampistors are used for one pixel. Note that this is an oxide semiconductor film according to one embodiment of the present invention. This can be used in the channel formation region of an n-channel transistor. The pixel circuit can be fitted with digital time-based grayscale driving.

[0206] Regarding the applicable pixel circuit configuration and the operation of pixels when digital time-gradation driving is applied. I will explain.

[0207] Pixel 720 consists of a switching transistor 721, a driving transistor 722, and a light-emitting element. It has a sub-element 724 and a capacitive element 723. The switching transistor 721 is a gateway The electrode layer is connected to the scan line 726, and the first electrode (one of the source electrode layer and drain electrode layer) is connected to the source electrode layer. ) is connected to signal line 725, and the second electrode (the other of the source electrode layer and drain electrode layer) is driven It is connected to the gate electrode layer of the drive transistor 722. The drive transistor 722 is The gate electrode layer is connected to the power line 727 via the capacitive element 723, and the first electrode is connected to the power line 7 It is connected to 27, and the second electrode is connected to the first electrode (pixel electrode) of the light-emitting element 724. The second electrode of the light-emitting element 724 corresponds to the common electrode 728. The common electrode 728 is on the same substrate. It is electrically connected to a common potential line formed therein.

[0208] In the above embodiment, the switching transistor 721 and the driving transistor 722 are The transistors described can be used as appropriate. This allows for a highly reliable organic EL display. A display panel can be provided.

[0209] The potential of the second electrode (common electrode 728) of the light-emitting element 724 is set to the low power supply potential. The power supply potential is a potential lower than the high power supply potential supplied to power line 727, for example, GND. The forward threshold of the light-emitting element 724 The high and low power supply potentials are set so that they are equal to or greater than the value voltage, and the potential difference between them is used to power the light-emitting element 724 By applying a current to the light-emitting element 724, an electric current is passed through it, causing it to emit light. The forward voltage in 4 refers to the voltage required to achieve the desired brightness, and at least the forward voltage is... Includes high-value voltage.

[0210] Furthermore, the capacitive element 723 is replaced by the gate capacitance of the drive transistor 722, thus saving space. It can be abbreviated. Regarding the gate capacitance of the drive transistor 722, the channel formation region and the gate A capacitance may be formed between the electrode layer and the electrode layer. Next, we will explain the signal input to the drive transistor 722. Voltage input Voltage drive method In this case, the driving transistor 722 is either fully on or completely off. A video signal like this is input to the drive transistor 722. To operate the 722 in the linear region, a voltage higher than the voltage of the power line 727 is used for the drive. It is applied to the gate electrode layer of transistor 722. Additionally, the signal line 725 is driven by the power line voltage. Apply a voltage greater than or equal to the threshold voltage Vth of transistor 722.

[0211] When performing analog grayscale driving, the gate electrode layer of the driving transistor 722 has an emissive element 72 A voltage greater than or equal to the sum of the forward voltage of 4 and the threshold voltage Vth of the drive transistor 722 is required. The video signal is input so that the drive transistor 722 operates in the saturation region. Then, current is passed to the light-emitting element 724. Also, the drive transistor 722 is operated in the saturation region. To achieve this, the potential of the power line 727 is set higher than the gate potential of the drive transistor 722. By converting the video signal to analog, a current corresponding to the video signal is supplied to the light-emitting element 724. It can perform analog grayscale driving.

[0212] Note that the pixel circuit configuration is not limited to the pixel configuration shown in Figure 14(C). For example, Figure 14 (C) The pixel circuit shown contains switches, resistors, capacitives, sensors, transistors or logic You may add circuits or other components.

[0213] When applying the transistor exemplified in the above embodiment to the circuit exemplified in Figure 14, the low potential The source electrode (first electrode) is on the side with the high potential, and the drain electrode (second electrode) is on the high potential side with the electrical currents. The configuration is designed to connect them precisely. Furthermore, the potential of the first gate electrode is controlled by a control circuit, etc. The second gate electrode is connected to the source electrode via wiring (not shown) at a potential lower than the potential applied to the source electrode. The configuration should be such that it can accept the potential values ​​exemplified above.

[0214] The configurations and methods described in this embodiment are compatible with the configurations and methods described in other embodiments. They can be used in any combination.

[0215] (Embodiment 7) A semiconductor device according to one aspect of the present invention comprises a display device, a personal computer, and a recording medium. Image playback devices (typically DVDs: Digital Versatile Discs) To be used in a device that has a display capable of playing back recording media such as the above and displaying the images thereof. This is possible. In addition, electronic devices that can use a semiconductor device according to one aspect of the present invention And mobile phones, game consoles including portable models, portable data terminals, e-books, video cameras, and Digital still cameras and other cameras, goggle-type displays (head-mounted displays) ), navigation systems, sound playback devices (car audio, digital audio players) (e.g., photocopiers, fax machines, printers, multifunction printers, ATMs) Examples include ATMs and vending machines. Specific examples of these electronic devices are shown in Figure 10.

[0216] Figure 10(A) shows a portable game console, consisting of a casing 901, casing 902, display unit 903, and display unit. 904, Microphone 905, Speaker 906, Control Keys 907, Stylus 908 It has the following features. The portable game console shown in Figure 10(A) has two display units 903 and a display unit. Although it has part 904, the number of display units that a portable game console has is not limited to this. .

[0217] Figure 10(B) shows a portable data terminal, comprising a first housing 911, a second housing 912, and a first display unit 9 13. It has a second display unit 914, a connection unit 915, an operation key 916, etc. First display unit 913 The first housing 911 is provided, and the second display unit 914 is provided in the second housing 912. Furthermore, the first housing 911 and the second housing 912 are connected by a connecting part 915. The angle between the first housing 911 and the second housing 912 can be changed by the connecting part 915. The video in the first display unit 913 is connected to the first housing 911 and the second housing 9 in the connection unit 915. It may also be configured to switch according to the angle between 12 and 12. Also, the first display unit 913 and A display device in which at least one of the second display unit 914 is provided with a function as a position input device. You may also use a touch panel. Note that the function as a position input device is provided by the display device. It can be added by providing a panel. Alternatively, the function as a position input device is It can also be added by installing a photoelectric conversion element, also called a photosensor, in the pixel section of the display device. It is possible.

[0218] Figure 10(C) shows a notebook personal computer, comprising a casing 921, a display unit 922, and a keyboard. It includes a board 923, a pointing device 924, and the like.

[0219] Figure 10(D) shows an electric refrigerator-freezer, consisting of a casing 931, a refrigerator door 932, and a freezer door 93 It has a third-class rating.

[0220] Figure 10(E) shows a video camera, comprising a first housing 941, a second housing 942, a display unit 943, It has an operation key 944, a lens 945, a connecting part 946, etc. Operation key 944 and lens 945 is provided in the first housing 941, and the display unit 943 is provided in the second housing 942. And the first housing 941 and the second housing 942 are connected by a connecting part 946. The angle between the first housing 941 and the second housing 942 can be changed by the connecting part 946. The video on the display unit 943 is connected to the first housing 941 and the second housing 94 in the connection unit 946. It could also be configured to switch according to the angle between 2 and 3.

[0221] Figure 10(F) is a regular passenger car, consisting of the body 951, wheels 952, dashboard 953, and It has Ito 954, etc.

[0222] The configurations and methods described in this embodiment are compatible with the configurations and methods described in other embodiments. They can be used in any combination.

[0223] (Embodiment 8) In this embodiment, an example of the use of an RFIC according to one aspect of the present invention will be shown with reference to Figure 11. Let me explain. RFICs have a wide range of applications, such as banknotes, coins, securities, and bearer cards. Bonds, certificates (such as driver's licenses and residence certificates, see Figure 11(A)), packaging containers (wrapping paper and Bottles, etc. (see Figure 11(C)), recording media (DVD software, videotapes, etc., see Figure 11(B)) (See Figure 11(D)), vehicles (bicycles, etc.), personal belongings (bags, glasses, etc.), food Plants, animals, human bodies, clothing, household goods, medicines and pharmaceuticals, or electronic devices Items such as devices (LCD displays, EL displays, television equipment, or mobile phones), if Alternatively, it can be used by attaching it to a tag (see Figures 11(E) and 11(F)) attached to each item. It is possible.

[0224] RFIC4000 according to one aspect of the present invention is used to attach or embed an RFIC4000 on a surface, thereby enabling the use of an RFIC4000 on a surface. It is fixed to the product. For example, in the case of a book, it is embedded in the paper, and in the case of a package made of organic resin. The organic resin is then embedded inside and fixed to each article. RFIC according to one aspect of the present invention The 4000 is designed to be small, thin, and lightweight, and even after being fixed to an object, it does not affect the design of the object itself. It does not impair the integrity of banknotes, coins, securities, bearer bonds, or certificates. By providing an RFIC4000 according to one aspect of the present invention in the same type of device, an authentication function can be provided. This allows for counterfeiting to be prevented by utilizing this authentication function. Furthermore, packaging containers... The present invention applies to items such as recording media, personal belongings, food products, clothing, household goods, or electronic devices. By installing an RFIC (Radio Frequency Control) as described above, the efficiency of systems such as inspection systems can be improved. It is possible to attach an RFIC according to one aspect of the present invention to vehicles. This enhances security against theft and other crimes.

[0225] As described above, the RFIC according to one aspect of the present invention can be used in each of the applications listed in this embodiment. This reduces the operating power, including the power required for writing and reading information, thus extending the maximum communication distance. It becomes possible to store information for a long period of time. Furthermore, even when the power is cut off, information can be stored for an extremely long period of time. Because it can retain data for extended periods, it can be suitably used in applications where the frequency of writing and reading is low. Cut.

[0226] The configurations and methods described in this embodiment are compatible with the configurations and methods described in other embodiments. They can be used in any combination. [Examples]

[0227] In this embodiment, the cross-sectional structure of the electrode layer fabricated by a fabrication method according to one aspect of the present invention is described below. This will be shown together with comparative examples. First, the sample 1 of this example and comparative examples 1 to 3 are shown. The manufacturing method is shown below.

[0228] <Sample 1> A 10 nm tungsten film is placed on a silicon substrate as a conductive film that will become the first electrode layer 206. The film was formed under the following conditions: under an argon atmosphere (flow rate 80 sccm), pressure With a pressure of 0.8 Pa, a power supply (DC) of 1 kW, a substrate temperature of 200°C, and a distance between the substrate and the target... The film was deposited using the sputtering method with a gap of 60 mm.

[0229] Next, an oxide semiconductor film 208 is formed on the first electrode layer 206 as In:Ga:Zn=1: A sputtering method using an oxide target with a 3:2 atomic ratio was used to create a film thickness of 5 nm. An In-Ga-Zn oxide film was formed. The film deposition conditions were under an argon and oxygen atmosphere (argon (Oxygen: 30 sccm: 15 sccm), Pressure 0.4 Pa, Power Supply (DC) 0.5kJ The wattage (W) was set to 200°C, the substrate temperature to 200°C, and the distance between the substrate and the target to 60 mm.

[0230] Next, an insulating film 210 corresponding to the gate insulating film is applied to the oxide semiconductor film 208, with a film thickness of 1 A 0 nm silicon oxidnitride film was deposited by CVD. The deposition temperature was 350°C and the pressure was 2 It was set to 00 Pa.

[0231] A first conductive film 212 with a thickness of 10 nm is formed on the insulating film 210 by sputtering. A tantalum film was formed. The deposition conditions for the tantalum nitride film were under an argon and nitrogen atmosphere (algone). (Gon:Nitrogen = 50 sccm:10 sccm), Pressure 0.6 Pa, Power supply (DC) 1 kW The substrate temperature was set to room temperature, and the distance between the substrate and the target was set to 60 mm.

[0232] Next, an organic coating film with a thickness of approximately 20 nm is applied to the first conductive film 212, and then a film with a thickness of approximately 100 nm is applied. The resist films were deposited using a coating method. Subsequently, an electron beam was applied to the resist films. After scanning and exposure, a pattern is formed on the resist film by developing it, and the resist mat It was firm.

[0233] Next, using a resist mask, an organic coating film, a first conductive film 212 (tantalum nitride film), and The insulating film 210 (silicon oxidnitride film) is etched to reach the oxide semiconductor film 208. An opening was formed. The etching conditions were: tetrafluoride methane (flow rate 1) as the etching gas. Using 00 sccm, the power supply was set to 2kW, the bias power to 50W, and the pressure to 0.67 Pa. .

[0234] Subsequently, the organic coating film and resist are removed by a plasma ashing process under an oxygen atmosphere. The mask was removed. The ashing treatment conditions were an oxygen flow rate of 100 sccm and RF The test was performed for 30 seconds under conditions of a bias power of 200W and a pressure of 500mTorr.

[0235] Next, the oxide semiconductor film 208 is made using the first conductive film 212 having an opening as a mask. Etching was performed to form an opening that reached the first electrode layer 206. The etching conditions were initially In addition, a mixed gas of methane tetrafluoride and argon (CF4:Ar=16s) is used as the etching gas. Using ccm:32sccm, power supply power 600W, bias power 100W, pressure 3.0 After processing at Pa for 3 seconds, the pressure was changed to 1.0 Pa and processed for 20 seconds.

[0236] Next, reverse sputtering is performed, and the surface of the first conductive film 212 is treated by the ashing process described above. The formed oxide film was removed. The reverse sputtering conditions were under an argon atmosphere (flow rate 50s). The sample was processed for 45 seconds at ccm, a pressure of 0.6 Pa, and a power supply (RF) of 200 W.

[0237] Subsequently, the first electrode layer 206 exposed from the opening of the oxide semiconductor film 208 is brought into contact with it. A tungsten film with a thickness of 10 nm is formed on the first conductive film 212 as the second conductive film 214. Success. The conditions for depositing the tungsten film were under an argon atmosphere (flow rate 100 sccm) and pressure The parameters are 2.0 Pa, power supply (DC) 1 kW, substrate temperature 200°C, and the distance between the substrate and the target. The film was deposited using the sputtering method with a gap of 60 mm.

[0238] Sample 1 of this embodiment was formed by the above manufacturing process.

[0239] <Comparison Sample 1> In comparative sample 1, the oxide semiconductor film 208 and insulating film 21 were formed using the same manufacturing method as sample 1. After forming an opening by an etching process once per 0, the resist mask is ashing. The material was removed by force, and a first conductive film 212 and a second conductive film 214 were formed to cover the opening. The detailed manufacturing method is shown below.

[0240] Using the same fabrication method as sample 1, a first electrode layer 206 and a first electrode layer are prepared on a silicon substrate. An oxide semiconductor film 208 is formed on 206, and an insulating film 210 is formed on the oxide semiconductor film 208. Subsequently, an organic coating film and a resist mask were formed on the insulating film 210 in the same manner as in sample 1. Ta.

[0241] Next, using a resist mask, an organic coating film, an insulating film 210 (silicon oxide nitride film) and The oxide semiconductor film 208 was etched to form an opening that reached the first electrode layer 206. The etching conditions are as follows: First, methane tetrafluoride (flow rate 100 sccm) is used as the etching gas. Using a power supply of 2kW, bias power of 50W, pressure of 0.67Pa, and substrate temperature of -10℃ The organic coating film was etched by treating it for 12 seconds. Then, as the etching gas, A mixed gas of trifluoromethane and helium (CHF3:He=50sccm:100sc) Using cm, with a power supply of 475W, bias power of 300W, and pressure of 5.5Pa, for 3 seconds. After processing, the etching gas flow rate ratio was set to CHF3:He = 7.5 sccm:142.5 s. The process is changed to CCM and treated for 16 seconds to etch the insulating film 210 and the oxide semiconductor film 208. I did it.

[0242] Subsequently, the organic coating film and resist are removed by a plasma ashing process under an oxygen atmosphere. The mask was removed. The ashing treatment conditions were an oxygen flow rate of 300 sccm and RF The test was conducted for 3 minutes under conditions of 1800W power and 66.5Pa pressure.

[0243] Next, a tantalum nitride film is formed on the insulating film 210 as a first conductive film 212 that covers the opening. Then, a tungsten film was formed on the tantalum nitride film as a second conductive film 214. The film deposition conditions for the electrical film 212 and the second conductive film 214 are the same as those for sample 1.

[0244] Comparative sample 1 of this embodiment was formed by the above manufacturing process.

[0245] <Comparison Sample 2> In comparative sample 2, the insulating film 210 and oxide semiconductor film 20 were produced using the same process as comparative sample 1. In step 8, an opening is formed that reaches the first electrode layer 206, followed by an ashing treatment and a chemical solution (exfoliation). The organic coating film and resist mask were removed by liquid treatment.

[0246] In comparative sample 2, the removal of the organic coating film and resist mask was performed under the same conditions as in comparative sample 1. After the ashing process, treatment with a stripping solution was performed.

[0247] In comparative sample 2, the steps other than the removal of the organic resin film and resist mask were the same as in comparative sample 1. The same procedure was followed. Comparative sample 2 of this example was formed through the above manufacturing steps.

[0248] <Comparative sample 3> In comparative sample 3, the first conductive film 212 was used as a mask, prepared using the same method as sample 1. The oxide semiconductor film 208 was etched to form an opening that reached the first electrode layer 206. Subsequently, without removing the oxide film on the surface of the first conductive film 212 by reverse sputtering, the second A conductive film 214 was formed.

[0249] Comparative sample 3 was prepared in the same manner as sample 1, except that reverse sputtering was not performed. Comparative sample 3 of this embodiment was formed accordingly.

[0250] The following are the results of Sample 1, Comparative Sample 1, Comparative Sample 2, and Comparative Sample 3 of this embodiment obtained as described above. An electrode layer 206 and a second electrode layer including a first conductive film 212 and a second conductive film 214 The cross-sectional structure of the connection part is examined using a scanning transmission electron microscope (STEM). Images observed using a mission electron microscope. The true result is shown in Figure 12. Figure 12(A) is a cross-sectional STEM image of comparative sample 1, and Figure 12(B) Figure 12(C) is a cross-sectional STEM image of comparative sample 2, and Figure 12(C) is a cross-sectional STEM image of comparative sample 3. Figure 12(D) is a cross-sectional STEM image of sample 1.

[0251] As shown in Figure 12(A), a tiny opening of about 60 nm in diameter is formed in comparative sample 1, and the first It was confirmed that the conductive film 212 and the second conductive film 214 are provided to fill the opening. However, as shown in the area 100 enclosed by the dotted line in Figure 12(A), the first electric It was confirmed that an oxide layer was formed between the polar layer 206 and the first conductive film 212. The oxide layer is exposed from the opening when the organic coating film and resist mask are ashing. This suggests that the first electrode layer 206 that was exposed was formed by oxidation.

[0252] Furthermore, as shown in Figure 12(B), when removing the resist mask, comparative sample 2 used a stripping solution. A shape defect was observed in the oxide semiconductor film 208 (region 110) facing the opening. This can be understood as damage to the oxide semiconductor film 208 that was exposed to the stripping solution.

[0253] Furthermore, as shown in Figure 12(C), in comparative sample 3, which did not undergo reverse sputtering, the diameter was approximately 60 nm. A tiny opening is formed, and at the opening, the first electrode layer 206 and the second conductive film 214 It was confirmed that they were in contact. However, the area 100 enclosed by the dotted line in Figure 12(C) As shown, an oxide layer is formed between the first conductive film 212 and the second conductive film 214. It was confirmed that the oxide layer was present during the ashing process of the organic coating film and the resist mask. This suggests that the surface of the first conductive film 212 is a layer formed by oxidation during the process. .

[0254] On the other hand, as shown in Figure 12(D), sample 1 of this embodiment has a tiny opening with a diameter of about 60 nm. This is achieved, and the first electrode layer 206 and the second conductive film 214 are in contact at the opening, and further, It is confirmed that the first conductive film 212 and the second conductive film 214 are in contact on the edge film 210. It was confirmed. That is, in sample 1 obtained by the manufacturing method of one aspect of the present invention, the oxide semi was It was shown that the electrode layers located above and below the conductive film 208 can be connected well. In sample 1 of the example, the ashing process for removing the resist mask was performed by acid from the opening. Since the process is carried out with the ionized semiconductor film 208 exposed, oxidation of the surface of the first electrode layer 206 This prevents plasma damage to the insulating film 210 and also suppresses it.

[0255] The configurations and methods described in this embodiment are similar to those described in other embodiments of this specification. It can be used in appropriate combinations. [Explanation of symbols]

[0256] 100 areas 110 areas 300 transistors 310 transistors 320 Capacitive elements 360 transistors 400 circuit boards 402 Underlying insulating film 404 oxide semiconductor layer 404a oxide semiconductor layer 404b oxide semiconductor layer 405 oxide semiconductor layer 406a Source electrode layer 406b Drain electrode layer 406c source electrode layer 406d Drain electrode layer 408 Oxide semiconductor film 410 Gate Insulator 412 Conductive film 412a conductive layer 412b conductive layer 412c conductive layer 412d conductive layer 414 Conductive film 414a conductive layer 414b Conductive layer 414c conductive layer 414d conductive layer 415 Opening 416a Guardgate layer 416b Electrode layer 416c electrode 416d Grid control layer 417 Opening 418 Protective insulating film 420 Insulating film 422 Conductive layer 429 Organic coating film 430 Resist Mask 431 Oxide film 700 circuit boards 701 pixel section 702 Scan Line Drive Circuit 703 Scan line drive circuit 704 Signal Line Drive Circuit 710 Capacitance wiring 712 Gate Wiring 713 Gate wiring 714 Drain electrode layer 716 transistors 717 transistors 718 Liquid crystal elements 719 Liquid crystal elements 720 pixels 721 Switching Transistors 722 Driver Transistor 723 Capacitive element 724 Light-emitting element 725 Signal Line 726 scan lines 727 Power line 728 Common electrode 800 RFIC tags 801 Communication device 802 Antenna 803 Wireless signal 804 Antenna 805 Rectifier circuit 806 Constant Voltage Circuit 807 Demodulation Circuit 808 Modulation Circuit 809 Logic Circuits 810 Memory circuit 811 ROM 901 cabinet 902 cabinet 903 Display section 904 Display section 905 Microphone 906 Speakers 907 Operation Keys 908 Stylus 911 cabinet 912 cabinet 913 Display section 914 Display section 915 Connection part 916 Operation Keys 921 cabinet 922 Display section 923 Keyboard 924 Pointing Devices 931 cabinet 932 Refrigerator door 933 Freezer door 941 cabinet 942 cabinets 943 Display section 944 Operation Keys 945 lens 946 Connection part 951 Body 952 wheels 953 Dashboard 954 Light 1189 ROM Interface 1190 circuit board 1191 ALU 1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Register 1197 Register Controller 1198 Bus Interface 1199 ROM 1200 memory elements 1201 Circuit 1202 Circuit 1203 Switch 1204 Switch 1206 Logic Element 1207 Capacitive element 1208 Capacitive element 1209 Transistors 1210 Transistors 1213 Transistors 1214 Transistors 1220 Circuit 4000 RFIC

Claims

1. A device comprising a first transistor, a second transistor, and a capacitive element, A semiconductor device in which one of the source electrode and drain electrode of the first transistor, one electrode of the capacitive element, and the gate electrode of the second transistor are electrically connected to each other, The first insulating layer, A first oxide semiconductor layer having a region in contact with the upper surface of the first insulating layer and having a channel formation region for the first transistor, A second oxide semiconductor layer having a region in contact with the upper surface of the first insulating layer and having a channel formation region for the second transistor, A first conductive layer having a region located above the first oxide semiconductor layer and functioning as the gate electrode of the first transistor, A second conductive layer having a region in contact with the upper surface of the first oxide semiconductor layer, and having the function of one of the source and drain electrodes of the first transistor, and the function of one electrode of the capacitive element, A third conductive layer having a region overlapping with the second conductive layer and functioning as the other electrode of the capacitive element, A second insulating layer having a region in contact with the upper surface of the first conductive layer and a region in contact with the upper surface of the third conductive layer, A fourth conductive layer having a region in contact with the second conductive layer and functioning as the gate electrode of the second transistor, The third conductive layer has the same material as the first conductive layer, A semiconductor device in which the channel length direction of the first transistor and the channel length direction of the second transistor intersect each other.

2. A device comprising a first transistor, a second transistor, and a capacitive element, A semiconductor device in which one of the source electrode and drain electrode of the first transistor, one electrode of the capacitive element, and the gate electrode of the second transistor are electrically connected to each other, The first insulating layer, A first oxide semiconductor layer having a region in contact with the upper surface of the first insulating layer and having a channel formation region for the first transistor, A second oxide semiconductor layer having a region in contact with the upper surface of the first insulating layer and having a channel formation region for the second transistor, A first conductive layer having a region located above the first oxide semiconductor layer and functioning as the gate electrode of the first transistor, A second conductive layer having a region in contact with the upper surface of the first oxide semiconductor layer, and having the function of one of the source and drain electrodes of the first transistor, and the function of one electrode of the capacitive element, A third conductive layer having a region overlapping with the second conductive layer and functioning as the other electrode of the capacitive element, A second insulating layer having a region in contact with the upper surface of the first conductive layer and a region in contact with the upper surface of the third conductive layer, A fourth conductive layer having a region in contact with the second conductive layer and functioning as the gate electrode of the second transistor, The third conductive layer has the same material as the first conductive layer, The channel length direction of the first transistor and the channel length direction of the second transistor are in directions that intersect each other. A semiconductor device wherein, in a plan view, at least a portion of the region where the second conductive layer and the third conductive layer overlap each other is located between the channel formation region of the first transistor and the channel formation region of the second transistor.

3. A device comprising a first transistor, a second transistor, and a capacitive element, A semiconductor device in which one of the source electrode and drain electrode of the first transistor, one electrode of the capacitive element, and the gate electrode of the second transistor are electrically connected to each other, The first insulating layer, A first oxide semiconductor layer having a region in contact with the upper surface of the first insulating layer and having a channel formation region for the first transistor, A second oxide semiconductor layer having a region in contact with the upper surface of the first insulating layer and having a channel formation region for the second transistor, A first conductive layer having a region located above the first oxide semiconductor layer and functioning as the gate electrode of the first transistor, A second conductive layer having a region in contact with the upper surface of the first oxide semiconductor layer, and having the function of one of the source and drain electrodes of the first transistor, and the function of one electrode of the capacitive element, A third conductive layer having a region overlapping with the second conductive layer and functioning as the other electrode of the capacitive element, A second insulating layer having a region in contact with the upper surface of the first conductive layer and a region in contact with the upper surface of the third conductive layer, A fourth conductive layer having a region in contact with the second conductive layer and functioning as the gate electrode of the second transistor, The third conductive layer has the same material as the first conductive layer, The channel length direction of the first transistor and the channel length direction of the second transistor are in directions that intersect each other. In a plan view, the channel width direction of the first transistor is the first direction, A semiconductor device wherein, in a plan view, the length of the second conductive layer in the first direction is greater than the length of the first oxide semiconductor layer in the first direction.

4. A device comprising a first transistor, a second transistor, and a capacitive element, A semiconductor device in which one of the source electrode and drain electrode of the first transistor, one electrode of the capacitive element, and the gate electrode of the second transistor are electrically connected to each other, The first insulating layer, A first oxide semiconductor layer having a region in contact with the upper surface of the first insulating layer and having a channel formation region for the first transistor, A second oxide semiconductor layer having a region in contact with the upper surface of the first insulating layer and having a channel formation region for the second transistor, A first conductive layer having a region located above the first oxide semiconductor layer and functioning as the gate electrode of the first transistor, A second conductive layer having a region in contact with the upper surface of the first oxide semiconductor layer, and having the function of one of the source and drain electrodes of the first transistor, and the function of one electrode of the capacitive element, A third conductive layer having a region overlapping with the second conductive layer and functioning as the other electrode of the capacitive element, A second insulating layer having a region in contact with the upper surface of the first conductive layer and a region in contact with the upper surface of the third conductive layer, A fourth conductive layer having a region in contact with the second conductive layer and functioning as the gate electrode of the second transistor, The third conductive layer has the same material as the first conductive layer, The channel length direction of the first transistor and the channel length direction of the second transistor are in directions that intersect each other. In a plan view, the channel width direction of the first transistor is the first direction, A semiconductor device wherein, in a plan view, the width of the second conductive layer in the first direction in the portion including the region where the second conductive layer and the fourth conductive layer are in contact with each other is greater than the width of the fourth conductive layer in the first direction in the portion including the contact region.

5. A device comprising a first transistor, a second transistor, and a capacitive element, A semiconductor device in which one of the source electrode and drain electrode of the first transistor, one electrode of the capacitive element, and the gate electrode of the second transistor are electrically connected to each other, The first insulating layer, A first oxide semiconductor layer having a region in contact with the upper surface of the first insulating layer and having a channel formation region for the first transistor, A second oxide semiconductor layer having a region in contact with the upper surface of the first insulating layer and having a channel formation region for the second transistor, A first conductive layer having a region located above the first oxide semiconductor layer and functioning as the gate electrode of the first transistor, A second conductive layer having a region in contact with the upper surface of the first oxide semiconductor layer, and having the function of one of the source and drain electrodes of the first transistor, and the function of one electrode of the capacitive element, A third conductive layer having a region overlapping with the second conductive layer and functioning as the other electrode of the capacitive element, A second insulating layer having a region in contact with the upper surface of the first conductive layer and a region in contact with the upper surface of the third conductive layer, A fourth conductive layer having a region in contact with the second conductive layer and functioning as the gate electrode of the second transistor, The third conductive layer has the same material as the first conductive layer, The channel length direction of the first transistor and the channel length direction of the second transistor are in directions that intersect each other. In a plan view, at least a portion of the region where the second conductive layer and the third conductive layer overlap each other is located between the channel formation region of the first transistor and the channel formation region of the second transistor. In a plan view, the channel width direction of the first transistor is the first direction, A semiconductor device wherein, in a plan view, the length of the second conductive layer in the first direction is greater than the length of the first oxide semiconductor layer in the first direction.

6. A device comprising a first transistor, a second transistor, and a capacitive element, A semiconductor device in which one of the source electrode and drain electrode of the first transistor, one electrode of the capacitive element, and the gate electrode of the second transistor are electrically connected to each other, The first insulating layer, A first oxide semiconductor layer having a region in contact with the upper surface of the first insulating layer and having a channel formation region for the first transistor, A second oxide semiconductor layer having a region in contact with the upper surface of the first insulating layer and having a channel formation region for the second transistor, A first conductive layer having a region located above the first oxide semiconductor layer and functioning as the gate electrode of the first transistor, A second conductive layer having a region in contact with the upper surface of the first oxide semiconductor layer, and having the function of one of the source and drain electrodes of the first transistor, and the function of one electrode of the capacitive element, A third conductive layer having a region overlapping with the second conductive layer and functioning as the other electrode of the capacitive element, A second insulating layer having a region in contact with the upper surface of the first conductive layer and a region in contact with the upper surface of the third conductive layer, A fourth conductive layer having a region in contact with the second conductive layer and functioning as the gate electrode of the second transistor, The third conductive layer has the same material as the first conductive layer, The channel length direction of the first transistor and the channel length direction of the second transistor are in directions that intersect each other. In a plan view, at least a portion of the region where the second conductive layer and the third conductive layer overlap each other is located between the channel formation region of the first transistor and the channel formation region of the second transistor. In a plan view, the channel width direction of the first transistor is the first direction, A semiconductor device wherein, in a plan view, the width of the second conductive layer in the first direction in the portion including the region where the second conductive layer and the fourth conductive layer are in contact with each other is greater than the width of the fourth conductive layer in the first direction in the portion including the contact region.

7. A device comprising a first transistor, a second transistor, and a capacitive element, A semiconductor device in which one of the source electrode and drain electrode of the first transistor, one electrode of the capacitive element, and the gate electrode of the second transistor are electrically connected to each other, The first insulating layer, A first oxide semiconductor layer having a region in contact with the upper surface of the first insulating layer and having a channel formation region for the first transistor, A second oxide semiconductor layer having a region in contact with the upper surface of the first insulating layer and having a channel formation region for the second transistor, A first conductive layer having a region located above the first oxide semiconductor layer and functioning as the gate electrode of the first transistor, A second conductive layer having a region in contact with the upper surface of the first oxide semiconductor layer, and having the function of one of the source and drain electrodes of the first transistor, and the function of one electrode of the capacitive element, A third conductive layer having a region overlapping with the second conductive layer and functioning as the other electrode of the capacitive element, A second insulating layer having a region in contact with the upper surface of the first conductive layer and a region in contact with the upper surface of the third conductive layer, A fourth conductive layer having a region in contact with the second conductive layer and functioning as the gate electrode of the second transistor, The third conductive layer has the same material as the first conductive layer, The channel length direction of the first transistor and the channel length direction of the second transistor are in directions that intersect each other. In a plan view, the channel width direction of the first transistor is the first direction, In a plan view, the length of the second conductive layer in the first direction is greater than the length of the first oxide semiconductor layer in the first direction. A semiconductor device wherein, in a plan view, the width of the second conductive layer in the first direction in the portion including the region where the second conductive layer and the fourth conductive layer are in contact with each other is greater than the width of the fourth conductive layer in the first direction in the portion including the contact region.

8. A device comprising a first transistor, a second transistor, and a capacitive element, A semiconductor device in which one of the source electrode and drain electrode of the first transistor, one electrode of the capacitive element, and the gate electrode of the second transistor are electrically connected to each other, The first insulating layer, A first oxide semiconductor layer having a region in contact with the upper surface of the first insulating layer and having a channel formation region for the first transistor, A second oxide semiconductor layer having a region in contact with the upper surface of the first insulating layer and having a channel formation region for the second transistor, A first conductive layer having a region located above the first oxide semiconductor layer and functioning as the gate electrode of the first transistor, A second conductive layer having a region in contact with the upper surface of the first oxide semiconductor layer, and having the function of one of the source and drain electrodes of the first transistor, and the function of one electrode of the capacitive element, A third conductive layer having a region overlapping with the second conductive layer and functioning as the other electrode of the capacitive element, A second insulating layer having a region in contact with the upper surface of the first conductive layer and a region in contact with the upper surface of the third conductive layer, A fourth conductive layer having a region in contact with the second conductive layer and functioning as the gate electrode of the second transistor, The third conductive layer has the same material as the first conductive layer, The channel length direction of the first transistor and the channel length direction of the second transistor are in directions that intersect each other. In a plan view, at least a portion of the region where the second conductive layer and the third conductive layer overlap each other is located between the channel formation region of the first transistor and the channel formation region of the second transistor. In a plan view, the channel width direction of the first transistor is the first direction, In a plan view, the length of the second conductive layer in the first direction is greater than the length of the first oxide semiconductor layer in the first direction. A semiconductor device wherein, in a plan view, the width of the second conductive layer in the first direction in the portion including the region where the second conductive layer and the fourth conductive layer are in contact with each other is greater than the width of the fourth conductive layer in the first direction in the portion including the contact region.

9. In any one of claims 1 to 8, A semiconductor device wherein the first conductive layer and the third conductive layer each have a laminated structure.

10. In any one of claims 1 to 9, In a plan view, the area of ​​the second conductive layer is larger than the area of ​​the first oxide semiconductor layer. A semiconductor device wherein, in a plan view, the area of ​​the second conductive layer is larger than the area of ​​the second oxide semiconductor layer.

11. In any one of claims 1 to 10, The first insulating layer has a first region overlapping with the first oxide semiconductor layer, a second region overlapping with the second oxide semiconductor layer, and a third region that does not overlap with either the first or second oxide semiconductor layer, but overlaps with the third conductive layer. The thickness of the first insulating layer in the third region is smaller than the thickness of the first insulating layer in the first region. A semiconductor device wherein the thickness of the first insulating layer in the third region is smaller than the thickness of the first insulating layer in the second region.

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