Light-receiving element and method for manufacturing the same

Abstract

The present invention provides a photodetector capable of reducing dark current and a method for manufacturing the same. [Solution] A photodetector comprising a first semiconductor layer having a first conductivity type, a second semiconductor layer, a light-receiving layer, and a third semiconductor layer having a second conductivity type, wherein the first semiconductor layer, the second semiconductor layer, the light-receiving layer, and the third semiconductor layer are stacked in this order, the second semiconductor layer, the light-receiving layer, and the third semiconductor layer form a first mesa, and in the direction in which the light-receiving layer expands, the width of the second semiconductor layer is smaller than the width of the light-receiving layer.

Description

Technical Field

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[0001] The present disclosure relates to a light-receiving element and a method for manufacturing the same.

Background Art

[0002] In a light-receiving element, a mesa is formed to separate the elements (for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] By applying a voltage, the semiconductor layer of the mesa is depleted. When an electric field concentrates at the edge of the depleted light-receiving layer, the dark current may increase. Therefore, an object is to provide a light-receiving element capable of reducing the dark current and a method for manufacturing the same.

Means for Solving the Problems

[0005] The light-receiving element according to the present disclosure includes a first semiconductor layer having a first conductivity type, a second semiconductor layer, a light-receiving layer, and a third semiconductor layer having a second conductivity type, and the first semiconductor layer, the second semiconductor layer, the light-receiving layer, and the third semiconductor layer are laminated in this order. The second semiconductor layer, the light-receiving layer, and the third semiconductor layer form a first mesa, and in the direction in which the light-receiving layer spreads, the width of the second semiconductor layer is smaller than the width of the light-receiving layer.

Effects of the Invention

[0006] According to the present disclosure, it is possible to provide a light-receiving element capable of reducing the dark current and a method for manufacturing the same.

Brief Description of the Drawings

[0007] [Figure 1] Figure 1 is a plan view illustrating a light-receiving element according to an embodiment. [Figure 2] Figure 2 is a cross-sectional view illustrating a light-receiving element. [Figure 3A] Figure 3A is a cross-sectional view illustrating a light-receiving element. [Figure 3B] Figure 3B is a cross-sectional view illustrating a light-receiving element. [Figure 3C] Figure 3C is a cross-sectional view illustrating a light-receiving element. [Figure 3D] Figure 3D is a cross-sectional view illustrating a light-receiving element. [Figure 4A] Figure 4A is a cross-sectional view illustrating a method for manufacturing a light-receiving element. [Figure 4B] Figure 4B is a cross-sectional view illustrating a method for manufacturing a light-receiving element. [Figure 5] Figure 5 is a cross-sectional view illustrating a photodetector related to a comparative example. [Modes for carrying out the invention]

[0008] [Description of Embodiments in this Disclosure] First, the contents of the embodiments of this disclosure will be listed and explained.

[0009] One embodiment of the present disclosure is a photodetector comprising (1) a first semiconductor layer having a first conductivity type, a second semiconductor layer, a light-receiving layer, and a third semiconductor layer having a second conductivity type, wherein the first semiconductor layer, the second semiconductor layer, the light-receiving layer, and the third semiconductor layer are stacked in this order, the second semiconductor layer, the light-receiving layer, and the third semiconductor layer form a first mesa, and in the direction in which the light-receiving layer expands, the width of the second semiconductor layer is smaller than the width of the light-receiving layer. The width of the depletion region is about the same as the width of the second semiconductor layer and smaller than the width of the light-receiving layer. Dark current can be reduced because an electric field is less likely to be applied to the edge of the light-receiving layer. (2) In (1) above, the second semiconductor layer includes a multiplier layer and an electric field relaxation layer, and the width of the multiplier layer and the width of the electric field relaxation layer may be smaller than the width of the light-receiving layer. The light-receiving element is an avalanche photodiode and has high sensitivity. Since an electric field is less likely to be applied to the edge of the light-receiving layer, the dark current can be reduced. (3) In (2) above, the light-receiving layer may be formed of indium gallium arsenide, and the multiplier layer may be formed of aluminum gallium arsenide antimony. The etching rate of the multiplier layer is higher than the etching rate of the light-receiving layer. The multiplier layer is etched and its width is reduced. (4) In (2) or (3) above, the doping concentration of the multiplier layer may be lower than the doping concentration of the first semiconductor layer. Depletion occurs sequentially from the multiplier layer. The width of the depletion region is about the same as the width of the multiplier layer and smaller than the width of the photodetector layer. Dark current can be reduced. (5) In any of (1) to (4) above, the third semiconductor layer includes a second mesa, and the width of the second mesa may be smaller than the width of the second semiconductor layer. The electric field is narrowed by the second mesa and applied to the layer directly below the second mesa. The electric field is applied to the portion of the light-receiving layer below the second mesa. Since the electric field is less likely to concentrate at the edges of the light-receiving layer, the dark current can be reduced. (6) In any of (1) to (5) above, a fourth semiconductor layer is laminated between the light-receiving layer and the third semiconductor layer, and the fourth semiconductor layer may be included in the first mesa and the second mesa. The capacitance of the light-receiving element decreases as the fourth semiconductor layer becomes depleted. (7) In any of (1) to (6) above, the first semiconductor layer may have an n-type conductivity and the third semiconductor layer may have a p-type conductivity. A pin junction is formed. (8) A method for manufacturing a photodetector comprising the steps of stacking a first semiconductor layer, a second semiconductor layer, a photodetector layer, and a third semiconductor layer in this order, and forming a mesa by wet etching the second semiconductor layer, the photodetector layer, and the third semiconductor layer, wherein the first semiconductor layer has a first conductivity type, the second semiconductor layer has a second conductivity type, and after the wet etching, in the direction in which the photodetector layer expands, the width of the second semiconductor layer is smaller than the width of the photodetector layer. The width of the depletion region is about the same as the width of the second semiconductor layer and smaller than the width of the photodetector layer. Dark current can be reduced because an electric field is less likely to be applied to the edge of the photodetector layer. (9) In (8) above, the second semiconductor layer includes a multiplier layer and an electric field relaxation layer, wherein the width of the multiplier layer and the width of the electric field relaxation layer are smaller than the width of the light-receiving layer, the light-receiving layer is formed of indium gallium arsenide, the multiplier layer is formed of aluminum gallium arsenide antimony, and the wet etching etchant may contain citric acid. The etching rate of the multiplier layer is higher than the etching rate of the light-receiving layer. Side etching progresses, and the width of the multiplier layer decreases.

[0010] [Details of the embodiments of this disclosure] Specific examples of light-receiving elements and methods for manufacturing the same according to embodiments of this disclosure will be described below with reference to the drawings. However, this disclosure is not limited to these examples and is intended to include all modifications within the meaning and scope of the claims as indicated by the claims.

[0011] <Embodiment> Figure 1 is a plan view illustrating a photodetector 100 according to an embodiment. The photodetector 100 is rectangular in plan view. Two sides of the photodetector 100 are parallel to the X-axis. The other two sides are parallel to the Y-axis. The Z-axis direction is the thickness direction of the photodetector 100. The X-axis, Y-axis, and Z-axis directions are orthogonal to each other. The length L1 of the photodetector 100 in the X-axis direction is, for example, 900 μm. The length L2 of the mesa 10 is, for example, 900 μm. The main surface of the semiconductor layer, such as the photodetector layer 28, extends parallel to the XY plane. The Z-axis direction is the normal direction of the main surface.

[0012] The light-receiving element 100 is an avalanche photodiode (APD), and detects light with a wavelength of, for example, 1550 nm. The light-receiving element 100 has a mesa 10 (first mesa), a terrace 12, a mesa 13 (second mesa), an electrode 14, an electrode 16, and an outer peripheral portion 17. The outer peripheral portion 17 is the outer periphery of the light-receiving element 100 in the XY plane. The recess 19 is provided inside the outer peripheral portion 17 and is, for example, in the shape of a square ring. Inside the recess 19, the mesa 10, the terrace 12, and the mesa 13 are provided.

[0013] The terrace 12 is a plate-like portion, is parallel to the XY plane, and extends outside the mesa 10. The mesa 10 is provided inside the terrace 12 in the XY plane and protrudes more than the terrace 12 in the Z-axis direction. A mesa 13 is provided inside the mesa 10.

[0014] The electrode 14 is provided on the terrace 12 and surrounds the mesa 10. The electrode 16 is provided on the mesa 13. In plan view, the electrode 16 has an annular shape, and a pad portion protrudes outward from the annulus. The portion of the mesa 13 surrounded by the electrode 16 becomes the light-receiving region 11. The planar shape of the light-receiving region 11 is circular. The diameter D1 of the light-receiving region 11 is, for example, 200 μm. The outer periphery of the mesa 10 has a curved shape along the electrode 16.

[0015] FIG. 2 is a cross-sectional view illustrating the light-receiving element 100, and shows a cross-section taken along line A-A in FIG. 1. As shown in FIG. 2, it has a substrate 20, a contact layer 22 (first semiconductor layer), a multiplication layer 24 (second semiconductor layer), an electric field relaxation layer 26 (second semiconductor layer), a light-receiving layer 28, a cap layer 30 (fourth semiconductor layer), a cap layer 32 (third semiconductor layer), and a contact layer 34 (third semiconductor layer). In the Z-axis direction, on one surface of the substrate 20, the contact layer 22, the multiplication layer 24, the electric field relaxation layer 26, the light-receiving layer 28, the cap layer 30, the cap layer 32, and the contact layer 34 are laminated in this order.

[0016] The contact layer 22 includes terraces 12. The central part of the contact layer 22 is located inward of terraces 12 in the XY plane and protrudes beyond terraces 12 in the Z-axis direction. Layers from multiplication layer 24 to contact layer 34 are stacked on the protruding portion of the contact layer 22. The central part of the cap layer 30 protrudes beyond the outer periphery of the cap layer 30 in the Z-axis direction. A cap layer 32 is stacked on the central part of the cap layer 30. An annular contact layer 34 is stacked on the upper surface of the cap layer 32. The layers from the central part of the contact layer 22 to contact layer 34 form a mesa 10. The central part of the cap layer 30, cap layer 32, and contact layer 34 form a mesa 13.

[0017] The mesa 10 has a recess 40 and a wide portion 42. In the Z-axis direction, the recess 40 is located between the wide portion 42 and the substrate 20. The recess 40 includes a portion of the contact layer 22, the multiplication layer 24, and a portion of the field relaxation layer 26. The wide portion 42 includes a portion of the field relaxation layer 26, the light-receiving layer 28, and a portion of the cap layer 30.

[0018] The direction of the XY plane is the width direction. Within the XY plane, the recess 40 is narrower than the wide portion 42. The wide portion 42 protrudes outward from the recess 40. The side surface of the recess 40 is, for example, curved and constricts inward. The side surface of the wide portion 42 is, for example, inclined from the Z axis and has a tapered shape that narrows from bottom to top in Figure 2.

[0019] Among the layers contained in the recess 40, the multiplier layer 24 has the smallest width. Let W1 be the minimum width within the multiplier layer 24. Within the light-receiving layer 28, for example, the interface with the cap layer 30 is the narrowest. Let W2 be the minimum width of the light-receiving layer 28. The minimum width W1 of the multiplier layer 24 is smaller than the minimum width W2 of the light-receiving layer 28. The difference between widths W1 and W2 is, for example, 1 μm or more and 20 μm or less. Width W1 is, for example, 310 μm. Width W2 is, for example, 320 μm. The width W3 of the mesa 13 is smaller than the width W1 of the recess 40 and the width W2 of the wide portion 42, for example, 280 μm.

[0020] The surfaces of mesa 10 and mesa 13, and terrace 12, are covered with an insulating film 36. An opening is provided in the portion of the insulating film 36 that covers terrace 12. Electrode 14 is provided in this opening and is in contact with contact layer 22. An opening is provided in the portion of the insulating film 36 that covers contact layer 34. Electrode 16 is provided in this opening and is in contact with contact layer 34.

[0021] The substrate 20 is formed of, for example, indium phosphide (InP). The contact layer 22 is formed of, for example, n-type (first conductivity type) indium gallium arsenide (n-InGaAs). The thickness of the contact layer 22 is, for example, 1.5 μm. The multiplier layer 24 is formed of, for example, aluminum gallium arsenide antimony (AlGaAsSb). The thickness of the multiplier layer 24 is, for example, 0.3 μm. The field relaxation layer 26 is formed of, for example, AlGaAsSb. The thickness of the field relaxation layer 26 is, for example, 0.6 μm. The multiplier layer 24 and the field relaxation layer 26 may be undoped or n-type. The doping concentration of the multiplier layer 24 and the field relaxation layer 26 is lower than the doping concentration of the contact layer 22.

[0022] The light-receiving layer 28 is formed of, for example, undoped indium gallium arsenide (i-InGaAs). The thickness of the light-receiving layer 28 is, for example, 1 μm. The cap layer 30 is formed of, for example, aluminum indium arsenide (AlInAs). The thickness of the cap layer 30 is, for example, 1.0 μm. The cap layer 30 may be, for example, undoped or p-type. The cap layer 32 is formed of, for example, p+ type (second conductivity type) AlInAs. The thickness of the cap layer 32 is, for example, 0.4 μm. The contact layer 34 is formed of, for example, p-type InGaAs. The thickness of the contact layer 34 is, for example, 0.2 μm. The n-type contact layer 22, the i-type light-receiving layer 28, the p-type cap layer 32, and the contact layer 34 form a pin (positive-intrinsic-negative) junction.

[0023] The light-receiving element 100 may be formed from a compound semiconductor other than those described above, or it may include other semiconductor layers. For example, pile-up prevention layers may be provided between the light-receiving layer 28 and the field relaxation layer 26, and between the light-receiving layer 28 and the cap layer 30. The electrodes 14 and 16 are made of metal. The insulating film 36 is made of an insulator such as silicon nitride (SiN).

[0024] When using the photodetector 100, a reverse bias voltage is applied to the photodetector 100. A positive voltage is applied to electrode 14. A negative voltage is applied to electrode 16. The semiconductor layer of mesa 10 is depleted. An electric field is applied below mesa 13 in the Z-axis direction. For example, infrared light is incident on the photodetector region 11. The photodetector layer 28 absorbs the infrared light and generates carriers (electron-hole pairs). The carriers move due to the electric field and are output as a photocurrent. The number of carriers increases as they collide with atoms in the multiplier layer 24. High sensitivity is obtained.

[0025] Figures 3A to 3D are cross-sectional views illustrating the photodetector 100. The depletion region 50 is shown by a dashed line. Depletion progresses from Figure 3A to Figure 3C in response to the application of voltage.

[0026] As shown in Figure 3A, when a voltage is applied, the multiplier layer 24 is depleted first, followed by the electric field relaxation layer 26. As shown in Figure 3B, the light-receiving layer 28 is also depleted. As shown in Figure 3C, the capping layer 30 is also depleted. Since the multiplier layer 24 in the recess 40 is depleted first, the width of the depletion region 50 is determined by the recess 40. That is, the width of the depletion region 50 is approximately the same as the width W1 of the multiplier layer 24 and narrower than the width W2 of the light-receiving layer 28. The portions of the light-receiving layer 28 and the capping layer 30 directly above the recess 40 are depleted. The portions of the light-receiving layer 28 and the capping layer 30 that protrude beyond the recess 40 are not depleted.

[0027] An electric field is applied to the depleted layer during the depletion process. The portions of the light-receiving layer 28 and the capping layer 30 that protrude beyond the recess 40 are not depleted and are therefore less susceptible to the electric field. Because electric field concentration at the edge of the light-receiving layer 28 is less likely to occur, the dark current can be reduced.

[0028] The dotted line in Figure 3D schematically represents the electric field. The electric field extends from the capping layer 30 to the multiplier layer 24. The electric field is constricted by the mesa 13. The width of the electric field is defined by the mesa 13. In the Z-axis direction, the electric field is present in the area directly below the mesa 13. In the XY plane, the electric field is less likely to be present in the area outside the mesa 13. The electric field is present in the capping layer 30 and the portion of the light-receiving layer 28 that overlaps with the mesa 13. The electric field is less likely to be present in the portion of the capping layer 30 and the light-receiving layer 28 that is outside the mesa 13.

[0029] (Manufacturing method) Figures 4A and 4B are cross-sectional views illustrating a method for manufacturing the photodetector 100. As shown in Figure 4A, for example, a contact layer 22, a multiplier layer 24, a field relaxation layer 26, a photodetector layer 28, a cap layer 30, a cap layer 32, and a contact layer 34 are epitaxially grown on one surface of the substrate 20 by metal-organic chemical vapor deposition (MOCVD).

[0030] As shown in Figure 4B, for example, wet etching is performed to form terraces 12, mesa 10, and mesa 13. The recess 40 of mesa 10 is formed by utilizing the etching selectivity ratio between the photodetector layer 28 and the multiplier layer 24. Because the etching rate of the multiplier layer 24 is higher than that of the photodetector layer 28, side etching proceeds and the recess 40 is formed. The semiconductor layer material and etchant are selected so that the etching rate is of an appropriate size. For example, an etchant containing citric acid is used for the photodetector layer 28 made of AlGaAsSb and the multiplier layer 24 made of InGaAs.

[0031] Multiple etching steps may be performed. Mesa 10 and mesa 13 can be formed by changing the mask or etchant. Multiple wet etching steps may be performed. Wet etching and dry etching may be performed. For example, mesa 10 and mesa 13 are formed by dry etching. A recess 40 is formed in mesa 10 by wet etching.

[0032] After forming mesa 10 and mesa 13, an insulating film 36 is deposited by plasma CVD (PECVD: Plasma Enhanced CVD) or the like. Openings are formed in the portion of the insulating film 36 above terrace 12. Openings are also formed in the portion of the insulating film 36 above contact layer 34. Electrodes 14 and 16 are formed by vacuum deposition and lift-off. The photodetector 100 is then formed.

[0033] (Comparative example) Figure 5 is a cross-sectional view illustrating a photodetector 110 according to a comparative example. The mesa 10 does not have recesses or wide sections. The photodetector layer 28, the field relaxation layer 26, and the multiplier layer 24 have the same width.

[0034] The dashed line in Figure 5 represents the depletion region 50. The width of the depletion region 50 is the same as the width of the mesa 10. That is, the depletion region 50 extends to the side of the mesa 10. The dark current increases as the electric field concentrates at the edge of the photodetector layer 28.

[0035] According to one embodiment, as shown in Figure 2, the mesa 10 includes a multiplier layer 24, an electric field relaxation layer 26, a light-receiving layer 28, and a cap layer 30. The wide portion 42 of the mesa 10 includes the light-receiving layer 28. The recess 40 of the mesa 10 includes the multiplier layer 24. The width W1 of the multiplier layer 24 is smaller than the width W2 of the light-receiving layer 28. When a voltage is applied to the light-receiving element 100, depletion occurs sequentially from the multiplier layer 24 to the cap layer 30. As shown in Figures 3A to 3D, the width of the depletion region 50 is approximately the same as the width W1 of the multiplier layer 24 and smaller than the width W2 of the light-receiving layer 28. Because the electric field is less likely to be applied to the edge of the light-receiving layer 28, the dark current can be reduced.

[0036] The recess 40 includes a multiplier layer 24 and an electric field relaxation layer 26. In response to the application of voltage, the multiplier layer 24 and the electric field relaxation layer 26 are depleted. A high electric field is applied to the multiplier layer 24, accelerating carriers and causing them to collide with atoms in the multiplier layer 24, generating even more carriers. In other words, the photodetector 100 is an avalanche photodiode and has high sensitivity. The widths of the multiplier layer 24 and the electric field relaxation layer 26 are smaller than the width W2 of the photodetector layer 28. Because the electric field is less likely to be applied to the edges of the photodetector layer 28, the dark current can be reduced.

[0037] The light-receiving layer 28 is made of InGaAs. The multiplier layer 24 is made of AlGaAsSb. Because there is an etching selectivity ratio between these layers, the recesses 40 and wide portions 42 of the mesa 10 can be formed by wet etching. A citric acid-based substance such as an aqueous citric acid solution or citric acid hydrochloride is used as the etchant. The etching rate of the multiplier layer 24 is higher than the etching rate of the light-receiving layer 28. The multiplier layer 24 is side-etched, and the recesses 40 are formed.

[0038] The doping concentration of the multiplier layer 24 is lower than that of the contact layer 22. For example, the multiplier layer 24 may be undoped or n-type. When a voltage is applied to the photodetector 100, the depletion region 50 expands from the multiplier layer 24. The width of the depletion region 50 is determined by the multiplier layer 24 and is narrower than that of the photodetector layer 28. Since the electric field is less likely to be applied to the part of the photodetector layer 28 outside the recess 40, the dark current can be reduced. As shown in Figure 3D, the part of the photodetector layer 28 that overlaps with the recess 40 in the Z-axis direction is depleted and can output carriers.

[0039] As shown in Figure 2, the cap layer 32 and the contact layer 34 form a mesa 13. The width W3 of the mesa 13 is smaller than the width W1 of the multiplier layer 24 and the width W2 of the photodetector layer 28. As shown in Figure 3D, the electric field is constricted by the mesa 13 and acts on the portion directly beneath the mesa 13. The central part of the photodetector layer 28 is located directly beneath the mesa 13 and is subjected to the constricted electric field. Carriers generated in the photodetector layer 28 are moved by the electric field. The edges of the photodetector layer 28 are located outside the mesa 13, making it difficult for the electric field to concentrate there. Dark current can be reduced.

[0040] A capping layer 30 is provided between the light-receiving layer 28 and the capping layer 32. The capping layer 30 is i-type or p-type and is depleted. This reduces the capacitance of the light-receiving element 100. High-speed operation is possible.

[0041] The contact layer 22 is n-type. The cap layer 32 and contact layer 34 are p-type. The light-receiving layer 28 is i-type. A pin junction is formed. A depletion region 50 is generated in the mesa 10 in response to the application of voltage. Light incident from the light-receiving region 11 can be detected.

[0042] A p-type semiconductor layer may be provided between the light-receiving layer 28 and the substrate 20, and an n-type semiconductor layer may be provided on the opposite side of the light-receiving layer 28 from the substrate 20. The light-receiving element 100 may be a photodiode other than an avalanche photodiode.

[0043] Although embodiments of this disclosure have been described in detail above, this disclosure is not limited to these specific embodiments, and various modifications and changes are possible within the scope of the gist of this disclosure as described in the claims. [Explanation of Symbols]

[0044] 10, 13 Mesas 11 Light receiving area 12 Terrace 14, 16 electrodes 17 Outer perimeter 19, 40 recess 20 circuit boards 22, 34 Contact layer 24 multiplier layers 26. Electric field relaxation layer 28 Light-receiving layer 30, 32 cap layers 36 Insulating Film 42 Wide section 100, 110 light-receiving elements

Claims

1. A first semiconductor layer having a first conductivity type, The second semiconductor layer, The light-receiving layer, It comprises a third semiconductor layer having a second conductivity type, The first semiconductor layer, the second semiconductor layer, the light-receiving layer, and the third semiconductor layer are stacked in this order. The second semiconductor layer, the light-receiving layer, and the third semiconductor layer form a first mesa. A photodetector in which the width of the second semiconductor layer is smaller than the width of the light-receiving layer in the direction in which the light-receiving layer expands.

2. The aforementioned second semiconductor layer includes a multiplier layer and an electric field relaxation layer, The photodetector according to claim 1, wherein the width of the multiplier layer and the width of the field relaxation layer are smaller than the width of the photodetector layer.

3. The light-receiving layer is formed of indium gallium arsenide. The photodetector according to claim 2, wherein the multiplier layer is formed of aluminum gallium arsenide antimony.

4. The photodetector according to claim 2, wherein the doping concentration of the multiplier layer is lower than the doping concentration of the first semiconductor layer.

5. The third semiconductor layer includes a second mesa, The photodetector according to claim 1 or claim 2, wherein the width of the second mesa is smaller than the width of the second semiconductor layer.

6. The present invention comprises a fourth semiconductor layer laminated between the light-receiving layer and the third semiconductor layer, The photodetector according to claim 5, wherein the fourth semiconductor layer is included in the first mesa and the second mesa.

7. The first semiconductor layer has an n-type conductivity, The photodetector according to claim 1 or claim 2, wherein the third semiconductor layer has a p-type conductivity.

8. A process of stacking a first semiconductor layer, a second semiconductor layer, a light-receiving layer, and a third semiconductor layer in this order, The process includes a step of forming a mesa by wet etching the second semiconductor layer, the light-receiving layer, and the third semiconductor layer, The first semiconductor layer has a first conductivity type, The second semiconductor layer has a second conductivity type, A method for manufacturing a photodetector, wherein, after the wet etching, the width of the second semiconductor layer is smaller than the width of the photodetector in the direction in which the photodetector expands.

9. The aforementioned second semiconductor layer includes a multiplier layer and an electric field relaxation layer, The width of the multiplier layer and the width of the electric field relaxation layer are smaller than the width of the light receiving layer. The light-receiving layer is formed of indium gallium arsenide. The multiplier layer is formed of aluminum gallium arsenide antimony. The method for manufacturing a photodetector according to claim 8, wherein the wet etching etchant contains citric acid.

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