Semiconductor equipment

Abstract

This suppresses misalignment between two wiring boards. [Solution] The semiconductor device comprises a first wiring board, an electronic component, a second wiring board, and a plurality of connecting members. The electronic component is provided on the first wiring board. The second wiring board is laminated on the first wiring board with the electronic component in between. The plurality of connecting members are arranged around the electronic component and connect the first wiring board and the second wiring board. Each of the plurality of connecting members has a pair of cores adjacent to each other in the lamination direction of the first and second wiring boards, and a conductive film covering the pair of cores. In at least the connecting members arranged in the innermost or outermost row relative to the electronic component, one of the pair of cores closer to the second wiring board is offset relative to the other core closer to the first wiring board in a direction toward or toward the electronic component.

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] In recent years, in order to achieve high-density component mounting, semiconductor devices that incorporate electronic components such as semiconductor chips inside a substrate have attracted attention. Such a semiconductor device has, for example, two wiring substrates. An electronic component such as a semiconductor chip is mounted on one wiring substrate, and such an electronic component is sandwiched between the one wiring substrate and the other wiring substrate.

[0003] The two wiring substrates are connected by a connecting member. Specifically, a conductor ball mounted on the other wiring substrate is disposed above a conductor ball mounted on the one wiring substrate, and the other wiring substrate is laminated on the one wiring substrate. The conductor ball is formed by coating a spherical core with a conductor film such as solder. Then, the conductor films of the two conductor balls mounted on the two laminated wiring substrates are melted and integrated by heat and pressure. Thereby, the two wiring substrates are connected by a connecting member having a pair of cores adjacent to each other in the stacking direction of the two wiring substrates and a conductor film covering the pair of cores.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] Incidentally, when the conductive films of two conductive balls mounted on two wiring boards melt and fuse together due to heat and pressure, the two conductive balls are pressed vertically by the two wiring boards. At this time, since the contact between the two conductive balls being pressed is a point contact, the two conductive balls tend to slip from each other. As a result, the upper conductive ball slides off the lower conductive ball, causing a misalignment between the two wiring boards that are pressing the two conductive balls.

[0006] The disclosed technology has been made in view of the above, and aims to provide a semiconductor device that can suppress misalignment between two wiring boards. [Means for solving the problem]

[0007] In one embodiment, the semiconductor device disclosed in this application includes a first wiring board, an electronic component, a second wiring board, and a plurality of connecting members. The electronic component is provided on the first wiring board. The second wiring board is laminated on the first wiring board with the electronic component in between. The plurality of connecting members are arranged around the electronic component and connect the first wiring board and the second wiring board. Each of the plurality of connecting members has a pair of cores adjacent to each other in the lamination direction of the first and second wiring boards, and a conductive film covering the pair of cores. In at least the connecting members arranged in the innermost or outermost row relative to the electronic component, one of the pair of cores closer to the second wiring board is offset relative to the other core closer to the first wiring board in a direction toward or toward the electronic component. [Effects of the Invention]

[0008] According to one embodiment of the semiconductor device disclosed in this application, the effect is achieved that misalignment between two wiring boards can be suppressed. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 is a diagram showing the configuration of a semiconductor device according to an embodiment. [Figure 2] Figure 2 shows an example of the arrangement of multiple connecting members, a lower core, and an upper core according to the embodiment. [Figure 3] Figure 3 shows another example of the arrangement of multiple connecting members, a lower core, and an upper core according to the embodiment. [Figure 4] Figure 4 is a flowchart showing the method for manufacturing the first wiring board according to the embodiment. [Figure 5] Figure 5 is a schematic diagram showing a cross-section of the first wiring board. [Figure 6] Figure 6 is a diagram illustrating the mounting of electronic components. [Figure 7] Figure 7 shows a specific example of the conductive ball mounting process. [Figure 8] Figure 8 is a flowchart showing the method for manufacturing the second wiring board according to the embodiment. [Figure 9] Figure 9 is a schematic diagram showing a cross-section of the second wiring board. [Figure 10] Figure 10 shows a specific example of the conductive ball mounting process. [Figure 11] Figure 11 is a flowchart showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 12] Figure 12 illustrates the stacking of the first and second wiring boards. [Figure 13] Figure 13 shows a specific example of the joining process. [Figure 14] Figure 14 shows a specific example of the molding process. [Figure 15] Figure 15 shows a specific example of the individualization process. [Figure 16] Figure 16 shows an example of the arrangement of multiple connecting members, a lower core, and an upper core according to Modification 1 of the Embodiment. [Figure 17] Figure 17 shows an example of the arrangement of multiple connecting members, a lower core, and an upper core according to a modified example 2 of the embodiment. [Figure 18] Figure 18 shows an example of the arrangement of multiple connecting members, a lower core, and an upper core according to a modified example 3 of the embodiment. [Figure 19]FIG. 19 is a diagram showing an example of the arrangement of a plurality of connection members, a lower core, and an upper core according to Modification 4 of the embodiment. [Figure 20] FIG. 20 is a diagram showing an example of the arrangement of a plurality of connection members, a lower core, and an upper core according to Modification 5 of the embodiment. [Figure 21] FIG. 21 is a diagram showing an example of the arrangement of a plurality of connection members, a lower core, and an upper core according to Modification 6 of the embodiment.

BEST MODE FOR CARRYING OUT THE INVENTION

[0010] Hereinafter, embodiments of the semiconductor device disclosed in the present application will be described in detail based on the drawings. Note that the techniques disclosed by this embodiment are not limited thereto.

[0011] (Embodiment) FIG. 1 is a diagram showing the configuration of a semiconductor device 100 according to the embodiment. In FIG. 1, a cross-section of the semiconductor device 100 is schematically shown. Hereinafter, for convenience, the direction from the first wiring board 110 to the second wiring board 120 is defined as the upward direction, the direction from the second wiring board 120 to the first wiring board 110 is defined as the downward direction, and the vertical direction of the semiconductor device 100 is defined accordingly. However, the semiconductor device 100 may be manufactured and used, for example, with the top and bottom reversed, or may be manufactured and used in any orientation.

[0012] The semiconductor device 100 shown in FIG. 1 has stacked first and second wiring boards 110 and 120, and has a sealing resin 101 that covers an electronic component 140 disposed between the first wiring board 110 and the second wiring board 120. Specifically, the semiconductor device 100 is configured such that the first wiring board 110 and the second wiring board 120 are connected by a plurality of connection members 130. An electronic component 140 is mounted on the upper surface of the first wiring board 110. This electronic component 140 is sandwiched between the first wiring board 110 and the second wiring board 120 and is covered with the sealing resin 101. A plurality of connection members 130 are arranged around the electronic component 140.

[0013] The sealing resin 101 is an insulating resin such as a thermosetting epoxy resin containing an inorganic filler such as alumina, silica, aluminum nitride, or silicon carbide. The electronic component 140 is, for example, a semiconductor chip.

[0014] The first wiring board 110 includes a substrate 111, a protective insulating layer 112 (an example of the first insulating layer), an upper pad 113, a solder resist layer 114, and a lower pad 115. Although not shown in Figure 1, the upper pad 113 and the lower pad 115 are electrically connected by via wiring provided in the substrate 111.

[0015] The substrate 111 is an insulating plate-shaped member and is the base material for the first wiring board 110. As the material for the substrate 111, for example, a glass epoxy resin can be used, which is obtained by impregnating a reinforcing material, such as glass cloth (glass woven fabric), with a thermosetting insulating resin mainly composed of epoxy resin and then curing it. The reinforcing material is not limited to glass cloth; for example, glass nonwoven fabric, aramid woven fabric, aramid nonwoven fabric, liquid crystal polymer (LCP) woven fabric, and LCP nonwoven fabric can be used. In addition to epoxy resin, other thermosetting insulating resins such as polyimide resin and cyanate resin can also be used. Wiring layers, including an upper pad 113 and a lower pad 115, are formed on both sides of the substrate 111. As the material for the wiring layers, for example, copper or a copper alloy can be used.

[0016] The substrate 111 is not limited to a single-layer insulating material, but may also be a multilayer substrate with an insulating layer and a wiring layer laminated together. When the substrate 111 is a multilayer substrate, the wiring layers sandwiching the insulating layer are electrically connected by vias that penetrate the insulating layer. As the material for the insulating layer, for example, insulating resins such as epoxy resin and polyimide resin, or resin materials in which fillers such as silica and alumina are mixed into these resins can be used. As the material for the wiring layer, for example, copper (Cu) or a copper alloy can be used.

[0017] The protective insulating layer 112 is an insulating layer that covers the upper surface of the substrate 111. An opening is provided in a part of the protective insulating layer 112, and the upper surface pad 113 is exposed through the opening. As the material for the protective insulating layer 112, an insulating resin such as epoxy resin or acrylic resin can be used.

[0018] The top pad 113 is formed in the wiring layer on the top surface of the substrate 111 and is exposed through an opening in the protective insulating layer 112 for connection to the connecting member 130 and mounting of the electronic component 140. Specifically, the connecting member 130 is connected to the top pad 113a of the top pad 113. The top pad 113a includes an inner pad 113-1 (an example of a first pad) and an outer pad 113-2. The inner pad 113-1 is connected to the connecting member 130a, which is arranged in the innermost row relative to the electronic component 140 among the multiple connecting members 130, and the outer pad 113-2 is connected to the connecting member 130b, which is located further away from the electronic component 140 than the connecting member 130a. The electronic component 140 is connected to the top pad 113b of the top pad 113. Specifically, for example, the electronic component 140 is flip-chip connected to the top pad 113b by a solder bump 141. Then, an underfill material 142 is filled between the first wiring board 110 and the electronic component 140. As for the material of the top pad 113, similar to the wiring layer, for example, copper or a copper alloy can be used.

[0019] The solder resist layer 114 is an insulating layer that covers the underside of the substrate 111. An opening is provided in a part of the solder resist layer 114, and the underside pad 115 is exposed through the opening. As the material for the solder resist layer 114, an insulating resin such as epoxy resin or acrylic resin can be used.

[0020] The bottom pad 115 is formed in the wiring layer on the bottom surface of the substrate 111 and is exposed through an opening in the solder resist layer 114 for the formation of external connection terminals. That is, external connection terminals (not shown), such as solder balls, are formed on the bottom pad 115. As for the material of the bottom pad 115, copper or a copper alloy can be used, similar to the wiring layer.

[0021] The second wiring board 120 includes a substrate 121, a solder resist layer 122, an upper pad 123, a protective insulating layer 124 (an example of a second insulating layer), and a lower pad 125. Although not shown in Figure 1, the upper pad 123 and the lower pad 125 are electrically connected by via wiring provided in the substrate 121.

[0022] The substrate 121 is an insulating plate-shaped member and serves as the base material for the second wiring board 120. As the material for the substrate 121, for example, a glass epoxy resin can be used, which is obtained by impregnating a reinforcing material, such as glass cloth (glass woven fabric), with a thermosetting insulating resin mainly composed of epoxy resin and then curing it. The reinforcing material is not limited to glass cloth; for example, glass nonwoven fabric, aramid woven fabric, aramid nonwoven fabric, LCP woven fabric, and LCP nonwoven fabric can be used. Furthermore, as the thermosetting insulating resin, in addition to epoxy resin, for example, polyimide resin and cyanate resin can be used. Wiring layers, including an upper pad 123 and a lower pad 125, are formed on both sides of the substrate 121. As the material for the wiring layers, for example, copper or a copper alloy can be used.

[0023] The substrate 121 is not limited to a single-layer insulating material, but may also be a multilayer substrate with an insulating layer and a wiring layer laminated together. When the substrate 121 is a multilayer substrate, the wiring layers sandwiching the insulating layer are electrically connected by vias that penetrate the insulating layer. As the material for the insulating layer, for example, insulating resins such as epoxy resin and polyimide resin, or resin materials in which fillers such as silica and alumina are mixed into these resins can be used. As the material for the wiring layer, for example, copper (Cu) or a copper alloy can be used.

[0024] The solder resist layer 122 is an insulating layer that covers the upper surface of the substrate 121. An opening is provided in a part of the solder resist layer 122, and the upper surface pad 123 is exposed through the opening. As the material for the solder resist layer 122, an insulating resin such as epoxy resin or acrylic resin can be used.

[0025] The top pad 123 is formed on the wiring layer on the top surface of the substrate 121 and is exposed through an opening in the solder resist layer 122 for the formation of external connection terminals. That is, external connection terminals (not shown), such as solder balls, are formed on the top pad 123. As for the material of the top pad 123, copper or a copper alloy can be used, similar to the wiring layer.

[0026] The protective insulating layer 124 is an insulating layer that covers the lower surface of the substrate 121. An opening is provided in a part of the protective insulating layer 124, and the lower surface pad 125 is exposed through the opening. As the material for the protective insulating layer 124, an insulating resin such as epoxy resin or acrylic resin can be used.

[0027] The bottom pad 125 is formed in the wiring layer on the bottom surface of the substrate 121 and is exposed through an opening in the protective insulating layer 124 for connection with the connecting member 130. That is, the connecting member 130 is bonded to the bottom pad 125. The bottom pad 125 includes an inner pad 125-1 (an example of a second pad) and an outer pad 125-2. The inner pad 125-1 is connected to the connecting member 130a, which is arranged in the innermost row relative to the electronic component 140 among the multiple connecting members 130, and the outer pad 125-2 is connected to the connecting member 130b, which is located further away from the electronic component 140 than the connecting member 130a. As for the material of the bottom pad 125, similar to the wiring layer, for example, copper or a copper alloy can be used.

[0028] Multiple connecting members 130 are arranged around the electronic component 140 to connect the first wiring board 110 and the second wiring board 120. Each of the multiple connecting members 130 has a spherical lower core 131 and an upper core 132 (an example of a pair of cores) adjacent to each other in a direction parallel to the stacking direction Z of the first wiring board 110 and the second wiring board 120, and solder 133 (an example of a conductive film) covering the lower core 131 and the upper core 132. The lower core 131 is the core that is relatively closer to the first wiring board 110 among the lower core 131 and the upper core 132, and the upper core 132 is the core that is relatively closer to 120 among the lower core 131 and the upper core 132. For the lower core 131 and the upper core 132, metal cores made of metals such as copper (Cu), gold (Au), and nickel (Ni), or resin cores made of resin can be used. As the solder 133, for example, an alloy containing lead (Pb), an alloy of tin (Sn) and copper (Cu), an alloy of tin (Sn) and antimony (Sb), an alloy of tin (Sn) and silver (Ag), an alloy of tin (Sn), silver (Ag), and copper (Cu) can be used. Each of the multiple connecting members 130 is formed by covering the lower core 131 with solder and integrating the solder of the conductor ball mounted on the first wiring board 110 with the solder of the upper core 132 and mounted on the second wiring board 120.

[0029] Figure 2 shows an example of the arrangement of multiple connecting members 130, a lower core 131, and an upper core 132 according to the embodiment. In Figure 2, a top view of the semiconductor device 100 as seen from the stacking direction Z (see Figure 1) is shown. Note that in Figure 2, for the sake of explanation, the second wiring board 120, sealing resin 101, solder 133, etc. are omitted from the illustration.

[0030] As shown in Figure 2, in the semiconductor device 100 according to this embodiment, in at least the connection member 130a arranged in the innermost row relative to the electronic component 140 among the plurality of connection members 130, the upper core 132 is offset relative to the lower core 131 in a direction that moves toward the electronic component 140. For example, in the 16 connection members 130a arranged in the innermost row among the plurality of connection members 130 shown in Figure 2, the upper core 132 is offset relative to the lower core 131 in a direction that moves toward the electronic component 140.

[0031] Let's assume that in all of the multiple connecting members 130, the positions of the upper core 132 and the lower core 131 are aligned along the stacking direction Z (see Figure 1). In this case, when the solder of the two conductor balls mounted on the first wiring board 110 and the second wiring board 120 melts and fuses together due to heat and pressure, the contact between the two pressurized conductor balls is a point contact, making the two conductor balls prone to slipping from each other. As a result, the upper conductor ball may slip off the lower conductor ball, potentially causing misalignment between the first wiring board 110 and the second wiring board 120 that pressurize the two conductor balls.

[0032] In contrast, in the semiconductor device 100 according to the embodiment, the upper core 132 of the connecting member 130a, which is arranged in the innermost row of the plurality of connecting members 130, is offset relative to the lower core 131 in a direction toward the electronic component 140. Therefore, when the solder of the two conductive balls mounted on the first wiring board 110 and the second wiring board 120 melts and becomes one due to heat and pressure, stress acts from the lower core 131 to the upper core 132 in a direction toward the electronic component 140, and the sliding of the upper conductive ball is restricted. Accordingly, according to the semiconductor device 100 according to the embodiment, the positions of the two conductive balls mounted on the first wiring board 110 and the second wiring board 120 can be fixed, and as a result, misalignment between the first wiring board 110 and the second wiring board 120 can be suppressed.

[0033] Furthermore, the multiple connecting members 130 may be arranged on multiple (in this case, two) frame lines L1 and L2 that surround the outer circumference of the electronic component 140 and are at different distances from the center of the electronic component 140, in a plan view from the stacking direction Z (see Figure 1). The multiple frame lines L1 and L2 may, for example, have a rectangular shape. In the connecting member 130a arranged on the frame line L1 closest to the electronic component 140, the upper core 132 may be offset relative to the lower core 131 in a direction that moves closer to the electronic component 140.

[0034] With this configuration, the sliding of the upper core 132 can be easily limited at the connecting member 130a arranged on the frame line L1 closest to the electronic component 140. Therefore, with the semiconductor device 100 having this configuration, the positions of the two conductive balls mounted on the first wiring board 110 and the second wiring board 120 can be fixed with a simple configuration, and as a result, misalignment between the first wiring board 110 and the second wiring board 120 can be efficiently suppressed.

[0035] The direction in which the upper core 132 is offset from the lower core 131 may be either towards the center C of the electronic component 140 or away from the center C of the electronic component 140. The center C of the electronic component 140 may be, for example, the intersection of two diagonals on the upper surface of the electronic component 140 when the electronic component 140 is formed in a rectangular shape in a plan view from the stacking direction Z (see Figure 1).

[0036] Figure 3 shows another example of the arrangement of the multiple connecting members 130, the lower core 131, and the upper core 132 according to the embodiment. In Figure 3, a top view of the semiconductor device 100 as seen from the stacking direction Z (see Figure 1) is shown. Note that in Figure 3, for the sake of explanation, the second wiring board 120, sealing resin 101, solder 133, etc. are omitted from the illustration.

[0037] As shown in Figure 3, in the case of a connecting member 130a that is arranged on the rectangular frame line L1 closest to the electronic component 140 and is not located at the four corners of the frame line L1, the upper core 132 may be offset relative to the lower core 131. In other words, in the case of a connecting member 130a located at the four corners of the rectangular frame line L1, the upper core 132 does not have to be offset relative to the lower core 131. This reduces the possibility of interference between a connecting member 130a located at the four corners of the rectangular frame line L1 and other connecting members 130a adjacent to that connecting member 130a.

[0038] Next, a method for manufacturing the semiconductor device 100 configured as described above will be explained. Below, a method for manufacturing the first wiring board 110 and a method for manufacturing the second wiring board 120 will be explained, followed by a method for manufacturing the semiconductor device 100 having the first wiring board 110 and the second wiring board 120.

[0039] Figure 4 is a flowchart showing the manufacturing method of the first wiring board 110 according to the embodiment.

[0040] First, wiring layers are formed on the upper and lower surfaces of the substrate 111 (step S101). Specifically, the wiring layers on the upper and lower surfaces of the substrate 111 are formed sequentially, for example, by a semi-additive method. The wiring layer on the upper surface of the substrate 111 includes an upper pad 113, and the wiring layer on the lower surface of the substrate 111 includes a lower pad 115. Then, a solder resist layer 114 having an opening at the position of the lower pad 115 is formed on the lower surface of the substrate 111 (step S102), and a protective insulating layer 112 having an opening at the position of the upper pad 113 is formed on the upper surface of the substrate 111 (step S103). The protective insulating layer 112 and the solder resist layer 114 can be obtained, for example, by laminating a photosensitive resin film onto the upper and lower surfaces of the substrate 111, or by applying a liquid or paste-like resin, and then exposing and developing the laminated or applied resin by photolithography to pattern it into the desired shape.

[0041] Through the steps completed so far, a first wiring board 110 is formed in which, for example as shown in Figure 5, the upper surface pads 113a and 113b are exposed on the upper surface of the substrate 111 through the opening 112a of the protective insulating layer 112, and the lower surface pad 115 is exposed on the lower surface of the substrate 111 through the opening 114a of the solder resist layer 114. Figure 5 is a schematic diagram showing a cross-section of the first wiring board. The upper surface pad 113a is a pad that connects to the connecting member 130, and includes an inner pad 113-1 and an outer pad 113-2. The inner pad 113-1 is a pad that connects to the connecting member 130a which is arranged in the innermost row relative to the electronic component 140 among the multiple connecting members 130, and the outer pad 113-2 is a pad that connects to the connecting member 130b which is located further away from the electronic component 140 than the connecting member 130a. The upper surface pad 113b is a pad that flip-chip connects the electronic component 140. The exposed areas of these upper pads 113a and 113b may be different from each other. Furthermore, the width of the exposed portion of the upper pad 113a can be, for example, about 120 to 160 μm.

[0042] Solder paste is printed on the top pad 113b because an electronic component 140 will be mounted there (step S104). Then, the electronic component 140 is mounted at the position of the top pad 113b (step S105). The electronic component 140 is mounted on the first wiring board 110 after undergoing a reflow process (step S106). In addition, if necessary, an underfill material 142 made of insulating resin is filled between the electronic component 140 and the top surface of the first wiring board 110 (step S107).

[0043] As a result of the steps taken so far, an electronic component 140, which is flip-chip connected to the top pad 113b by solder bumps 141, is mounted on the top surface of the first wiring board 110, for example, as shown in Figure 6. Figure 6 is a diagram illustrating the mounting of the electronic component 140.

[0044] When the electronic components 140 are mounted on the upper surface of the first wiring board 110, a conductive ball 130A (an example of a first conductive ball) used to form the connecting member 130 is mounted at the position of the upper pad 113a (step S108). The conductive ball 130A is formed by covering the lower core 131 with solder 133. Then, through a reflow process (step S109), the conductive ball 130A is joined to the upper pad 113a by the solder 133 around the lower core 131.

[0045] Through the steps described so far, the conductive balls 130A are bonded to the upper pad 113a, as shown in Figure 7. This yields the first wiring board 110, which forms the lower layer of the semiconductor device 100. Figure 7 shows a specific example of the conductive ball mounting process. Electronic components 140 are mounted on the upper surface of the obtained first wiring board 110, and the conductive balls 130A are bonded to the upper pad 113a exposed through the opening in the protective insulating layer 112. The diameter of the conductive balls 130A can be, for example, about 100 to 250 μm.

[0046] Furthermore, it is preferable that the first wiring board 110 is not manufactured as a single unit, but rather as an assembly of multiple first wiring boards 110 arranged in a grid. In the assembly, for example, the first wiring board 110 is manufactured in individual sections divided in a grid pattern.

[0047] Next, Figure 8 is a flowchart showing the manufacturing method of the second wiring board 120 according to the embodiment.

[0048] First, wiring layers are formed on the upper and lower surfaces of the substrate 121 (step S201). Specifically, the wiring layers on the upper and lower surfaces of the substrate 121 are formed sequentially, for example, by a semi-additive method. The wiring layer on the upper surface of the substrate 121 includes an upper pad 123, and the wiring layer on the lower surface of the substrate 121 includes a lower pad 125. Then, a protective insulating layer 124 having an opening at the position of the lower pad 125 is formed on the lower surface of the substrate 121 (step S202), and a solder resist layer 122 having an opening at the position of the upper pad 123 is formed on the upper surface of the substrate 121 (step S203). The solder resist layer 122 and the protective insulating layer 124 can be obtained, for example, by laminating a photosensitive resin film onto the upper and lower surfaces of the substrate 121, or by applying a liquid or paste-like resin, and then exposing and developing the laminated or applied resin by photolithography to pattern it into the desired shape.

[0049] Through the steps described so far, a second wiring board 120 is formed in which, for example as shown in Figure 9, the upper pad 123 is exposed on the upper surface of the substrate 121 through an opening 122a in the solder resist layer 122, and the lower pad 125 is exposed on the lower surface of the substrate 121 through an opening 124a in the protective insulating layer 124. Figure 9 is a schematic diagram showing a cross-section of the second wiring board. The lower pad 125 is a pad that connects to the connecting member 130, and includes an inner pad 125-1 and an outer pad 125-2. The inner pad 125-1 is a pad that connects to the connecting member 130a which is arranged in the innermost row relative to the electronic component 140 among the plurality of connecting members 130, and the outer pad 125-2 is a pad that connects to the connecting member 130b which is located further away from the electronic component 140 than the connecting member 130a.

[0050] Furthermore, the inner pad 125-1 is positioned offset from the inner pad 113-1 in a direction that moves it closer to the electronic component 140. This allows the position of the inner pad 125-1 to be offset to a position suitable for connection with the connecting member 130a, which is arranged in the innermost row relative to the electronic component 140.

[0051] Furthermore, the opening 124a of the protective insulating layer 124 is offset relative to the opening 112a of the protective insulating layer 112 in a direction toward the electronic component 140. This allows the area of ​​the inner pad 125-1 exposed from the opening 124a of the protective insulating layer 124 to be maintained at an area suitable for connection with the connecting member 130a arranged in the innermost row relative to the electronic component 140.

[0052] Since the connecting member 130 is connected to the lower pad 125, a conductive ball 130B (an example of a second conductive ball) used to form the connecting member 130 is mounted at the position of the lower pad 125 (step S204). The conductive ball 130B is formed by covering the upper core 132 with solder 133. Then, through a reflow process (step S205), the conductive ball 130B is joined to the lower pad 125 by the solder 133 around the upper core 132.

[0053] Through the steps described so far, the conductive balls 130B are bonded to the bottom pad 125, as shown in Figure 10. This yields the second wiring board 120 that forms the upper layer of the semiconductor device 100. Figure 10 shows a specific example of the conductive ball mounting process. In the obtained second wiring board 120, the conductive balls 130B are bonded to the bottom pad 125 that is exposed from the opening of the protective insulating layer 124. The diameter of the conductive balls 130B can be, for example, about 100 to 250 μm, similar to the conductive balls 130A. The diameter of the conductive balls 130B may differ from that of the conductive balls 130A.

[0054] Furthermore, it is preferable that the second wiring board 120 is not manufactured individually, but rather as an assembly of multiple second wiring boards 120 arranged in a grid. In the assembly, for example, the second wiring board 120 is manufactured in individual sections divided in a grid pattern.

[0055] Next, Figure 11 is a flowchart illustrating a method for manufacturing the semiconductor device 100 according to the embodiment. The semiconductor device 100 is manufactured using the first wiring board 110 and the second wiring board 120 described above.

[0056] The first wiring board 110 and the second wiring board 120 are joined together, for example, by the Thermal Compression Bonding (TCB) method (step S301). First, as shown in Figure 12, for example, a conductor ball 130B bonded to the lower pad 125 of the second wiring board 120 is placed above a conductor ball 130A bonded to the upper pad 113a of the first wiring board 110, and the second wiring board 120 is stacked on top of the first wiring board 110. Figure 12 is a diagram illustrating the stacking of the first wiring board 110 and the second wiring board 120. An electronic component 140 is placed between the first wiring board 110 and the second wiring board 120. The inner pad 125-1 of the second wiring board 120 is offset from the inner pad 113-1 of the first wiring board 110 in the direction toward the electronic component 140. The conductor ball 130B bonded to the inner pad 125-1 of the second wiring board 120 is positioned offset from the conductor ball 130A bonded to the inner pad 113-1 of the first wiring board 110, in a direction toward the electronic component 140.

[0057] From the viewpoint of properly integrating the solder 133 of the conductor ball 130A and the solder 133 of the conductor ball 130B, it is preferable that the offset amount d of the upper core 132 relative to the lower core 131 be smaller than the diameter of the conductor ball 130A or the conductor ball 130B. For example, the offset amount d can be about 1 to 10% of the diameter of the conductor ball 130A or the conductor ball 130B. If the diameters of the conductor ball 130A and the conductor ball 130B are different, the offset amount d is adjusted based on the diameter of the larger conductor ball. Also, if the diameters of the conductor ball 130A and the conductor ball 130B are different, the second wiring board 120, which does not have electronic components mounted and does not have underfill material formed on it, has a higher degree of design freedom, and it is preferable to make the diameter of the conductor ball 130B larger than that of the conductor ball 130A.

[0058] Next, the solder 133 of the conductor ball 130A and the solder 133 of the conductor ball 130B are melted and integrated by heat and pressure, forming a connecting member 130 having a lower core 131, an upper core 132, and solder 133. As a result, the first wiring board 110 and the second wiring board 120 are joined by multiple connecting members 130, for example, as shown in Figure 13. At this time, due to the offset between the conductor ball 130B joined to the inner pad 125-1 and the conductor ball 130A joined to the inner pad 113-1, stress acts from the lower core 131 to the upper core 132 in a direction toward the electronic component 140. This limits the sliding of the upper conductor ball 130B, and the positions of the two conductor balls 130A and 130B mounted on the first wiring board 110 and the second wiring board 120 can be fixed. As a result, misalignment between the first wiring board 110 and the second wiring board 120 can be suppressed. Figure 13 shows a specific example of the joining process.

[0059] Then, for example, by performing a transfer mold (step S302), the sealing resin 101 is filled into the space between the first wiring board 110 and the second wiring board 120. In the transfer mold, the joined first wiring board 110 and the second wiring board 120 are placed in a mold, and the fluidized sealing resin 101 is injected into the mold. The sealing resin 101 is then heated to a predetermined temperature (for example, 175 degrees) and cured. As a result, as shown in Figure 14, for example, the sealing resin 101 is filled into the space between the first wiring board 110 and the second wiring board 120, sealing the connecting member 130 and the electronic component 140. Figure 14 is a diagram showing a specific example of the molding process.

[0060] Through the steps performed so far, a structure having the same structure as the semiconductor device 100 is obtained, for example, as shown in Figure 14. Since this structure is composed of an assembly containing a plurality of first wiring boards 110 and an assembly containing a plurality of second wiring boards 120, the individual first wiring boards 110 and second wiring boards 120 are cut out to form individual pieces (step S303). Figure 15 shows a specific example of the piece formation process. Specifically, the structure shown in Figure 15 is cut along a cutting line A located outside the connecting member 130b, for example, by a dicer or slicer, to obtain the semiconductor device 100.

[0061] (modified version) Next, various modifications of the embodiment will be described with reference to Figures 16 to 21. In the modifications shown below, the same reference numerals are used for parts that are the same as in the embodiment, and redundant explanations may be omitted.

[0062] Figure 16 shows an example of the arrangement of multiple connecting members 130, a lower core 131, and an upper core 132 according to a modified example of the embodiment 1. In Figure 16, a top view of the semiconductor device 100 as seen from the stacking direction Z (see Figure 1) is shown. Note that in Figure 16, for the sake of explanation, the second wiring board 120, sealing resin 101, solder 133, etc. are omitted from the illustration.

[0063] As shown in Figure 16, in the semiconductor device 100 according to the modified example 1, in all of the multiple connecting members 130, the upper core 132 is offset relative to the lower core 131 in a direction that moves it closer to the electronic component 140.

[0064] This configuration allows for more stable fixing of the positions of the two conductive balls mounted on the first wiring board 110 and the second wiring board 120, and as a result, positional misalignment between the first wiring board 110 and the second wiring board 120 can be further suppressed.

[0065] The direction in which the upper core 132 is offset from the lower core 131 may be either towards the center C of the electronic component 140 or away from the center C of the electronic component 140. The center C of the electronic component 140 may be, for example, the intersection of two diagonals on the upper surface of the electronic component 140 when the electronic component 140 is formed in a rectangular shape in a plan view from the stacking direction Z (see Figure 1).

[0066] Figure 17 shows an example of the arrangement of multiple connecting members 130, a lower core 131, and an upper core 132 according to a modified example 2 of the embodiment. In Figure 17, a top view of the semiconductor device 100 as seen from the stacking direction Z (see Figure 1) is shown. Note that in Figure 17, for the sake of explanation, the second wiring board 120, sealing resin 101, solder 133, etc. are omitted from the illustration.

[0067] As shown in Figure 17, in the semiconductor device 100 according to the modified example 2, in at least the outermost row of connection members 130b among the plurality of connection members 130, the upper core 132 is offset relative to the lower core 131 in a direction away from the electronic component 140. For example, in the 24 connection members 130a arranged in the outermost row among the plurality of connection members 130 shown in Figure 17, the upper core 132 is offset relative to the lower core 131 in a direction closer to the electronic component 140.

[0068] With this configuration, when the solder of the two conductive balls mounted on the first wiring board 110 and the second wiring board 120 melts and fuses together due to heat and pressure, stress acts from the lower core 131 to the upper core 132 in a direction away from the electronic component 140, limiting the sliding of the upper conductive ball. Therefore, with the semiconductor device 100 having this configuration, the positions of the two conductive balls mounted on the first wiring board 110 and the second wiring board 120 can be fixed, and as a result, misalignment between the first wiring board 110 and the second wiring board 120 can be suppressed.

[0069] Furthermore, in the semiconductor device 100 according to the modified example 2, the upper core 132 of the connecting member 130b, which is arranged on the frame line L2 furthest from the electronic component 140 among the multiple connecting members 130, may be offset relative to the lower core 131 in a direction that moves closer to the electronic component 140.

[0070] With this configuration, the sliding of the upper core 132 can be easily limited at the connecting member 130b arranged on the frame line L2 furthest from the electronic component 140. Therefore, with the semiconductor device 100 having this configuration, the positions of the two conductive balls mounted on the first wiring board 110 and the second wiring board 120 can be fixed with a simple configuration, and as a result, misalignment between the first wiring board 110 and the second wiring board 120 can be efficiently suppressed.

[0071] The direction in which the upper core 132 is offset from the lower core 131 may be either towards the center C of the electronic component 140 or away from the center C of the electronic component 140. The center C of the electronic component 140 may be, for example, the intersection of two diagonals on the upper surface of the electronic component 140 when the electronic component 140 is formed in a rectangular shape in a plan view from the stacking direction Z (see Figure 1).

[0072] Figure 18 shows an example of the arrangement of multiple connecting members 130, a lower core 131, and an upper core 132 according to a modified example of the embodiment 3. In Figure 18, a top view of the semiconductor device 100 as seen from the stacking direction Z (see Figure 1) is shown. Note that in Figure 18, for the sake of explanation, the second wiring board 120, sealing resin 101, solder 133, etc. are omitted from the illustration.

[0073] In the semiconductor device 100 according to Modification 3, the multiple connecting members 130 are arranged on multiple straight lines L3 to L5 that extend along two opposing sides of the electronic component 140 and are at different distances from the center of the electronic component 140, when viewed in a plan view from the stacking direction Z (see Figure 1). Among the multiple connecting members 130, the connecting member 130a arranged on the straight line L3 closest to the electronic component 140 has an upper core 132 that is offset relative to the lower core 131 in a direction that moves closer to the electronic component 140.

[0074] With this configuration, the slippage of the upper core 132 can be easily limited at the connecting member 130a arranged on the straight line L3 closest to the electronic component 140. Therefore, with the semiconductor device 100 having this configuration, the positions of the two conductive balls mounted on the first wiring board 110 and the second wiring board 120 can be fixed with a simple configuration, and as a result, misalignment between the first wiring board 110 and the second wiring board 120 can be efficiently suppressed.

[0075] In the modified example 3, the case where the upper core 132 is offset toward the electronic component 140 in the connecting member 130a arranged on the straight line L3 closest to the electronic component 140 was explained as an example, but the offset of the upper core 132 is not limited to this. For example, in the connecting member 130b arranged on the straight line L5 furthest from the electronic component 140 among the multiple connecting members 130, the upper core 132 may be positioned offset toward the electronic component 140 relative to the lower core 131.

[0076] Furthermore, the direction in which the upper core 132 is offset from the lower core 131 may be either a direction toward the center C of the electronic component 140 or a direction toward the center C of the electronic component 140. The center C of the electronic component 140 may be, for example, the intersection of two diagonals on the upper surface of the electronic component 140 when the electronic component 140 is formed in a rectangular shape in a plan view from the stacking direction Z (see Figure 1).

[0077] Figure 19 shows an example of the arrangement of multiple connecting members 130, a lower core 131, and an upper core 132 according to a modified example 4 of the embodiment. Figure 19 shows a top view of the semiconductor device 100 as seen from the stacking direction Z (see Figure 1). For the sake of explanation, the second wiring board 120, sealing resin 101, solder 133, etc. are omitted from the illustration in Figure 19.

[0078] In the semiconductor device 100 according to Modification 4, the multiple connecting members 130 are arranged on multiple straight lines L3 to L5 and on multiple other straight lines L6 that extend along two other opposing sides of the electronic component 140, in a plan view from the stacking direction Z (see Figure 1). Among the multiple connecting members 130, the upper core 132 is positioned offset from the lower core 131 in the direction toward the electronic component 140, in the connecting member 130a arranged on the straight line L3 and the other straight line L6 that are closest to the electronic component 140.

[0079] With this configuration, the slippage of the upper core 132 can be easily limited at the connecting members 130a arranged on the straight line L3 closest to the electronic component 140 and on another straight line L6. Therefore, with the semiconductor device 100 having this configuration, the positions of the two conductive balls mounted on the first wiring board 110 and the second wiring board 120 can be fixed with a simple configuration, and as a result, misalignment between the first wiring board 110 and the second wiring board 120 can be efficiently suppressed.

[0080] In the modified example 4, the case where the upper core 132 is offset in the direction toward the electronic component 140 in the connecting members 130a arranged on the straight line L3 closest to the electronic component 140 and on another straight line L6 was explained as an example, but the offset of the upper core 132 is not limited to this. For example, in the connecting member 130a arranged on the straight line L3 closest to the electronic component 140 and on another straight line L6 among the multiple connecting members 130, the upper core 132 may be positioned offset in the direction toward away from the electronic component 140 relative to the lower core 131.

[0081] Furthermore, in the modified example 4, the upper core 132 does not need to be offset relative to the lower core 131 in the connecting member 130a located at the intersection of the straight line L3 closest to the electronic component 140 and another straight line L6. This reduces the possibility of interference between the connecting member 130a located at the intersection of the straight line L3 and the other straight line L6 and other connecting members 130a adjacent to that connecting member 130a.

[0082] Figure 20 shows an example of the arrangement of multiple connecting members 130, a lower core 131, and an upper core 132 according to a modified example 5 of the embodiment. In Figure 20, a top view of the semiconductor device 100 as seen from the stacking direction Z (see Figure 1) is shown. Note that in Figure 20, for the sake of explanation, the second wiring board 120, sealing resin 101, solder 133, etc. are omitted from the illustration.

[0083] In the semiconductor device 100 according to Modification 5, a plurality of connecting members 130 are arranged on a plurality of straight lines L3 to L5 and another plurality of straight lines L6 in a plan view from the stacking direction Z (see Figure 1), surrounding the outer periphery of the electronic component 140.

[0084] With this configuration, the slippage of the upper core 132 can be easily limited at the connecting members 130a arranged on the straight line L3 closest to the electronic component 140 and on another straight line L6. Therefore, with the semiconductor device 100 having this configuration, the positions of the two conductive balls mounted on the first wiring board 110 and the second wiring board 120 can be fixed with a simple configuration, and as a result, misalignment between the first wiring board 110 and the second wiring board 120 can be efficiently suppressed.

[0085] Figure 21 is a diagram showing an example of the arrangement of multiple connecting members 130, a lower core 131, and an upper core 132 according to a modified example 6 of the embodiment. In Figure 21, a top view of the semiconductor device 100 as seen from the stacking direction Z (see Figure 1) is shown. Note that in Figure 21, for the sake of explanation, the second wiring board 120, sealing resin 101, solder 133, etc. are omitted from the illustration.

[0086] The arrangement of the multiple connecting members 130, the lower core 131, and the upper core 132 shown in Figure 21 is a variation of the arrangement of the multiple connecting members 130, the lower core 131, and the upper core 132 shown in Figure 2.

[0087] Figure 2 shows an example where the direction in which the upper core 132 is offset relative to the lower core 131 is towards the center C of the electronic component 140. However, the direction in which the upper core 132 is offset relative to the lower core 131 is not limited to the direction towards the center C of the electronic component 140. For example, as shown in Figure 21, the direction in which the upper core 132 is offset relative to the lower core 131 may be towards each side of the electronic component 140.

[0088] As described above, the semiconductor device according to the embodiment (for example, semiconductor device 100) includes a first wiring board (for example, first wiring board 110), an electronic component (for example, electronic component 140), a second wiring board (for example, second wiring board 120), and a plurality of connecting members (for example, connecting member 130). The electronic component is provided on the first wiring board. The second wiring board is stacked on the first wiring board with the electronic component in between. The plurality of connecting members are arranged around the electronic component to connect the first wiring board and the second wiring board. Each of the plurality of connecting members has a pair of cores (for example, lower core 131 and upper core 132) adjacent to each other in the stacking direction of the first and second wiring boards (for example, stacking direction Z), and a conductive film (for example, solder 133) covering the pair of cores. In a plurality of connecting members, at least in the innermost or outermost row relative to the electronic component (for example, connecting members 130a and 130b), one of a pair of cores, the core closer to the second wiring board (for example, the upper core 132), is offset relative to the other core closer to the first wiring board (for example, the lower core 131) in a direction toward or toward the electronic component. This makes it possible to suppress misalignment between the two wiring boards.

[0089] Furthermore, the multiple connecting members may be arranged on multiple frame lines (for example, frame lines L1, L2) that surround the outer periphery of the electronic component and are at different distances from the center of the electronic component, in a plan view from the stacking direction. Among the multiple connecting members, the connecting member (for example, connecting member 130a, 130b) arranged on the frame line closest to the electronic component (for example, frame line L1) or the frame line furthest from the electronic component (for example, frame line L2) may have one core offset relative to the other core in a direction toward or away from the electronic component. This makes it possible to efficiently suppress misalignment between the two wiring boards.

[0090] Furthermore, the multiple connecting members may be arranged on multiple straight lines (for example, lines L3 to L5) that extend along two opposing sides of the electronic component and are at different distances from the center of the electronic component, when viewed in a plan view from the stacking direction. Among the multiple connecting members, the connecting member (for example, connecting member 130a, 130b) arranged on the straight line closest to the electronic component (for example, line L3) or the straight line furthest from the electronic component (for example, line L5) may have one core offset relative to the other core in a direction toward or away from the electronic component. This makes it possible to efficiently suppress misalignment between the two wiring boards.

[0091] Furthermore, the multiple connecting members may be arranged on multiple straight lines and on multiple other straight lines (for example, straight line L6) extending along two other opposing sides of the electronic component in a plan view from the stacking direction. Among the multiple connecting members, the connecting members arranged on the straight line closest to the electronic component and on another straight line (for example, connecting member 130a) may have one core offset relative to the other core in a direction toward or toward the electronic component. This effectively suppresses misalignment between the two wiring boards.

[0092] Furthermore, in all of the multiple connecting members, one core may be offset relative to the other core in a direction toward or toward the electronic component. This can further suppress misalignment between the two wiring boards.

[0093] Furthermore, the first wiring board may have a first pad (for example, an inner pad 113-1) connected to a connecting member arranged in the innermost or outermost row relative to the electronic components. The second wiring board may have a second pad (for example, an inner pad 125-1) connected to a connecting member arranged in the innermost or outermost row relative to the electronic components. The second pad may be offset relative to the first pad in a direction toward the electronic components or away from the electronic components. This allows the position of the second pad to be offset to a position suitable for connection with the connecting member arranged in the innermost row relative to the electronic components.

[0094] Furthermore, the first wiring board may have a first insulating layer (for example, a protective insulating layer 112) that covers the upper surface of the substrate of the first wiring board (for example, substrate 111) and has an opening (for example, an opening 112a) that exposes the first pad. The second wiring board may have a second insulating layer (for example, a protective insulating layer 124) that covers the lower surface of the substrate of the second wiring board (for example, substrate 121) and has an opening (for example, an opening 124a) that exposes the second pad. The opening of the second insulating layer may be offset from the opening of the first insulating layer in a direction toward the electronic component or away from the electronic component. This makes it possible to maintain the area of ​​the second pad exposed from the opening of the second insulating layer as an area suitable for connection with the innermost row of connecting members to the electronic component.

[0095] Furthermore, each of the multiple connecting members may be an integrated product formed by integrating the conductive film of a first conductor ball (for example, conductor ball 130A) mounted on a first wiring board, which is formed by covering one core with a conductive film, and the conductive film of a second conductor ball (for example, conductor ball 130B) mounted on a second wiring board, which is formed by covering the other core with a conductive film. The offset amount of one core relative to the other core (for example, offset amount d) may be smaller than the diameter of the first conductor ball or the second conductor ball. This allows the conductive film of the first conductor ball and the conductive film of the second conductor ball to be properly integrated. [Explanation of symbols]

[0096] 100 Semiconductor Equipment 110 First Wiring Board 112, 124 Protective insulating layer 112a, 124a opening 113, 113a, 113b Top pad 113-1, 125-1 Inner pad 113-2, 125-2 Outer pad 120 Second Wiring Board 121 circuit boards 125 Bottom pad 130, 130a, 130b connecting members 130A, 130B Conductor Balls 131 Lower Core 132 upper core 140 Electronic Components

Claims

1. First wiring board and Electronic components provided on the first wiring board, A second wiring board is laminated on the first wiring board with the electronic components sandwiched in between, A plurality of connecting members arranged around the aforementioned electronic component to connect the first wiring board and the second wiring board. It has, Each of the aforementioned plurality of connecting members is A pair of cores adjacent to each other in the stacking direction of the first wiring board and the second wiring board, A conductive film covering the pair of cores and It has, In at least one of the plurality of connecting members arranged in the innermost or outermost row relative to the electronic component, one of the pair of cores, the core closer to the second wiring board, is offset relative to the other core closer to the first wiring board in a direction toward or toward the electronic component. A semiconductor device characterized by the following features.

2. The aforementioned plurality of connecting members are In a plan view from the stacking direction, the electronic component is arranged on multiple frame lines that surround its outer circumference and are at different distances from the center of the electronic component. In a connecting member arranged on the frame line closest to the electronic component or on the frame line furthest from the electronic component, one of the connecting members is offset relative to the other core in a direction toward the electronic component or away from the electronic component. The semiconductor device according to claim 1.

3. The aforementioned plurality of connecting members are In a plan view from the stacking direction, the electronic components are arranged along a plurality of straight lines that extend along two opposing sides of the electronic component and are at different distances from the center of the electronic component. In a connecting member arranged on a straight line closest to the electronic component or on a straight line furthest from the electronic component, one of the cores is offset relative to the other core in a direction toward the electronic component or away from the electronic component. The semiconductor device according to claim 1.

4. The aforementioned plurality of connecting members are In a plan view from the stacking direction, the components are arranged along the plurality of straight lines and along two other opposing sides of the electronic component. In the connecting members arranged on the straight line closest to the electronic component and on another straight line among the plurality of connecting members, one core is offset from the other core in a direction toward the electronic component or away from the electronic component. The semiconductor device according to claim 3.

5. In all of the aforementioned connecting members, one core is positioned offset from the other core in a direction toward the electronic component or away from the electronic component. The semiconductor device according to claim 1.

6. The first wiring board is, It has a first pad connected to a connecting member arranged in the innermost or outermost row to the aforementioned electronic component, The aforementioned second wiring board is It has a second pad connected to a connecting member arranged in the innermost or outermost row to the aforementioned electronic component, The aforementioned second pad is The first pad is positioned offset from the electronic component in either a direction toward the electronic component or a direction toward the electronic component. The semiconductor device according to feature 1.

7. The first wiring board is, The first insulating layer covers the upper surface of the substrate of the first wiring board and has an opening that exposes the first pad, The aforementioned second wiring board is The second insulating layer covers the lower surface of the substrate of the second wiring board and has an opening that exposes the second pad, The opening in the second insulating layer is It is positioned offset from the opening of the first insulating layer in a direction approaching the electronic component or in a direction away from the electronic component. The semiconductor device according to feature 6.

8. Each of the aforementioned plurality of connecting members is This is an integrated product formed by integrating the conductive film of a first conductor ball, which is formed by covering one of the aforementioned cores with a conductive film and mounted on the first wiring board, with the conductive film of a second conductor ball, which is formed by covering the other core with a conductive film and mounted on the second wiring board. The offset amount of one core relative to the other core is, Smaller than the diameter of the first conductor ball or the second conductor ball The semiconductor device according to feature 1.

9. In at least one of the plurality of connecting members arranged in the innermost or outermost row relative to the electronic component, one of the pair of cores, the core closer to the second wiring board, is offset relative to the other core closer to the first wiring board in a direction toward the center of the electronic component or away from the center of the electronic component. The semiconductor device according to feature 1.

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