Photodetector and electronic equipment

Abstract

The present invention provides an optical detection device and electronic equipment that reduces the number of wiring layers and lowers costs by appropriately arranging circuits and wiring in the light-receiving chip and the detection chip. [Solution] The light detection device comprises a first chip including a light receiving unit that converts incident light into an electrical signal, a part of a conversion circuit that converts the electrical signal into a voltage signal, a first buffer circuit that outputs a first detection signal corresponding to the voltage signal, and first and second capacitive elements with one end connected to the output of the first buffer circuit; and a second chip including a first comparator connected to the other end of the first capacitive element that outputs a first output signal when the first or second detection signal exceeds a first threshold voltage higher than the first or second detection signal, and a second comparator connected to the other end of the second capacitive element that outputs a second output signal when the first or second detection signal falls below a second threshold voltage lower than the first or second detection signal, with the first chip and the second chip stacked.

Description

Technical Field

[0006] , ,

[0007] , ,

[0001] The present disclosure relates to a light detection device and an electronic device.

Background Art

[0002] A light detection device that detects an event signal in real time when the amount of light of a pixel exceeds a threshold has been developed. Such a light detection device that detects such an event signal is called an EVS (Event Vision Sensor). The EVS is a sensor that detects a change in the luminance of a pixel and outputs the changed data in combination with coordinate and time information.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The EVS may be configured by laminating a plurality of semiconductor chips. Such a stacked EVS is composed of a light receiving chip having a photodiode and a detection chip having a detection circuit.

[0005] However, since the circuit and wiring designs in conventional light receiving chips and detection chips were not appropriate, there was a problem in that there were many wiring layers and the manufacturing cost was high.

[0006] The present technology has been made in view of such problems, and provides a light detection device and an electronic device capable of appropriately arranging circuits and wirings in a light receiving chip and a detection chip to reduce the number of wiring layers and reduce the cost.

Means for Solving the Problems

[0007] One aspect of the present disclosure of a photodetector includes a first chip comprising: a light receiving unit that converts incident light into an electrical signal by photoelectric conversion; a part of a conversion circuit that converts the electrical signal into a voltage signal; a first buffer circuit that outputs a first detection signal corresponding to the voltage signal; and first and second capacitive elements, one end of which is connected to the output of the first buffer circuit; and a second chip comprising: a first comparator connected to the other end of the first capacitive element and outputting a first output signal when the first detection signal exceeds a first threshold voltage; and a second comparator connected to the other end of the second capacitive element and outputting a second output signal when the first detection signal falls below a second threshold voltage which is lower than the first threshold voltage, wherein the first chip and the second chip are stacked.

[0008] A first capacitance element is provided between the output of the first buffer circuit and one input terminal of the first comparator, and a second capacitance element is provided between the output of the first buffer circuit and one input terminal of the second comparator. A first threshold voltage is applied to the other input terminal of the first comparator, and a second threshold voltage is applied to the other input terminal of the second comparator.

[0009] The photodetector further comprises a first junction provided between the other end of the first capacitive element and one input terminal of the first comparator, and a second junction provided between the other end of the second capacitive element and one input terminal of the second comparator.

[0010] The first and second joints are joints where the wiring of the first chip and the wiring of the second chip are directly joined.

[0011] The power supply section of the conversion circuit is located on the second chip.

[0012] The second chip further includes a quantizer that binarizes the first and second output signals.

[0013] The first chip includes an N-type transistor but does not have a P-type transistor.

[0014] The second chip has a CMOS (Complementary Metal Oxide Semiconductor).

[0015] The first chip has an analog circuit composed of a first transistor, and the second chip has a digital circuit composed of a second transistor with a lower voltage rating than the first transistor.

[0016] The power supply section of the first buffer circuit is shared with the power supply section of the conversion circuit and is located on the second chip.

[0017] The light detection device further includes a third junction that electrically connects the power supply portion of the conversion circuit to the power supply of the first chip for each pixel of the light-receiving section, and a fourth junction that electrically connects the power supply portion of the first buffer circuit to the power supply of the first chip for each pixel of the light-receiving section.

[0018] The power supply sections for the first buffer circuit and the conversion circuit are shared and located on the first chip.

[0019] The first chip has analog circuitry, and the second chip has digital circuitry.

[0020] One aspect of the present disclosure is an electronic device comprising: a first chip including a light receiving unit that converts incident light into an electrical signal by photoelectric conversion; a part of a conversion circuit that converts the electrical signal into a voltage signal; a first buffer circuit that outputs a first detection signal corresponding to the voltage signal; and first and second capacitive elements with one end connected to the output of the first buffer circuit; and a second chip including a first comparator connected to the other end of the first capacitive element and outputting a first output signal when the first detection signal exceeds a first threshold voltage; and a second comparator connected to the other end of the second capacitive element and outputting a second output signal when the first detection signal falls below a second threshold voltage which is lower than the first threshold voltage, wherein the first chip and the second chip are stacked. [Brief explanation of the drawing]

[0021] [Figure 1] A block diagram showing one example configuration of a light detection device according to the first embodiment. [Figure 2]A diagram showing an example of the stacked structure of a solid-state imaging device according to the first embodiment. [Figure 3] An example of a plan view of a light-receiving chip. [Figure 4] An example of a plan view of a pixel array section. [Figure 5] An example of a plan view of a detection chip. [Figure 6] An example of a plan view of a detection section. [Figure 7] A block diagram showing an example of the configuration of an event detection circuit. [Figure 8] A circuit diagram showing an example of the configuration of an event detection circuit. [Figure 9] A schematic cross-sectional view showing an example of the configuration of an optical detection device according to the first embodiment. [Figure 10] A schematic cross-sectional view showing an optical detection device according to a comparative example. [Figure 11] A diagram showing an example of the configuration of an event detection circuit according to the second embodiment. [Figure 12] A schematic perspective view showing an example of the configuration of an optical detection device when a power supply line of a buffer is provided on the light-receiving chip side. [Figure 13] A schematic perspective view showing an example of the connection configuration of the power supply of transistors in a logarithmic conversion circuit. [Figure 14] A diagram showing an example of the configuration of an event detection circuit according to the third embodiment. [Figure 15] A diagram showing another example of the configuration of a buffer according to the fourth embodiment. [Figure 16] A block diagram showing an example of the schematic configuration of a vehicle control system. [Figure 17] An explanatory diagram showing an example of the installation positions of an outside-vehicle information detection section and an imaging section.

Embodiments for Carrying Out the Invention

[0022] The following describes specific embodiments of this technology with reference to the drawings. The drawings are schematic or conceptual, and the proportions of each part may not necessarily be the same as those of actual objects. In the specification and drawings, elements similar to those described above are denoted by the same reference numerals with respect to previously shown drawings, and detailed explanations are omitted as appropriate.

[0023] (First Embodiment) Figure 1 is a block diagram showing an example configuration of a light detection device 1 according to the first embodiment. The light detection device 1 is, for example, an EVS or DVS (Dynamic Vision Sensor). The light detection device 1 comprises an imaging lens 10, a solid-state image sensor 20, a recording area 30, and a control unit 40. Examples of the light detection device 1 include electronic devices such as cameras mounted on industrial robots, in-vehicle cameras, and surveillance cameras.

[0024] The imaging lens 10 focuses the incident light and guides it to the solid-state image sensor 20. The solid-state image sensor 20 converts the incident light into photoelectric power to generate a voltage signal corresponding to the amount of light received, and also detects changes in the amount of light received as an event signal based on the amount of change in the voltage signal. The detected event signal is output to the recording area 30.

[0025] The recording area 30 records event signals from the solid-state image sensor 20. The recording area 30 may be, for example, a latch circuit, a semiconductor memory such as DRAM (Dynamic Random Access Memory), or a flash memory. The internal configuration of the recording area 30 will be described in more detail later.

[0026] The control unit 40 is configured with a microcomputer equipped with, for example, a CPU (Central Processing Unit), ROM (Read Only Memory), RAM, etc., and controls the operation of the light detection device 1 by having the CPU execute processing according to the program. In particular, the control unit 40 controls the solid-state image sensor 20 to perform the event signal detection operation described above, controls the recording area 30 to record the event signal, and executes the process of reading the event signal from the recording area 30.

[0027] Figure 2 shows an example of a stacked structure of a solid-state image sensor 20 according to the first embodiment. The solid-state image sensor 20 comprises a detection chip 202 and a light-receiving chip 201 stacked on the detection chip 202. In such a stacked structure, the light-receiving chip 201 and the detection chip 202 are electrically connected via connection points such as vias. In addition to vias, connections can also be made by Cu-Cu junctions or bumps.

[0028] Figure 3 is an example of a plan view of the light-receiving chip 201. The light-receiving chip 201 is provided with a pixel array section 220 and via arrangement sections 211, 212, and 213. Vias connected to the detection chip 202 are arranged in the via arrangement sections 211, 212, and 213.

[0029] Figure 4 is an example of a plan view of the pixel array section 220. The pixel array section 220 has multiple light-receiving sections 221 arranged in a two-dimensional grid. The light-receiving sections 221 are, for example, photodiodes. The light-receiving sections 221 convert incident light into photoelectric current. Each light-receiving section 221 is assigned a pixel address consisting of a row address and a column address.

[0030] Figure 5 is an example of a plan view of the detection chip 202. The detection chip 202 is provided with via placement sections 231, 232, and 233, a signal processing circuit 240, a row drive circuit 251, a column drive circuit 252, and a detection unit 260. Vias connected to the light receiving chip 201 are arranged in the via placement sections 231, 232, and 233.

[0031] The row drive circuit 251 selects a row address in the pixel array section 220 and outputs a photocurrent corresponding to that row address to the detection unit 260. The column drive circuit 252 selects a column address in the pixel array section 220 and outputs a photocurrent corresponding to that column address to the detection unit 260.

[0032] The detection unit 260 detects an event signal by quantizing the voltage signal obtained by logarithmically transforming the input photocurrent, and outputs the detected event signal to the signal processing circuit 240. An event indicates that the amount of change in the voltage signal obtained by logarithmically transforming the photocurrent has exceeded or fallen below a predetermined threshold. The event signal is activated (for example, raised) when an event occurs. The event signal is a signal that has been quantized (binarized) by the quantizer 340. The signal processing circuit 240 performs predetermined signal processing on the event signal output from the detection unit 260 and outputs it to the recording area 30.

[0033] Figure 6 is an example of a plan view of the detection unit 260. Multiple event detection circuits 300 are arranged in a two-dimensional grid within the detection unit 260. Each event detection circuit 300 is assigned a pixel address and connected to a light receiving unit 221 with the same address. The event detection circuit 300 quantizes the voltage signal corresponding to the photocurrent from the corresponding light receiving unit 221 and outputs it as an event signal.

[0034] Figure 7 is a block diagram showing an example of the configuration of the event detection circuit 300. The event detection circuit 300 includes a logarithmic transformation circuit 310, a buffer 320, a subtractor 330, and a quantizer 340.

[0035] The logarithmic conversion circuit 310 converts the photocurrent from the corresponding light receiving unit 221 into a logarithmically converted voltage signal. The logarithmic conversion circuit 310 supplies the converted voltage signal to the buffer 320.

[0036] Buffer 320 corrects the voltage signal from logarithmic conversion circuit 310. Buffer 320 outputs the corrected voltage signal to subtractor 330.

[0037] The subtractor 330 compares the amount of change in the input voltage signal with a predetermined threshold (reference voltage) and outputs a detection signal to the quantizer 340 indicating whether the value has exceeded or fallen below the threshold.

[0038] The quantizer 340 quantizes the detection signal into a digital signal and outputs it as an event signal to the signal processing circuit 240.

[0039] The control unit 40 controls the operation of the subtractor 330 and the quantizer 340, and controls the reading of the event signal.

[0040] Figure 8 shows an example of the configuration of the event detection circuit 300. The logarithmic transformation circuit 310 comprises N-type transistors 311 to 314 and a P-type transistor 315. For example, MOS (Metal-Oxide-Semiconductor) transistors are used as these transistors.

[0041] The source of transistor 311 is connected to ground, and the drain of transistor 311 is connected to the source of transistor 313 and the gate of N-type transistor 312. The gate of transistor 311 is connected to the cathode of the light-receiving unit 221.

[0042] The drain of transistor 312 is connected to the source of transistor 314, and the source of transistor 312 is connected to the cathode of the light-receiving unit 221. The gate of transistor 312 is connected to the node between transistors 311 and 313.

[0043] The drain of transistor 313 is connected to the gate of transistor 314 and the drain of transistor 315, and the source of transistor 313 is connected to the drain of transistor 311. The gate of transistor 313 is connected to the node between transistor 312 and transistor 314.

[0044] The drain of transistor 314 is connected to the power line of voltage PVDD, and the source of transistor 314 is connected to the drain of transistor 312 and the gate of transistor 313. The gate of transistor 314 is connected to node Npr between the drain of transistor 313 and the drain of transistor 315.

[0045] The drain of transistor 315 is connected to the gate of transistor 314 and the drain of transistor 313, and the source of transistor 315 is connected to the power supply line of voltage AVDD. The gate of transistor 315 is subjected to a predetermined bias voltage Bias_pr.

[0046] P-type transistor 315 and N-type transistors 313 and 311 are connected in series between the voltage AVDD power line and ground. N-type transistors 314 and 312 are also connected in series between the voltage PVDD power line and the cathode of the light receiving unit 221.

[0047] N-type transistors 311-314 constitute a source follower circuit. Through this source follower circuit, the photocurrent from the light-receiving unit 221 is converted into a logarithmically transformed voltage signal Vpr. This voltage signal Vpr is then transmitted to node Npr. Additionally, P-type transistor 315 is a power supply transistor that supplies a constant current to the N-type transistors 311 and 313. In this way, the logarithmic transformation circuit 310 logarithmically transforms the light intensity received by the light-receiving unit 221 and converts it into a voltage signal Vpr.

[0048] Note that the ground of the light-receiving chip 201 and the ground of the detection chip 202 in Figure 2 are separated from each other to prevent interference. Furthermore, the light-receiving chip 201 may contain the light-receiving unit 221 and the N-type transistors 311 to 314 of the event detection circuit 300, while the detection chip 202 may contain the event detection circuit 300 composed of CMOS (Complementary MOS) circuits other than the N-type transistors 311 to 314.

[0049] Buffer 320 outputs a detection signal Vsf that depends on the illuminance and changes in illuminance of the light received by the light receiving unit 221. Buffer 320 includes N-type transistors 323 and 324. The drain of transistor 324 is connected to the power supply line (first voltage source) of voltage AVDD. The source of transistor 324 is connected to the drain of transistor 323. The gate of transistor 324 is connected to node Npr and receives the voltage signal Vpr. The drain of transistor 323 is connected to the source of transistor 324. The source of transistor 323 is connected to ground. The gate of transistor 323 receives a predetermined bias voltage Bias_fo. Transistor 323 functions as a constant current source that supplies a constant current to transistor 324. As a result, buffer 320 outputs a detection signal Vsf according to the voltage signal Vpr to subtractor 330.

[0050] The subtractor 330 includes a first subtraction circuit 331 and a second subtraction circuit 332. The first subtraction circuit 331 compares the detection signal Vsf with a first threshold voltage Vth_on. When the detection signal Vsf exceeds the first threshold voltage Vth_on, the first subtraction circuit 331 raises the output signal. The second subtraction circuit 332 compares the detection signal Vsf with a second threshold voltage Vth_off. When the detection signal Vsf falls below the second threshold voltage Vth_off, the second subtraction circuit 332 lowers the output signal. The first threshold voltage Vth_on is greater than the second threshold voltage Vth_off. Therefore, when the detection signal Vsf is between the first threshold voltage Vth_on and the second threshold voltage Vth_off, the first and second subtraction circuits 331 and 332 do not change the output signals. Furthermore, the first threshold voltage Vth_on is set to a voltage that is a predetermined voltage higher than the detection signal Vsf when reset. The second threshold voltage Vth_off is set to a voltage that is a predetermined voltage lower than the detection signal Vsf when reset.

[0051] The first subtraction circuit 331 includes a capacitive element C1 and a comparator CMP1. One end of the capacitive element C1 is connected to node Nsf, and the other end is connected to the first input terminal of comparator CMP1. That is, the capacitive element C1 is provided between the output of buffer 320 and the first input terminal of comparator CMP1. The capacitive element C1 can be a high-capacitance element, such as MIM (Metal-Insulator-Metal) or MOM (Metal-Oxide-Metal). The first input terminal of comparator CMP1 is connected to the other end of the capacitive element C1, and the second input terminal receives the first threshold voltage Vth_on. Comparator CMP1 is capacitively connected to node Nsf via the capacitive element C1 and receives the detection signal Vsf at the first input terminal. Comparator CMP1 is powered by the voltage source of voltage DVDD and ground. The comparator CMP1 compares the detection signal Vsf with the first threshold voltage Vth_on, and raises the output signal when the detection signal Vsf exceeds the first threshold voltage Vth_on. When the detection signal Vsf exceeds the first threshold voltage Vth_on, the first subtraction circuit 331 is reset, and the first threshold voltage Vth_on is set to a voltage that is a predetermined voltage higher than the detection signal Vsf at that time.

[0052] The second subtraction circuit 332 includes a capacitive element C2 and a comparator CMP2. One end of the capacitive element C2 is connected to node Nsf, and the other end is connected to the third input terminal of the comparator CMP2. That is, the capacitive element C2 is provided between the output of buffer 320 and the third input terminal of comparator CMP2. The capacitive element C2 can also be a high-capacitance element, such as MIM or MOM. The third input terminal of comparator CMP2 is connected to the other end of the capacitive element C2, and the fourth input terminal receives the second threshold voltage Vth_off. Comparator CMP2 is capacitively connected to node Nsf via the capacitive element C2 and receives the detection signal Vsf at the third input terminal. Comparator CMP2 is powered by the voltage source DVDD and ground. Comparator CMP2 compares the detection signal Vsf with the second threshold voltage Vth_off, and lowers the output signal when the detection signal Vsf falls below the second threshold voltage Vth_off. When the detection signal Vsf falls below the second threshold voltage Vth_off, the second subtraction circuit 332 is reset, and the second threshold voltage Vth_off is set to a voltage that is a predetermined voltage lower than the detection signal Vsf at that time. The comparators CMP1 and CMP2 are not shown in the figure, but may be composed of, for example, CMOS circuits.

[0053] The quantizer 340 includes a first quantization circuit 341 and a second quantization circuit 342. The first quantization circuit 341 outputs an on-event Eon in response to the rising edge of the output signal from the first subtraction circuit 331. The second quantization circuit 342 outputs an off-event Eoff in response to the falling edge of the output signal from the second subtraction circuit 332.

[0054] The first quantization circuit 341 includes a P-type transistor 343 and an N-type transistor 344. The drain of transistor 343 is connected to the output node Non and the drain of transistor 344. The source of transistor 343 is connected to the power supply line of voltage DVDD. The gate of transistor 343 receives the output signal of the first subtraction circuit 331. The drain of transistor 344 is connected to the output node Non and the drain of transistor 343. The source of transistor 344 is connected to ground. The gate of transistor 344 receives a predetermined voltage. Transistors 343 and 344 are connected in series between the power supply line of voltage DVDD and ground. Transistor 344 supplies a constant current to transistor 343. As a result, when the first subtraction circuit 331 raises its output signal, the first quantization circuit 341 outputs an on-event Eon from the output node Non.

[0055] The second quantization circuit 342 includes a P-type transistor 345 and an N-type transistor 346. The drain of transistor 345 is connected to the output node Noff and the drain of transistor 346. The source of transistor 345 is connected to the power supply line of the voltage DVDD. The gate of transistor 345 receives the output signal of the second subtraction circuit 332. The drain of transistor 346 is connected to the output node Noff and the drain of transistor 345. The source of transistor 346 is connected to ground. The gate of transistor 346 receives a predetermined voltage. Transistors 345 and 346 are connected in series between the power supply line of the voltage DVDD and ground. Transistor 346 supplies a constant current to transistor 345. As a result, when the second subtraction circuit 332 drops its output signal, the second quantization circuit 342 outputs an off-event Eoff from the output node Noff. For example, MOS transistors can be used for transistors 343-346.

[0056] The on-event Eon and off-event Eoff are output to the signal processing circuit 240.

[0057] Next, we will explain the configuration of the light receiving chip 201 and the detection chip 202.

[0058] In the first embodiment, the light detection device 1 has a stacked structure of a light receiving chip 201 and a detection chip 202.

[0059] The light-receiving chip 201 includes a light-receiving section (photodiode) 221, a buffer 320, part of a logarithmic conversion circuit 310, and capacitive elements C1 and C2. The buffer 320 and part of the logarithmic conversion circuit 310 provided on the light-receiving chip 201 are transistors 311-314, 323, and 324, all of which are N-type MOSFETs. The light-receiving chip 201 does not have P-type MOSFETs. This simplifies the configuration of the light-receiving chip 201 and simplifies its manufacturing.

[0060] On the other hand, the detection chip 202 includes the remaining parts of the logarithmic transformation circuit 310, comparators CMP1 and CMP2, and a quantizer 340. The remaining parts of the logarithmic transformation circuit 310 are transistor 315, which is a P-type MOSFET. Transistor 315 is a power supply transistor that receives power from the voltage AVDD power supply line provided on the detection chip 202. Furthermore, comparators CMP1 and CMP2 and the quantizer 340 are made of CMOS and include P-type MOSFETs. Therefore, the circuit including the P-type MOSFET is provided on the detection chip 202.

[0061] The light-receiving chip 201 and the detection chip 202 are electrically connected at junctions 250_1 to 250_3 for each pixel. Junctions 250_1 to 250_3 are, for example, Cu-Cu junctions that directly connect the copper wiring of the light-receiving chip 201 and the detection chip 202. This allows for power supply and signal exchange between the light-receiving chip 201 and the detection chip 202.

[0062] Junction 250_1 electrically connects the drain of transistor 315 and node Npr (the output of logarithmic transformation circuit 310 and the gate of transistor 324). Junction 250_2 is provided between the other end of capacitive element C1 and one input terminal of comparator CMP1, and electrically connects them. Junction 250_3 is provided between the other end of capacitive element C2 and one input terminal of comparator CMP2, and electrically connects them.

[0063] Figure 9 is a schematic cross-sectional view showing an example of the configuration of a photodetector according to the first embodiment. Figure 9 shows a cross-section of one pixel.

[0064] The light detection device 1 has a stacked structure of a light receiving chip 201 and a detection chip 202. The light receiving chip 201 and the detection chip 202 are electrically joined by junctions 250_1 to 250_3.

[0065] The light-receiving chip 201 comprises a photodiode PD of the light-receiving section 221, a microlens ML, a transistor TR1, capacitive elements C1 and C2, wiring WR1, contact CNT1, and interlayer insulating film ILD1.

[0066] The photodiode PD is located in the semiconductor layer and converts the photocurrent into a logarithmically transformed voltage signal. The microlens ML is located on the photodiode PD and guides the light to the photodiode PD.

[0067] Transistor TR1 is located on the opposite side of the semiconductor layer from the microlens ML. Transistor TR1 is an N-type transistor that makes up transistors 311-314 of the logarithmic conversion circuit 310 and transistors 323 and 324 of the buffer 320. In Figure 9, transistors 311-314, 323, and 324 are conveniently grouped together as transistor TR1. Transistor TR1 is electrically connected to junction 250_1 via wiring WR1 and contact CNT1.

[0068] Capacitive elements C1 and C2 are composed of MIM, MOM, etc., provided within the interlayer insulating film ILD1. One end of capacitive elements C1 and C2 is electrically connected to one of transistors TR1 (transistors 323 and 324) via wiring WR1 and contact CNT1. The other end of capacitive elements C1 and C2 is electrically connected to junctions 250_2 and 25_3 via wiring WR1 and contact CNT1.

[0069] The detection chip 202 comprises a substrate SUB, a transistor TR2, wiring WR2, contact CNT2, and interlayer insulating film ILD2.

[0070] The substrate SUB is, for example, a semiconductor substrate such as a silicon substrate.

[0071] Transistor TR2 is a CMOS transistor located on the substrate SUB. Transistor TR2 is a component of the P-type transistor 315 for power supply of the logarithmic conversion circuit 310, the CMOS transistors that make up the comparators CMP1 and CMP2 of the subtractor 330, and the transistors 343 to 346 of the quantizer 340. In Figure 9, the CMOS transistors that make up transistors 315, 343 to 346 and the comparators CMP1 and CMP2 are conveniently collectively referred to as transistor TR2. Transistor TR2 is electrically connected to one of the junctions 250_1 to 250_3 via wiring WR2 and contact CNT2.

[0072] As described above, the light detection device 1 according to the first embodiment has the logarithmic conversion circuit 310 and buffer 320, consisting of N-type transistors 311-314, 323, 324 and capacitive elements C1, C2, provided on the light receiving chip 201 together with the photodiode PD. The N-type transistors 311-314, 323, 324 of the logarithmic conversion circuit 310 and buffer 320 operate as analog circuits and are composed of relatively high-voltage (HV) transistors. By providing such HV-type N-type transistors on the light receiving chip 201 side, it becomes unnecessary to form HV-type transistors on the detection chip 202 side. That is, it is sufficient to form a logic circuit on the detection chip 202 side consisting of LV (Low Voltage) transistors with lower voltage ratings than transistors 311-314, 323, 324. Furthermore, it becomes unnecessary to form P-type transistors on the light receiving chip 201 side. This leads to simplification of the manufacturing process for both the light-receiving chip 201 and the detection chip 202.

[0073] Figure 10 is a schematic cross-sectional view showing a photodetector according to a comparative example. In the comparative example, the N-type transistors 311-314 of the logarithmic conversion circuit 310 are provided on the light-receiving chip 201 together with the photodiode PD. However, the N-type transistors 324 and 323 and the capacitive elements C1 and C2 of the buffer 320 are provided on the detection chip 202.

[0074] In the detection chip 202, a smaller LV-type transistor TR2 is provided for the logic circuit compared to the HV-type transistor TR1. Therefore, the lower layer wiring close to the substrate SUB is narrow, and the design layout of the wiring layer is complex. Consequently, the capacitive elements C1 and C2 must be constructed using upper layer wiring relatively far from the substrate SUB. As a result, as shown by the dashed line in Figure 10, the distance between the lower and upper wiring layers increases, leading to a lot of unnecessary wiring. This increases the manufacturing process of the detection chip 202 and also increases the pixel size.

[0075] In contrast, in the light detection device 1 according to this embodiment, the N-type transistors 323 and 324 and capacitive elements C1 and C2 of the analog-operating buffer 320 are provided on the light-receiving chip 201 side, where there is relatively little wiring and ample space in the design layout of the wiring layers. As a result, the wiring layers of the detection chip 202 can be greatly reduced without significantly increasing the wiring layers of the light-receiving chip 201. This shortens the wiring distance of the detection chip 202 and reduces unnecessary wiring. Consequently, the manufacturing process of the detection chip 202 is shortened and the pixel size is reduced.

[0076] (Second Embodiment) Figure 11 shows an example of the configuration of the event detection circuit 300 according to the second embodiment. In the second embodiment, the power supply line of the buffer 320 (voltage AVDD) is connected to and shared with the power supply line of the logarithmic conversion circuit 310 (voltage AVDD). The power supply lines of the buffer 320, transistor 315, and logarithmic conversion circuit 310 are provided on the detection chip 202. By sharing the power supply lines of the buffer 320 and the logarithmic conversion circuit 310, voltage drops in only one of the power supplies can be suppressed, and variations in power supply voltage within the pixel can be suppressed. This makes it possible to suppress shading or unevenness in imaging.

[0077] For example, Figure 12 is a schematic perspective view showing an example configuration of a photodetector when the power supply line of the buffer 320 is located on the light-receiving chip 201 side. The power supply for the buffer 320 is connected to the second power supply ring RNG2, located on the outer edge of the detection chip 202, at an outer junction 250_p (e.g., a Cu-Cu junction) in the first power supply ring RNG1 located on the outer edge of the light-receiving chip 201. In this case, the power supply for the buffer 320 voltage AVDD is obtained from the power supply of the detection chip 202 via the second power supply ring RNG2, the junction 250_p, and the first power supply ring RNG1, through a mesh-like power supply wiring MSH. Therefore, there is a risk that the voltage drop of the buffer 320 voltage AVDD will increase.

[0078] On the other hand, Figure 13 is a schematic perspective view showing an example of the power supply connection configuration for the transistor 315 of the logarithmic conversion circuit 310. The power supply for the voltage AVDD of transistor 315 is provided at a junction 250_1 for each pixel, and is connected to the power supply of the detection chip 202 for each pixel, so each pixel receives power directly. Therefore, the voltage drop of the power supply for transistor 315 is relatively small.

[0079] Thus, if the power supply line for the buffer 320 is provided on the light-receiving chip 201 side separately from the power supply line for the logarithmic conversion circuit 310, the voltage drop of the buffer 320 voltage AVDD will be greater than the voltage drop of the power supply line for the logarithmic conversion circuit 310, causing shading or unevenness in the image.

[0080] In contrast, according to the second embodiment, the power supply line of the buffer 320 is shared with the power supply line of the logarithmic conversion circuit 310. That is, the power supply line of the buffer 320 is provided for each pixel, similar to the power supply line of the logarithmic conversion circuit 310. As shown in Figure 13, the junction 250_4 of the power supply line of the buffer 320 is provided for each pixel, similar to the junction 250_1 of the power supply line of the logarithmic conversion circuit 310. As a result, the voltage drop of the voltage AVDD of the buffer 320 and the voltage drop of the power supply line of the logarithmic conversion circuit 310 are both small and approximately equal. As a result, shading or unevenness in imaging can be suppressed.

[0081] Other configurations of the second embodiment may be the same as the corresponding configurations of the first embodiment. Therefore, the second embodiment can also obtain the effects of the first embodiment.

[0082] (Third embodiment) Figure 14 shows an example of the configuration of the event detection circuit 300 according to the third embodiment. The third embodiment is the same as the second embodiment in that the power supply lines for the voltage AVDD of the buffer 320 and the logarithmic conversion circuit 310 are shared. However, in the third embodiment, the power supply lines for the voltage AVDD of the buffer 320 and the logarithmic conversion circuit 310 are provided on the light receiving chip 201 side. Also, in the third embodiment, the entire logarithmic conversion circuit 310, including the transistor 315, is provided on the light receiving chip 201.

[0083] In this case, the light-receiving chip 201 needs to have not only an N-type transistor but also a P-type transistor 315. However, the light-receiving chip 201 is provided with an analog circuit composed of an HV-type transistor, and the detection chip 202 is provided with a logic circuit composed of an LV-type transistor. This makes it possible to manufacture transistors with different characteristics for the light-receiving chip 201 and the detection chip 202. Therefore, the manufacturing process for the light-receiving chip 201 and the detection chip 202 is simplified. In addition, since the power supply lines for the voltage AVDD of the buffer 320 and the logarithmic conversion circuit 310 are common, even if the voltage drop is large, shading or unevenness in the image can be suppressed.

[0084] Other configurations of the third embodiment may be the same as the corresponding configurations of the first embodiment. Therefore, the third embodiment can also obtain the effects of the first embodiment.

[0085] (Fourth Embodiment) Figure 15 shows another example of a buffer configuration according to the fourth embodiment. The fourth embodiment may be applied to any of the buffers 320 of the above embodiments.

[0086] The buffer 320 according to the fourth embodiment includes a first buffer circuit 321 and a second buffer circuit 322. The first buffer circuit 321 outputs a detection signal (first detection signal) Vsf that depends on the illuminance and changes in illuminance of the light received by the light receiving unit 221. The second buffer circuit 322 outputs a pseudo-signal that does not depend on illuminance or changes in illuminance as a detection signal (second detection signal) Vsf. The first buffer circuit 321 and the second buffer circuit 322 are driven exclusively and selectively. Therefore, when either the first buffer circuit 321 or the second buffer circuit 322 is driven, the other is stopped.

[0087] The first buffer circuit 321 includes N-type transistors 324 and 325. The drain of transistor 324 is connected to the power supply line (first voltage source) of voltage AVDD. The source of transistor 324 is connected to the drain of transistor 325. The gate of transistor 324 is connected to node Npr and receives the voltage signal Vpr. The drain of transistor 325 is connected to the source of transistor 324. The source of transistor 325 is connected to the drain of transistor 323. Also, the source of transistor 325 is connected to node Nsf between the first buffer circuit 321 and the second buffer circuit 322. The gate of transistor 325 receives the selection signal SEL_px.

[0088] The second buffer circuit 322 includes N-type transistors 326 and 327. The drain of transistor 326 is connected to the power supply line of voltage AVDD. The source of transistor 326 is connected to the drain of transistor 327. The gate of transistor 326 receives a pseudo-signal V_Lux. The drain of transistor 327 is connected to the source of transistor 326. The source of transistor 327 is connected to node Nsf. The gate of transistor 327 receives a selection signal xSEL_px. The selection signals SEL_px and xSEL_px are mutually exclusive signals where if one is selected to a high level, the other is deselected to a low level. The selection signals SEL_px and xSEL_px can be controlled by the control unit 40. The pseudo-signal V_Lux is used in place of the voltage signal Vpr and is a voltage signal that does not depend on the light received by the photodetector 221, and can be arbitrarily set by the control unit 40.

[0089] The drain of the N-type transistor 323 is connected to node Nsf. The source of transistor 323 is connected to ground. The gate of transistor 323 receives a predetermined bias voltage Bias_fo. Transistor 323 functions as a constant current source, supplying a constant current to the first and second buffer circuits 321 and 322. As a result, the first buffer circuit 321 outputs a detection signal Vsf according to the voltage signal Vpr to the subtractor 330. The second buffer circuit 322 outputs a detection signal Vsf according to the pseudo-signal V_Lux to the subtractor 330.

[0090] Thus, in the fourth embodiment, the light detection device 1 is configured such that the first buffer circuit 321 outputs a detection signal Vsf corresponding to the pixel signal, and the second buffer circuit 322 outputs a detection signal Vsf corresponding to the pseudo-signal V_Lux. As a result, even if the light receiving unit 221 is receiving a constant illumination from a stationary object, the pixels can repeatedly output on-event Eon and off-event Eoff according to their respective illumination levels. Consequently, the light detection device 1 can accurately focus on a stationary object even when imaging it.

[0091] Furthermore, by using a pseudo-signal V_Lux, it is not necessary to use modulated light, which is easily affected by the characteristics of the optical system, and the latency and other characteristics of the circuit itself after the output of buffer 320 (node ​​Nsf), with the influence of the optical system removed, can be easily and accurately evaluated. When the logic circuit including the subtractor 330 and quantizer 340 after node Nsf is placed on the detection chip 202 shown in Figure 2, the characteristics of the detection circuit can be evaluated using only the semiconductor wafer of the detection chip 202.

[0092] (Examples of applications to mobile devices) The technology disclosed herein (the Technology) can be applied to various electronic devices. For example, the Technology disclosed herein may be implemented as a device mounted on any type of mobile vehicle, such as an automobile, electric vehicle, hybrid electric vehicle, motorcycle, bicycle, personal mobility device, airplane, drone, ship, or robot.

[0093] Figure 16 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology described herein may be applied.

[0094] The vehicle control system 12000 comprises multiple electronic control units connected via a communication network 12001. In the example shown in Figure 16, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 is shown in the figure, which includes a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface 12053.

[0095] The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 12010 functions as a control device for a drivetrain generating device that generates driving force for the vehicle, such as an internal combustion engine or a drive motor; a drivetrain transmission mechanism that transmits driving force to the wheels; a steering mechanism that adjusts the steering angle of the vehicle; and a braking device that generates braking force for the vehicle.

[0096] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 12020 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0097] The external information detection unit 12030 detects information from outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle and receives the captured images. Based on the received images, the external information detection unit 12030 may perform object detection processing such as detecting people, cars, obstacles, signs, or characters on the road surface, or distance detection processing.

[0098] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0099] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver status detection unit 12041 that detects the driver's state. The driver status detection unit 12041 includes, for example, a camera that images the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy, based on the detection information input from the driver status detection unit 12041.

[0100] The microcomputer 12051 can calculate control target values ​​for the drive force generator, steering mechanism, or braking system based on information from inside and outside the vehicle acquired by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including collision avoidance or impact mitigation, following based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

[0101] Furthermore, the microcomputer 12051 can perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on information about the vehicle's surroundings acquired by the external information detection unit 12030 or the internal information detection unit 12040.

[0102] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of a preceding or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control aimed at reducing glare, such as switching from high beams to low beams.

[0103] The audio-image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to the vehicle's occupants or to those outside the vehicle. In the example in Figure 16, the output devices are exemplified as an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

[0104] Figure 17 shows an example of the installation position of the imaging unit 12031.

[0105] In Figure 17, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0106] The imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle 12100. The imaging unit 12101 installed on the front nose and the imaging unit 12105 installed on the upper part of the windshield inside the vehicle mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 installed on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 installed on the upper part of the windshield inside the vehicle is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0107] Figure 17 shows an example of the imaging range of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 12101 to 12104, an overhead view image of the vehicle 12100 can be obtained.

[0108] At least one of the imaging units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple image sensors, or an image sensor having pixels for phase difference detection.

[0109] For example, the microcomputer 12051, based on distance information obtained from imaging units 12101 to 12104, can determine the distance to each object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed to vehicle 12100). In particular, it can extract the nearest object on the vehicle 12100's path that is traveling in approximately the same direction as vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to be maintained before the preceding vehicle and perform automatic braking control (including follow-and-stop control) and automatic acceleration control (including follow-and-start control), etc. In this way, cooperative control aimed at autonomous driving, where the vehicle drives autonomously without driver intervention, can be performed.

[0110] For example, the microcomputer 12051 can use distance information obtained from imaging units 12101 to 12104 to classify and extract three-dimensional object data related to three-dimensional objects, such as motorcycles, passenger cars, heavy vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is above a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance to avoid collisions by outputting a warning to the driver via the audio speaker 12061 or display unit 12062, or by performing forced deceleration or evasive steering via the drive system control unit 12010.

[0111] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not pedestrians are present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by a procedure to extract feature points from the images captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure to perform pattern matching on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes a pedestrian, the audio-image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio-image output unit 12052 may also control the display unit 12062 to display an icon indicating a pedestrian at a desired position.

[0112] The above describes an example of a vehicle control system to which the technology described herein may be applied. The technology described herein may be applied to, for example, the imaging unit 12031 of the configuration described above.

[0113] Furthermore, this technology can be configured as follows:

[0114] (1) A first chip comprising: a light receiving unit that converts incident light into an electrical signal; a part of a conversion circuit that converts the electrical signal into a voltage signal; a first buffer circuit that outputs a first detection signal corresponding to the voltage signal; and first and second capacitive elements, one end of which is connected to the output of the first buffer circuit; and The second chip includes: a first comparator connected to the other end of the first capacitive element, which outputs a first output signal when the first or second detection signal exceeds a first threshold voltage higher than the first or second detection signal; and a second comparator connected to the other end of the second capacitive element, which outputs a second output signal when the first or second detection signal falls below a second threshold voltage lower than the first or second detection signal. A light detection device in which the first chip and the second chip are stacked.

[0115] (2) The first capacitive element is provided between the output of the first buffer circuit and one of the input terminals of the first comparator. The second capacitive element is provided between the output of the first buffer circuit and one of the input terminals of the second comparator. The first threshold voltage is applied to the other input terminal of the first comparator. The photodetector according to (1), wherein the second threshold voltage is applied to the other input terminal of the second comparator.

[0116] (3) A first junction is provided between the other end of the first capacitive element and one input terminal of the first comparator, The photodetector according to (1) or (2), further comprising a second junction provided between the other end of the second capacitive element and one input terminal of the second comparator.

[0117] (4) The photodetector according to (3), wherein the first and second joints are joints formed by directly joining the wiring of the first chip and the wiring of the second chip.

[0118] (5) The power supply portion of the conversion circuit is provided on the second chip, and is the light detection device according to any one of (1) to (4).

[0119] (6) The photodetector according to any one of (1) to (5), further comprising a second chip which quantizes the first and second output signals.

[0120] (7) The first chip includes an N-type transistor and does not have a P-type transistor, as described in any one of (1) to (6).

[0121] (8) The second chip is a CMOS-based photodetector according to any one of (1) to (7).

[0122] (9) The first chip has an analog circuit configured using the first transistor, The photodetector according to any one of (1) to (8), wherein the second chip has a digital circuit configured using a second transistor having a lower breakdown voltage than the first transistor.

[0123] (10) The power supply portion of the first buffer circuit is shared with the power supply portion of the conversion circuit and is provided on the second chip, as described in (5) for the light detection device.

[0124] (11) A third junction electrically connects the power supply portion of the conversion circuit and the power supply of the first chip for each pixel of the light receiving section, The light detection device according to (10), further comprising a fourth junction that electrically connects the power supply portion of the first buffer circuit and the power supply of the first chip to each pixel of the light receiving section.

[0125] (12) The power supply portion of the first buffer circuit and the power supply portion of the conversion circuit are common and provided on the first chip, the light detection device according to any one of (1) to (4).

[0126] (13) The first chip has an analog circuit, The second chip is a light detection device according to (12), having a digital circuit.

[0127] (14) A first chip comprising: a light receiving unit that converts incident light into an electrical signal; a part of a conversion circuit that converts the electrical signal into a voltage signal; a first buffer circuit that outputs a first detection signal corresponding to the voltage signal; and first and second capacitive elements, one end of which is connected to the output of the first buffer circuit; and The second chip includes: a first comparator connected to the other end of the first capacitive element, which outputs a first output signal when the first or second detection signal exceeds a first threshold voltage higher than the first or second detection signal; and a second comparator connected to the other end of the second capacitive element, which outputs a second output signal when the first or second detection signal falls below a second threshold voltage lower than the first or second detection signal. An electronic device having a light detection device, wherein the first chip and the second chip are stacked.

[0128] Furthermore, this disclosure is not limited to the embodiments described above, and various modifications are possible without departing from the gist of this disclosure. Also, the effects described herein are merely illustrative and not limiting, and other effects may exist. [Explanation of Symbols]

[0129] 300 Event Detection Circuit 310 Logarithmic Conversion Circuit 320 buffers 330 Subtractor 331 First Subtraction Circuit 332 Second Subtraction Circuit 340 Quantizer 341 1st quantization circuit 342 Second quantization circuit

Claims

1. A first chip comprising: a light receiving unit that converts incident light into an electrical signal; a part of a conversion circuit that converts the electrical signal into a voltage signal; a first buffer circuit that outputs a first detection signal corresponding to the voltage signal; and first and second capacitive elements, one end of which is connected to the output of the first buffer circuit; and The second chip includes a first comparator connected to the other end of the first capacitive element, which outputs a first output signal when the first detection signal exceeds a first threshold voltage, and a second comparator connected to the other end of the second capacitive element, which outputs a second output signal when the first detection signal falls below a second threshold voltage that is lower than the first threshold voltage. A light detection device in which the first chip and the second chip are stacked.

2. The first capacitive element is provided between the output of the first buffer circuit and one of the input terminals of the first comparator. The second capacitive element is provided between the output of the first buffer circuit and one of the input terminals of the second comparator. The first threshold voltage is applied to the other input terminal of the first comparator. The photodetector according to claim 1, wherein the second threshold voltage is applied to the other input terminal of the second comparator.

3. A first junction is provided between the other end of the first capacitive element and one input terminal of the first comparator, The photodetector according to claim 1, further comprising a second junction provided between the other end of the second capacitive element and one input terminal of the second comparator.

4. The photodetector according to claim 3, wherein the first and second joints are joints formed by directly joining the wiring of the first chip and the wiring of the second chip.

5. The light detection device according to claim 1, wherein the power supply portion of the conversion circuit is provided on the second chip.

6. The photodetector according to claim 1, wherein the second chip further includes a quantizer that binarizes the first and second output signals.

7. The photodetector according to claim 1, wherein the first chip includes an N-type transistor and does not have a P-type transistor.

8. The photodetector according to claim 1, wherein the second chip has a CMOS (Complementary Metal Oxide Semiconductor).

9. The first chip has an analog circuit configured using the first transistor, The photodetector according to claim 1, wherein the second chip has a digital circuit configured using a second transistor having a lower breakdown voltage than the first transistor.

10. The light detection device according to claim 5, wherein the power supply portion of the first buffer circuit is shared with the power supply portion of the conversion circuit and is provided on the second chip.

11. A third junction electrically connects the power supply portion of the conversion circuit and the power supply of the first chip for each pixel of the light receiving section, The light detection device according to claim 10, further comprising a fourth junction that electrically connects the power supply portion of the first buffer circuit and the power supply of the first chip to each pixel of the light receiving unit.

12. The light detection device according to claim 1, wherein the power supply portion of the first buffer circuit and the power supply portion of the conversion circuit are common and provided on the first chip.

13. The first chip has an analog circuit, The light detection device according to claim 12, wherein the second chip has a digital circuit.

14. A first chip comprising: a light receiving unit that converts incident light into an electrical signal; a part of a conversion circuit that converts the electrical signal into a voltage signal; a first buffer circuit that outputs a first detection signal corresponding to the voltage signal; and first and second capacitive elements, one end of which is connected to the output of the first buffer circuit; and The second chip includes a first comparator connected to the other end of the first capacitive element, which outputs a first output signal when the first detection signal exceeds a first threshold voltage, and a second comparator connected to the other end of the second capacitive element, which outputs a second output signal when the first detection signal falls below a second threshold voltage that is lower than the first threshold voltage. An electronic device having a light detection device, wherein the first chip and the second chip are stacked.

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