Semiconductor devices and methods for manufacturing the same
The semiconductor device manufacturing method through damascene formation of drain sections and columnar structures addresses the uneven channel hole issue, ensuring a straight channel material layer and reducing oxide layer damage, thus enhancing device performance and reliability.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- SWAYSURE TECHNOLOGY CO LTD
- Filing Date
- 2025-09-29
- Publication Date
- 2026-05-07
AI Technical Summary
The conventional manufacturing method of semiconductor devices with vertical transistor structures faces challenges in controlling the etching selectivity ratio, leading to uneven channel holes and damage to oxide layers, which affects electrical characteristics and results in device failures.
A method involving damascene formation of drain sections and columnar structures, followed by a channel material layer surrounding these structures, avoids multiple etching steps and ensures a straight channel material layer, thereby improving device performance and reducing damage to oxide layers.
This approach enhances the flatness and integrity of the channel material layer, improving the semiconductor device's electrical performance and reliability by avoiding etching and wet cleaning steps that damage oxide layers.
Smart Images
Figure 2026075057000001_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and more specifically, to semiconductor devices and manufacturing methods thereof.
Background Art
[0002] In the manufacture of semiconductor devices having a conventional vertical transistor structure, typically, after forming a source layer and a first oxide layer on the source layer, a gate layer and a second oxide layer on the gate layer are formed above the first oxide layer. Then, a channel hole penetrating the second oxide layer, the gate layer, and the first oxide layer is formed, and then a channel material layer is formed in the channel hole.
Summary of the Invention
Problems to be Solved by the Invention
[0003] In this manufacturing method, when forming the channel hole, it is necessary to etch film layers of a plurality of different materials, and it is difficult to control the etching selectivity ratio. Therefore, the entire inner wall of the channel hole becomes uneven, and a non-straight channel material layer is formed according to the shape of the hole, which affects the electrical characteristics of the semiconductor device. Furthermore, during the etching and wet cleaning for opening the source layer, damage to the top oxide liner, the bottom oxide liner, and the gate oxide layer is also caused, and furthermore, a failure in the VBD test of the device occurs. Therefore, an improvement is needed to at least partially solve the above problems.
[0004] In the [Summary of the Invention] of the present invention, a series of simplified concepts are introduced. Details thereof will be described in [Modes for Carrying Out the Invention]. The [Summary of the Invention] part of the present invention is not intended to identify the essential features and necessary features of the technical solution for which protection is sought, nor is it intended to specify the protection scope of the technical solution for which protection is sought.
Means for Solving the Problems
[0005] To at least partially solve the above problems, according to a first aspect of the present invention, a method for manufacturing a semiconductor device is provided, which includes the following: To provide a semiconductor structure comprising a first insulating layer, a source layer located on the first insulating layer, and a second insulating layer located on the source layer. Multiple drain sections are formed on the upper part of the second insulating layer, with damascene formation and arranged in an array. Multiple columnar structures are formed on the upper surface of the source layer by etching the second insulating layer so that multiple drain portions are exposed on the source layer, using multiple drain portions as photomasks. Here, each columnar structure includes insulating posts located on the source layer and drain portions located on the insulating posts, and the multiple columnar structures are separated from each other by first trenches formed by etching the second insulating layer. To form a channel material layer that surrounds the columnar structure along its circumferential direction. A gate insulating layer and a gate structure are formed on one side of the channel material layer that is separated from the columnar structure.
[0006] As an example, forming multiple drain sections arranged in an array and damascene-like structure on the upper part of the second insulating layer includes the following: To form a first patterned resist layer on the upper surface of the second insulating layer. 1. Using a patterned resist layer as a photomask, the second insulating layer is etched to form multiple second trenches on top of the second insulating layer, each corresponding to a drain portion. 1. Remove the patterned resist layer and fill the second trench with drain material. The drain portion is formed by polishing and removing the upper surface of the drain material using a chemical mechanical polishing process until it is on the same surface as the upper surface of the second insulating layer.
[0007] As an example, forming a channel material layer surrounding a columnar structure along its circumference involves depositing semiconductor material layers on the inner wall surface of the first trench and the upper surface of the columnar structure. Here, a portion of the semiconductor material layer surrounding the columnar structure along its circumference constitutes a channel material layer.
[0008] As an example, the manufacturing method further includes performing a pre-cleaning treatment on the first trench and the columnar structure before forming a channel material layer that surrounds the columnar structure along the circumferential direction.
[0009] As an example, performing pre-cleaning treatment on the first trench and columnar structures includes the following: The upper surface of the drain portion that was damaged when the second insulating layer was etched using the drain portion as a photomask is subjected to oxidation treatment. Remove oxides formed on the upper surface of the drain section using a wet or dry method, and clean the trench.
[0010] As an example, forming a gate insulating layer and gate structure on one side of the channel material layer that is separated from the columnar structure includes the following: Forming a gate insulating layer so as to conformally cover the surface shape of the semiconductor material layer. A third insulating layer is formed by filling the first trench with insulating material and performing a surface planarization treatment. Here, the upper surface of the third insulating layer is higher than the upper surface of the gate insulating layer. To form a second patterned resist layer on the upper surface of the third insulating layer. Using the second patterned resist layer as a photomask, the third insulating layer, gate insulating layer, semiconductor material layer, and source layer are etched so as to be exposed from the first insulating layer, thereby forming multiple source line cut grooves. The source layer is then extended along the first direction and cut into multiple source lines arranged at intervals in the second direction, and each of the source lines is connected to form a columnar structure arranged along the first direction. Here, both the first and second directions are parallel to the plane on which the first insulating layer exists, and the first and second directions intersect. A fourth insulating layer is formed by filling the source wire cut groove with insulating material and performing a surface planarization treatment. The upper surface of the fourth insulating layer is higher than the gate insulating layer. The first etching back groove is formed by etching back into the fourth insulating layer. Here, the bottom of the first etching back groove is higher than the lowest upper surface of the gate insulating layer. To form a gate structure within the first etching back groove.
[0011] As an example, forming a gate structure within the first etching back groove includes the following: A gate material layer is formed by filling the first etching back groove with gate material and performing a surface planarization treatment. A second etching back groove is formed by etching back against the gate material layer. Here, the bottom of the second etching back groove is lower than the top surface of the drain section. A fifth insulating layer is formed by filling the second etching back groove with gate material and performing a surface planarization treatment. To form a third patterned resist layer on the upper surface of the fifth insulating layer. Using the third patterned resist layer as a photomask, the fifth insulating layer and the gate material layer are etched so as to be exposed from the gate insulating layer, thereby forming multiple word line cut grooves. The gate material layer is then stretched along the second direction and cut into multiple word lines that are spaced apart in the first direction, and each word line connects to form a columnar structure that is arranged along the second direction. Here, some of the word lines that curve around the side of the gate insulating layer away from the columnar structure constitute the gate structure. Fill the word line cut groove with insulating material and perform surface planarization until it is exposed from the top surface of the drain section.
[0012] As an example, the gate material layer includes a composite layer of a barrier layer and a gate metal layer. Filling the first etching back groove with gate material and performing a surface planarization treatment to form a gate material layer includes the following: Depositing a barrier layer conformally on the inner surface of the first etched-back groove and the uppermost upper surface of the gate insulating layer. Filling the remaining space of the first etched-back groove with a gate metal material and performing a surface planarization process to form a gate metal layer. The upper surface of the gate metal layer is higher than the uppermost upper surface of the barrier layer. Forming a second etched-back groove by etching back the gate material layer is as follows. By etching back the barrier layer and the gate metal layer, the uppermost upper surface of the barrier layer and the upper surface of the gate metal layer become coplanar and lower than the upper surface of the drain portion.
[0013] As an example, the barrier layer is a titanium nitride layer and the gate metal layer is a tungsten layer.
[0014] As an example, the gate insulating layer includes a silicon dioxide layer and a silicon nitride layer sequentially deposited following the shape on the semiconductor material layer.
[0015] As an example, in forming the first etched-back groove by etching back the fourth insulating layer, back-etching is performed on the fourth insulating layer using a non-plasma dry etching process.
[0016] As an example, the source layer includes a tungsten layer, a titanium nitride layer, and a polysilicon layer sequentially deposited on the insulating layer, the material of the drain portion is polysilicon, and the material of the channel material layer is polysilicon.
[0017] According to a second aspect of the present invention, a semiconductor device manufactured by the above manufacturing method is provided.
[0018] According to the method for manufacturing a semiconductor device according to the present invention, first, a plurality of drain portions are formed on the upper portion of a second insulating layer located on a source layer. Next, using the drain portions as a photomask, the second insulating layer is etched so as to expose the source layer, thereby forming a plurality of columnar structures arranged in an array on the upper surface of the source layer. Thereafter, a channel material layer is formed to surround the columnar structures along the circumferential direction. Here, since the columnar structures are formed by etching a single material layer, namely the second insulating layer, and do not include a plurality of material layers, the circumferential surface thereof can have good flatness, and a straight channel material layer can be formed on the circumferential surface thereof, thereby effectively improving the performance of the formed semiconductor device. Further, in the method for manufacturing a semiconductor device according to the present invention, first, a channel material layer is formed to surround the columnar structures along the circumferential direction, and thereafter a gate insulating layer and a gate structure are formed, thus avoiding the steps of etching and wet cleaning for opening the source layer. Therefore, the top oxide liner, the bottom oxide liner, and the gate oxide layer are not damaged, and the step of depositing a protective film on the surface of the gate oxide layer is also unnecessary, simplifying the process.
Brief Description of the Drawings
[0019] The following drawings of the present invention are incorporated as part of the present invention and are intended to facilitate the understanding of the present application. The drawings show embodiments of the present invention and their descriptions, and interpret the apparatus and principles of the present invention. In the drawings, it is as follows. [Figure 1] It is a schematic diagram showing a schematic flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 2] It is a top view of the device in each step of the method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 3] It is a top view of the device in each step of the method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 4] It is a top view of the device in each step of the method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 5] This is a schematic top view of the device in each step of the method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 6] This is a schematic top view of the device in each step of the method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7] This is a schematic top view of the device in each step of the method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 8] This is a schematic top view of the device in each step of the method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 9] This is a schematic top view of the device in each step of the method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 10] This is a schematic top view of the device in each step of the method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 11] This is a schematic top view of the device in each step of the method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 12] This is a schematic top view of the device in each step of the method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 13] This is a schematic top view of the device in each step of the method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 14] This is a schematic top view of the device in each step of the method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 15] This is a schematic top view of the device in each step of the method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 16] This is a schematic top view of the device in each step of the method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 17] Figure 2 is a schematic cross-sectional view along line XX. [Figure 18] Figure 3 is a schematic cross-sectional view along line XX. [Figure 19] Figure 4 is a schematic cross-sectional view along line XX. [Figure 20] Figure 5 is a schematic cross-sectional view along line XX. [Figure 21] Figure 6 is a schematic cross-sectional view along line XX. [Figure 22] Figure 7 is a schematic cross-sectional view along line XX. [Figure 23] Figure 8 is a schematic cross-sectional view along line XX. [Figure 24] Figure 9 is a schematic cross-sectional view along line XX. [Figure 25] Figure 10 is a schematic cross-sectional view along line XX. [Figure 26] Figure 11 is a schematic cross-sectional view along line XX. [Figure 27] Figure 12 is a schematic cross-sectional view along line XX. [Figure 28] Figure 13 is a schematic cross-sectional view along line XX. [Figure 29] Figure 14 is a schematic cross-sectional view along the Y-Y line. [Figure 30] Figure 15 is a schematic cross-sectional view along the Y-Y line. [Figure 31] Figure 16 is a schematic cross-sectional view along line XX. [Figure 32] Figure 16 is a schematic cross-sectional view along the Y-Y line. [Modes for carrying out the invention]
[0020] The following description includes numerous specific details to provide a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the invention can be carried out without one or more of these details. In other examples, some technical features known in the art are not described in order to avoid confusion with the present invention.
[0021] For a complete understanding of the present invention, the following description will illustrate the invention with detailed structural details. It will be apparent that the present invention is not limited to specific details well known to those skilled in the art in its implementation. Preferred embodiments of the present invention will be described in detail below, but in addition to these detailed descriptions, the present invention may have other embodiments and should not be construed as being limited to the embodiments shown herein.
[0022] This application should not be construed as being limited to the embodiments described herein, but rather as being implementable in different forms. Rather, by providing these embodiments, the disclosure becomes thorough and complete, and the scope of this application is fully communicated to those skilled in the art. In the drawings, for clarity, the dimensions of layers and areas, as well as relative dimensions, may be exaggerated. Also, the same reference numerals throughout represent the same components.
[0023] The terms “first,” “second,” “third,” etc., may be used to describe various elements, components, regions, layers, and / or parts, but it should be understood that these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used solely to distinguish one element, component, region, layer, or part from another. Accordingly, without departing from the teachings of this application, the first element, component, region, layer, or part discussed below may be referred to as the second element, component, region, layer, or part.
[0024] Spatial relation terms such as "below," "below," "on top," and "on the surface" can be used here for convenience to describe the relationship between one element or feature shown in the drawing and another element or feature. It should be understood that, in addition to the orientation shown in the drawing, spatial relation terms are intended to include different orientations of the device during use and operation.
[0025] It should be understood that the terms used herein are intended solely to describe specific embodiments and are not intended to limit the invention. Furthermore, the singular forms “one,” “one,” and “the / the” are also intended to include the plural form unless the context clearly indicates otherwise. Where the terms “compose” and / or “include” are used herein, they indicate the presence of the aforementioned features, wholes, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or combinations thereof. Where used herein, the terms “and / or” include any and all combinations of the relevant enumerated items.
[0026] Embodiments of the present invention will now be described with reference to a schematic cross-sectional view of an ideal embodiment (and intermediate structure) of the present invention. Thus, variations in the shown shape are expected, for example, due to manufacturing techniques and / or tolerances. Therefore, the embodiments of this application should not be limited to the specific shapes shown herein, and include manufacturing-related shape deviations. Accordingly, what is shown in the figures is essentially schematic, and their shapes are not intended to represent the actual shape of the device and are not intended to limit the scope of the present invention.
[0027] A method for manufacturing a semiconductor device according to an embodiment of the present invention will be illustrated with reference to Figures 1 to 32. Referring to Figure 1, the manufacturing method includes the following steps. S10: A step of providing a semiconductor structure including a first insulating layer, a source layer on the first insulating layer, and a second insulating layer on the source layer. S20: A step of forming multiple drain portions arranged in an array on the upper part of the second insulating layer by forming damascene. S30: A step of forming a plurality of columnar structures arranged in an array on the upper surface of the source layer by etching the second insulating layer so that multiple drain portions are exposed on the source layer using multiple drain portions as photomasks. Here, the columnar structures include insulating posts located on the source layer and drain portions located on the insulating posts, and the plurality of columnar structures are separated from each other by first trenches formed by etching the second insulating layer. S40: A step of forming a channel material layer that surrounds the columnar structure along the circumferential direction. S50: A step of forming a gate insulating layer and a gate structure on one side of the channel material layer that is separated from the columnar structure.
[0028] According to the semiconductor device manufacturing method of the present invention, first, a plurality of drain portions are formed on the upper part of a second insulating layer located on a source layer. Next, the drain portions are used as photomasks to etch the second insulating layer so that it is exposed to the source layer, thereby forming a plurality of columnar structures arranged in a row on the upper surface of the source layer. Subsequently, a channel material layer is formed surrounding the columnar structures along the circumferential direction. Here, the columnar structures are formed by etching a single material layer, the second insulating layer. Because it does not contain multiple material layers, its circumferential surface can have good flatness, and by forming a straight channel material layer on its circumferential surface, the performance of the formed semiconductor device can be effectively improved. Furthermore, the semiconductor device manufacturing method of the present invention avoids the etching and wet cleaning steps for opening the source layer because it first forms a channel material layer surrounding the columnar structures along the circumferential direction, and then forms a gate insulating layer and gate structure. Therefore, the top oxide liner, bottom oxide liner, and gate oxide layer are not damaged, and the step of depositing a protective film on the surface of the gate oxide layer is also unnecessary, simplifying the process.
[0029] The steps for manufacturing a semiconductor device according to an embodiment of the present invention will be described in detail below with reference to Figures 2 to 32.
[0030] Referring to Figures 2 and 17 (Figure 17 is a schematic cross-sectional view of line XX in Figure 2), a semiconductor structure is provided in step S10. The semiconductor structure includes a first insulating layer 100, a source layer 110 located on the first insulating layer 100, and a second insulating layer 120 located on the source layer 110. In this embodiment, the first insulating layer 100 and the second insulating layer 120 are silicon dioxide layers, and the source layer 110 includes a tungsten layer 111, a titanium nitride layer 112, and a polysilicon layer 113 sequentially deposited on the first insulating layer 100.
[0031] In step S20, first, with reference to Figures 3 and 18 (Figure 18 is a schematic cross-sectional view of line XX in Figure 3), a first patterned resist layer 130 is formed on the upper surface of the second insulating layer 120. Specifically, a resist layer is formed on the upper surface of the second insulating layer 120 by a spin coating process or the like, and then the resist layer is patterned by photolithography process steps such as pre-sintering, exposure, development, and post-sintering to form the first patterned resist layer 130. The first patterned resist layer 130 has a plurality of circular openings 131 arranged in an array.
[0032] Next, referring to Figures 4 and 19 (Figure 19 is a schematic cross-sectional view of line XX in Figure 4), the second insulating layer 120 is etched using the first patterned resist layer 130 as a photomask to form multiple second trenches 10 on top of the second insulating layer 120. The depth of the second trenches 10 is much smaller than the thickness of the second insulating layer 120. The second trenches 10 and the drain portions 140 correspond to each other. That is, each second trench 10 is used to form one drain portion 140 thereafter. After that, the first patterned resist layer 130 is removed and the second trenches 10 are filled with drain material. Specifically, the first patterned resist layer 130 is removed by a rubber removal method such as wet stripping or plasma ashing, and the second trenches 10 are filled with drain material by a deposition process such as CVD (Chemical Vapor Deposition). The filled drain material fills the second trench 10 and protrudes from the upper surface of the second insulating layer 120. Subsequently, the drain portion 140 is formed by polishing the upper surface of the drain material until it is flush with the upper surface of the second insulating layer 120 using a chemical mechanical polishing (CMP) process. Multiple drain portions 140 are damascened on the upper part of the second insulating layer 120 and arranged in an array on the upper part of the second insulating layer 120. In this embodiment, the drain material is polysilicon, that is, the material of the formed drain portion 140 is polysilicon.
[0033] In step S30, referring to Figures 5 and 20 (Figure 20 is a schematic cross-sectional view of line XX in Figure 5), the second insulating layer 120 is etched by a dry etching process or the like, using multiple drain portions 140 as photomasks to expose them to the source layer 110. Specifically, it is etched so as to expose the polysilicon layer 113 of the source layer 110, forming multiple columnar structures 150 arranged in a row on the upper surface of the source layer 110. Here, the columnar structures 150 include insulating posts 121 located on the source layer 110 and drain portions 140 located on the insulating posts 121, and the insulating posts 121 are formed by the second insulating layer 120 remaining after etching. The multiple columnar structures 150 arranged in a row are separated from each other by first trenches 20 formed by etching the second insulating layer 120.
[0034] Since the etching processes in steps S20 and S30 are related only to etching a single material layer, the second insulating layer 120, and not to multiple material layers, the etching process and quality can be controlled more easily, and as a result, the circumferential surface of the columnar structure 150 formed by etching can have good flatness.
[0035] In step S40, referring to Figures 6 and 21 (Figure 21 is a schematic cross-sectional view along line XX in Figure 6), a semiconductor material layer 160 is deposited on the inner wall surface of the first trench 20 and on the upper surface of the columnar structure 150. Specifically, the semiconductor material layer 160 is deposited on the inner wall surface of the first trench 20 and on the upper surface of the columnar structure 150 by a deposition process such as CVD (Chemical Vapor Deposition). Here, a portion of the semiconductor material layer 160 surrounding the columnar structure 150 along the circumferential direction constitutes a channel material layer 161, and a portion of the semiconductor material layer 160 located on the upper surface of the columnar structure 150 performs the same function as the drain portion 140. That is, it functions as a drain of the semiconductor device. In this embodiment, the semiconductor material layer 160 is a polysilicon layer, and therefore the material of the channel material layer 161 is polysilicon.
[0036] Because the circumferential surface of the columnar structure 150 has good flatness, a straight channel material layer 161 can be formed on the circumferential surface of the columnar structure 150 in step S40. As a result, the performance of the finally formed semiconductor device, such as the breakdown voltage (Breakdown Voltage, V~BD~), can be effectively improved, and the semiconductor device will have higher reliability and safety.
[0037] As an example, before process S40 (after process S30), the manufacturing method further includes a step of performing a pre-cleaning treatment on the first trench 20 and the columnar structure 150. The pre-cleaning treatment effectively removes etching residue and improves the cleanliness of the surfaces of the first trench 20 and the columnar structure 150. This effectively improves the deposition quality of the semiconductor material layer 160 in process S40.
[0038] For example, the pre-cleaning process includes oxidizing the damaged upper surface of the drain portion 140 when the second insulating layer 120 was etched using the drain portion 140 as a photomask, and then removing the oxide formed on the upper surface of the drain portion 140 using a wet or dry method, as well as cleaning the first trench 20. For example, a thin oxide layer can be formed on the upper surface of the drain portion 140 by a thermal oxidation process, and then the upper surface of the drain portion 140 and the inner wall surface of the first trench 20 can be cleaned using a wet or dry cleaning process to remove the oxide layer formed on the upper surface of the drain portion 140 and the etching residue on the inner wall surface of the first trench 20.
[0039] If pre-cleaning is performed before step S40, the channel material layer 161, gate insulating layer 170, gate structure, etc., have not yet been formed, so the pre-cleaning process does not involve these structures and does not damage them. There is no need to form a specific protective layer to protect specific structures before pre-cleaning, making the process simpler. In conventional technology, it is usually necessary to form a specific protective layer to protect the gate oxide layer, thus avoiding damage during etching to expose the source layer and during the cleaning process. After pre-cleaning, the protective layer must be removed, making the process complex.
[0040] In step S50, first, a gate insulating layer 170 conformally covering the semiconductor material layer 160 is formed, referring to Figures 7 and 22 (Figure 22 is a schematic cross-sectional view of line XX in Figure 7). In this embodiment, the gate insulating layer 170 includes a silicon dioxide layer 171 and a silicon nitride layer 172 that are sequentially conformally covering the semiconductor material layer 160. Specifically, by a deposition process such as a CVD process, a silicon dioxide layer 171 conformally covering the semiconductor material layer 160 is first deposited, and then a silicon nitride layer 172 conformally covering the silicon dioxide layer 171 is deposited.
[0041] Next, referring to Figures 8 and 23 (Figure 23 is a schematic cross-sectional view of line XX in Figure 8), the third insulating layer 180 is formed by filling the first trench 20 with insulating material and performing a surface planarization treatment. The upper surface of the third insulating layer 180 is higher than the upper surface of the gate insulating layer 170. Subsequently, a second patterned resist layer 190 is formed on the upper surface of the third insulating layer 180. In this embodiment, the insulating material is silicon dioxide, and the third insulating layer 180 is a silicon dioxide layer. Specifically, when filling the first trench 20 with insulating material, TEOS (tetraethoxysilane) can be used as a precursor and the CVD process can be used. During the CVD process, TEOS is introduced into the reaction chamber as a precursor gas, and under constant temperature and pressure conditions, TEOS undergoes thermal decomposition or chemical reaction with other reaction gases, generating and depositing silicon dioxide inside the first trench 20 and on the gate insulating layer 170 on the columnar structure 150. TEOS is a relatively inexpensive precursor material, and the CVD process is relatively mature with relatively low equipment costs, thus offering a clear cost advantage. After the generated silicon dioxide fills the first trench 20, a planarization process is performed using a CMP process to form a third insulating layer 180 whose upper surface is higher than the upper surface of the gate insulating layer 170. Subsequently, a resist layer is formed on the upper surface of the third insulating layer 180 by a spin coating process or the like, and then the resist layer is patterned by photolithography process steps such as pre-sintering, exposure, development, and post-sintering to form a second patterned resist layer 190. The second patterned resist layer 190 has a plurality of linear trenches 191 that extend along a first direction and are spaced apart along a second direction. The projection of the linear trenches 191 into the first trench 20 is located between two adjacent rows of columnar structures 150 (and the semiconductor material layer 160 and the gate insulating layer 170 on their surrounding surfaces) that extend along the first direction.
[0042] Next, referring to Figures 9 and 24 (Figure 24 is a schematic cross-sectional view of line XX in Figure 9), the third insulating layer 180, gate insulating layer 170, semiconductor material layer 160, and source layer 110 are etched using the second patterned resist layer 190 as a photomask to expose them to the first insulating layer 100, thereby forming a plurality of source line cut grooves 30. This cuts the source layer 110 into a plurality of source lines 200 that extend along the first direction and are spaced apart along the second direction (left-right direction in Figure 9). Each source line 200 connects a row of columnar structures 150 arranged along the first direction. Both the first and second directions are parallel to the plane on which the first insulating layer 100 is located, and the first and second directions intersect perpendicularly. In some other embodiments, the angle range formed between the first and second directions is between 0° and 90°.
[0043] Next, referring to Figures 10 and 25 (Figure 25 is a schematic cross-sectional view of line XX in Figure 10), the source wire cut groove 30 is filled with insulating material and the surface is planarized to form the fourth insulating layer 210. The upper surface of the fourth insulating layer 210 is higher than the upper surface of the gate insulating layer 170. In this embodiment, the insulating material is silicon dioxide, and the fourth insulating layer 210 is a silicon dioxide layer. Specifically, when filling the source wire cut groove 30 with insulating material, silicon dioxide is first deposited in the source wire cut groove 30 by an ALD (Atomic Layer Deposition) process. The ALD process alternately introduces different precursor gases into the reaction chamber, causing a chemical reaction on the surface of the source wire cut groove 30 and depositing thin films layer by layer. For ALD deposition of silicon dioxide, silicon-containing precursors such as silane and tetraethoxysilane, and oxygen-containing precursors such as oxygen, ozone, and water are usually used. The ALD process can conformally and uniformly deposit silicon dioxide in trenches with a high aspect ratio, but the deposition rate is slow.
[0044] After coating the inner wall of the source wire cut groove 30 with silicon dioxide to a certain thickness using the ALD process, silicon dioxide is deposited using the CVD process with TEOS (tetraethoxysilane) as a precursor. The deposition rate of silicon dioxide using the CVD process is fast. During the CVD process, TEOS is introduced into the reaction chamber as a precursor gas, and under constant temperature and pressure conditions, TEOS undergoes thermal decomposition or chemical reaction with other reaction gases, generating and depositing silicon dioxide on top of the silicon dioxide formed by the ALD process and on top of the third insulating layer 180 remaining after etching. TEOS is a relatively inexpensive precursor material, and the CVD process is relatively mature with relatively low equipment costs, thus offering a clear cost advantage. Subsequently, the deposited silicon dioxide is planarized using the CMP process to form a fourth insulating layer 210 whose upper surface is higher than the upper surface of the gate insulating layer 170. By sequentially using the ALD process and the CVD process to form the fourth insulating layer 210, the formation quality, production speed, and production cost of the fourth insulating layer 210 can be effectively balanced.
[0045] Next, referring to Figures 11 and 26 (Figure 26 is a schematic cross-sectional view along line XX in Figure 11), etching back is performed on the fourth insulating layer 210 to form the first etching back groove 40. The bottom of the first etching back groove 40 is higher than the lowermost upper surface of the gate insulating layer 170. The first etching back groove 40 is exposed on the gate insulating layer 170 located on the upper part of the columnar structure 150 and on a portion of the gate insulating layer 170 located in the circumferential direction of the columnar structure 150. When etching back is performed on the fourth insulating layer 210, a portion of the third insulating layer 180 remaining from the previous etching is also etched simultaneously. Specifically, when etching back is performed on the fourth insulating layer 210, a non-plasma dry etching process is used to avoid the plasma damaging the silicon nitride layer 172 in the gate insulating layer 170. As an example, the non-plasma dry etching process may be an etching process such as a chemical vapor reaction etching process, which is well known to those skilled in the art.
[0046] Subsequently, a gate structure is formed in the first etching back groove 40. First, referring to Figures 12 and 27 (Figure 27 is a schematic cross-sectional view along line XX in Figure 12), gate material is filled into the first etching back groove 40 and a surface planarization treatment is performed to form a gate material layer 220. In this embodiment, the gate material layer 220 is a composite layer including a barrier layer 221 and a gate metal layer 222. The barrier layer may be a titanium nitride layer, and the gate metal layer may be a tungsten layer. Specifically, first, the barrier layer 221 is conformally deposited on the inner surface of the first etching back groove 40 and on the uppermost surface of the gate insulating layer 170. As an example, the barrier layer 221 can be deposited by a deposition process such as a CVD process or a PVD process. Next, the gate metal material is filled into the remaining space of the first etching back groove 40 and a surface planarization treatment is performed to form a gate metal layer 222. The upper surface of the gate metal layer 222 is higher than the uppermost surface of the barrier layer 221. In other words, the gate metal layer 222 completely covers the barrier layer 221. As an example, the remaining space of the first etching back groove 40 is filled with gate metal material by a deposition process such as a PVD process, a sputtering process, or an electroplating process, and then the surface is planarized using a CMP process.
[0047] Next, referring to Figures 13 and 28 (Figure 28 is a schematic cross-sectional view along line XX in Figure 13), etching back is performed on the gate material layer 220 to form a second etching back groove 50. The bottom of the second etching back groove 50 is lower than the upper surface of the drain portion 140. The second etching back groove 50 is exposed to at least the gate insulating layer 170 located on the upper part of the columnar structure 150 and the gate insulating layer 170 located circumferentially on the drain portion 140. Specifically, etching back is performed on the barrier layer 221 and the gate metal layer 222 so that the uppermost upper surface of the barrier layer 221 and the upper surface of the gate metal layer 222 are on the same plane, and the etching back is performed so that the upper surface is lower than the upper surface of the drain portion 140. As an example, etching back can be performed on the barrier layer 221 and the gate metal layer 222 simultaneously using a wet etching process or the like.
[0048] Next, referring to Figures 14 and 29 (Figure 29 is a schematic cross-sectional view along the YY line in Figure 14), the second etching back groove 50 is filled with insulating material and the surface is planarized to form the fifth insulating layer 230. Subsequently, the third patterned resist layer 240 is formed on the upper surface of the fifth insulating layer 230. In this embodiment, the insulating material is silicon dioxide, and the fifth insulating layer 230 is a silicon dioxide layer. Specifically, when filling the second etching back groove 50 with insulating material, TEOS (tetraethoxysilane) can be used as a precursor and the CVD process can be employed. During the CVD process, TEOS is introduced into the reaction chamber as a precursor gas, and under constant temperature and pressure conditions, TEOS undergoes thermal decomposition or chemical reaction with other reaction gases, generating and depositing silicon dioxide inside the second etching back groove 50 and on the uppermost surface of the gate insulating layer 170. TEOS is a relatively inexpensive precursor material, and the CVD process is relatively mature and has relatively low equipment costs, thus offering a clear cost advantage. Subsequently, the filled silicon dioxide is planarized using a CMP process to form a fifth insulating layer 230 whose upper surface is higher than the upper surface of the gate insulating layer 170. Then, a resist layer is formed on the upper surface of the fifth insulating layer 230 by a spin coating process or the like, and the resist layer is then patterned by photolithography process steps such as pre-sintering, exposure, development, and post-sintering to form a third patterned resist layer 240. The third patterned resist layer 240 has a plurality of linear trenches 241 that extend along a second direction and are spaced apart along a first direction. The projection of the linear trenches 241 into the second trench 10 is located between two adjacent rows of columnar structures 150 (and a portion of the semiconductor material layer 160, gate insulating layer 170, and gate material layer 220 on their surrounding surfaces) that extend along the second direction.
[0049] Next, referring to Figures 15 and 30 (Figure 30 is a schematic cross-sectional view of YY in Figure 15), the third patterned resist layer 240 is used as a photomask to etch the fifth insulating layer 230 and the gate material layer 220 so that they are exposed to the gate insulating layer 170, thereby forming a plurality of word line cut grooves 60. This cuts the gate material layer 220 into a plurality of word lines 250 that extend along the second direction and are spaced apart along the first direction. Each word line 250 connects a row of columnar structures 150 arranged along the second direction (the word lines 250 are connected to the columnar structures 150 via the gate insulating layer 170; that is, the word lines 250 and the columnar structures 150 are separated by the gate insulating layer 170). Here, a portion of the word lines 250 surrounding the side of the gate insulating layer 170 away from the columnar structures 150 constitutes the gate structure.
[0050] Next, referring to Figures 16, 31, and 32 (Figure 31 is a cross-sectional view along line XX in Figure 16, and Figure 32 is a cross-sectional view along line YY in Figure 16), insulating material 260 is filled into the word line cut groove 60 so as to expose the upper surface of the semiconductor material layer 160, and then a surface planarization treatment is performed. In this embodiment, the insulating material 260 is silicon dioxide. Specifically, when filling the word line cut groove 60 with insulating material 260, silicon dioxide is first deposited into the word line cut groove 60 by an ALD (Atomic Layer Deposition) process. In the ALD process, different precursor gases are alternately introduced into the reaction chamber, causing a chemical reaction on the surface of the word line cut groove 60, and a thin film is deposited layer by layer. For ALD deposition of silicon dioxide, silicon-containing precursors such as silane and tetraethoxysilane, and oxygen-containing precursors such as oxygen, ozone, and water are usually used. The ALD process can conformally and uniformly deposit silicon dioxide in trenches with a high aspect ratio, but the deposition rate is slow.
[0051] After covering the inner wall of the word line cut groove 60 with silicon dioxide to a certain thickness using the ALD process, silicon dioxide is deposited using the CVD process with TEOS (tetraethoxysilane) as a precursor. The deposition rate of silicon dioxide using the CVD process is fast. During the CVD process, TEOS is introduced into the reaction chamber as a precursor gas, and under constant temperature and pressure conditions, TEOS undergoes thermal decomposition or chemical reaction with other reaction gases, generating and depositing silicon dioxide on top of the silicon dioxide formed by the ALD process and on top of the fifth insulating layer 230 remaining after etching. TEOS is a relatively inexpensive precursor material, and the CVD process is relatively mature and has relatively low equipment costs, thus offering a clear cost advantage. Subsequently, the semiconductor material layer 160 is used as a polishing stop layer, and the filled silicon dioxide and gate insulating layer 170 are planarized using the CMP process so as to expose the upper surface of the semiconductor material layer 160. By sequentially using the ALD process and the CVD process to fill the insulating material 260, it is possible to effectively balance the filling quality, production speed, and production cost of the insulating material 260.
[0052] This concludes the introduction to the steps relating to the method for manufacturing a semiconductor device in the embodiment of the present invention. After the above steps, other conventional steps for manufacturing a semiconductor device may be included, but these will not be described in further detail here. In addition to the above steps, the manufacturing method in this embodiment may include other steps within or between each of the above steps, and these steps can all be implemented by various processes of the prior art, but will not be described in further detail here.
[0053] The present invention further provides a semiconductor device manufactured by the above-described manufacturing method. The semiconductor device provided in the present invention can be applied to memories such as Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), and Flash Memory. Of course, it can also be applied to other memory devices not listed here, and these will not be listed one by one.
[0054] While exemplary embodiments are described here with reference to the drawings, it should be understood that these exemplary embodiments are merely illustrative and not intended to limit the invention to the embodiments described herein. Those skilled in the art will understand that a wider variety of modifications and alterations can be made without departing from the scope and spirit of the invention, all of which fall within the scope of the protections claimed by the invention.
[0055] In some embodiments provided by the present invention, it should be understood that the disclosed equipment and methods can be implemented in other ways. For example, the embodiments of equipment described above are merely illustrative. For example, the division of units is merely a division of logical functions, and in actual implementation there may be other methods of division, such as multiple units or components being combined, being combined with another device, or some features being omitted or not performed.
[0056] The specification provided herein describes numerous specific details. However, it will be understood that the embodiments of this application can be practiced even without these specific details. In order not to obscure the understanding of this specification, some examples do not describe in detail known methods, structures and techniques.
[0057] Similarly, in order to simplify the invention and to help understand one or more aspects of the invention, various features of the invention may sometimes be grouped together in a single embodiment, drawing, or description in the description of exemplary embodiments of the application for the invention. However, the methods of the invention should not be interpreted as having the following intent: namely, the invention seeking protection requires more features than those explicitly stated in each claim. Rather, as reflected in the corresponding claims, the inventive concept aims to solve a corresponding technical problem using fewer features than all the features of a single disclosed embodiment combined. Accordingly, claims according to a specific embodiment are described in that specific embodiment, where each claim itself may be a single embodiment of the invention.
[0058] Those skilled in the art will understand that, except where the features conflict with each other, any combination of all features disclosed herein (including the claims, abstract, and drawings) and all processes or units of the methods or equipment thus disclosed may be employed. Unless otherwise expressly stated, alternative features that serve a similar, equivalent, or similar purpose may be employed in place of each feature disclosed herein (including the claims, abstract, and drawings).
[0059] Furthermore, those skilled in the art will understand that while some embodiments described herein contain certain features found in other embodiments rather than others, combinations of features from different embodiments fall within the scope of the present invention and constitute different embodiments. For example, any combination of the embodiments for which protection is sought can be used in the claims.
[0060] It should be understood that the above embodiments are illustrative of the present invention and are not intended to limit it. Furthermore, it should be noted that those skilled in the art can design embodiments within the scope of the claims. [Explanation of symbols]
[0061] 100: First insulating layer 110: Source layer 111: Tungsten layer 112: Titanium nitride layer 113: Polysilicon layer 120: Second insulating layer 121: Insulating Post 130: First patterned resist layer 131: Circular opening 140: Drain section 150: Columnar structure 160: Semiconductor material layer 161: Channel material layer 170: Gate Insulation Layer 171: Silicon dioxide layer 172: Silicon Nitride Layer 180: Third insulating layer 190: Second patterned resist layer 191: Linear trench 200: Source line 210: Fourth insulating layer 220: Gate material layer 221: Barrier layer 222: Gate metal layer 230: Fifth insulating layer 240: Third patterned resist layer 241: Linear trench 250: Word line 260: Insulating materials 10: Trench 2 20: Trench 1 30: Source wire cut groove 40: First etching back groove 50: Second etching back groove 60: Word line cut groove
Claims
1. To provide a semiconductor structure comprising a first insulating layer, a source layer located on the first insulating layer, and a second insulating layer located on the source layer, A plurality of drain portions are formed on the upper part of the second insulating layer, arranged in a damascene pattern, Multiple columnar structures are formed on the upper surface of the source layer by etching the second insulating layer so that the multiple drain portions are exposed on the source layer, wherein each columnar structure includes insulating posts located on the source layer and drain portions located on the insulating posts, and the multiple columnar structures are separated from each other by first trenches formed by etching the second insulating layer. Forming a channel material layer that surrounds the columnar structure along the circumferential direction, A gate insulating layer and a gate structure are formed on one side of the channel material layer that is separated from the columnar structure. A method for manufacturing semiconductor devices, including [the specified element].
2. Forming a plurality of drain portions arranged in an array on the upper part of the second insulating layer, which are formed as damascene, A first patterned resist layer is formed on the upper surface of the second insulating layer. Using the patterned resist layer as a photomask, the second insulating layer is etched to form a plurality of second trenches on the upper part of the second insulating layer that correspond one-to-one with the drain portions. Remove the patterned resist layer and fill the second trench with drain material. The drain portion is formed by polishing and removing the upper surface of the drain material by a chemical mechanical polishing process until it is co-surface with the upper surface of the second insulating layer. The manufacturing method according to claim 1, characterized by including
3. Forming the channel material layer surrounding the columnar structure along the circumferential direction includes depositing a semiconductor material layer on the inner wall surface of the first trench and on the upper surface of the columnar structure. The manufacturing method according to claim 1, characterized in that a portion of the semiconductor material layer surrounding the columnar structure along the circumferential direction constitutes the channel material layer.
4. The manufacturing method according to claim 3, further comprising performing a pre-cleaning treatment on the first trench and the columnar structure before forming the channel material layer that surrounds the columnar structure along the circumferential direction.
5. Performing a pre-cleaning treatment on the first trench and the columnar structure is When the drain portion is used as a photomask to etch the second insulating layer, the damaged upper surface of the drain portion is subjected to oxidation treatment. The oxide formed on the upper surface of the drain section is removed by a wet or dry method, and the first trench is cleaned. The manufacturing method according to claim 4, characterized by including
6. Forming the gate insulating layer and the gate structure on one side of the channel material layer that is separated from the columnar structure means that The gate insulating layer is formed so as to conformally cover the surface shape of the semiconductor material layer. A third insulating layer is formed by filling the first trench with insulating material and performing a surface planarization treatment, wherein the upper surface of the third insulating layer is higher than the upper surface of the gate insulating layer. A second patterned resist layer is formed on the upper surface of the third insulating layer. Using the second patterned resist layer as a photomask, the third insulating layer, the gate insulating layer, the semiconductor material layer, and the source layer are etched so as to be exposed from the first insulating layer, thereby forming a plurality of source line cut grooves, the source layer is stretched along a first direction and cut into a plurality of source lines arranged at intervals in a second direction, and each of the source lines is connected to a row of columnar structures arranged along the first direction, wherein both the first and second directions are parallel to the plane on which the first insulating layer exists, and the first and second directions intersect. A fourth insulating layer is formed by filling the source wire cut groove with insulating material and performing a surface planarization treatment, and the upper surface of the fourth insulating layer is higher than the gate insulating layer. By etching back the fourth insulating layer, a first etching back groove is formed, where the bottom of the first etching back groove is higher than the lowest upper surface of the gate insulating layer. To form the gate structure in the first etching back groove, The manufacturing method according to claim 3, characterized by including
7. Forming the gate structure within the first etching back groove means A gate material layer is formed by filling the first etching back groove with gate material and performing a surface planarization treatment. A second etching back groove is formed by etching back into the gate material layer, where the bottom of the second etching back groove is lower than the upper surface of the drain portion. A gate material is filled into the second etching back groove and a surface planarization treatment is performed to form a fifth insulating layer. A third patterned resist layer is formed on the upper surface of the fifth insulating layer. Using the third patterned resist layer as a photomask, the fifth insulating layer and the gate material layer are etched so as to be exposed from the gate insulating layer to form a plurality of word line cut grooves, the gate material layer is stretched along the second direction and cut into a plurality of word lines arranged at intervals in the first direction, each of the word lines connects to a row of columnar structures arranged along the second direction, where a portion of the word lines that curve around the side of the gate insulating layer away from the columnar structures constitute the gate structure. Fill the word line cut groove with insulating material and perform surface planarization treatment until it is exposed from the upper surface of the drain portion. The manufacturing method according to claim 6, characterized by including
8. The gate material layer includes a composite layer of a barrier layer and a gate metal layer. Filling the first etching back groove with gate material and performing a surface planarization treatment to form the gate material layer is, The barrier layer is conformally deposited on the inner surface of the first etching back groove and the uppermost surface of the gate insulating layer. The gate metal layer is formed by filling the remaining space of the first etching back groove with gate metal material and performing a surface planarization treatment, and the upper surface of the gate metal layer is higher than the uppermost upper surface of the barrier layer. Forming the second etching back groove by etching back against the gate material layer is, By etching back the barrier layer and the gate metal layer, the uppermost surface of the barrier layer and the upper surface of the gate metal layer become coplane, and are lower than the upper surface of the drain portion. The manufacturing method according to claim 7, characterized in that it
9. The aforementioned barrier layer is a titanium nitride layer, The gate metal layer is a tungsten layer. The manufacturing method according to claim 8.
10. The manufacturing method according to claim 6, characterized in that the gate insulating layer includes a silicon dioxide layer and a silicon nitride layer that are sequentially deposited on the semiconductor material layer in accordance with its shape.
11. The manufacturing method according to claim 10, characterized in that, in forming the first etching back groove by etching back the fourth insulating layer, a non-plasma dry etching process is used to perform back etching on the fourth insulating layer.
12. The source layer includes a tungsten layer, a titanium nitride layer, and a polysilicon layer that are sequentially deposited on the first insulating layer. The material of the drain section is polysilicon. The manufacturing method according to claim 1, characterized in that the material of the channel material layer is polysilicon.
13. A semiconductor device characterized by being manufactured by the manufacturing method described in any one of claims 1 to 12.