Image sensor

Abstract

To provide an image sensor that can improve performance and productivity. [Solution] The image sensor according to the present invention comprises a substrate having a first surface and a second surface facing each other, a photoelectric conversion unit disposed on the substrate, a pixel circuit disposed on the first surface side of the substrate, and a separation pattern that penetrates at least a part of the substrate and includes a separation portion that defines a region where the photoelectric conversion unit is disposed. The pixel circuit includes a first transistor including a first transmission transistor and a second transmission transistor, and the active region of the substrate disposed on the first surface of the substrate includes a first active portion where the first transmission transistor is disposed, a second active portion where the second transmission transistor is disposed, and a connecting active portion that connects the first active portion and the second active portion in a first diagonal direction inclined with respect to the separation portion.

Description

Technical Field

[0001] The present invention relates to an image sensor, and more particularly to an image sensor with an improved structure.

Background Art

[0002] An image sensor is a semiconductor device that converts an optical image into an electrical signal. Image sensors are classified into charge-coupled device (CCD) type image sensors based on silicon semiconductors and complementary metal oxide semiconductor (CMOS) type image sensors (CIS). Among these, CMOS type image sensors have a simple driving method, can integrate a signal processing circuit on a single chip, can be miniaturized, have low power consumption, and are applicable to products with limited battery capacity.

[0003] Therefore, as the electronics industry develops, continuous research on improving the performance of CMOS type image sensors has become an everyday issue.

Summary of the Invention

Problems to be Solved by the Invention

[0004] The present invention has been made in view of the problems in the above-mentioned conventional image sensors, and an object of the present invention is to provide an image sensor capable of improving performance and productivity.

Means for Solving the Problems

[0005] To achieve the above objective, the present invention provides an image sensor comprising: a substrate having a first surface and a second surface facing each other; a photoelectric conversion unit disposed on the substrate; a pixel circuit disposed on the first surface side of the substrate; and a separation pattern that penetrates at least a portion of the substrate and includes a separation portion defining a region where the photoelectric conversion unit is disposed. The pixel circuit includes a first transistor including a first transmission transistor and a second transmission transistor, and the active region of the substrate disposed on the first surface of the substrate includes a first active region comprising a first active portion where the first transmission transistor is disposed, a second active portion where the second transmission transistor is disposed, and a connecting active portion that connects the first active portion and the second active portion in a first diagonal direction inclined with respect to the separation portion.

[0006] Furthermore, an image sensor according to the present invention, made to achieve the above objective, comprises a substrate having a first surface and a second surface facing each other, a photoelectric conversion unit disposed on the substrate, a pixel circuit disposed on the first surface side of the substrate, and a separation pattern penetrating at least a part of the substrate, wherein the photoelectric conversion unit includes a first conversion portion disposed on the first side in a first direction and a second conversion portion disposed on the second side opposite to the first side, and the pixel circuit includes a first transistor which includes a first transmission transistor electrically connected to the first conversion portion and disposed on the third side in a second direction intersecting the first direction, and a second transmission transistor electrically connected to the second conversion portion and disposed on the fourth side opposite to the third side in the second direction.

[0007] Furthermore, the image sensor according to the present invention, made to achieve the above objective, comprises a substrate having a first surface and a second surface facing each other, a plurality of pixel regions each including a photoelectric conversion unit disposed on the substrate and a pixel circuit disposed on the first surface side of the substrate, and a separation pattern including a separation portion that penetrates at least a part of the substrate and defines a region in which the photoelectric conversion unit is disposed, wherein the photoelectric conversion unit includes a first conversion portion disposed on the first side in a first direction and a second conversion portion disposed on the second side opposite to the first side, and the pixel circuit has a point-symmetric shape in the pixel region and an asymmetric shape in the first direction. [Effects of the Invention]

[0008] According to the image sensor of the present invention, the first transmission transistor and the second transmission transistor are arranged on both sides in the first diagonal direction, the first active region is extended in the first diagonal direction, and the first active region has a symmetrical shape (for example, a point-symmetric shape) with respect to the first internal portion and the second internal portion of the separation pattern. Furthermore, the second and third transistors are arranged on both sides in the second diagonal direction, respectively, which increases the degree of freedom and area of ​​placement for the second and third transistors, and ensures spacing between multiple transistors. This can improve the performance and productivity of image sensors. [Brief explanation of the drawing]

[0009] [Figure 1] This block diagram shows a schematic configuration of an example of an image sensor according to an embodiment of the present invention. [Figure 2] Figure 1 is a circuit diagram of the pixel array included in the image sensor shown. [Figure 3] This is a partial cross-sectional view showing a part of an image sensor according to one embodiment of the present invention. [Figure 4] Figure 3 is a schematic plan view showing multiple pixel regions of the image sensor. [Figure 5]This is a plan view showing one of the multiple pixel regions shown in Figure 4. [Figure 6] This is a cross-sectional view taken along the line C-C' in Figure 5. [Figure 7] This is a schematic plan view showing multiple pixel regions of an image sensor according to another embodiment of the present invention. [Figure 8] This is a schematic plan view showing multiple pixel regions of an image sensor according to another embodiment of the present invention. [Figure 9] This is a schematic plan view showing multiple pixel regions of an image sensor according to another embodiment of the present invention. [Figure 10] This is a schematic plan view showing multiple pixel regions of an image sensor according to another embodiment of the present invention. [Figure 11] This is a schematic plan view showing multiple pixel regions of an image sensor according to another embodiment of the present invention. [Figure 12] This is a schematic plan view showing multiple pixel regions of an image sensor according to another embodiment of the present invention. [Figure 13] This is a schematic plan view showing the pixel region of an image sensor according to another embodiment of the present invention. [Figure 14] This is a schematic plan view showing the pixel region of an image sensor according to another embodiment of the present invention. [Figure 15] This is a partial cross-sectional view showing a part of an image sensor according to another embodiment of the present invention. [Modes for carrying out the invention]

[0010] Next, specific examples of embodiments for implementing the image sensor according to the present invention will be described with reference to the drawings.

[0011] The embodiments can be realized in a variety of forms and are not limited to the embodiments described herein. To clearly explain the present invention, unnecessary explanatory parts have been omitted, and the same reference numerals are used throughout the specification for identical or similar components. Also, the sizes and thicknesses of each configuration shown in the drawings are arbitrarily shown for the convenience of explanation, and the present invention is not limited to the drawings. For the convenience of explanation and / or for simple illustration, the thicknesses of some layers and regions are enlarged or exaggerated.

[0012] Also, when a part such as a layer, film, region, or plate is "above" another part, this includes not only the case where it is directly above the other part but also the case where there are other parts in between. Conversely, when a part is "directly above" another part, it means that there are no other parts in between. Also, being "above" a reference part means being located above or below the reference part, and does not necessarily mean being located "above" in the direction opposite to gravity. Also, throughout the specification, when a part "includes" a certain component, this means that, unless otherwise stated to the contrary, it can further include other components rather than excluding other components. Also, throughout the specification, "on a plane" or "in a plan view" means when looking at the target part from above, and "in a cross-section" or "when looking at a cross-section" means when looking at the cross-section obtained by vertically cutting the target part from the side.

[0013] Hereinafter, referring to FIGS. 1 to 6, an image sensor according to an embodiment of the present invention will be described in detail. FIG. 1 is a block diagram showing a schematic configuration of an example of an image sensor 10 according to an embodiment of the present invention. Referring to FIG. 1, an image sensor 10 according to an embodiment of the present invention includes a pixel array 10a and a logic circuit 20 that controls the pixel array 10a.

[0014] The logic circuit 20 is a circuit for controlling the pixel array 10a and includes, for example, a controller 22, a timing generator 24, a load driver 26a, a readout circuit 26b, a lamp signal generator 26c, and a data buffer 28. Furthermore, the image sensor 10 may further include an image signal processor 30. Depending on the embodiment, the image signal processor 30 may be located outside the image sensor 10. The image sensor 10 converts light received from an external source into an electrical signal to generate an image signal, and the image signal generated by the image sensor 10 is provided to the image signal processor 30.

[0015] The image sensor 10 can be mounted on an electronic device having an image or light sensing function. For example, the image sensor 10 can be mounted on electronic devices such as cameras, smartphones, wearable devices, Internet of Things (IoT) devices, home appliances, tablets, personal digital assistants (PDAs), portable multimedia players (PMPs), navigation systems, drones, or advanced driver assistance systems (ADAS). Alternatively, the image sensor 10 can be mounted as a component in an electronic device that is installed in a vehicle, furniture, manufacturing equipment, door, or various measuring instruments.

[0016] The pixel array 10a includes multiple pixel regions PX, and multiple row lines RL and multiple column lines CL connected to each of the multiple pixel regions PX. In one embodiment, each pixel region PX includes at least one photoelectric conversion element. The photoelectric conversion element senses the incident light and converts the incident light into an electrical signal based on the amount of light, that is, multiple analog pixel signals. The photoelectric conversion element may be a photodiode, phototransistor, photogate, or pinned photodiode (PPD). Alternatively, the photoelectric conversion element may be a single-photon avalanche diode (SPAD) applied to the 3D sensor pixel. The level of the analog pixel signal output from the photoelectric conversion element is proportional to the amount of light supplied to each pixel region PX or the amount of charge output from the photoelectric conversion element.

[0017] Multiple low lines RL are extended in one direction and connected to multiple pixel regions PX that are arranged along that direction. For example, a control signal output from the low driver 26a to the low line RL is transmitted to the gates of transistors in multiple pixel regions PX connected to the low line RL. The column line CL extends in one direction and in a direction intersecting it, and connects to multiple pixel regions PX arranged along the direction intersecting it. Multiple pixel signals output from multiple pixel regions PX are transmitted to the readout circuit 26b through multiple column lines CL. In one embodiment, multiple pixel regions PX are grouped in the form of multiple columns and / or multiple rows to constitute a single unit pixel group. In other words, multiple pixels arranged in the direction of extension of the row line RL and / or multiple pixel regions PX arranged in the direction of extension of the column line CL constitute a single unit pixel group.

[0018] For example, one unit pixel group includes multiple pixel regions PX arranged in the form of two columns and / or two rows, and one unit pixel group outputs one pixel signal. However, the embodiments are not limited to these, and various modifications are possible. As another example, a single pixel region PX can constitute a single unit pixel group. Depending on the embodiment, each pixel region PX includes a pixel circuit that processes the charge generated by a photoelectric conversion element and outputs an electrical signal. The pixel circuit includes transmission transistors, reset transistors, selection transistors, drive transistors, and so on. The embodiments are not limited thereto, and the pixel circuit can have a variety of structures.

[0019] The controller 22 provides overall control over the timing generator 24, low driver 26a, readout circuit 26b, ramp signal generator 26c, data buffer 28, and other components included in the image sensor 10. For example, controller 22 controls the timing of the operation using a control signal. In one embodiment, the controller 22 receives a mode signal from the application processor that instructs the imaging mode, and controls the image sensor 10 overall based on the received mode signal. The timing generator 24 generates a signal that serves as a reference for the operating timing of the image sensor 10. The timing generator 24 provides control signals to control the timing of the low driver 26a, the readout circuit 26b, and the ramp signal generator 26c.

[0020] The low driver 26a generates control signals to drive the pixel array 10a in response to control signals from the timing generator 24, and provides control signals to multiple pixel regions PX of the pixel array 10a through multiple low lines RL. For example, the low driver 26a generates and provides to the pixel array 10a transmission signals to control the transmission transistors, reset control signals to control the reset transistors, and selection control signals to control the selection transistors. The readout circuit 26b converts the pixel signal (or electrical signal) output through the corresponding column line CL into a pixel value indicating the amount of light. The ramp signal generator 26c generates a reference signal or ramp signal and transmits it to the readout circuit 26b. For example, the readout circuit 26b compares the ramp signal and the pixel signal and converts the pixel signal into a pixel value. Pixel values ​​are image data that have multiple bits.

[0021] The data buffer 28 stores the pixel values ​​of the pixel region PX transmitted from the readout circuit 26b and outputs the stored pixel values ​​in response to a signal from the controller 22. The image signal processor 30 performs image signal processing on the image signal received from the data buffer 28. For example, the image signal processor 30 receives multiple image signals from the data buffer 28 and combines the received image signals to generate a single image. The image sensor 10 described above is merely an example, and its structure, method, and other aspects can be varied in many ways.

[0022] Figure 2 is a circuit diagram of the pixel array 10a included in the image sensor 10 shown in Figure 1. Referring to Figure 2, the pixel array 10a includes a photoelectric conversion unit PD, a transmission transistor TX, a reset transistor RX, gain control transistors (DCX, MCX), a drive transistor SF, and a selection transistor SX. The photoelectric conversion unit PD shown in Figure 2 corresponds to the photoelectric conversion unit 120 shown in Figure 3. The transmission transistor TX is connected between the photoelectric conversion unit PD and the first floating diffusion node FD1. In response to a transmission control signal TS applied to the gate of the transmission transistor TX, the transmission transistor TX transmits the charge generated in the photoelectric conversion unit PD to the first floating diffusion node FD1.

[0023] The gain control transistors (DCX, MCX) are connected between the first floating diffusion node FD1 and the reset transistor RX. Gain control transistors (DCX, MCX) are controlled by gain control signals (DCG, MCG). Gain-controlled transistors (DCX, MCX) are transistors used to reduce the conversion gain, which is the ratio at which electric charge is converted into voltage, by adjusting capacitance. In this embodiment, the gain control transistors (DCX, MCX) may be provided in multiple units. For example, the gain control transistors (DCX, MCX) include a first gain control transistor DCX connected between a first floating diffusion node FD1 and a second floating diffusion node FD2, and a second gain control transistor MCX connected between a second floating diffusion node FD2 and a third floating diffusion node FD3. The first gain control transistor DCX and the second gain control transistor MCX are turned on or off to operate in low conversion gain (LCG) mode, middle conversion gain (MCG) mode, and high conversion gain (HCG) mode.

[0024] The reset transistor RX is connected between the power supply voltage line that supplies the power supply voltage and the third floating diffusion node FD3. When the reset control signal RS is applied to the reset transistor RX, the charge accumulated in the third floating diffusion node FD3 is reset. When the first gain control transistor DCX and / or the second gain control transistor MCX are turned on while the reset control signal RS is applied to the reset transistor RX, the charge accumulated in the first floating diffusion node FD1 and / or the second floating diffusion node FD2 is reset. However, the embodiments are not limited to these. As an example, the pixel array 10a may include one of the first gain control transistor DCX and the second gain control transistor MCX, but may not include the other. As another example, the pixel array 10a does not need to include gain control transistors (DCX, MCX). If gain control transistors (DCX, MCX) are not included, one end of the reset transistor RX is directly connected to the first floating diffusion node FD1.

[0025] The gate of the drive transistor SF is connected to the first floating diffusion node FD1. The drive transistor SF acts as a source follower buffer amplifier, buffering the signal based on the amount of charge charged to the first floating diffusion node FD1. The drive transistor SF amplifies the potential change at the first floating diffusion node FD1 and outputs the amplified result to the output node N1. Figure 2 illustrates a configuration in which the drive transistors SF include a first drive transistor SF1 and a second drive transistor SF2, which are connected in parallel to each other. However, the embodiment is not limited to this, and it may also include a single drive transistor SF. The selection transistor SX is connected between the output node N1 and the column line CL. The selection transistor SX can output a pixel signal VS to the column line CL in response to the selection control signal SEL.

[0026] Figure 3 is a partial cross-sectional view showing a part of an image sensor 10 according to one embodiment of the present invention, and Figure 4 is a schematic plan view showing multiple pixel regions PX of the image sensor 10 shown in Figure 3. Figure 3 is a cross-sectional view taken along lines A-A' and B-B' in Figure 4. Figure 4 is a rear plan view shown with reference to the first surface 110a of the substrate 110 adjacent to the wiring section 170. For clearer understanding, Figure 4 primarily shows the gate electrode 140g for the second transistor 144 and the third transistor 146.

[0027] Referring to Figures 3 and 4, in one embodiment of the present invention, the image sensor 10 includes a substrate 110 having a first surface 110a and a second surface 110b that are opposite to each other, a photoelectric conversion unit 120 disposed on the substrate 110, a pixel circuit 130 located on the first surface 110a side of the substrate 110, and a separation pattern 126 that penetrates at least a portion of the substrate 110. In this embodiment, the substrate 110 may include a semiconductor substrate containing a semiconductor material. For example, the substrate 110 may be a bulk substrate containing a semiconductor material, a substrate on which an epitaxial layer is formed, or a semiconductor-on-insulator. At this time, the semiconductor material provided on the substrate 110 has a second conductivity type (for example, p-type or n-type) that is opposite to the first conductivity type region 122.

[0028] The semiconductor material contained in the substrate 110 may include at least one of the following: a group IV semiconductor, a group III-V compound semiconductor, and a group II-VI compound semiconductor. For example, the semiconductor material contained in the substrate 110 may include at least one of Si, Ge, SiGe, SiC, GaAs, InAs, GaP, InP, InSb, InGaAs, ZnTe, and CdS. For example, the bulk substrate may be a single-crystal or polycrystalline semiconductor substrate and may contain Si, Ge, or SiGe. For example, a semiconductor-on-insulator may be a silicon-on-insulator (SOI), a germanium-on-insulator (SGOI), or a silicon-germanium-on-insulator (SGOI).

[0029] The doping region is located in an active region (reference numeral 118 in Figure 5, hereafter the same) on the first surface 110a side of the substrate 110 (for example, on a part of the substrate 110 adjacent to the first surface 110a). The doping region includes the floating diffusion region 120f, the grounding region, and so on. For the sake of simplicity, Figure 4 shows the floating diffusion region 120f, and the grounded region is omitted from the illustration.

[0030] The floating diffusion region 120f is a region having a first conductivity type opposite to that of the substrate 110, and is a region where the charge generated by the photoelectric conversion unit 120 accumulates. The location of the floating diffusion region 120f, its electrical connection structure, and other details will be explained in more detail later. The grounding region is a region having the same second conductivity type as the substrate 110 and a higher doping concentration than the substrate 110 or the second conductivity type region 124. A ground voltage is applied to the grounded area. The grounding region can be formed in part of the active region 118. However, the embodiments are not limited thereto, and the floating diffusion region 120f and / or grounding region may not be included. Alternatively, the system may further include doping regions other than the floating diffusion region 120f and / or the grounded region.

[0031] In this embodiment, the image sensor 10 includes a plurality of pixel regions PX. Each of the multiple pixel regions PX includes a photoelectric conversion unit 120 arranged on the substrate 110, and a pixel circuit 130 arranged on the first surface 110a side of the substrate 110. Multiple pixel regions PX include a first pixel region PX1 and a second pixel region PX2 that are adjacent in the first direction (the X-axis direction of the drawing), and a third pixel region PX3 and a fourth pixel region PX4 that are adjacent to the first pixel region PX1 and the second pixel region PX2, respectively, in the second direction (the Y-axis direction of the drawing) that intersects with the first direction (the X-axis direction of the drawing). For example, the first pixel region PX1, the second pixel region PX2, the third pixel region PX3, and the fourth pixel region PX4 shown in Figure 4 constitute a single unit pixel group, but the embodiment is not limited to this.

[0032] The photoelectric conversion unit 120, which is located on the substrate 110, converts light incident from the outside into an electrical signal. For example, the photoelectric conversion unit 120 includes a first conductivity region 122 containing a first conductivity dopant and having a first conductivity type (e.g., n-type or p-type) opposite to that of the substrate 110, and a second conductivity region 124 containing a second conductivity dopant and having a second conductivity type (e.g., p-type or n-type) opposite to that of the first conductivity type. The first conductivity type region 122 is formed by doping the substrate 110 with the first conductivity type dopant. The second conductivity region 124 is formed by doping the second conductivity dopant into a portion of the substrate 110 adjacent to the first surface 110a of the substrate 110, or it is composed of a portion of the substrate 110 that does not have the first conductivity region 122. A photodiode is formed by a pn junction between a first conductivity region 122 and a second conductivity region 124. The photoelectric conversion unit 120 can generate and store electric charge in proportion to the amount of light supplied to each pixel region PX.

[0033] The separation pattern 126, which penetrates at least a portion of the substrate 110, is positioned to define the region in which the active region 118 and / or the photoelectric conversion unit 120 are located. At least a portion of the separation pattern 126 (for example, at least a portion of the second separation pattern 128) is positioned to correspond to the boundary of each pixel region PX. In this embodiment, in a cross-sectional view, the separation pattern 126 penetrates at least a portion of the substrate 110 in the thickness direction (Z-axis direction in the drawing). The separation pattern 126 includes a first separation pattern 127 positioned on the first surface 110a side of the substrate 110 and defining an active region 118 in each pixel region PX, and a second separation pattern 128 located further from the first surface 110a of the substrate 110 than the first separation pattern 127 and defining a region where the photoelectric conversion unit 120 is located.

[0034] In one embodiment, the separation pattern 126 may be a portion comprising a first separation pattern 127 having a relatively small depth and a second separation pattern 128 having a relatively deep depth. For example, the first separation pattern 127 corresponds to a shallow trench isolation (STI) pattern, and the second separation pattern 128 could be a deep trench isolation (DTI) pattern. In a plan view, an example was shown in which the second separation pattern 128 is formed by penetrating a part (e.g., an internal portion) of the first separation pattern 127, but the embodiments are not limited to this. In one embodiment, the second isolation pattern 128 includes a front deep trench isolation pattern (FDTI) that includes a portion adjacent to the first surface 110a of the substrate 110 and / or a back deep trench isolation pattern (BDTI) that includes a portion adjacent to the second surface 110b of the substrate 110. In the drawings, the second separation pattern 128 is illustrated as including a front deep trench separation pattern that penetrates the entire substrate 110, but the embodiments are not limited to this.

[0035] The first separation portion of the separation pattern 126 adjacent to the first surface 110a of the substrate 110 defines an active region 118 in a cross-sectional view, in the portion adjacent to the first surface 110a of the substrate 110. For example, the first separation portion of the separation pattern 126, which is positioned adjacent to the first surface 110a of the substrate 110, is positioned in a portion other than the active region 118. The active region 118 will be explained in more detail later with reference to Figures 5 and 6. In the drawings, the first separation portion of the separation pattern 126 adjacent to the first surface 110a of the substrate 110 is illustrated as including a first separation pattern 127 and a second separation pattern 128. For clearer understanding, the boundary between the first separation pattern 127 and the second separation pattern 128 is shown in the drawing. However, the embodiments are not limited to these. The first separation portion of the separation pattern 126 adjacent to the first surface 110a of the substrate 110 may consist of a single part, or the boundary between the first separation pattern 127 and the second separation pattern 128 may be difficult to confirm and thus judged to be a single part. The second separation portion of the separation pattern 126, which is located further from the first surface 110a of the substrate 110 than the first separation portion of the separation pattern 126, defines the region in which the photoelectric conversion unit 120 is located.

[0036] For example, the second separation portion of separation pattern 126 or the second separation pattern 128 includes a first extension portion 128a that extends in a first direction (the X-axis direction in the drawing) and a second extension portion 128b that extends in a second direction (the Y-axis direction in the drawing). The first extension portion 128a and the second extension portion 128b are positioned to correspond to the boundaries of each pixel region PX. For example, in a plan view, the second separation portion of separation pattern 126 or the second separation pattern 128 has a grid shape corresponding to the boundaries of multiple pixel regions PX. As a result, in a plan view, a pair of first extension portions 128a extending in the first direction are arranged on both sides of each pixel region PX in the second direction, and a pair of second extension portions 128b extending in the second direction are arranged on both sides of each pixel region PX in the first direction. In a plan view, the photoelectric conversion unit 120 located in each pixel region PX is surrounded by a pair of first extension portions 128a and a pair of second extension portions 128b.

[0037] In the embodiment, the separation pattern 126 (e.g., the second separation pattern 128) further includes a first internal portion 128c and a second internal portion 128d that extend into the interior of the pixel region PX. For example, the first internal portion 128c and the second internal portion 128d are extended from a pair of first extension portions 128a, respectively, and are extended between the first portion (reference numeral P1 in Figure 5) and the second portion (reference numeral P2 in Figure 5), or between the first conversion portion 122a and the second conversion portion 122b. The first internal portion 128c and the second internal portion 128d face each other within the pixel region PX, with a separation portion SP in between. For example, the separation portion SP is placed in the central region of each pixel region PX, and the first internal portion 128c and the second internal portion 128d are placed separated from each other in the central region. In one embodiment, the first internal portion 128c and the second internal portion 128d extend into the pixel region PX, forming the boundary between the first portion (reference numeral P1 in Figure 5) and the second portion (reference numeral P2 in Figure 5) in the pixel region PX. This will be explained in more detail later with reference to Figures 5 and 6.

[0038] Separation pattern 126 includes an insulating material layer. The separation pattern 126 may include at least one of silicon oxide, silicon nitride, and silicon oxidnitride as an insulating material layer, and may include a single layer or multiple layers. However, the embodiments are not limited thereto, and the material of the insulating layer of the separation pattern 126 can be varied in many ways. For example, if the first separation pattern 127 and the second separation pattern 128 contain the same substance, the first separation portion adjacent to the first surface 110a of the substrate 110 may entirely contain the same substance. As another example, if the first separation pattern 127 and the second separation pattern 128 contain different materials, the boundary between the first separation pattern 127 and the second separation pattern 128 can be observed in the first separation portion adjacent to the first surface 110a of the substrate 110. Another example is when a layer included only in the first separation pattern 127 is observed in the first separation portion adjacent to the first surface 110a of the substrate 110. However, the embodiments are not limited thereto.

[0039] In one embodiment, the separation pattern 126 further includes a conductive layer 126c. For example, the conductive layer 126c of the separation pattern 126 contains a semiconductor material (e.g., silicon). By applying a negative voltage to the conductive layer 126c of the separation pattern 126, the dark current can be improved through hole accumulation. However, the embodiments are not limited to these. A negative voltage may not be applied to the conductive layer 126c of the separation pattern 126, or the separation pattern 126 may not include the conductive layer 126c. A sidewall doping region is placed on the substrate 110 in the portion adjacent to the separation pattern 126 (for example, the second separation pattern 128). The sidewall doping regions are formed in portions adjacent to at least the sidewalls of the separation pattern 126 (e.g., the second separation pattern 128). The sidewall doping region, along with the conductive layer 126c of the separation pattern 126, plays a role in improving dark current. The sidewall doping region may have the same second conductivity type (p-type or n-type) as the substrate 110, for example, it may have the p-type. For example, the sidewall doping region may contain p-type dopants such as boron, aluminum, gallium, and indium.

[0040] Figure 3 illustrates a case where the surface of the separation pattern 126, which is located on the first surface 110a side of the substrate 110, is arranged on the same plane as the first surface 110a of the substrate 110. However, the embodiments are not limited thereto, and the first surface 110a of the substrate 110 and the surface of the separation pattern 126 may be arranged on different planes. The pixel circuit 130 adjacent to the first surface 110a of the substrate 110 includes a plurality of transistors 140. The pixel circuit 130 and the transistor 140 included therein will be described in more detail later. A wiring section 170, which is electrically connected to the pixel circuit 130, is placed on the first surface 110a of the substrate 110. In other words, the wiring section 170 is located on the first surface 110a side of the substrate 110 opposite to the second surface 110b that receives light, and is situated on the path of light incident on the image sensor 10. This minimizes optical interference caused by the wiring section 170.

[0041] The wiring section 170 may include one or more wiring layers 176 that are electrically connected to the pixel circuit 130 by contact vias 174 that penetrate the interlayer insulating layer 172. The wiring layer 176 and contact via 174 are connected to form the desired circuit. The contact vias 174 can be formed together with the wiring layer 176 in the same process, or they can be formed in a separate process from the wiring layer 176. The interlayer insulating layer 172 contains an insulating material. For example, the interlayer insulating layer 172 may include silicon oxide, silicon nitride, silicon oxynitride, and / or a low dielectric constant material. Here, a low dielectric constant material is a material that has a dielectric constant lower than that of silicon oxide.

[0042] The wiring layer 176 or contact via 174 may contain at least one of the following: metal, metal alloy, metal nitride, metal silicide, and doped semiconductor material. Here, the metal or metal alloy may include at least one of tungsten, molybdenum, titanium, tantalum, aluminum, copper, nickel, ruthenium, and cobalt, and the metal nitride may include at least one of tungsten nitride, molybdenum nitride, titanium nitride, and tantalum nitride. The wiring layer 176 or contact via 174 may further contain a metal oxide or metal oxynitride obtained by oxidizing the aforementioned substance. The wiring layer 176 or contact via 174 may consist of a single layer or multiple layers. However, the embodiments are not limited thereto, and the interlayer insulating layer 172 may contain a variety of insulating materials, and the wiring layer 176 or contact via 174 may contain a variety of conductive materials.

[0043] A horizontal insulating layer 180, a color filter 182, a filter separation section 184, a protective layer 186, and a microlens 188 are arranged on the second surface 110b of the substrate 110. More specifically, a horizontal insulating layer 180 is placed on the second surface 110b of the substrate 110. The horizontal insulating layer 180 is positioned to cover the second surface 110b and / or the separation pattern 126 of the substrate 110. The horizontal insulating layer 180 acts as a kind of planarizing layer that flattens the surface, ensuring that the color filter 182, microlens 188, etc., formed on the horizontal insulating layer 180 are stably formed. The horizontal insulating layer 180 may contain a variety of insulating materials. For example, the horizontal insulating layer 180 may include oxides, nitrides, oxynitrides, and fluorides containing at least one of hafnium, zirconium, aluminum, tantalum, titanium, yttrium, cerium, lanthanum, neodymium, praseodymium, ytterbium, and silicon. For example, the horizontal insulating layer 180 can also serve as an anti-reflective layer, but the embodiment is not limited to this.

[0044] In one embodiment, the horizontal insulating layer 180 comprises a plurality of layers containing different materials and having different thicknesses. For example, in the horizontal insulating layer 180, the first horizontal insulating layer located adjacent to the second surface 110b of the substrate 110 is a fixed charge layer having a negative fixed charge. This would allow for improvement of dark current through hole accumulation around the fixed charge layer. In one embodiment, the first horizontal insulating layer may contain a metal oxide or metal fluoride comprising at least one of hafnium, zirconium, aluminum, tantalum, titanium, and yttrium. As an example, the horizontal insulating layer 180 or anti-reflective layer includes a first horizontal insulating layer containing hafnium oxide, a second horizontal insulating layer containing silicon oxide or silicon nitride, and a third horizontal insulating layer containing hafnium oxide.

[0045] However, the embodiments are not limited to this, and the number of layers, thickness, etc., included in the horizontal insulating layer 180 can be varied in various ways. As another example, a structure capable of reflecting light can be formed on the second surface 110b of the substrate 110. For example, a nanoporous structure with a nanometer-level size is formed on the second surface 110b of the substrate 110 using a laser or etching to reflect light. Here, nanometer-level size refers to a size less than 1 μm (e.g., average width, average diameter, or average pitch). According to this, the structure and manufacturing process can be simplified by omitting the anti-reflective layer in the horizontal insulating layer 180. However, the embodiments are not limited thereto, and the horizontal insulating layer 180 may also include an anti-reflective layer when a structure capable of reflecting light is formed on the second surface 110b of the substrate 110.

[0046] The filter separation section 184 is positioned on the horizontal insulating layer 180. In one embodiment, the filter separation portion 184 is formed to surround at least a part of the color filter 182. For example, the filter separation section 184 has the same or similar grid shape as the second separation pattern 128 of the separation pattern 126, but the embodiment is not limited thereto. The filter separation section 184 can also be referred to as a fence pattern, grid pattern, or the like. The filter separation unit 184 prevents light that is obliquely incident into the color filter 182 of one of the multiple pixel regions PX from entering the color filter 182 of the adjacent pixel region PX. This prevents crosstalk between multiple pixel regions (PX).

[0047] In one embodiment, the filter separation section 184 includes a material having a refractive index smaller than that of the color filter 182 or silicon oxide, or a material having a refractive index of about 1.0 to about 1.4. When the filter separation section 184 contains a material with a small refractive index, the light incident on the filter separation section 184 undergoes total internal reflection and is directed inward towards the pixel region PX. For example, the filter separation section 184 may contain polymethyl methacrylate (PMMA), silicon acrylate, cellulose acetate butyrate (CAB), silica, or fluoro-silicon acrylate (FSA). For example, the filter separation section 184 contains a polymer material in which silica particles are dispersed. However, the embodiments are not limited thereto, and the filter separation unit 184 may also contain substances other than those described above.

[0048] A color filter 182 is placed on top of the horizontal insulating layer 180. Multiple color filters 182 are separated from each other by a filter separation unit 184. The multiple color filters 182 include, for example, a green filter, a blue filter, and a red filter. Depending on the embodiment, the color filter 182 may include a cyan filter, a magenta filter, a yellow filter, an infrared filter for passing infrared light, and the like. Alternatively, a pixel region PX into which all visible light is incident may be provided.

[0049] A protective layer 186 is placed on the color filter 182 and / or the filter separation section 184. Figure 3 illustrates an example in which the protective layer 186 is placed on the filter separation section 184 and between the filter separation section 184 and the color filter 182. The protective layer 186 may contain a variety of materials, such as organic materials, silicon oxides, silicon oxynitrides, and aluminum oxides. However, the embodiments are not limited to the material of the protective layer 186. Furthermore, the protective layer 186 may not be provided, or the protective layer 186 may be placed on the color filter 182 and the filter separation section 184.

[0050] The microlens 188, positioned on the color filter 182 and / or protective layer 186, includes a portion having a convex shape so as to be able to focus light incident on the pixel area PX. The microlens 188 may contain a variety of resin materials, such as styrene resins, acrylic resins, styrene-acrylic copolymer resins, or siloxane resins. However, the embodiments are not limited to this, and the shape, material, etc., of the microlens 188 can be varied in many ways. For example, a metalens may be provided instead of the microlens 188. Metalenses include nanostructures having nanorod and nanopillar forms with a size at the nanometer level. In a metalens, a meta-surface formed by the periodic arrangement of metaatoms smaller than the wavelength of light changes the direction of incident light so that it is directed towards a specific point. This allows it to function as a lens. The metalens or nanostructures may contain materials such as Si, SiN, GaN, and TiO2.

[0051] Figure 3 illustrates an example where the microlenses 188 are arranged to correspond to each pixel region PX. However, the embodiments are not limited to these. As another example, a single microlens 188 may be arranged to correspond to multiple pixel regions PX. Another example is that one microlens 188 may be positioned to correspond to a portion of the pixel area PX. Depending on the embodiment, a protective layer or the like may be further placed on the outer surface of the microlens 188. Figure 3 illustrates an example where the filter separation units 184 are arranged to correspond to each pixel region PX. However, the embodiments are not limited to these, and various modifications are possible.

[0052] In one embodiment, the relative positions of the pixel region PX and the color filter 182 and / or the relative positions of the pixel region PX and the microlens 188 differ in the central region of the image sensor 10 and the edge region of the image sensor 10, respectively, when viewed from a planar perspective. In other words, the area of ​​the color filter 182 superimposed on the pixel region PX and / or the area of ​​the microlens 188 superimposed on the pixel region PX are smaller in the edge region of the image sensor 10 than in the central region of the image sensor 10 when viewed from a planar perspective. For example, the area of ​​the color filter 182 superimposed on the pixel region PX and / or the area of ​​the microlens 188 superimposed on the pixel region PX become smaller in a planar view as you move from the central region of the image sensor 10 towards the edge region of the image sensor 10. As described above, the relative positions of the pixel region PX and the color filter 182 and / or microlens 188 are adjusted so that as much light as possible reaches the photoelectric conversion unit 120 of the pixel region PX. For example, the positions of the microlens 188, the color filter 182, and the photoelectric conversion unit 120 of the pixel area PX are arranged to overlap each other along the direction of the light path. Since light is incident at an oblique angle in the edge region of the image sensor 10, the relative positions of the pixel region PX and the color filter 182 and / or microlens 188 are adjusted so that as much of the light incident at an oblique angle as possible can be transmitted to the photoelectric conversion unit 120 of the pixel region PX.

[0053] An additional wiring section 200 is further placed on top of the photoelectric conversion substrate 100 (for example, the wiring section 170). The additional wiring section 200 may include the circuit board 210, a logic circuit section including transistors 240 and wiring 270, a power supply section, and the like. Thus, the image sensor 10 can have a multilayer laminated structure including a photoelectric conversion substrate 100 and an additional wiring portion 200. By including the additional wiring section 200 in this way, the arrangement density of wiring, circuit elements, etc., included in the pixel circuit 130, wiring section 170, and additional wiring section 200 can be improved. This makes it possible to improve the integration density and performance of the image sensor 10. Figure 3 illustrates an example in which the image sensor 10 has a two-layer stacked structure including a photoelectric conversion substrate 100 and an additional wiring portion 200. However, the embodiments are not limited to these. As another example, the wiring section 170 placed on the substrate 110 may include components that are part of the additional wiring section 200, and the image sensor 10 may be configured as a single part. Another example is that the image sensor 10 may have a stacked structure of three or more layers. An embodiment of the image sensor 10 having a three-layer stacked structure will be described in detail later with reference to Figure 15.

[0054] In the embodiment, the image sensor 10 receives light from an external source, which is collected by the microlens 188 and then passed through the color filter 182 before being directed to the photoelectric conversion unit 120. Light incident on the photoelectric conversion unit 120 is converted into an electrical signal depending on the amount of light. The active region 118, photoelectric conversion unit 120, and pixel circuit 130 provided in each pixel region PX of the image sensor 10 according to this embodiment will be described in more detail with reference to Figures 5 and 6, along with Figures 3 and 4.

[0055] Figure 5 is a plan view showing one of the multiple pixel regions PX of the image sensor 10 shown in Figure 4, and Figure 6 is a cross-sectional view taken along the line C-C' in Figure 5. For a clearer understanding, Figure 5 shows the first pixel region PX1 shown in Figure 4, and the following explanation will be based on the first pixel region PX1. Unless otherwise specified, the description for the first pixel region PX1 applies to the second pixel region PX2, the third pixel region PX3, and the fourth pixel region PX4. For clearer understanding, Figure 5 shows the location of the gate electrode 140g for the second transistor 144 or the third transistor 146. For clearer understanding, Figure 6 shows the first transistor 142 at the location of the transmission gate electrode 142g.

[0056] Referring to Figures 3 to 6, each pixel region PX includes a first portion P1 located on the first side S1 (e.g., the left side) in the first direction (the X-axis direction in the drawing) and a second portion P2 located on the second side S2 (e.g., the right side) opposite to the first side S1. In Figure 5, an example is shown in which, within each pixel region PX, the first portion P1 and the second portion P2 are adjacent to each other in the first direction (the X-axis direction in the drawing) and have a shape (for example, a vertically extended shape) that extends in the second direction (the Y-axis direction in the drawing). For example, in a plan view, the first part P1 is defined by a pair of first extensions 128a, one second extension 128b, a first interior part 128c, and a second interior part 128d, and the second part P2 is defined by a pair of first extensions 128a, another second extension 128b, a first interior part 128c, and a second interior part 128d.

[0057] However, the embodiments are not limited to this, and the number and arrangement of the first part P1 and the second part P2 provided in each pixel region PX, as well as the number and arrangement of the first internal part 128c and the second internal part 128d, can be varied in various ways. For example, each pixel region PX may have a shape (e.g., a lateral extension) in which the first portion P1 and the second portion P2 are adjacent to each other in the second direction (the Y-axis direction in the drawing) and each extends in the first direction (the X-axis direction in the drawing). Another example is that in at least one of the multiple pixel regions PX, the first portion P1 and the second portion P2 are adjacent to each other in a first direction and extend in a second direction (e.g., a vertically extended shape), and in at least one of the multiple pixel regions PX, the first portion P1 and the second portion P2 are adjacent to each other in a second direction and extend in a first direction (e.g., a horizontally extended shape). This will be explained in more detail later with reference to Figures 10 to 12.

[0058] In this embodiment, each photoelectric conversion unit 120 (for example, a first conductivity type region 122) located in each pixel region PX includes a plurality of conversion sections. In one embodiment, the conversion portion of the photoelectric conversion unit 120 (for example, the first conductivity type region 122) is arranged in the first portion P1 and the second portion P2, respectively. For example, the first conversion portion 122a of the first conductivity type region 122 is located in the first portion P1, and the second conversion portion 122b of the first conductivity type region 122 is located in the second portion P2. As a result, in each pixel region PX, the first transformation portion 122a is positioned on the first side S1 (for example, the left side) in the first direction (the X-axis direction of the drawing), and the second transformation portion 122b is positioned on the second side S2 (for example, the right side) in the first direction. Furthermore, it includes a connection portion 122d of the first conductive region 122 that connects the first conversion portion 122a and the second conversion portion 122b between the first internal portion 128c and the second internal portion 128d. Figure 5 illustrates a configuration in which the first transformation portion 122a and the second transformation portion 122b are adjacent to each other in the first direction (the X-axis direction in the drawing) and each has a shape (for example, a vertically extended shape) that extends in the second direction (the Y-axis direction in the drawing). However, the embodiments are not limited to these. Therefore, the number and arrangement of conversion parts included in the first conductivity type region 122 can be varied in many ways. In each pixel region PX, the autofocus (AF) characteristics of the image sensor 10 can be improved by using the difference between the signal output from the first conversion section 122a and the signal output from the second conversion section 122b to automatically adjust the focus of the image sensor 10. The active region 118 of the substrate 110 is defined by the first separation portion or first separation pattern 127 of the separation pattern 126, which is arranged on the first surface 110a side of the substrate 110. The active region 118 is the area where the transistor 140 and / or the doping region are located.

[0059] Transistor 140 includes a first transistor 142, a second transistor 144, and a third transistor 146. In each pixel region PX, the active region 118 includes a first active region 112 where the first transistor 142 is located. Furthermore, in each pixel region PX, the active region 118 further includes a second active region 114 where the second transistor 144 is located, and a third active region 116 where the third transistor 146 is located. The first transistor 142 includes a transmission transistor TX, and a floating diffusion region 120f is located in the first active region 112. The second transistor 144 or the third transistor 146 may include a reset transistor RX, a first gain control transistor DCX, a second gain control transistor MCX, a selection transistor SX, a drive transistor SF, a dummy transistor, and the like.

[0060] The first transistor 142 includes a transmission gate electrode 142g. The transmission gate electrode 142g is a vertical transfer gate (VTG) electrode having a cross-sectional shape in which the length in the thickness direction (Z-axis direction in the drawing) of the image sensor 10 (e.g., maximum length) is larger than the width in the plane of the transmission gate electrode 142g (e.g., minimum width in the X-axis or Y-axis direction in the drawing). The first transistor 142 further includes a transmission gate insulating layer 142i, which is disposed between the transmission gate electrode 142g and the substrate 110. In this embodiment, the first transistor 142 includes a first transmission transistor 142a electrically connected to the first conversion section 122a and a second transmission transistor 142b electrically connected to the second conversion section 122b. The second transistor 144 or the third transistor 146 may have a different structure, shape, or depth from the first transistor 142. Here, having different structures, shapes, or depths means that the electrodes, layers, or doping portions included in or associated with the transistor are different, their position, arrangement, etc., or the cross-sectional structure or shape of the electrodes, layers, or doping portions included in or associated with the transistor are different, or there are differences in the depth of the transistor or the depth of the gate electrode. In other words, differences in width, length, shape, etc., on a plane do not necessarily mean that two objects have different structures or shapes. For example, the second transistor 144 or the third transistor 146 may have a different cross-sectional structure from the first transistor 142.

[0061] In one embodiment, the second transistor 144 or the third transistor 146 has a planar structure. For example, the second transistor 144 or the third transistor 146 includes a gate insulating layer 140i and a gate electrode 140g arranged sequentially on the substrate 110, spacers 140p arranged on both sides of the gate insulating layer 140i and the gate electrode 140g, and a source region 140s and a drain region 140d arranged on the portion of the substrate 110 outside the gate electrode 140g and spacers 140p. The gate insulating layer 140i and the gate electrode 140g have a shape that extends planarly on the first surface 110a of the substrate 110. In this embodiment, the first active region 112 includes a first active portion 112a on which the first transmission transistor 142a is located, a second active portion 112b on which the second transmission transistor 142b is located, and a connecting active portion 112c that connects the first active portion 112a and the second active portion 112b.

[0062] In this embodiment, the connecting active portion 112c has a line shape that extends long in one direction. The first active portion 112a and the second active portion 112b are positioned on both sides in a direction inclined to the first direction (X-axis direction in the drawing) and the second direction (Y-axis direction in the drawing), for example, in the first diagonal direction D1. The connecting active portion 112c extends in a direction inclined to the first direction (X-axis direction in the drawing) and the second direction (Y-axis direction in the drawing), for example, in the first diagonal direction D1, connecting the first active portion 112a and the second active portion 112b. For example, the first active region 112 or connecting active portion 112c extends along the first diagonal direction D1 from one side of the separation portion SP (e.g., the first portion P1 or the first conversion portion 122a) to the other side (e.g., the second portion P2 or the second conversion portion 122b). Here, the first diagonal direction D1 means a direction inclined with at least a portion of the second separation pattern 128.

[0063] For example, the first diagonal direction D1 has an acute angle (an angle greater than 0 degrees and less than 90 degrees) with the extension direction of the first extension portion 128a, or an acute angle with the extension direction of the second extension portion 128b, or an acute angle with the first internal portion 128c or the second internal portion 128d. That is, the extension direction of the first active region 112 or the connecting active portion 112c is at an acute angle with the extension direction of the first extension portion 128a, or at an acute angle with the extension direction of the second extension portion 128b, or at an acute angle with the extension direction of the first internal portion 128c or the second internal portion 128d. For example, the extension direction of the first active region 112 or the connecting active portion 112c is at an angle of 30 to 60 degrees with the extension direction of the first extension portion 128a, or at an angle of 30 to 60 degrees with the extension direction of the second extension portion 128b, or at an angle of 30 to 60 degrees with the first internal portion 128c or the second internal portion 128d. However, the embodiments are not limited thereto, and depending on the size, ratio, arrangement, and manufacturing error of the pixel region PX, the extension direction of the first extension portion 128a or the second extension portion 128b or the first internal portion 128c or the second internal portion 128d and the extension direction of the connecting active portion 112c may have an angle of less than 30 degrees or more than 60 degrees.

[0064] In the embodiment, the connecting active portion 112c does not have to include a bent portion, a curved portion, etc., that extends in one direction and has a single extension direction, but the embodiment is not limited thereto. The embodiment includes a case in which a virtual straight line connecting one side of the first active region 112 (e.g., the connecting active portion 112c) to the other side of the first active region 112 (e.g., the connecting active portion 112c) has a first diagonal direction D1. In this case, the connecting active portion 112c may include a bent portion, a curved portion, etc. In other words, the embodiment can have various structures in which one side of the connecting active portion 112c is arranged adjacent to the third side S3 with the first portion P1, and the other side of the connecting active portion 112c is arranged adjacent to the fourth side S4 with the second portion P2. The first active portion 112a and the second active portion 112b may be symmetrical with respect to each other in the first diagonal direction D1 to which the connecting active portion 112c is extended. In this specification, symmetry in one direction means that the two objects are symmetrical with respect to an orthogonal direction perpendicular to that direction. In other words, being symmetrical with respect to the first diagonal direction D1 means being symmetrical with respect to the direction perpendicular to the first diagonal direction D1 (for example, the second diagonal direction D2).

[0065] In this embodiment, the first active region 112 has a point-symmetric shape in the pixel region PX. For example, in a plan view, the first active portion 112a and the second active portion 112b have a point-symmetric shape in the pixel region PX. Here, the statement that two regions, two parts, or two arrangements have a point-symmetric shape in the pixel region PX means that they have a point-symmetric shape with respect to the center of the pixel region PX. In other words, if two regions, two parts, or two arrangements have a point-symmetric shape in the pixel region PX, then in a plan view, the two regions, two parts, or two arrangements have a shape that is rotated 180 degrees with respect to the center of the pixel region PX.

[0066] In one embodiment, the first active portion 112a is extended in a direction that intersects (for example, perpendicular to) the connecting active portion 112c, and the second active portion 112b is extended in a direction that intersects (for example, perpendicular to) the connecting active portion 112c. For example, the first active portion 112a and the second active portion 112b are extended in a second diagonal direction D2 that intersects (e.g., orthogonal to) the first diagonal direction D1, and are extended parallel to each other. For example, the first active portion 112a includes a first and second edge extending in the second diagonal direction D2, and a third and fourth edge extending in the first diagonal direction D1. For example, the second active portion 112b includes a first and second edge extending in the second diagonal direction D2, and a third and fourth edge extending in the first diagonal direction D1. The first to fourth edges of the first active portion 112a and the first to fourth edges of the second active portion 112b have a point-symmetric shape in the pixel region PX. Furthermore, the first active portion 112a and the second active portion 112b have substantially the same planar area. Here, substantially identical planar area includes cases where the difference is within the tolerance of the manufacturing process (e.g., within 10%).

[0067] In this embodiment, the width of the first active portion 112a is greater than the width of the connecting active portion 112c, and the width of the second active portion 112b is greater than the width of the connecting active portion 112c. Here, the width of the first active portion 112a or the width of the second active portion 112b refers to the width in a direction perpendicular to the extension direction of the connecting active portion 112c (e.g., the first diagonal direction D1) (e.g., the second diagonal direction D2), and for example, it refers to the maximum width. The width of the connecting active portion 112c refers to the width in a direction perpendicular to the extension direction of the connecting active portion 112c, and for example, it refers to the minimum width.

[0068] The first transmission transistor 142a located in the first active portion 112a has a dual vertical transfer gate (dual VTG) structure, and the second transmission transistor 142b located in the second active portion 112b also has a dual vertical transfer gate structure. That is, the first transmission transistor 142a includes two gate electrode portions 142h that extend into the substrate 110, and the second transmission transistor 142b also includes two gate electrode portions 142h that extend into the substrate 110. The two gate electrode portions 142h provided in the first transmission transistor 142a or the second transmission transistor 142b are respectively arranged on both sides in the extension direction (for example, the second diagonal direction D2) of the first active portion 112a or the second active portion 112b.

[0069] If the first transmission transistor 142a or the second transmission transistor 142b has a dual vertical transmission gate structure, the charge generated in the photoelectric conversion unit 120 can be effectively transmitted by the transmission transistor TX. Figure 5 illustrates a configuration in which two gate electrode portions 142h, each located on a single first active portion 112a, are separated from each other and connected at a point adjacent to the first surface 110a of the substrate 110. However, the embodiments are not limited to these. As another example, two gate electrode portions 142h connected to one first active portion 112a are arranged spaced apart from each other. As another example, the first transmission transistor 142a and / or the second transmission transistor 142b may have a single vertical transfer gate (single VTG) structure. Other diverse forms are possible.

[0070] The second active region 114 is located on one side of the first active region 112 in the second diagonal direction D2, which intersects with the first diagonal direction D1, and the third active region 116 is located on the other side of the first active region 112 in the second diagonal direction D2. For example, the second active region 114 and the third active region 116 are arranged symmetrically with respect to each other in the second diagonal direction D2. In other words, the second active region 114 and the third active region 116 are arranged to be symmetrical with respect to a direction perpendicular to the second diagonal direction D2 (for example, the first diagonal direction D1). The second active region 114 and the third active region 116 have a point-symmetric shape in the pixel region PX. The second active region 114 includes a first and second edge extending in a first direction (the X-axis direction in the drawing), a third and fourth edge extending in a second direction (the Y-axis direction in the drawing), and a fifth edge that extends in a direction inclined with respect to the first to fourth edges (for example, the first diagonal direction D1) in the portion facing the first active region 112. The third active region 116 includes a first and second edge extending in a first direction, a third and fourth edge extending in a second direction, and a fifth edge that extends in a direction inclined with the first to fourth edges (for example, the first diagonal direction D1) in the portion facing the first active region 112. The first to fifth edges of the second active region 114 and the first to fifth edges of the third active region 116 have a point-symmetric shape in the pixel region PX. Furthermore, the second active region 114 and the third active region 116 have substantially the same planar area.

[0071] In Figure 5, the gate electrode 140g of the second transistor 144 or the third transistor 146 is shown as being extended in a first direction (the X-axis direction in the drawing) that intersects (for example, is perpendicular to) the extension direction of the first internal portion 128c or the second internal portion 128d. According to this, the spacing between multiple transistors 140 can be increased, thereby improving the structure or density of the wiring section 170. However, the embodiments are not limited thereto, and the gate electrode 140g of the second transistor 144 or the third transistor 146 may be extended in the second direction (the Y-axis direction in the drawing). In this embodiment, each pixel region PX is provided with a first transistor 142, a second transistor 144, and a third transistor 146, and multiple pixel regions PX constituting a single unit pixel group share the second transistor 144 and the third transistor 146, which operate in different ways from each other.

[0072] A floating diffusion region 120f is positioned in the portion of the first active region 112 located between the first internal region 128c and the second internal region 128d (for example, in the central portion of the separation region SP or the pixel region PX). For example, in a plan view, the floating diffusion region 120f is located in the central part of the connection active portion 112c. In a plan view, the first active portion 112a and the second active portion 112b have a point-symmetric shape with respect to the floating diffusion region 120f. In other words, in a plan view, the first active portion 112a and the second active portion 112b have shapes that are rotated 180 degrees with respect to the floating diffusion region 120f. In a plan view, the first internal portion 128c and the first active region 112 are arranged point-symmetrically with respect to the second internal portion 128d and the first active region 112. In plan view, the arrangement of the first internal portion 128c and the first active region 112, and the arrangement of the second internal portion 128d and the first active region 112, have a point-symmetric shape in the pixel region PX. For example, in a plan view, the arrangement of the first internal portion 128c and the first active portion 112a and the arrangement of the second internal portion 128d and the second active portion 112b have a point-symmetric shape in the pixel region PX. For example, in a plan view, the arrangement of the first internal portion 128c and the adjacent connected active portion 112c, and the arrangement of the second internal portion 128d and the adjacent connected active portion 112c, have a point-symmetric shape in the pixel region PX.

[0073] In a plan view, the arrangement of the first internal portion 128c and the first active region 112, and the arrangement of the second internal portion 128d and the first active region 112, have a point-symmetric shape with respect to the floating diffusion region 120f. For example, in a plan view, the arrangement of the first internal portion 128c and the first active portion 112a and the arrangement of the second internal portion 128d and the second active portion 112b have a point-symmetric shape with respect to the floating diffusion region 120f. For example, in a plan view, the arrangement of the first internal portion 128c and the adjacent connecting active portion 112c, and the arrangement of the second internal portion 128d and the adjacent connecting active portion 112c, have a point-symmetric shape with respect to the floating diffusion region 120f.

[0074] In this embodiment, in each pixel region PX, in a plan view, the first transmission transistor 142a is positioned on the third side S3 in a second direction (Y-axis direction in the drawing) that intersects the first direction, superimposed on the first conversion portion 122a which is positioned on the first side S1 in the first direction (X-axis direction in the drawing). In each pixel region PX, in a plan view, the second transmission transistor 142b is positioned on the fourth side S4 in the second direction, opposite to the third side S3, at a position superimposed on the second conversion portion 122b, which is located on the second side S2 in the first direction. In each pixel region PX, in a plan view, the third transistor 146 is positioned on the fourth side S4 in the second direction, superimposed on the first conversion portion 122a. In each pixel region PX, in a plan view, the second transistor 144 is positioned on the third side S3 in the second direction, superimposed on the second conversion portion 122b. As a result, when viewed with reference to the central region of the pixel region PX, the first transmission transistor 142a and the second transmission transistor 142b are positioned on either side in the first diagonal direction D1, respectively.

[0075] When viewed with reference to the central region of the pixel area PX, the second transistor 144 and the third transistor 146 are positioned on either side in the second diagonal direction D2, respectively. Specifically, the second transistor 144 is positioned on one side of the first active region 112 in the second diagonal direction D2, and the third transistor 146 is positioned on the other side of the first active region 112 in the second diagonal direction D2. Then, in the first direction (X-axis direction in the drawing), the first transmission transistor 142a and the second transistor 144 are arranged on either side of the first internal portion 128c, and in the first direction, the second transmission transistor 142b and the third transistor 146 are arranged on either side of the second internal portion 128d, with the second internal portion 128d in between. In a plan view, the first transmission transistor 142a and the second transmission transistor 142b have a point-symmetric shape in the pixel region PX. In a plan view, the second transistor 144 and the third transistor 146 have a point-symmetric shape in the pixel region PX. In this specification, even when the gate electrode 140g is extended so that one of the second transistor 144 and the third transistor 146 is shared with another pixel region PX, and the other is positioned to correspond to one pixel region PX, if at least two of the multiple edges (e.g., three or more, four as an example) are symmetrical, or if the overlapping regions of the gate electrode 140g and the active region 118 are symmetrical with respect to each other, they can be considered to have a point-symmetric shape with respect to each other.

[0076] As described above, in the embodiment, the first active region 112 has a point-symmetric shape in the pixel region PX, and the second active region 114 and the third active region 116 have point-symmetric shapes. Furthermore, in the pixel region PX, the first transmission transistor 142a and the second transmission transistor 142b have a point-symmetric shape, and the second transistor 144 and the third transistor 146 also have a point-symmetric shape. That is, in the pixel region PX, the active region 118 or the pixel circuit 130 has a point-symmetrical shape. Furthermore, the active region 118 has an asymmetrical shape in the first direction (X-axis direction in the drawing) and / or the second direction (Y-axis direction in the drawing). Here, having an asymmetrical shape in the first direction means that the shapes are not symmetrical with respect to the direction perpendicular to the first direction (for example, the second direction), and having an asymmetrical shape in the second direction means that the shapes are not symmetrical with respect to the direction perpendicular to the second direction (for example, the first direction). For example, the first active region 112 has an asymmetric shape in the first direction and / or the second direction. The second active region 114 and the third active region 116 have an asymmetric shape in the first direction and / or the second direction. Furthermore, the pixel circuit 130 has an asymmetrical shape in the first direction (X-axis direction in the drawing) and / or the second direction (Y-axis direction in the drawing). For example, the first transmission transistor 142a and the second transmission transistor 142b have asymmetric shapes in the first and / or second directions. For example, the second transistor 144 and the third transistor 146 have asymmetric shapes in the first and / or second directions. In this embodiment, the multiple transistors 140 are electrically connected by a wiring layer 170 (for example, a first wiring layer adjacent to the multiple transistors 140) to form a desired circuit.

[0077] The arrangement of transistor 140 and active region 118 in multiple pixel regions PX will be described in detail with reference to Figures 2, 4, and 5. Referring to Figures 2, 4, and 5, two pixel regions PX within the first to fourth pixel regions (PX1, PX2, PX3, PX4) have a symmetrical arrangement or have an identical arrangement. More specifically, the active regions 118 (for example, the first active region 112, the second active region 114, and the third active region 116) contained within two pixel regions PX of the first to fourth pixel regions (PX1, PX2, PX3, PX4) are arranged symmetrically to each other or have the same arrangement. Furthermore, the pixel circuits 130 included in two pixel regions PX of the first to fourth pixel regions (PX1, PX2, PX3, PX4) have a symmetrical arrangement or an identical arrangement.

[0078] In the following explanation, for the sake of clarity, in each pixel region PX, the transmission transistor TX located near the center of the unit pixel group in the second direction (the Y-axis direction in the drawing) will be referred to as the first transmission transistor 142a, and the transmission transistor TX located far from the center of the unit pixel group in the second direction will be referred to as the second transmission transistor 142b. Furthermore, among the second transistor 144 and third transistor 146 located in each pixel region PX, the transistor closer to the center of the unit pixel group is referred to as the second transistor 144, and the transistor located further away from the center of the unit pixel group is referred to as the third transistor 146.

[0079] In the first pixel region PX1, the first active region 112 is formed in the first diagonal direction D1, and the second active region 114 and the third active region 116 are arranged symmetrically with respect to each other in the second diagonal direction D2. Furthermore, the first transmission transistor 142a and the second transmission transistor 142b are symmetrical with respect to each other in the first diagonal direction D1, and the second transistor 144 and the third transistor 146 are symmetrical with respect to each other in the second diagonal direction D2. The second pixel region PX2 is positioned symmetrically with the first pixel region PX1 in the first direction (the X-axis direction of the drawing). Specifically, in the second pixel region PX2, the first active region 112 is formed in the second diagonal direction D2, and the second active region 114 and the third active region 116 are arranged symmetrically with respect to each other in the first diagonal direction D1. Furthermore, the first transmission transistor 142a and the second transmission transistor 142b are symmetrical with respect to each other in the second diagonal direction D2, and the second transistor 144 and the third transistor 146 are symmetrical with respect to each other in the first diagonal direction D1.

[0080] The third pixel region PX3 is positioned symmetrically with the first pixel region PX1 in the second direction (the Y-axis direction in the drawing). Alternatively, the third pixel region PX3 may have the same arrangement as the second pixel region PX2. Specifically, in the third pixel region PX3, the first active region 112 is formed in the second diagonal direction D2, and the second active region 114 and the third active region 116 are arranged symmetrically with respect to each other in the first diagonal direction D1. Furthermore, the first transmission transistor 142a and the second transmission transistor 142b are symmetrical with respect to each other in the second diagonal direction D2, and the second transistor 144 and the third transistor 146 are symmetrical with respect to each other in the first diagonal direction D1. The fourth pixel region PX4 is positioned symmetrically with the second pixel region PX2 in the second direction (the Y-axis direction in the drawing). Alternatively, the fourth pixel region PX4 may have the same arrangement as the first pixel region PX1. Specifically, in the fourth pixel region PX4, the first active region 112 is formed in the first diagonal direction D1, and the second active region 114 and the third active region 116 are arranged symmetrically to each other in the second diagonal direction D2. Furthermore, the first transmission transistor 142a and the second transmission transistor 142b are symmetrical with respect to each other in the first diagonal direction D1, and the second transistor 144 and the third transistor 146 are symmetrical with respect to each other in the second diagonal direction D2.

[0081] The second transistor 144 of each pixel region PX (i.e., the four second transistors 144 provided in the first to fourth pixel regions (PX1, PX2, PX3, PX4) respectively) constitute the drive transistor SF. The gate electrode 140g is shared between the second transistor 144 in the first pixel region PX1 and the second transistor 144 in the second pixel region PX2 to form the first drive transistor SF1. The second transistor 144 in the third pixel region PX3 and the second transistor 144 in the fourth pixel region PX4 share a gate electrode 140g to form the second drive transistor SF2. The first drive transistor SF1 and the second drive transistor SF2 are connected in parallel. In this way, if the gate electrode 140g is shared between the second transistor 144 of the first pixel region PX1 and the second transistor 144 of the second pixel region PX2, or if the gate electrode 140g is shared between the second transistor 144 of the third pixel region PX3 and the second transistor 144 of the fourth pixel region PX4, or if the first drive transistor SF1 provided in at least one of the multiple pixel regions PX and the second drive transistor SF2 provided in at least one of the multiple pixel regions PX are connected in parallel, the transistor width can be increased and performance can be improved. Furthermore, the second transistor 144 of each pixel region PX constituting the drive transistor SF is located adjacent to the center of the unit pixel group, thereby simplifying the structure of the wiring section 170.

[0082] The third transistor 146 in the first pixel region PX1 constitutes the selection transistor SX, the third transistor 146 in the second pixel region PX2 constitutes the reset transistor RX, and the third transistor 146 in the third pixel region PX3 and the third transistor 146 in the fourth pixel region PX4 constitute the conversion gain transistors (DCX and MCX), respectively. However, the arrangement of the second transistor 144 or the third transistor 146 in the first to fourth pixel regions (PX1, PX2, PX3, PX4) is illustrative, and the embodiments are not limited thereto.

[0083] According to the embodiment, the first transmission transistor 142a and the second transmission transistor 142b are arranged on both sides in the first diagonal direction D1, the first active region 112 is extended in the first diagonal direction D1, and the first active region 112 has a symmetrical shape (for example, a point-symmetric shape) with respect to the first internal portion 128c and the second internal portion 128d of the separation pattern 126. This prevents problems that may occur when the first active region has an asymmetric shape with respect to the first internal portion 128c and the second internal portion 128d of the separation pattern 126. This makes it possible to improve the performance and productivity of the image sensor 10.

[0084] For example, in a comparative example where the arrangement of the first active region and the first internal portion is asymmetrical with respect to the arrangement of the first active region and the second internal portion in the second direction, the end shape of the first internal portion adjacent to the first active region and the end shape of the second internal portion adjacent to the first active region may unintentionally differ. For example, if the first active region has a V-shape, the first internal portion located between the V-shapes has a pointed shape, and the end of the second internal portion located outside the V-shape has a rounded shape. As a result, the distance between the first active region and the first internal portion in the second direction and the distance between the first active region and the second internal portion in the second direction may unintentionally become different from each other. For example, the distance between the first active region and the first internal region in the second direction may be smaller than the distance between the first active region and the second internal region in the second direction. This can lead to current leakage or defects due to process variations. This can lead to a decrease in image sensor performance or reduced productivity.

[0085] Furthermore, the second transistor 144 and the third transistor 146 are arranged on both sides in the second diagonal direction D2, respectively, which increases the degree of freedom and area of ​​arrangement for the second transistor 144 and the third transistor 146, and ensures spacing between multiple transistors 140. At this time, a gap can be secured between the second transistor 144 and the third transistor 146, and space can be secured for additional wiring (for example, connection wiring 150) without changing the design of transistor 140. The connection wiring 150 will be explained in detail later with reference to Figures 8 and 9.

[0086] The first transmission transistor 142a and the second transmission transistor 142b are separated from the floating diffusion region 120f in the first diagonal direction D1, while sharing one floating diffusion region 120f. The first transmission transistor 142a and the second transmission transistor 142b share a single floating diffusion region 120f, which reduces the wiring length of the wiring section 170 and thereby improves the conversion gain. By ensuring sufficient distance between the first transmission transistor 142a and the floating diffusion region 120f, and between the second transmission transistor 142b and the floating diffusion region 120f, the electrical characteristics can be improved. For example, it can reduce gate-induced drain leakage (GIDL).

[0087] Below, we will describe in more detail an image sensor according to an embodiment different from the one described above, with reference to Figures 7 to 15. Detailed explanations of parts that are identical or very similar to those already explained will be omitted, and only the different parts will be explained in detail. Figure 7 is a schematic plan view showing multiple pixel regions PX of an image sensor according to another embodiment of the present invention. Figure 7 shows the portion corresponding to Figure 4, and for the second transistor 144 and the third transistor 146, the gate electrodes are primarily shown.

[0088] Referring to Figure 7, two pixel regions PX within the first to fourth pixel regions (PX1, PX2, PX3, PX4) have a symmetrical arrangement or have an identical arrangement. More specifically, the active regions 118 (for example, the first active region 112, the second active region 114, and the third active region 116) contained within two pixel regions PX of the first to fourth pixel regions (PX1, PX2, PX3, PX4) are arranged symmetrically to each other or have the same arrangement. Furthermore, the pixel circuits 130 contained in two pixel regions PX of the first to fourth pixel regions (PX1, PX2, PX3, PX4) have a symmetrical arrangement with respect to each other, or have the same arrangement with respect to each other.

[0089] For the sake of clarity in the following explanation, in each pixel region PX, the transmission transistor TX located near the center of the unit pixel group in the second direction (the Y-axis direction in the drawing) will be referred to as the first transmission transistor 142a, and the transmission transistor TX located far from the center of the unit pixel group in the second direction will be referred to as the second transmission transistor 142b. Furthermore, among the second transistor 144 and third transistor 146 located in each pixel region PX, the transistor adjacent to the first side (left side in the diagram) is referred to as the second transistor 144, and the transistor adjacent to the second side (right side in the diagram) is referred to as the third transistor 146. In the first pixel region PX1 or the second pixel region PX2, the first active region 112 is formed in the second diagonal direction D2, and the second active region 114 and the third active region 116 are arranged symmetrically with respect to each other in the first diagonal direction D1. Furthermore, the first transmission transistor 142a and the second transmission transistor 142b are symmetrical with respect to each other in the second diagonal direction D2, and the second transistor 144 and the third transistor 146 are symmetrical with respect to each other in the first diagonal direction D1.

[0090] The third pixel area PX3 or the fourth pixel area PX4 is positioned symmetrically with the first pixel area PX1 or the second pixel area PX2 in the second direction (the Y-axis direction in the drawing). In the third pixel region PX3 or the fourth pixel region PX4, the first active region 112 is formed in the first diagonal direction D1, and the second active region 114 and the third active region 116 are arranged symmetrically with respect to each other in the second diagonal direction D2. Furthermore, the first transmission transistor 142a and the second transmission transistor 142b are symmetrical with respect to each other in the first diagonal direction D1, and the second transistor 144 and the third transistor 146 are symmetrical with respect to each other in the second diagonal direction D2. The second transistor 144 in the first pixel region PX1 and the third pixel region PX3 constitute a dummy transistor DX. For example, a dummy transistor DX can improve structural stability without performing the function of a transistor. As another example, dummy transistor DX can serve a variety of roles.

[0091] The second transistor 144 in the second pixel region PX2 and the fourth pixel region PX4 constitute the drive transistor SF. For example, the second transistor 144 in the second pixel region PX2 constitutes the first drive transistor SF1, and the second transistor 144 in the fourth pixel region PX4 constitutes the second drive transistor SF2. The first drive transistor SF1 and the second drive transistor SF2 are connected in parallel. When the first drive transistor SF1 and the second drive transistor SF2 are connected in parallel in this way, the transistor width can be increased and performance can be improved. Furthermore, the second transistors 144 of the second pixel region PX2 and the fourth pixel region PX4, which constitute the drive transistor SF, are arranged adjacent to each other in the center of the unit pixel group, thereby simplifying the structure of the wiring section. The third transistor 146 in the first pixel region PX1 and the third transistor 146 in the second pixel region PX2 each constitute a conversion gain transistor (DCX, MCX). The third transistor 146 in the third pixel region PX3 constitutes the selection transistor SX, and the third transistor 146 in the fourth pixel region PX4 constitutes the reset transistor RX. However, the arrangement of the second transistor 144 or the third transistor 146 in the first to fourth pixel regions (PX1, PX2, PX3, PX4) is illustrative, and the embodiment is not limited thereto.

[0092] According to this embodiment, it is advantageous in the manufacturing process for the first pixel region PX1 and the third pixel region PX3 to have the same arrangement as the second pixel region PX2 and the fourth pixel region PX4, respectively. For example, using masks with the same pattern can facilitate manufacturing processes (e.g., doping processes). As one variation, the first to fourth pixel regions (PX1, PX2, PX3, PX4) can each have the same arrangement as the others. More specifically, the active regions 118 contained within the first to fourth pixel regions (PX1, PX2, PX3, PX4), respectively (for example, the first active region 112, the second active region 114, and the third active region 116), can also have the same arrangement as each other. Furthermore, the pixel circuits 130 included in the first to fourth pixel regions (PX1, PX2, PX3, PX4) can also have the same arrangement as each other.

[0093] Figure 8 is a schematic plan view showing multiple pixel regions PX of an image sensor according to another embodiment of the present invention. Figure 8 shows the portion corresponding to Figure 4, and for the second transistor 144 and the third transistor 146, the gate electrodes are mainly shown. Referring to Figure 8, in this embodiment, the pixel circuit 130 includes a connecting wire 150 that extends planar from the gate electrode of the second transistor 144 (e.g., the driving transistor SF) and is electrically connected to the floating diffusion region 120f.

[0094] For example, the connecting wire 150 is a portion that extends in a plane from the gate electrode of the second transistor 144 (e.g., the driving transistor SF), and contains the same material (e.g., a polycrystalline semiconductor material) as the gate electrode of the second transistor 144 (e.g., the driving transistor SF). The connecting wiring 150 may be called a polylocal interconnector. As an example, the connecting wire 150 and the gate electrode of the second transistor 144 (for example, the driving transistor SF) are formed together in the same process to constitute a single body. However, the embodiments are not limited thereto.

[0095] In this embodiment, the second transistor 144 and the third transistor 146 are positioned on opposite sides in the second diagonal direction D2, respectively, to ensure spacing between the multiple transistors 140. Therefore, sufficient space can be secured for the connection wiring 150 to be formed. On the other hand, in comparative examples where the second and third transistors are adjacent in the first or second direction, the gap between the second and third transistors is small, making it difficult to apply connecting wiring. For example, in the comparative example, redesigns of the second and third transistors were required to secure space for the connecting wiring. In one embodiment, the connecting wire 150 is electrically connected to the floating diffusion region 120f by contacting one surface of the floating diffusion region 120f. However, the embodiments are not limited thereto, and the structure in which the connecting wiring 150 is electrically connected to the floating diffusion region 120f can be modified in various ways.

[0096] In this embodiment, the connection wiring 150 reduces the number of contact vias and wiring portions that are electrically connected to the drive transistor SF. This reduces parasitic capacitance, improves conversion gain, and reduces noise. However, the embodiments are not limited thereto and may further include, depending on the circumstances, contact vias and / or wiring portions electrically connected to the drive transistor SF. In this embodiment, the connection wiring 150 includes a first common connection wiring 150a and a second common connection wiring 150b. The first common connection wiring 150a electrically connects the floating diffusion region 120f located in the first pixel region PX1, the floating diffusion region 120f located in the third pixel region PX3, one side of the gate electrode of the first drive transistor SF1, and one side of the gate electrode of the second drive transistor SF2. The second common connection wiring 150b electrically connects the floating diffusion region 120f located in the second pixel region PX2, the floating diffusion region 120f located in the fourth pixel region PX4, the other side of the gate electrode of the first drive transistor SF1, and the other side of the gate electrode of the second drive transistor SF2. According to this, the structure of the first common connection wiring 150a and the second common connection wiring 150b can be simplified. However, the embodiments are not limited to these, and the shape, arrangement, etc., of the first common connection wiring 150a and the second common connection wiring 150b can be varied in many ways.

[0097] In the previous explanation, an example was given in which the connecting wire 150 electrically connects the second transistor 144 and the floating diffusion region 120f. However, the embodiments are not limited thereto, and the connecting wiring 150 may also include parts that electrically connect multiple doping regions, parts that electrically connect the doping regions and the transistor 140, parts that electrically connect multiple transistors 140, and so on. Furthermore, the connecting wire 150 may be positioned at a distance from the gate electrode of the second transistor 144. Two pixel regions PX within the first to fourth pixel regions (PX1, PX2, PX3, PX4) are arranged symmetrically to each other, or have identical arrangements. Figure 8 illustrates an example in which the arrangement of the active regions 118 and pixel circuits 130 contained in the first to fourth pixel regions (PX1, PX2, PX3, PX4) is as shown in Figure 4, but the embodiment is not limited to this. As an example, the arrangement of the active region 118 and the pixel circuit 130 can also be as shown in Figure 7. Other diverse forms are possible.

[0098] Figure 9 is a schematic plan view showing multiple pixel regions PX of an image sensor according to another embodiment of the present invention. Figure 9 shows the portion corresponding to Figure 4, and for the second transistor 144 and the third transistor 146, the gate electrodes are primarily shown. Referring to Figure 9, in this embodiment, the pixel circuit 130 includes a connecting wire 150 that extends planar from the gate electrode of the second transistor 144 (e.g., the driving transistor SF) and is electrically connected to the floating diffusion region 120f. Unless otherwise specified, the explanation regarding connection wiring 150, as shown in Figure 8, applies.

[0099] In this embodiment, the connection wiring 150 includes the first to fifth connection wirings (151, 152, 153, 154, 155). The first connection wiring 151 electrically connects the floating diffusion region 120f located in the first pixel region PX1 to one side of the gate electrode of the first drive transistor SF1. The second connection wiring 152 electrically connects the floating diffusion region 120f located in the second pixel region PX2 to the other side of the gate electrode of the first drive transistor SF1. The third connection wiring 153 electrically connects the floating diffusion region 120f located in the third pixel region PX3 to one side of the gate electrode of the second drive transistor SF2. The fourth connection wire 154 electrically connects the floating diffusion region 120f located in the fourth pixel region PX4 to the other side of the gate electrode of the second drive transistor SF2. The fifth connection wire 155 electrically connects the first drive transistor SF1 and the second drive transistor SF2. Although an example has been given in which the fifth connecting wire 155 is located in the center in the first direction (the X-axis direction in the drawing), the embodiment is not limited to this. According to this embodiment, the connecting wiring 150 can be made shorter to reduce parasitic capacitance.

[0100] Figure 10 is a schematic plan view showing multiple pixel regions PX of an image sensor according to another embodiment of the present invention. Figure 10 shows the portion corresponding to Figure 4, and for the second transistor 144 and the third transistor 146, the gate electrodes are mainly shown. Referring to Figure 10, in this embodiment, in at least one of the first to fourth pixel regions (PX1, PX2, PX3, PX4), the first internal portion 128c and the second internal portion 128d of the separation pattern 126 are extended in the first direction (X-axis direction in the drawing), and in at least one other, the first internal portion 128c and the second internal portion 128d are extended in the second direction (Y-axis direction in the drawing).

[0101] In this embodiment, the active region 118 is positioned diagonally in the first to fourth pixel regions (PX1, PX2, PX3, PX4), allowing the orientation of the first internal portion 128c and the second internal portion 128d to be freely changed. According to the embodiment, the autofocus characteristics in the first direction (X-axis direction in the drawing) can be improved in the first pixel area PX1 and the fourth pixel area PX4, respectively, and the autofocus characteristics in the second direction (Y-axis direction in the drawing) can be improved in the second pixel area PX2 and the third pixel area PX3, respectively. This effectively improves autofocus performance.

[0102] Figure 10 illustrates a shape in which the first pixel region PX1 and the fourth pixel region PX4, respectively, have a first portion P1 and a second portion P2 that are adjacent to each other in the first direction (the X-axis direction in the drawing) and extend in the second direction (the Y-axis direction in the drawing) (for example, a vertically extended shape). Furthermore, examples were given in which the second pixel region PX2 and the third pixel region PX3 each have a shape (for example, a lateral extension shape) in which the first portion P1 and the second portion P2 are adjacent to each other in the second direction and extend in the first direction. However, the embodiments are not limited to these.

[0103] In one embodiment, two pixel regions PX among the first to fourth pixel regions (PX1, PX2, PX3, PX4) have a symmetrical arrangement with respect to each other, or have the same arrangement with respect to each other. More specifically, the active regions 118 (for example, the first active region 112, the second active region 114, and the third active region 116) contained within two pixel regions PX of the first to fourth pixel regions (PX1, PX2, PX3, PX4) are arranged symmetrically to each other or have the same arrangement. Furthermore, the pixel circuits 130 contained in two pixel regions PX of the first to fourth pixel regions (PX1, PX2, PX3, PX4) have a symmetrical arrangement with respect to each other, or have the same arrangement with respect to each other.

[0104] For the sake of clarity in the following explanation, in each pixel region PX, the transmission transistor located near the center of the unit pixel group in the second direction (the Y-axis direction in the drawing) will be referred to as the first transmission transistor 142a, and the transmission transistor located far from the center of the unit pixel group in the second direction will be referred to as the second transmission transistor 142b. Furthermore, among the second transistor 144 and third transistor 146 located in each pixel region PX, the transistor closer to the center of the unit pixel group is referred to as the second transistor 144, and the transistor located further away from the center of the unit pixel group is referred to as the third transistor 146.

[0105] In the first pixel region PX1 or the fourth pixel region PX4, the first active region 112 is formed in the first diagonal direction D1, and the second active region 114 and the third active region 116 are arranged symmetrically with respect to each other in the second diagonal direction D2. Furthermore, the first transmission transistor 142a and the second transmission transistor 142b are symmetrical with respect to each other in the first diagonal direction D1, and the second transistor 144 and the third transistor 146 are symmetrical with respect to each other in the second diagonal direction D2. In the second pixel region PX2 or the third pixel region PX3, the first active region 112 is formed in the second diagonal direction D2, and the second active region 114 and the third active region 116 are arranged symmetrically with respect to each other in the first diagonal direction D1. Furthermore, the first transmission transistor 142a and the second transmission transistor 142b are symmetrical with respect to each other in the second diagonal direction D2, and the second transistor 144 and the third transistor 146 are symmetrical with respect to each other in the first diagonal direction D1.

[0106] The second transistor 144 in the first pixel region PX1 and the second transistor 144 in the second pixel region PX2 constitute the drive transistor SF. The gate electrodes of the second transistor 144 in the first pixel region PX1 and the second transistor 144 in the second pixel region PX2 are shared to form a drive transistor SF. The third transistor 146 in the first pixel region PX1 constitutes a dummy transistor DX, and the third transistor 146 in the second pixel region PX2 constitutes a reset transistor RX. The second transistor 144 and the third transistor 146 in the third pixel region PX3 constitute conversion gain transistors (DCX and MCX), respectively. The second transistor 144 in the fourth pixel region PX4 constitutes the selection transistor SX, and the third transistor 146 in the fourth pixel region PX4 constitutes the dummy transistor DX. However, the arrangement of the second transistor 144 or the third transistor 146 in the first to fourth pixel regions (PX1, PX2, PX3, PX4) is illustrative and the embodiment is not limited thereto.

[0107] Figure 10 illustrates a case in which the active region 118 comprises at least two pixel regions PX having a symmetrical shape. However, the embodiments are not limited thereto, and the arrangement of the active regions 118 contained in each of the first to fourth pixel regions (PX1, PX2, PX3, PX4) can be varied in many ways. Figure 10 illustrates an example in which the second transistor 144 in the first pixel region PX1 and the second pixel region PX2 is extended in the first direction (the X-axis direction in the drawing). According to this, the gate electrode of the second transistor 144 in the first pixel region PX1 and the second pixel region PX2 can be shared with a simple structure. However, the embodiments are not limited thereto, and at least one of the first pixel region PX1 and the second pixel region PX2 may also include a portion in which the second transistor 144 is extended in a direction other than the first direction.

[0108] Figure 10 illustrates a case in which the second transistor 144 in the third pixel region PX3 and the fourth pixel region PX4, and the third transistor 146 in the first to fourth pixel regions (PX1, PX2, PX3, PX4) are extended in a direction that intersects (for example, orthogonal) with the extension direction of the first internal portion 128c or the second internal portion 128d. That is, the second transistor 144 in the fourth pixel region PX4, the third transistor 146 in the first pixel region PX1, and the third transistor 146 in the fourth pixel region PX4 are extended in a first direction (the X-axis direction in the drawing) that intersects (for example, orthogonally) with the second direction (the Y-axis direction in the drawing), which is the extension direction of the first internal portion 128c or the second internal portion 128d. Then, the third transistor 146 in the second pixel region PX2, and the second transistor 144 and third transistor 146 in the third pixel region PX3 are extended in a second direction that intersects (for example, orthogonal to) the first direction, which is the extension direction of the first internal portion 128c or the second internal portion 128d. According to this, the spacing between multiple transistors 140 can be increased, thereby improving the structure or density of the wiring section. However, the embodiments are not limited to these. Therefore, at least one of the second transistors 144 in the third pixel region PX3 and the fourth pixel region PX4, and the third transistors 146 in the first to fourth pixel regions (PX1, PX2, PX3, PX4), can be extended in a direction parallel to the extension direction of the first internal portion 128c or the second internal portion 128d.

[0109] Figure 11 is a schematic plan view showing multiple pixel regions PX of an image sensor according to another embodiment of the present invention. Figure 11 shows the portion corresponding to Figure 4, and for the second transistor 144 and the third transistor 146, the gate electrodes are primarily shown. Referring to Figure 11, in this embodiment, in at least one of the first to fourth pixel regions (PX1, PX2, PX3, PX4), the first internal portion 128c and the second internal portion 128d of the separation pattern 126 are extended in the first direction (X-axis direction in the drawing), and in at least one other, the first internal portion 128c and the second internal portion 128d are extended in the second direction (Y-axis direction in the drawing). This effectively improves autofocus performance. Unless otherwise specified, the explanation in Figure 10 applies.

[0110] For the sake of clarity in the following explanation, in each pixel region PX, the transmission transistor located near the center of the unit pixel group in the second direction (the Y-axis direction in the drawing) will be referred to as the first transmission transistor 142a, and the transmission transistor located far from the center of the unit pixel group in the second direction will be referred to as the second transmission transistor 142b. Furthermore, among the second transistor 144 and third transistor 146 located in each pixel region PX, the transistor closer to the center of the unit pixel group is referred to as the second transistor 144, and the transistor located further away from the center of the unit pixel group is referred to as the third transistor 146.

[0111] In the first pixel region PX1 or the fourth pixel region PX4, the first active region 112 is formed in the first diagonal direction D1, and the second active region 114 and the third active region 116 are arranged symmetrically with respect to each other in the second diagonal direction D2. Furthermore, the first transmission transistor 142a and the second transmission transistor 142b are symmetrical with respect to each other in the first diagonal direction D1, and the second transistor 144 and the third transistor 146 are symmetrical with respect to each other in the second diagonal direction D2. In the second pixel region PX2 or the third pixel region PX3, the first active region 112 is formed in the second diagonal direction D2, and the second active region 114 and the third active region 116 are arranged symmetrically with respect to each other in the first diagonal direction D1. Furthermore, the first transmission transistor 142a and the second transmission transistor 142b are symmetrical with respect to each other in the second diagonal direction D2, and the second transistor 144 and the third transistor 146 are symmetrical with respect to each other in the first diagonal direction D1.

[0112] The four second transistors 144, each provided in a second transistor 144 of a pixel region PX (i.e., the first to fourth pixel regions (PX1, PX2, PX3, PX4)), constitute the drive transistor SF. The gate electrodes of the second transistor 144 in the first pixel region PX1 and the second transistor 144 in the second pixel region PX2 are shared to form the first drive transistor SF1. The gate electrodes of the second transistor 144 in the third pixel region PX3 and the second transistor 144 in the fourth pixel region PX4 are shared to form the second drive transistor SF2. The first drive transistor SF1 and the second drive transistor SF2 are connected in parallel. According to this, the transistor width can be increased to improve performance, and the structure of the wiring can be simplified. The third transistor 146 in the first pixel region PX1 constitutes the selection transistor SX, the third transistor 146 in the second pixel region PX2 constitutes the reset transistor RX, and the third transistor 146 in the third pixel region PX3 and the third transistor 146 in the fourth pixel region PX4 constitute the conversion gain transistors (DCX and MCX), respectively. However, the arrangement of the second transistor 144 or the third transistor 146 in the first to fourth pixel regions (PX1, PX2, PX3, PX4) is illustrative and the embodiment is not limited thereto.

[0113] Figure 12 is a schematic plan view showing multiple pixel regions PX of an image sensor according to another embodiment of the present invention. Figure 12 shows the portion corresponding to Figure 4, and for the second transistor 144 and the third transistor 146, the gate electrodes are primarily shown. Referring to Figure 12, in this embodiment, in at least one of the first to fourth pixel regions (PX1, PX2, PX3, PX4), the first internal portion 128c and the second internal portion 128d of the separation pattern 126 are extended in the first direction (X-axis direction in the drawing), and in at least one other, the first internal portion 128c and the second internal portion 128d are extended in the second direction (Y-axis direction in the drawing). This effectively improves autofocus performance. In Figure 12, the first to fourth pixel regions (PX1, PX2, PX3, PX4) are exemplified as having the arrangement shown in Figure 11, but the embodiment is not limited to this, and the arrangement in Figure 10 is also possible. Other diverse forms are possible.

[0114] In the following, for the sake of clarity, in each pixel region PX, the transmission transistor located near the center of the unit pixel group in the second direction (the Y-axis direction in the drawing) will be referred to as the first transmission transistor 142a, and the transmission transistor located far from the center of the unit pixel group in the second direction will be referred to as the second transmission transistor 142b. Furthermore, among the second transistor 144 and third transistor 146 located in each pixel region PX, the transistor closer to the center of the unit pixel group is referred to as the second transistor 144, and the transistor located further away from the center of the unit pixel group is referred to as the third transistor 146. In this embodiment, the connection wiring 150 is included, which extends planar from the gate electrode of the second transistor 144 (e.g., the driving transistor SF) and is electrically connected to the floating diffusion region 120f. Unless otherwise specified, the description of connection wiring 150 with reference to Figures 8 and 9 applies. Figure 12 illustrates an example where the connection wiring 150 includes the first to fifth connection wirings as shown in Figure 9. However, the embodiments are not limited thereto, and the connection wiring 150 may include a first common connection wiring and a second common connection wiring, as shown in Figure 8.

[0115] Figure 13 is a schematic plan view showing the pixel region PX of an image sensor according to another embodiment of the present invention. Figure 13 shows the portion corresponding to Figure 5. Referring to Figure 13, in this embodiment, the first active region 112 has a uniform width overall. For example, the first active portion 112a, the second active portion 112b, and the connecting active portion 112c have a uniform width. Then, in the first diagonal direction D1, the first transmission transistor 142a and the second transmission transistor 142b are positioned on both sides of the first active region 112, respectively. As an example, the first transmission transistor 142a and the second transmission transistor 142b have a single vertical transmission gate structure. In this embodiment, the first active region 112 where the first transmission transistor 142a and the second transmission transistor 142b are located can be formed with a uniform width to increase the distance between multiple active regions 118 or the distance between multiple transistors 140. This can reduce noise. The shape of the first active region 112 can be varied in many ways, taking into consideration electron collection efficiency and noise.

[0116] Figure 14 is a schematic plan view showing the pixel region PX of an image sensor according to another embodiment of the present invention. Figure 14 shows the portion corresponding to Figure 5. Referring to Figure 14, in this embodiment, the width of a portion of the connection active portion 112c where the floating diffusion region 120f is located (for example, the central portion) is greater than the width of other portions of the connection active portion 112c. According to this, a floating diffusion region 120f can be stably formed. However, the embodiments are not limited to these, and various modifications are possible.

[0117] Figure 15 is a partial cross-sectional view showing a part of an image sensor according to another embodiment of the present invention. Figure 15 shows the portion corresponding to Figure 3. Referring to Figure 15, the image sensor according to this embodiment includes a first additional wiring portion 200a and a second additional wiring portion 200b, in which the additional wiring portion 200 is sequentially arranged on the photoelectric conversion substrate 100. According to this, the image sensor has a photoelectric conversion substrate 100 and a multilayer laminated structure (for example, a three-layer laminated structure) including a first additional wiring portion 200a and a second additional wiring portion 200b.

[0118] Figure 15 illustrates a configuration in which the wiring section 170 and the first additional wiring section 200a are joined by a hybrid bond including metal bonding and insulating layer bonding, and the first additional wiring section 200a includes a semiconductor substrate 210a; however, the embodiment is not limited to this. After joining the wiring section 170 and the first additional wiring section 200a using an insulating layer bond, connecting members and the like for connecting the wiring section 170 and the first additional wiring section 200a can be further formed. The first additional wiring portion 200a and the second additional wiring portion 200b are joined by a hybrid bond including metal bonding and insulating layer bonding, but the embodiment is not limited thereto. By further including the first additional wiring section 200a and the second additional wiring section 200b in this manner, the degree of congestion in the arrangement of wiring, circuit elements, etc., included in the wiring section 170, and the first additional wiring section 200a and the second additional wiring section 200b can be effectively improved. This allows for miniaturization of the pixel area of ​​the image sensor, thereby improving the integration density and performance of the image sensor.

[0119] For example, the wiring section 170 may include wiring connected to the pixel circuit 130, the first additional wiring section 200a may include circuit elements (e.g., transistors), wiring, etc., and the second additional wiring section 200b may include a logic circuit section, a power supply section, wiring, etc. However, the embodiments are not limited to these, and various modifications are possible for the wiring section 170 and the wiring, circuits, etc., included in the first additional wiring section 200a and the second additional wiring section 200b. Alternatively, the image sensor may further include additional wiring portions other than the first additional wiring portion 200a and the second additional wiring portion 200b.

[0120] Furthermore, the present invention is not limited to the embodiments described above. It can be modified and implemented in various ways without departing from the technical scope of the present invention. [Explanation of Symbols]

[0121] 10 Image Sensors 10a pixel array 20 Logic Circuits 22 controllers 24 Timing Generator 26a Low Driver 26b Lead-out circuit 26c Lamp signal generator 28 Data buffer 30 Image signal processor 100 Photoelectric conversion substrate 110 Substrate 112 First active region 114 Second active region 116 Third active region 120 Photoelectric conversion section 120f Floating diffusion region 122 First conductivity type region 122a First conversion part 122b Second conversion part 122d Connection part 124 Second conductivity type region 126 Separation pattern 126c Conductive layer 127 First separation pattern 128 Second separation pattern 128a First extension part 128b Second extension part 128c First internal part 128d Second internal part 130 Pixel circuit 140 Transistor 140d Drain region 140g Gate electrode 140i Gate insulating layer 140p Spacer 140s Source region 142 First transistor 142a First transmission transistor 142b Second transmission transistor 142g Transmission gate electrode 142i Transmission gate insulating layer 144 Second transistor 146 Third transistor 170 Wiring part 172 Interlayer insulating layer 174 Contact via 176 Wiring layer 180 Horizontal insulating layer 182 Color Filters 184 Filter separation section 186 Protective layer 188 Microlenses 200 Additional wiring part 210 circuit boards 240 transistors 270 Wiring DCX, MCX Gain Control Transistor (Conversion Gain Transistor) PD Photoelectric Conversion Unit PX Pixel area PX1~PX4 (1st~4th) pixel area RX Reset Transistor SF drive transistor SF1, SF2 (first and second) drive transistors SP separation part SX Select Transistor TX transmission transistor

Claims

1. A substrate having a first surface and a second surface facing each other, The photoelectric conversion unit arranged on the substrate, A pixel circuit arranged on the first surface side of the substrate, The substrate has a separation pattern that includes a separation portion that penetrates at least a part of the substrate and defines a region in which the photoelectric conversion unit is arranged, The pixel circuit includes a first transistor which includes a first transmission transistor and a second transmission transistor, An image sensor characterized in that the active region of the substrate, which is arranged on the first surface of the substrate, includes a first active region which includes a first active portion on which the first transmission transistor is arranged, a second active portion on which the second transmission transistor is arranged, and a connecting active portion which connects the first active portion and the second active portion in a first diagonal direction inclined with respect to the separation portion.

2. The pixel region includes the photoelectric conversion unit and the pixel circuit, The image sensor according to claim 1, characterized in that the first active region or the pixel circuit has a point-symmetric shape in the pixel region and an asymmetric shape in the extension direction of the separated portion.

3. The photoelectric conversion unit includes a first conversion portion located on the first side in a first direction inclined with respect to the first diagonal direction, and a second conversion portion located on the second side opposite to the first side. The image sensor according to claim 1, characterized in that the first conversion portion and the second conversion portion are extended in a second direction that intersects the first direction which is inclined with the first diagonal direction.

4. The photoelectric conversion unit includes a first conversion portion located on the first side in a first direction inclined with respect to the first diagonal direction, and a second conversion portion located on the second side opposite to the first side. In a plan view, the first transmission transistor is positioned on the third side in a second direction that intersects the first direction at a position superimposed on the first conversion portion. The image sensor according to claim 1, characterized in that the second transmission transistor is positioned on the fourth side in the second direction opposite to the third side, at a position superimposed on the second conversion portion.

5. The image sensor according to claim 1, characterized in that the connection active portion has a line shape that extends long in the first diagonal direction.

6. In a plan view, a floating diffusion region is located in the central part of the connection active portion. The image sensor according to claim 1, characterized in that, in a plan view, the first active portion and the second active portion have a point-symmetric shape with respect to the floating diffusion region.

7. The first active portion and the second active portion each have a width greater than the connecting active portion, The image sensor according to claim 1, characterized in that the first transmission transistor and the second transmission transistor each have a dual vertical transmission gate (dual VTG) structure.

8. The pixel circuit includes a second transistor and a third transistor having a different cross-sectional shape from the first transistor. The second transistor is positioned on one side of the first active region in a second diagonal direction intersecting the first diagonal direction. The image sensor according to claim 1, characterized in that the third transistor is arranged on the other side of the first active region in the second diagonal direction.

9. The pixel circuit includes a second transistor and a third transistor having a different cross-sectional shape from the first transistor. The active region further includes a second active region where the second transistor is located, and a third active region where the third transistor is located. The second active region is located on one side of the first active region in a second diagonal direction that intersects with the first diagonal direction. The image sensor according to claim 1, characterized in that the third active region is located on the other side of the first active region in the second diagonal direction.

10. The photoelectric conversion unit includes a first conversion portion located on the first side in a first direction inclined with respect to the first diagonal direction, and a second conversion portion located on the second side opposite to the first side. The separation pattern includes a first internal portion and a second internal portion that extend between the first conversion portion and the second conversion portion and are separated from each other. The pixel circuit includes a second transistor and a third transistor having a different cross-sectional shape from the first transistor. In the first direction, the first transmission transistor and the second transistor are arranged on both sides of the first internal portion, with the first internal portion in between. The image sensor according to claim 1, characterized in that, in the first direction, the second transmission transistor and the third transistor are arranged on both sides of the second internal portion, with the second internal portion in between.

11. The photoelectric conversion unit includes a first conversion portion located on the first side in a first direction inclined with respect to the first diagonal direction, and a second conversion portion located on the second side opposite to the first side. The separation pattern includes a first internal portion and a second internal portion that extend between the first conversion portion and the second conversion portion and are separated from each other. The image sensor according to claim 1, characterized in that, in a plan view, the first internal portion and the first active portion are arranged point-symmetrically with respect to the second internal portion and the second active portion.

12. The first pixel region and the second pixel region adjacent in the first diagonal direction and the first inclined direction, It further comprises a third pixel region and a fourth pixel region adjacent to the first pixel region and the second pixel region, respectively, in a second direction intersecting the first direction, The image sensor according to claim 1, characterized in that the first active regions, each contained within two of the first to fourth pixel regions, have a symmetrical arrangement or the same arrangement.

13. The first pixel region and the second pixel region adjacent in the first diagonal direction and the first inclined direction, The system further includes a plurality of pixel regions, including a third pixel region and a fourth pixel region adjacent to the first pixel region and the second pixel region, respectively, in a second direction intersecting the first direction. The separation pattern includes a first internal portion and a second internal portion that extend within the pixel region and face each other with a separation portion in between. In at least one of the first to fourth pixel regions, the first internal portion and the second internal portion are extended in the first direction. The image sensor according to claim 1, characterized in that the first internal portion and the second internal portion are extended in the second direction in at least one of the first to fourth pixel regions.

14. A substrate having a first surface and a second surface facing each other, The photoelectric conversion unit arranged on the substrate, A pixel circuit arranged on the first surface side of the substrate, The substrate has a separation pattern that penetrates at least a portion of it, The photoelectric conversion unit includes a first conversion portion located on the first side in the first direction, and a second conversion portion located on the second side opposite to the first side. The pixel circuit includes a first transmission transistor electrically connected to the first conversion portion and positioned on the third side in a second direction intersecting the first direction, An image sensor characterized by including a first transistor which includes a second transmission transistor electrically connected to the second conversion portion and positioned on the fourth side opposite to the third side in the second direction.

15. The pixel region further includes the photoelectric conversion unit and the pixel circuit, The image sensor according to claim 14, characterized in that the first transmission transistor and the second transmission transistor have a point-symmetric shape in the pixel region and an asymmetric shape in the first or second direction.

16. The pixel circuit includes a second transistor and a third transistor having a different cross-sectional shape from the first transistor. In a plan view, the third transistor is positioned on the fourth side in the second direction, superimposed on the first conversion portion. The image sensor according to claim 14, characterized in that the second transistor is positioned on the third side in the second direction at a position superimposed on the second conversion portion.

17. A floating diffusion region is arranged in the active region of the substrate, which is located on the first surface side of the substrate. The image sensor according to claim 14, wherein the pixel circuit further includes a second transistor having a different cross-sectional shape from the first transistor, and a connecting wire that extends in a plane from the gate electrode of the second transistor and is electrically connected to the floating diffusion region.

18. A substrate having a first surface and a second surface facing each other, A plurality of pixel regions each including a photoelectric conversion unit arranged on the substrate and a pixel circuit arranged on the first surface side of the substrate, The substrate has a separation pattern that includes a separation portion that penetrates at least a part of the substrate and defines a region in which the photoelectric conversion unit is arranged, The photoelectric conversion unit includes a first conversion portion located on the first side in the first direction, and a second conversion portion located on the second side opposite to the first side. The image sensor is characterized in that the pixel circuit has a point-symmetric shape in the pixel region and an asymmetric shape in the first direction.

19. The pixel circuit includes a first transistor which includes a first transmission transistor and a second transmission transistor, The image sensor according to claim 18, characterized in that the first transmission transistor and the second transmission transistor are arranged on both sides in a first diagonal direction inclined with respect to the first direction.

20. The pixel circuit includes a second transistor and a third transistor having a different cross-sectional shape from the first transistor. The image sensor according to claim 19, characterized in that the second transistor and the third transistor are respectively arranged on both sides in a second diagonal direction that is inclined with respect to the first direction and intersects with the first diagonal direction.

Images