Method for manufacturing semiconductor structures
The method of converting amorphous silicon to polycrystalline silicon through heat treatment and subsequent oxidation in semiconductor structure manufacturing addresses pinhole defects and improves film quality, ensuring consistent contact resistance and dimensional accuracy, thereby enhancing the operational performance of semiconductor structures.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- SWAYSURE TECHNOLOGY CO LTD
- Filing Date
- 2025-09-03
- Publication Date
- 2026-05-13
AI Technical Summary
Conventional methods for manufacturing pillar electrical connection structures in semiconductor structures face issues such as pinhole defects, discontinuities in thin film layers, and poor dimensional uniformity, leading to reduced operational performance and reliability due to damage during etching processes.
A method involving the use of amorphous silicon as a protective material layer, followed by heat treatment to convert it to polycrystalline silicon, and subsequent oxidation to form a sacrificial layer, which is then etched away, improving the film quality and reducing pinhole defects, thereby enhancing the protective effect on sidewall layers.
This approach improves the film quality of sidewall layers, reduces leakage current, and enhances the operational performance of semiconductor structures by ensuring consistent contact resistance and dimensional accuracy.
Smart Images
Figure 2026077573000001_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and more particularly to a method for manufacturing a semiconductor structure.
Background Art
[0002] Pillar electrical connection structures play an important role in electronic devices, especially when high density, high reliability, and stable electrical connections are required. They are widely applied in fields such as integrated circuits, semiconductor devices, and packaging technology, providing strong support for improving the performance and reliability of electronic products.
[0003] With the rapid development of electronic technology, pillar electrical connection structures have also experienced continuous technological innovation and optimization. From the initial simple pillar structure to the current complex three-dimensional structure, their performance and reliability have been significantly improved. At the same time, with the continuous progress of material science, nanotechnology, and precision manufacturing technology, the design and manufacturing of pillar electrical connection structures have become more precise and efficient.
Summary of the Invention
Problems to be Solved by the Invention
[0004] Embodiments of the present invention provide a method for manufacturing a semiconductor structure, which at least partially solves the technical problems existing in the conventional method for manufacturing a pillar electrical connection structure and improves the operating performance of the semiconductor structure.
Means for Solving the Problems
[0005] To solve the above problems, an embodiment of the present invention provides a method for manufacturing a semiconductor structure, which provides a substrate in which an interconnect conductive layer is embedded, wherein the substrate exposes the surface of the interconnect conductive layer, a stack layer covering the substrate is formed on the substrate, and through holes are formed in the stack layer that penetrate the stack layer and expose the surface of the interconnect conductive layer, and the substrate is provided, which includes forming a sidewall material layer made of silicon oxide that covers at least the sidewall and bottom of the through holes, forming a protective material layer made of amorphous silicon that covers the sidewall material layer, performing heat treatment on the protective material layer to realize a material phase transition process in the protective material layer, etching off the material located above the interconnect conductive layer at the bottom of the through holes to expose the surface of the interconnect conductive layer, and at the same time making the sidewall material layer covering the sidewall of the through holes a sidewall layer and the remaining protective material layer covering the sidewall layer a protective layer, and removing the protective layer.
[0006] In the step of selectively heat-treating the protective material layer, the material of the protective material layer is converted from amorphous silicon to polycrystalline silicon.
[0007] In the step of selectively heat-treating the protective material layer, the heat treatment includes a rapid thermal process.
[0008] Selectively, after heat-treating the protective material layer, and before etching away the material located above the interconnecting conductive layer at the bottom of the through-hole, the manufacturing method further includes oxidizing the protective material layer to completely oxidize the protective material layer at the bottom of the through-hole and partially oxidizing the protective material layer on the sidewall of the through-hole to form a sacrificial layer, the sacrificial layer covering at least the remaining protective material layer on the sidewall of the through-hole.
[0009] The step of selectively etching away material located above the interconnecting conductive layer at the bottom of the through-hole includes etching away the sacrificial layer and the sidewall material layer at the bottom of the through-hole.
[0010] In the step of selectively oxidizing the protective material layer, the material of the sacrificial layer is the same as the material of the sidewall material layer, and the sacrificial layer and the sidewall material layer at the bottom of the through hole are etched off in the same process.
[0011] The step of selectively oxidizing the protective material layer includes oxidizing the protective material layer using an in-situ steam generation oxidation process or a furnace tube oxidation process.
[0012] Selectively, a wet etching process is employed to remove the sacrificial layer and the sidewall material layer at the bottom of the through-hole.
[0013] The method further includes selectively forming a buffer layer covering the protective material layer before performing an oxidation treatment on the protective material layer, and further including removing the buffer layer in the step of etching off the sacrificial layer and the sidewall material layer at the bottom of the through hole.
[0014] In the step of selectively forming a buffer layer that covers the protective material layer, the material of the buffer layer includes any one of silicon oxide, silicon nitride, and silicon oxynitride.
[0015] The step of selectively oxidizing the protective material layer includes forming a buffer layer made of an oxide material that covers the protective material layer, and simultaneously diffusing oxidation from the buffer layer into the protective material layer to completely oxidize the protective material layer at the bottom of the through hole and partially oxidize the protective material layer on the side wall of the through hole to form a sacrificial layer, and the step of etching off the sacrificial layer and the side wall material layer at the bottom of the through hole further includes removing the buffer layer.
[0016] Selectively, an atomic layer deposition process is employed to form a buffer layer that covers the protective material layer.
[0017] In the step of selectively forming a buffer layer that covers the protective material layer, the material of the buffer layer is the same as the material of the sacrificial layer, and the sacrificial layer and the buffer layer are removed in the same process.
[0018] Selectively, an atomic layer deposition process is employed to form a sidewall material layer that covers at least the sidewalls and bottom of the through-hole.
[0019] Selectively, a chemical vapor deposition process is employed to form a protective material layer that covers the sidewall material layer.
[0020] Selectively, a wet etching process is used to remove the protective layer.
[0021] Compared to the prior art, the technical method in the embodiment of the present invention has the following advantages. In the manufacturing method provided in the embodiment of the present invention, a protective material layer is formed to cover the sidewall material layer, the material of the protective material layer is amorphous silicon, the protective material layer is heat-treated to realize a material phase transition process in the protective material layer, and the material located above the interconnection conductive layer at the bottom of the through hole is etched off to expose the surface of the interconnection conductive layer, and in the embodiment of the present invention, the protective material layer is heat-treated before etching off the material located above the interconnection conductive layer at the bottom of the through hole to realize a material phase transition process in the protective material layer, thus crystallization in the conversion process from amorphous silicon to polycrystalline silicon Reconstructing the grid helps to remove pinhole defects in the protective material layer and improve the film deposition effect of the protective material layer. In the step of etching away the material located above the interconnect conductive layer at the bottom of the through-hole to expose the surface of the interconnect conductive layer, the protective effect of the protective material layer on the sidewall material layer of the through-hole sidewall is improved. This helps to avoid or improve damage to the sidewall material layers on both sides of the bottom of the through-hole due to pinhole defects when removing the protective material layer and sidewall material layer at the bottom of the through-hole, thereby improving the film quality of the sidewall layer, reducing or avoiding leakage current, and thereby improving the operational performance of the semiconductor structure. [Brief explanation of the drawing]
[0022] [Figure 1] This is a schematic diagram of the structure corresponding to each step in the manufacturing method of a semiconductor structure in the prior art. [Figure 2] It is a schematic structural diagram corresponding to each step in the method for manufacturing a semiconductor structure in the prior art. [Figure 3] It is a schematic structural diagram corresponding to each step in the method for manufacturing a semiconductor structure in the prior art. [Figure 4] It is a schematic structural diagram corresponding to each step in the method for manufacturing a semiconductor structure in the prior art. [Figure 5] It is a schematic structural diagram corresponding to each step in the method for manufacturing a semiconductor structure in the prior art. [Figure 6] It is a schematic structural diagram corresponding to each step in one embodiment of the method for manufacturing a semiconductor structure of the present invention. [Figure 7] It is a schematic structural diagram corresponding to each step in one embodiment of the method for manufacturing a semiconductor structure of the present invention. [Figure 8] It is a schematic structural diagram corresponding to each step in one embodiment of the method for manufacturing a semiconductor structure of the present invention. [Figure 9] It is a schematic structural diagram corresponding to each step in one embodiment of the method for manufacturing a semiconductor structure of the present invention. [Figure 10] It is a schematic structural diagram corresponding to each step in one embodiment of the method for manufacturing a semiconductor structure of the present invention. [Figure 11] It is a schematic structural diagram corresponding to each step in one embodiment of the method for manufacturing a semiconductor structure of the present invention. [Figure 12] It is a schematic structural diagram corresponding to each step in one embodiment of the method for manufacturing a semiconductor structure of the present invention. [Figure 13] It is a schematic structural diagram corresponding to each step in another embodiment of the method for manufacturing a semiconductor structure of the present invention. [Figure 14] It is a schematic structural diagram corresponding to each step in another embodiment of the method for manufacturing a semiconductor structure of the present invention. [Figure 15] It is a schematic structural diagram corresponding to each step in another embodiment of the method for manufacturing a semiconductor structure of the present invention. [Figure 16]This is a schematic diagram of the structure corresponding to each step in yet another embodiment of the method for manufacturing a semiconductor structure of the present invention. [Modes for carrying out the invention]
[0023] From the background technology, it is clear that improving the operational performance of semiconductor structures is difficult at present. Here, we will analyze the reasons why the operational performance of semiconductor structures has not yet improved, in relation to the manufacturing methods of semiconductor structures.
[0024] Figures 1 to 5 are schematic diagrams of structures corresponding to each step in the semiconductor structure manufacturing method.
[0025] Referring to Figure 1, a substrate 10 is provided in which an interconnecting conductive layer 11 is embedded, with the surface of the interconnecting conductive layer exposed on the substrate 10. A stack layer 20 covering the substrate 10 is formed on the substrate 10, and through holes 21 are formed within the stack layer 20 that penetrate the stack layer 20 and expose the surface of the interconnecting conductive layer 11.
[0026] Referring to Figure 2, a sidewall material layer 30 made of silicon oxide is formed, covering at least the sidewall and bottom of the through-hole 21.
[0027] Referring to Figure 3, a protective material layer 40 made of amorphous silicon is formed to cover the side wall material layer 30.
[0028] Referring to Figure 4, the material located above the interconnecting conductive layer 11 at the bottom of the through hole 21 is etched away to expose the surface of the interconnecting conductive layer 11. At the same time, the sidewall material layer 30 covering the sidewall of the through hole 21 is designated as the sidewall layer 31, and the protective material layer 40 covering the sidewall layer 31 is designated as the protective layer 41.
[0029] Because the protective material layer 40 is made of amorphous silicon, the aspect ratio of the through-hole 21 is relatively large and the dimension (CD) is relatively small. However, since the thickness of the amorphous silicon protective material layer 40 is usually quite thin, discontinuities in the thin film can occur, and pinhole defects may be generated on the film layer. In the process of removing the material located above the interconnecting conductive layer 11 at the bottom of the through-hole 21 by dry etching, the protective effect of the protective material layer 40 on the sidewall material layer 30 is relatively weak, causing dry etching damage to the sidewall material layer 30 through the pinholes.
[0030] Furthermore, since it is necessary to remove the material located above the interconnecting conductive layer 11 at the bottom of the through-hole 21 using dry etching, etching residue from dry etching tends to remain at the bottom of the through-hole 21, requiring further cleaning before subsequent removal of the protective layer 41. However, if there are pinhole defects in the protective layer 41, the cleaning solution can easily pass through the protective layer 41 and damage the sidewall layer 31 during the cleaning process. Similarly, when removing the protective layer 41 with wet etching afterward, the etching solution can easily pass through the protective layer 41 and damage the sidewall layer 31. In addition to the above, when dry etching is used to remove material located above the interconnecting conductive layer 11 at the bottom of the through-hole 21, the dimensions of the interconnecting conductive layer 11 that are exposed when the bottom of the through-hole 21 is opened vary considerably from area to area. This affects the dimensional accuracy of the process of removing material located above the interconnecting conductive layer 11 at the bottom of the through-hole 21, resulting in low dimensional uniformity of the interconnecting conductive layer 11 exposed in different areas of the bottom of the through-hole 21. Subsequently, the consistency of contact resistance when electrically connecting the interconnecting conductive layer 11 through the bottom of the through-hole 21 deteriorates, affecting the operating performance of the semiconductor structure.
[0031] Referring to Figure 5, the protective layer 41 has been removed.
[0032] After the protective layer 41 is removed, the interconnecting conductive layer 11 makes electrical connections through the bottom of the through-hole 21. However, damage to the sidewall layer 31 easily reduces the protective effect of the interconnecting conductive layer 11 on the electrical connections made through the bottom of the through-hole 21, thereby affecting the operational performance of the semiconductor structure.
[0033] To solve the technical problems, embodiments of the present invention provide a method for manufacturing a semiconductor structure, which provides a substrate in which an interconnect conductive layer is embedded, wherein the substrate exposes the surface of the interconnect conductive layer, a stack layer covering the substrate is formed on the substrate, and through holes are formed in the stack layer that penetrate the stack layer and expose the surface of the interconnect conductive layer, and the method includes forming a sidewall material layer made of silicon oxide that covers at least the sidewalls and bottom of the through holes, forming a protective material layer made of amorphous silicon that covers the sidewall material layer, performing heat treatment on the protective material layer to realize a material phase transition process in the protective material layer, etching off the material located above the interconnect conductive layer at the bottom of the through holes to expose the surface of the interconnect conductive layer, and at the same time making the sidewall material layer covering the sidewalls of the through holes a sidewall layer and the remaining protective material layer covering the sidewall layer a protective layer, and removing the protective layer.
[0034] In embodiments of the present invention, before etching away the material located above the interconnection conductive layer at the bottom of the through-hole, the protective material layer is subjected to heat treatment to realize a material phase transition process in the protective material layer. This helps to remove pinhole defects in the protective material layer by reconstructing the crystal lattice during the conversion process from amorphous silicon to polycrystalline silicon, thereby improving the film deposition effect of the protective material layer. In the step of etching away the material located above the interconnection conductive layer at the bottom of the through-hole to expose the surface of the interconnection conductive layer, the protective effect of the protective material layer on the sidewall material layer of the through-hole sidewall is improved. This helps to avoid or improve damage to the sidewall material layers on both sides of the bottom of the through-hole due to pinhole defects when removing the protective material layer and sidewall material layer at the bottom of the through-hole, thereby improving the film quality of the sidewall layer. Furthermore, it helps to improve the protective effect of the sidewall layer against electrical connections made by the interconnection conductive layer through the bottom of the through-hole, reducing or avoiding leakage current, and further improving the operational performance of the semiconductor structure.
[0035] To make the above-mentioned objectives, features, and advantages of the present invention clearer and easier to understand, specific embodiments of the present invention will be described in detail below, in conjunction with the drawings.
[0036] Figures 6 to 12 are schematic diagrams of structures corresponding to each step in one embodiment of the semiconductor structure manufacturing method of the present invention.
[0037] Referring to Figure 6, a substrate 100 is provided, with an interconnection conductive layer 110 embedded within the substrate 100, exposing the surface of the interconnection conductive layer 110. A stack layer 200 covering the substrate 100 is formed on the substrate 100, and through holes 210 are formed within the stack layer 200, penetrating the stack layer 200 and exposing the surface of the interconnection conductive layer 110.
[0038] The substrate 100 is used to provide a basis for process operations for the manufacturing process of semiconductor structures.
[0039] In this embodiment, an interconnection conductive layer 110 is embedded within the substrate 100, and the substrate 100 exposes the surface of the interconnection conductive layer 110.
[0040] The interconnection conductive layer 110 is used for external electrical connections to realize the basic circuit, and because the substrate 100 exposes the surface of the interconnection conductive layer 110, electrical connections with the outside are realized to the interconnection conductive layer 110 via the surface exposed from the substrate 100.
[0041] In this embodiment, the material of the interconnection conductive layer 110 is a metallic material.
[0042] As an example, in this embodiment, the interconnection conductive layer 110 is a bottom metal layer.
[0043] The stack layer 200 is used to provide a basis for process operations for the formation of the through-hole 210.
[0044] Specifically, in this embodiment, the stack layer 200 includes an etching stop layer (not shown) located at the very bottom.
[0045] The etching stop layer is used as an etching stop position when forming the through-holes 210, making the formation of the through-holes 210 simpler and more accurate, and also helps to improve the consistency of the height of the through-holes 210 in different areas.
[0046] The through-hole 210 is used to provide a spatial position for the formation of the subsequent side wall layer and the interconnection structure that enables electrical connection between the interconnection conductive layer 110 and the outside.
[0047] In this embodiment, the through-hole 210 penetrates the stack layer 200 and exposes the surface of the interconnection conductive layer 110, thereby bringing the interconnection structure formed within the through-hole 210 into contact with the interconnection conductive layer 110 and establishing an electrical connection.
[0048] Referring to Figure 7, a sidewall material layer 300 is formed that covers at least the sidewall and bottom of the through-hole 210, and the material of the sidewall material layer 300 is silicon oxide.
[0049] The sidewall material layer 300 is used to subsequently form the sidewall layer.
[0050] In this embodiment, the material of the sidewall material layer 300 is silicon oxide, which enhances the barrier performance and protective ability of the sidewall layer formed later. Subsequently, a sacrificial layer is formed to further cover the sidewall material layer 300, and since the material of both the sacrificial layer and the sidewall material layer 300 is silicon oxide, the sidewall material layer 300 at the bottom of the through hole 210 and the sacrificial layer are connected as a single structure, which helps to easily remove the sacrificial layer and the sidewall material layer 300 at the bottom of the through hole 210 in the same process.
[0051] Specifically, in this embodiment, in the step of forming a side wall material layer 300 that covers at least the side wall and bottom of the through hole 210, the side wall material layer 300 also covers the top of the stack layer 200.
[0052] In this embodiment, an atomic layer deposition (ALD) process is employed to form a sidewall material layer 300 that covers at least the sidewalls and bottom of the through-hole 210.
[0053] The sidewall material layer 300 formed by employing an atomic layer deposition process has good thickness uniformity and good step coverage capability, allowing the sidewall material layer 300 to properly conformally cover the bottom of the through hole 210 and the top of the sidewall and stack layer 200. It also helps to improve the thickness uniformity of the sidewall layer formed thereafter.
[0054] Referring to Figure 8, a protective material layer 400 is formed to cover the sidewall material layer 300, and the material of the protective material layer 400 is amorphous silicon.
[0055] The protective material layer 400 is used in subsequent manufacturing processes to provide protection to the sidewall material layer 300.
[0056] In this embodiment, the material of the protective material layer 400 is amorphous silicon (A-Si), which is useful in forming a protective material layer 400 with relatively good continuity and relatively high uniformity. Furthermore, since the amorphous silicon material is subsequently converted to polycrystalline silicon by heat treatment to rebuild the crystal lattice, pinhole defects can be eliminated as much as possible.
[0057] Specifically, in this embodiment, in the step of forming a protective material layer 400 that covers the side wall material layer 300, the protective material layer 400 covers the side wall material layer 300 located at the side wall and bottom of the through hole 210 and the side wall material layer 300 located at the top of the stack layer 200.
[0058] In this embodiment, a chemical vapor deposition (CVD) process is employed to form a protective material layer 400 that covers the sidewall material layer 300.
[0059] The chemical vapor deposition process has a relatively fast deposition rate and relatively good deposition effect, which helps to form a protective material layer 400 with relatively high continuity of film layers with fairly high efficiency.
[0060] Referring to Figure 9, a material phase transition process is realized in the protective material layer 400 by applying heat treatment to it.
[0061] The process of heat-treating the protective material layer 400 to induce a material phase transition means converting amorphous silicon into polycrystalline silicon through the reconstruction of the crystal lattice, thereby removing as many pinhole defects as possible from the protective material layer 400 and thereby enhancing the protective effect of the protective material layer 400 on the sidewall material layer 300.
[0062] In this embodiment, during the step of heat treatment of the protective material layer 400, the material of the protective material layer 400 is converted from amorphous silicon to polycrystalline silicon.
[0063] Specifically, when amorphous silicon undergoes heat treatment to reconstruct its crystal lattice and is converted into polycrystalline silicon, the resulting polycrystalline silicon has relatively few pinhole defects.
[0064] In this embodiment, the step of heat-treating the protective material layer 400 includes a rapid thermal processing (RTP) process.
[0065] The rapid thermal process is characterized by its high efficiency, flexibility, low contamination and energy consumption, and can perform highly efficient and rapid heat treatment on the protective material layer 400.
[0066] Referring to Figure 10, after heat treatment of the protective material layer 400, and before etching away the material located above the interconnecting conductive layer 110 at the bottom of the through hole 210, the manufacturing method further includes oxidizing the protective material layer 400 to completely oxidize the protective material layer 400 at the bottom of the through hole 210 and partially oxidizing the protective material layer 400 on the sidewall of the through hole 210 to form a sacrificial layer 500, the sacrificial layer 500 covering at least the remaining protective material layer 400 on the sidewall of the through hole 210.
[0067] By performing an oxidation treatment on the protective material layer 400, the protective material layer 400 at the bottom of the through hole 210 is completely oxidized, and the protective material layer 400 on the side walls of the through hole 210 is partially oxidized to form a sacrificial layer 500. Subsequently, the sacrificial layer 500 can be removed using a wet etching process. Furthermore, when removing the sacrificial layer 500, the etching selectivity ratio of the sacrificial layer 500 to that of the remaining protective material layer 400 is considerably higher, making it easy to remove the sacrificial layer 500 while leaving the remaining protective material layer 400. Moreover, the protective material layer 400 at the bottom of the through hole 210 is completely oxidized, and the through hole Since the protective material layer 400 on the side wall of the hole 210 is partially oxidized, removing the sacrificial layer 500 afterward completely removes the protective material layer 400 at the bottom of the through hole 210, exposing the side wall material layer 300 at the bottom of the through hole 210. This allows for the removal of the side wall material layer 300 at the bottom of the through hole 210, removing a portion of the protective material layer 400 on the side wall of the through hole 210, while retaining the remaining protective material layer 400 to protect the side wall material layer 300 of the through hole 210, thereby protecting the side wall material layer 300 of the through hole 210 during the etching process.
[0068] Specifically, in this embodiment, the sacrificial layer 500 also covers the remaining protective material layer 400 on top of the stack layer 200.
[0069] It should be explained that in this embodiment, in the step of forming a protective material layer 400 that covers the sidewall material layer 300, due to the limitation of silicon deposition step coverage, the sidewall material layer 300 at other locations becomes thicker than the sidewall material layer 300 at the bottom location, and as the aspect ratio of the through-hole 210 increases, the difference in thickness becomes more pronounced. Therefore, in the step of performing oxidation treatment on the protective material layer 400, it is possible to completely oxidize the protective material layer 400 at the bottom of the through-hole 210 while also partially oxidizing the protective material layer 400 on the sidewall of the through-hole 210.
[0070] Furthermore, in the step of forming a protective material layer 400 that covers the sidewall material layer 300, the thickness of the protective material layer 400 at the bottom of the through-hole 210 is obtained, and then, using the formula for polycrystalline silicon consumed to oxidize polycrystalline silicon to form silicon oxide, the thickness of the silicon oxide sacrificial layer 500 at the bottom of the through-hole 210 obtained after oxidation is calculated, and based on the calculated thickness of the silicon oxide sacrificial layer 500 at the bottom of the through-hole 210, process parameters for performing oxidation on the protective material layer 400 are selected, thereby achieving fairly precise control of the oxidation thickness, completely oxidizing the protective material layer 400 at the bottom of the through-hole 210 and partially oxidizing the protective material layer 400 on the sidewall of the through-hole 210.
[0071] In this embodiment, in the step of performing an oxidation treatment on the protective material layer 400 to completely oxidize the protective material layer 400 at the bottom of the through hole 210 and partially oxidizing the protective material layer 400 on the side wall of the through hole 210 to form a sacrificial layer 500, the material of the sacrificial layer 500 is silicon oxide.
[0072] Accordingly, in this embodiment, in the step of performing oxidation treatment on the protective material layer 400, the material of the sacrificial layer 500 is the same as the material of the side wall material layer 300.
[0073] Since the material of the sacrificial layer 500 is the same as the material of the side wall material layer 300, the sacrificial layer 500 can be integrally connected with the side wall material layer 300 at the bottom of the through hole 210, thereby allowing the side wall material layer 300 at the bottom of the through hole 210 to be removed together in the subsequent step of removing the sacrificial layer 500.
[0074] In this embodiment, the step of performing an oxidation treatment on the protective material layer 400 includes performing the oxidation treatment on the protective material layer 400 by employing an in-situ steam generation (ISSG) process or a furnace tube oxidation process.
[0075] The in-situ steam generation oxidation process facilitates high-speed film deposition, offers process flexibility, and has relatively low contamination potential.
[0076] The furnace tube oxidation process is relatively stable, easy to operate, and relatively inexpensive.
[0077] Referring to Figure 11, the material located above the interconnecting conductive layer 110 at the bottom of the through-hole 210 is etched away to expose the surface of the interconnecting conductive layer 110. At the same time, the sidewall material layer 300 covering the sidewall of the through-hole 210 is designated as the sidewall layer 310, and the remaining protective material layer 400 covering the sidewall layer 310 is designated as the protective layer 410.
[0078] By etching away the material located above the interconnection conductive layer 110 at the bottom of the through-hole 210, the surface of the interconnection conductive layer 110 is exposed, preparing the subsequent electrical connection between the interconnection conductive layer 110 and the outside. At the same time, the sidewall material layer 300 covering the sidewall of the through-hole 210 is used as the sidewall layer 310 to protect the interconnection structure subsequently formed inside the through-hole 210, and the remaining protective material layer 400 covering the sidewall layer 310 is used as the protective layer 410 to protect the sidewall layer 310 during the etching process.
[0079] In this embodiment, heat treatment is performed on the protective material layer 400 before etching away the material located above the interconnecting conductive layer 110 at the bottom of the through hole 210 to realize a material phase transition process in the protective material layer 400. This helps to remove pinhole defects in the protective material layer 400 by reconstructing the crystal lattice during the conversion process from amorphous silicon to polycrystalline silicon, thereby improving the film deposition effect of the protective material layer 400. In the step of etching away the material located above the interconnecting conductive layer 110 at the bottom of the through hole 210 to expose the surface of the interconnecting conductive layer 110, the protective effect of the protective material layer 400 on the sidewall material layer 300 of the through hole 210 sidewall is improved, and damage to the sidewall material layers 300 on both sides of the bottom of the through hole 210 due to pinhole defects is avoided when removing the protective material layer 400 and the sidewall material layer 300 at the bottom of the through hole 210. By doing so, or by improving it, it is possible to improve the film quality of the sidewall layer 310, and further improve the protective effect of the sidewall layer 310 against electrical connections made by the interconnect conductive layer 110 through the bottom of the through-hole 210. In addition, by oxidizing the entire polycrystalline silicon protective material layer at the bottom of the through-hole 210, the material located above the interconnect conductive layer 110 at the bottom of the through-hole 210, i.e., silicon oxide, can be removed in one step using wet etching, which helps to improve the precision of the process dimensions for removing the protective material layer 400 and the sidewall material layer 300 at the bottom of the through-hole 210. This improves the uniformity of the dimensions of the interconnect conductive layer 110 exposed at different areas of the bottom of the through-hole 210, improves the consistency of contact resistance when the interconnect conductive layer 110 is electrically connected through the bottom of the through-hole 210, and further improves the operational performance of the semiconductor structure.
[0080] Accordingly, in this embodiment, the step of etching away the material located above the interconnecting conductive layer 110 at the bottom of the through hole 210 includes etching away the sacrificial layer 500 and the sidewall material layer 300 at the bottom of the through hole 210.
[0081] When the sacrificial layer 500 and the sidewall material layer 300 at the bottom of the through-hole 210 are etched away to expose the top surface of the interconnecting conductive layer 110, the sacrificial layer 500 and the remaining protective material layer 400 have an etching selectivity ratio, and the sidewall material layer 300 also has an etching selectivity ratio with the remaining protective material layer 400. Therefore, during the process of etching away the sacrificial layer 500 and the sidewall material layer 300 at the bottom of the through-hole 210, the top surface of the interconnecting conductive layer 110 is exposed, and at the same time, the remaining protective material layer 400 can adequately protect the sidewall material layer 300 of the through-hole 210.
[0082] In this embodiment, the sacrificial layer 500 and the sidewall material layer 300 are made of the same material, and both the sacrificial layer 500 and the sidewall material layer 300 at the bottom of the through hole 210 are etched and removed in the same process, which helps to improve process efficiency and save process costs.
[0083] In this embodiment, a wet etching process is employed to remove the sacrificial layer 500 and the side wall material layer 300 at the bottom of the through hole 210.
[0084] The wet etching process is relatively inexpensive, has simple operating steps, and can achieve a relatively high etching selectivity ratio, thus helping to reduce damage to the remaining protective material layer 400 during the process of removing the sacrificial layer 500 and the sidewall material layer 300 at the bottom of the through-hole 210.
[0085] Furthermore, by employing a wet etching process, the sacrificial layer 500 and the side wall material layer 300 at the bottom of the through-hole 210 can be easily removed cleanly, and almost no etching residue remains at the bottom of the through-hole 210.
[0086] In other embodiments, a dry etching process can be employed to remove the sacrificial layer and the sidewall material layer at the bottom of the through-hole, and after etching, the etching residue can be washed away. However, in this case, since the pinhole defects are essentially removed from the protective layer, the cleaning solution used in the washing process is unlikely to penetrate the protective layer and damage the sidewall layer, thus ensuring the film quality of the sidewall layer.
[0087] It should be explained that in some other embodiments, after heat treatment of the protective material layer, the step of oxidizing the protective material layer is omitted. Instead, the protective material layer at the bottom of the through hole and the sidewall material layer are directly etched and removed, and a dry etching process is employed for etching. After etching, the etching residue can be washed away. In this case, since the pinhole defects are essentially removed from the protective layer, the cleaning solution used in the washing process rarely penetrates the protective layer and damages the sidewall layer, thus ensuring the film quality of the sidewall layer.
[0088] Referring to Figure 12, the protective layer 410 has been removed.
[0089] Removal of the protective layer 410 is preparation for forming an interconnection structure that will be electrically connected to the interconnection conductive layer 110 within the subsequent through-hole 210.
[0090] In this embodiment, a wet etching process is used to remove the protective layer 410.
[0091] The wet etching process is relatively low-cost, has simple operating steps, and can achieve a relatively high etching selectivity ratio, thus helping to reduce damage to the remaining sidewall layer 310 and interconnect conductive layer 110 during the removal of the protective layer 410.
[0092] Figures 13 to 15 are schematic diagrams of structures corresponding to each step in another embodiment of the semiconductor structure manufacturing method of the present invention.
[0093] The same parts of this embodiment as those of the previously described embodiment will not be repeated here. The difference between this embodiment and the previously described embodiment is that a buffer layer covering the protective material layer is formed before the oxidation treatment is performed on the protective material layer.
[0094] Referring to Figure 13, the process further includes forming a buffer layer 601 that covers the protective material layer 401 before performing an oxidation treatment on the protective material layer 401.
[0095] The formation of a buffer layer 601 covering the protective material layer 401 is used in the step of subsequently performing an oxidation treatment on the protective material layer 401 in order to slow down the rate of the oxidation treatment.
[0096] In response to this, in this embodiment, in the step of forming a buffer layer 601 that covers the protective material layer 401, the buffer layer 601 covers the protective material layer 401 on the side walls and bottom of the through hole 211 and the protective material layer 401 on the top of the stack layer 201.
[0097] In this embodiment, in the step of forming a buffer layer 601 that covers the protective material layer 401, the material of the buffer layer 601 includes any one of silicon oxide, silicon nitride, and silicon oxynitride.
[0098] A buffer layer 601 formed by employing any one of silicon dioxide, silicon nitride, and silicon oxynitride can achieve an excellent oxidation buffering effect.
[0099] In this embodiment, in the step of forming a buffer layer 601 that covers the protective material layer 401, the material of the buffer layer 601 is the same as the material of the sacrificial layer.
[0100] Since the material of the buffer layer 601 is the same as the material of the sacrificial layer that is formed later, when the sacrificial layer is removed afterward, the buffer layer 601 can also be removed at the same time.
[0101] As an example, in this embodiment, in the step of forming a buffer layer 601 that covers the protective material layer 401, the material of the buffer layer 601 is silicon oxide, and the material of the sacrificial layer formed after oxidation treatment of the protective material layer 401 is also silicon oxide. Since the materials of the buffer layer 601 and the sacrificial layer are the same, they can be connected as an integrated structure, and thereafter, the buffer layer 601 can be removed together with the sacrificial layer at the same time.
[0102] In this embodiment, a buffer layer 601 covering the protective material layer 401 is formed by employing an atomic layer deposition process.
[0103] The buffer layer 601 formed by employing an atomic layer deposition process has good thickness uniformity and good step coverage capability, and the protective material layer 401 covering the side walls and bottom of the through hole 211 and the protective material layer 401 on the top of the stack layer 201 can be appropriately conformally coated onto the buffer layer 601.
[0104] Referring to Figure 14, after forming a buffer layer 601 that covers the protective material layer 401, the protective material layer 401 is subjected to an oxidation treatment to completely oxidize the protective material layer 401 at the bottom of the through hole 211, and partially oxidize the protective material layer 401 on the side walls of the through hole 211 to form a sacrificial layer 501.
[0105] During the oxidation treatment process for the protective material layer 401, the separation buffer of the buffer layer 601 slows down the oxidation diffusion rate, which helps to control the oxidation process parameters more precisely. This allows for more precise control of the oxidation thickness, resulting in complete oxidation of the protective material layer 401 at the bottom of the through-hole 211 and partial oxidation of the protective material layer 401 on the side walls of the through-hole 211.
[0106] Referring to Figure 15, the step of etching away the sacrificial layer 501 and the sidewall material layer 311 at the bottom of the through hole 211 further includes removing the buffer layer 601.
[0107] Removing the buffer layer 601 makes it easier to expose the top surface of the interconnection conductive layer 111 in the substrate 101.
[0108] In this embodiment, the material of the buffer layer 601 is the same as the material of the sacrificial layer 501. Accordingly, the sacrificial layer 501 and the buffer layer 601 are removed in the same process, which improves process efficiency and helps save process costs.
[0109] Figure 16 is a schematic diagram of the structure corresponding to each step in yet another embodiment of the method for manufacturing a semiconductor structure of the present invention.
[0110] The same parts of this embodiment as those of the previously described embodiment will not be repeated here. The difference between this embodiment and the previously described embodiment is that a sacrificial layer is formed by forming a buffer layer that covers the protective material layer.
[0111] Referring to Figure 16, the step of performing an oxidation treatment on the protective material layer 402 includes forming a buffer layer 602 made of an oxide material that covers the protective material layer 402, and simultaneously diffusing oxidation from the buffer layer 602 into the protective material layer 402, thereby completely oxidizing the protective material layer 402 at the bottom of the through hole 212 and partially oxidizing the protective material layer 402 on the side walls of the through hole 212 to form a sacrificial layer 502.
[0112] If the buffer layer 602 is made of an oxide material, the amount of oxygen taken in during the process of forming the buffer layer 602 that covers the protective material layer 402 can be appropriately increased to form the buffer layer 602 and at the same time diffuse oxidation into the protective material layer 402, thereby oxidizing all of the protective material layer 402 at the bottom of the through hole 212 and a portion of the protective material layer 402 on the side walls of the through hole 212 to form a sacrificial layer 502.
[0113] In this embodiment, a buffer layer 602 covering the protective material layer 402 is formed at the same time as a sacrificial layer 502 is formed, which helps to simplify the process flow, improve process efficiency, and save process costs.
[0114] As an example, in this embodiment, a buffer layer 602 is formed to cover the protective material layer 402, and the material of the buffer layer 602 is silicon oxide.
[0115] It should be explained that in this embodiment, after forming the buffer layer 602 that covers the protective material layer 402, it is not necessary to perform the step of oxidizing the protective material layer 402 using an in-situ steam generation oxidation process or a furnace tube oxidation process, or the step of oxidizing the protective material layer 402 using an in-situ steam generation oxidation process or a furnace tube oxidation process may be performed immediately afterward.
[0116] Although disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the scope of protection of the present invention must be limited to the scope defined in the claims. [Explanation of symbols]
[0117] Circuit boards 10, 100, 101 Interconnection conductive layers 11, 110, 111 Stack layers 20, 200, 201 Through holes 21, 210, 211, 212 Sidewall material layer 30, 300, 311 Sidewall layers 31, 310 Protective material layer 40, 400, 401, 402 Protective layer 41, 410 Sacrificial layers 500, 501, 502 Buffer layers 601, 602
Claims
1. A method for manufacturing a semiconductor structure, To provide a substrate in which an interconnection conductive layer is embedded, wherein the substrate exposes the surface of the interconnection conductive layer, a stack layer covering the substrate is formed on the substrate, and through holes are formed in the stack layer that penetrate the stack layer and expose the surface of the interconnection conductive layer. Form a side wall material layer made of silicon oxide that covers at least the side walls and bottom of the through hole, A protective material layer made of amorphous silicon is formed to cover the aforementioned sidewall material layer, By performing heat treatment on the protective material layer, a material phase transition process is realized in the protective material layer. The material located above the interconnecting conductive layer at the bottom of the through hole is etched away to expose the surface of the interconnecting conductive layer, and at the same time, the sidewall material layer covering the sidewall of the through hole is made into a sidewall layer, and the remaining protective material layer covering the sidewall layer is made into a protective layer. Removing the aforementioned protective layer, A method for manufacturing a semiconductor structure, characterized by including the following:
2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, in the step of heat-treating the protective material layer, the material of the protective material layer is converted from amorphous silicon to polycrystalline silicon.
3. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, in the step of performing a heat treatment on the protective material layer, the heat treatment includes a rapid thermal process.
4. A method for manufacturing a semiconductor structure according to claim 1, wherein, after heat treatment of the protective material layer, and before etching off the material located above the interconnecting conductive layer at the bottom of the through hole, the manufacturing method further includes oxidizing the protective material layer to completely oxidize the protective material layer at the bottom of the through hole and partially oxidizing the protective material layer on the side wall of the through hole to form a sacrificial layer, wherein the sacrificial layer covers at least the remaining protective material layer on the side wall of the through hole.
5. The method for manufacturing a semiconductor structure according to claim 4, characterized in that the step of etching away the material located above the interconnecting conductive layer at the bottom of the through hole includes etching away the sacrificial layer and the side wall material layer at the bottom of the through hole.
6. In the step of performing an oxidation treatment on the protective material layer, the material of the sacrificial layer is the same as the material of the side wall material layer. A method for manufacturing a semiconductor structure according to claim 5, characterized in that the sacrificial layer and the side wall material layer at the bottom of the through hole are etched off in the same process.
7. The method for manufacturing a semiconductor structure according to claim 4, characterized in that the step of performing an oxidation treatment on the protective material layer includes performing the oxidation treatment on the protective material layer by employing an in-situ steam generation oxidation process or a furnace tube oxidation process.
8. A method for manufacturing a semiconductor structure according to claim 5, characterized in that a wet etching process is used to remove the sacrificial layer and the side wall material layer at the bottom of the through hole.
9. The method further includes forming a buffer layer that covers the protective material layer before performing an oxidation treatment on the protective material layer, The method for manufacturing a semiconductor structure according to claim 5, characterized in that the step of etching away the sacrificial layer and the side wall material layer at the bottom of the through hole further includes removing the buffer layer.
10. The method for manufacturing a semiconductor structure according to claim 9, characterized in that, in the step of forming a buffer layer covering the protective material layer, the material of the buffer layer includes any one of silicon oxide, silicon nitride, and silicon oxynitride.
11. The step of performing an oxidation treatment on the protective material layer includes forming a buffer layer made of an oxide material that covers the protective material layer, and simultaneously with the formation of the buffer layer, diffusing the oxidation from the buffer layer into the protective material layer to completely oxidize the protective material layer at the bottom of the through hole and partially oxidizing the protective material layer on the side wall of the through hole to form the sacrificial layer. The method for manufacturing a semiconductor structure according to claim 5, characterized in that the step of etching away the sacrificial layer and the side wall material layer at the bottom of the through hole further includes removing the buffer layer.
12. A method for manufacturing a semiconductor structure according to claim 9 or 11, characterized in that a buffer layer covering the protective material layer is formed by employing an atomic layer deposition process.
13. In the step of forming a buffer layer that covers the protective material layer, the material of the buffer layer is the same as the material of the sacrificial layer. A method for manufacturing a semiconductor structure according to claim 9 or 11, characterized in that the sacrificial layer and the buffer layer are removed in the same process.
14. A method for manufacturing a semiconductor structure according to claim 1, characterized in that an atomic layer deposition process is employed to form a sidewall material layer that covers at least the sidewall and bottom of the through-hole.
15. A method for manufacturing a semiconductor structure according to claim 1, characterized in that a protective material layer covering the sidewall material layer is formed by employing a chemical vapor deposition process.
16. A method for manufacturing a semiconductor structure according to claim 1, characterized in that the protective layer is removed by employing a wet etching process.