Phase change material device and method for forming the same

Abstract

This invention provides a method for manufacturing phase-change memory (PCM) devices without using a chemical mechanical polishing (CMP) process. [Solution] A phase-change memory device can be provided by forming a bottom electrode, a dielectric material layer, and via openings extending through the dielectric material layer, such that the top segment of the bottom electrode is exposed directly below the via openings, forming tubular dielectric spacers in the peripheral region of the via openings, depositing a continuous layer laminate including a heater liner layer, a phase-change material layer containing a phase-change material, and a top electrode material layer on the dielectric material layer and the tubular dielectric spacers, and patterning the continuous layer laminate into a laminate including a heater liner, a phase-change material portion, and a top electrode.

Description

[Background technology]

[0001] Phase-change material (PCM) devices can be used in memory-based computing applications due to their scalability and non-volatility. However, the manufacturing process sequence for PCM devices requires many processing steps. One time-consuming and costly process involves the formation of bottom electrodes and heater elements using chemical mechanical polishing processes. [Overview of the Initiative] [Problems that the invention aims to solve]

[0002] Phase-change memory (PCM) devices can be used in a variety of applications due to their scalability and non-volatility. However, the complexity of the manufacturing process for PCM devices can present challenges. For example, the manufacturing of heater elements is typically carried out using a chemical mechanical polishing (CMP) process. The CMP process not only requires expensive equipment and consumables but also demands strict process control, which can lead to increased production time and / or yield losses. [Means for solving the problem]

[0003] The present invention provides a method for forming a device structure in some embodiments. The method includes forming a bottom electrode, a dielectric material layer, and via openings extending through the dielectric material layer so that the top segment of the bottom electrode is exposed directly below the via openings; forming tubular dielectric spacers in the peripheral region of the via openings so that the central portion of the top segment is exposed below a void laterally surrounded by the tubular dielectric spacers; depositing a continuous layer laminate including a heater liner layer, a phase change material layer containing a phase change material, and a top electrode material layer on top of the dielectric material layer and the tubular dielectric spacers; and patterning the continuous layer laminate into a laminate including a heater liner, a phase change material portion, and a top electrode.

[0004] The present invention provides a method for forming a device structure in some embodiments. The method includes forming a bottom electrode, a dielectric material layer, and via openings extending through the dielectric material layer so that the top segment of the bottom electrode is exposed directly below the via openings; depositing a heater liner layer within a portion of the volume of the via openings and on the dielectric material layer; vertically recessing the horizontally extended portion of the heater liner layer; depositing a phase change material layer containing a phase change material and a top electrode material layer on the horizontally extended portion of the heater liner layer; and patterning the top electrode material layer, the phase change material layer, and the heater liner layer into a laminate including a heater liner, a phase change material portion, and a top electrode.

[0005] The present invention provides a device structure in several embodiments. The device structure includes a tubular dielectric spacer located within the range of via openings in a dielectric material layer; a heater liner including a vertically stretched portion laterally surrounded by the tubular dielectric spacer and a horizontally stretched portion overlapping the top surface segment of the dielectric material layer; a phase change material portion including a phase change material in contact with the top surface of the heater liner; and a top electrode in contact with the top surface of the phase change material portion. [Effects of the Invention]

[0006] Various embodiments of the present invention provide a set of manufacturing steps for manufacturing phase-change memory (PCM) devices while reducing the complexity and processing costs associated with manufacturing such devices. Specifically, the disclosed set of manufacturing steps provides a method for manufacturing PCM devices without using a CMP process. Specifically, a heater liner in contact with the bottom surface of the phase-change material portion is used to provide a dual function of heater element and heater liner for the phase-change material portion. The heater liner can be formed by providing a narrow via opening in a dielectric material layer, and then filling the entire or peripheral region of the via opening with a heater liner layer, and subsequently patterning the heater liner layer. The phase-change material layer and the top electrode material layer can be deposited on top of the heater material layer, and the heater liner layer, phase-change material layer, and top electrode material layer can be patterned using the same masking pattern. The heater liner includes a vertically extended portion formed in the via opening and a horizontally extended portion overlapping the dielectric material layer. The sidewall liner is formed on the laminate of the heater liner, phase change material, and top electrode to provide a phase change memory cell. Therefore, the phase change memory cell can be manufactured without using the costly CMP process. [Brief explanation of the drawing]

[0007] The aspects of the present invention will be best understood from the following detailed description in conjunction with the accompanying drawings. Note that, in accordance with standard industry practice, various features are not depicted to scale. Dimensions of various features may be arbitrarily enlarged or reduced for clarity in the description. [Figure 1] This is a vertical cross-sectional view of an intermediate structure of a first embodiment, according to one embodiment of the present invention, which includes a field-effect transistor, a metal wiring structure, and a dielectric material layer after its formation. [Figure 2] This is a vertical cross-sectional view of an intermediate structure of the first embodiment after the formation of via openings penetrating the dielectric material layer, according to one embodiment of the present invention. [Figure 3]This is a vertical cross-sectional view of an intermediate structure of a first embodiment after the formation of a dielectric spacer material layer, according to one embodiment of the present invention. [Figure 4] This is a vertical cross-sectional view of an intermediate structure of a first embodiment after the formation of a tubular dielectric spacer, according to one embodiment of the present invention. [Figure 5] This is a vertical cross-sectional view of an intermediate structure of a first embodiment after the formation of a continuous layer laminate including a heater liner layer, a phase change material layer, and a top electrode material layer, according to one embodiment of the present invention. [Figure 6] This is a vertical cross-sectional view of an intermediate structure of the first embodiment, after patterning a continuous layer laminate, which includes an in-process heater liner, an in-process phase change material portion, and an in-process top electrode, according to one embodiment of the present invention. [Figure 7] This is a vertical cross-sectional view of an intermediate structure of a first embodiment after the formation of a sidewall liner layer, according to one embodiment of the present invention. [Figure 8] This is a vertical cross-sectional view of an intermediate structure of a first embodiment after the formation of an in-process sidewall liner, according to one embodiment of the present invention. [Figure 9] This is a vertical cross-sectional view of an intermediate structure of the first embodiment, after patterning an in-process laminate, which includes a heater liner, a phase change material portion, and a top electrode, with the in-process sidewall liner being patterned as a sidewall liner, according to one embodiment of the present invention. [Figure 10] This is a vertical cross-sectional view of the structure of the first embodiment after the removal of the patterned etching mask layer, according to one embodiment of the present invention. [Figure 11A] Figures 8 to 10 show one of the sequential top views of the region of the first configuration of the first embodiment structure during the processing steps. [Figure 11B] Figures 8 to 10 show one of the sequential top views of the region of the first configuration of the first embodiment structure during the processing steps. [Figure 11C] Figures 8 to 10 show one of the sequential top views of the region of the first configuration of the first embodiment structure during the processing steps. [Figure 12A]Shows one of the continuous top views of the region of the second configuration of the embodiment structure during the processing steps of FIGS. 8 to 10. [Figure 12B] Shows one of the continuous top views of the region of the second configuration of the embodiment structure during the processing steps of FIGS. 8 to 10. [Figure 12C] Shows one of the continuous top views of the region of the second configuration of the embodiment structure during the processing steps of FIGS. 8 to 10. [Figure 13A] Shows one of the continuous top views of the region of the third configuration of the embodiment structure during the processing steps of FIGS. 8 to 10. [Figure 13B] Shows one of the continuous top views of the region of the third configuration of the embodiment structure during the processing steps of FIGS. 8 to 10. [Figure 13C] Shows one of the continuous top views of the region of the third configuration of the embodiment structure during the processing steps of FIGS. 8 to 10. [Figure 14] Shows the top view of the region of the fourth configuration of the embodiment structure after the processing step of FIG. 8. [Figure 15] Is a vertical cross-sectional view of the first embodiment structure after forming a sealing dielectric layer and an additional metal wiring structure according to an embodiment of the present invention. [Figure 16A] Is one of the various configurations of a phase change memory cell in various programmed resistance states according to an embodiment of the present invention. [Figure 16B] Is one of the various configurations of a phase change memory cell in various programmed resistance states according to an embodiment of the present invention. [Figure 16C] Is one of the various configurations of a phase change memory cell in various programmed resistance states according to an embodiment of the present invention. [Figure 16D] Is one of the various configurations of a phase change memory cell in various programmed resistance states according to an embodiment of the present invention. [Figure 17] Is a vertical cross-sectional view of the intermediate structure of the second embodiment after depositing a heater liner layer according to an embodiment of the present invention. [Figure 18]This is a vertical cross-sectional view of the intermediate structure of the second embodiment after the heater liner layer has been vertically recessed according to an embodiment of the present invention. [Figure 19] This is a vertical cross-sectional view of the intermediate structure of the second embodiment after the deposition of the phase change material layer and the top electrode material layer according to an embodiment of the present invention. [Figure 20] This is a vertical cross-sectional view of an intermediate structure of a second embodiment after forming an in-process laminate including an in-process heater liner, an in-process phase change material portion, and an in-process top electrode, respectively, according to an embodiment of the present invention. [Figure 21] This is a vertical cross-sectional view of the second embodiment structure after forming the sealing dielectric layer and additional metal wiring structure according to an embodiment of the present invention. [Figure 22] This is a vertical cross-sectional view of the intermediate structure of the third embodiment after the heater liner layer has been deposited, according to an embodiment of the present invention. [Figure 23] This is a vertical cross-sectional view of the intermediate structure of the third embodiment after the deposition of the phase change material layer and the top electrode material layer according to an embodiment of the present invention. [Figure 24] This is a vertical cross-sectional view of an intermediate structure of a third embodiment after forming an in-process laminate including an in-process heater liner, an in-process phase change material portion, and an in-process top electrode, respectively, according to an embodiment of the present invention. [Figure 25] This is a vertical cross-sectional view of the third embodiment structure after forming the sealing dielectric layer and additional metal wiring structure according to an embodiment of the present invention. [Figure 26] This is a first flowchart showing a general process for manufacturing a device structure according to embodiments of the present invention. [Figure 27] This is a second flowchart showing a general process for manufacturing a device structure according to an embodiment of the present invention. [Modes for carrying out the invention]

[0008] The following disclosure provides many different embodiments or examples for implementing various features of the subject matter provided. Specific examples of components and arrangements are described below to clarify the invention. These are merely examples and not limiting. The drawings are not drawn to scale. Elements with the same reference number refer to the same element and are presumed to have the same material composition and the same thickness range unless expressly indicated otherwise. All features of the original embodiment are presumed to be present in any derived embodiment unless expressly disclosed otherwise. Thus, features described in the drawings and / or specification with reference to relevant embodiments provide support for the features in the embodiment. Multiple instances of the described elements are explicitly intended to be repeated embodiments unless expressly indicated otherwise. Non-essential elements are explicitly intended to be omitted if they are known in the art even without such embodiments being expressly disclosed.

[0009] Furthermore, spatial relative terms such as “beneath,” “below,” “lower,” “above,” and “upper” may be used herein to facilitate description of geometric features between elements as shown in the drawings. A first physical element being “embedded” in a second physical element means that the entire volume of the first element lies within the scope of a virtual volume defined by a set of virtual surfaces that has the smallest total surface area among all virtual surface sets, including the entire outer surface of the second element, and is topologically homeomorphic to a sphere. Such a set of virtual surfaces, if an opening exists on the outer surface, covers each opening with the smallest surface segment among all possible open surface segments. Spatial relative terms are intended to encompass different orientations of a device in use or operation, in addition to the orientation depicted in the drawings. The device may be oriented differently (rotated 90 degrees or to other orientations), and the spatial relative descriptors used herein may be interpreted accordingly. Unless explicitly stated otherwise, each element with the same reference number is presumed to have the same material composition and thickness within the same thickness range.

[0010] The tubular dielectric spacer may be formed within the via opening before the heater liner is formed. In one embodiment, the void within the tubular dielectric spacer may be narrow enough to be completely filled during the deposition of the heater liner layer. In another embodiment, the void within the tubular dielectric spacer may be wider than twice the target thickness of the horizontally stretched portion of the heater liner that is later formed, and a combination of over-deposition and recess etching may be used to fill the void within the via opening while providing the target thickness to the horizontally stretched portion of the heater liner. In yet another embodiment, the void within the tubular dielectric spacer may be wider than twice the target thickness of the heater liner, and the remaining portion of the void may be filled with the vertically stretched portion of the phase change material. Various embodiments of the present invention will be described with reference to the accompanying drawings.

[0011] Referring to Figure 1, the structure of the first embodiment according to the present invention is illustrated. The structure of the first embodiment includes a substrate 8, which may be a semiconductor substrate such as a commercially available silicon substrate. The substrate 8 may include a semiconductor material layer 9 at least on its upper surface. The semiconductor material layer 9 may be the surface portion of a bulk semiconductor substrate, or it may be the top semiconductor layer of a semiconductor on-insulator (SOI) substrate. In one embodiment, the semiconductor material layer 9 includes a single-crystal semiconductor material such as single-crystal silicon. In one embodiment, the substrate 8 may include a single-crystal silicon substrate containing a single-crystal silicon material.

[0012] A shallow trench isolation structure 720 containing a dielectric material such as silicon oxide may be formed on top of the semiconductor material layer 9. Appropriately doped semiconductor wells, such as p-type wells and n-type wells, may be formed within the range of each region laterally enclosed by a portion of the shallow trench isolation structure 720.

[0013] The semiconductor device 700 may be formed on a semiconductor material layer 9. The semiconductor device 700 may include complementary metal-oxide-semiconductor (CMOS) transistors and optionally additional semiconductor devices (such as resistors, diodes, and capacitor structures). The semiconductor device 700 may include a programming transistor 701 formed in the memory array region 100 and a peripheral transistor 702 formed in the peripheral region 300. Each field-effect transistor (701, 702) may include a source region, a drain region, a channel region, a gate dielectric, and a gate electrode. In one embodiment, the channel region may include a portion of the semiconductor material layer 9 and may include a single-crystal semiconductor material. Each programming transistor 701 may be configured to provide a set of programming pulses to each phase-change memory cell formed later. The peripheral transistor 702 may be formed as a component of a peripheral circuit that controls the operation of the programming transistor 701 and interfaces with an input / output (I / O) circuit (not shown).

[0014] In one embodiment, the substrate 8 may include a single-crystal silicon substrate, and the field-effect transistors (701, 702) may include portions of the single-crystal silicon substrate as semiconductor channels. As used herein, the “semiconducting” element is defined as 1.0 × 10⁻¹⁶ -6 ~1.0×10 5 This refers to an element having an electrical conductivity in the range of S / cm. As used herein, "semiconductor material" means having an electrical conductivity of 1.0 × 10⁻⁶ in the absence of an electrical dopant. -6 ~1.0×10 5 It has an electrical conductivity in the range of S / cm, and can be appropriately doped with an electrical dopant to reach 1.0 to 1.0 × 10⁻⁶. 5 This refers to a material that can produce doped materials with electrical conductivity in the range of S / cm.

[0015] Various metal wiring structures may be formed within the range of dielectric material layers later formed on the substrate 8 and the semiconductor device. In exemplary embodiments, the dielectric material layers may include, for example, a first dielectric material layer 601 (sometimes called a contact-level dielectric material layer 601) which may be a layer surrounding a contact structure connected to a source and a drain, a first wiring layer dielectric material layer 610, a second wiring layer dielectric material layer 620, a third wiring layer dielectric material layer 630, and a fourth wiring layer dielectric material layer 640. The metal wiring structure may include a device contact via structure 612 formed within the first dielectric material layer 601 and in contact with each component of the semiconductor device 700, a first metal wiring structure 618 formed within the first wiring layer dielectric material layer 610, a first metal via structure 622 formed below the second wiring layer dielectric material layer 620, a second metal wiring structure 628 formed above the second wiring layer dielectric material layer 620, a second metal via structure 632 formed below the third wiring layer dielectric material layer 630, and a third metal wiring structure 638 formed above the third wiring layer dielectric material layer 630. An additional dielectric material layer, referred to herein as the lower fourth wiring layer dielectric material layer 641, may be formed on the third wiring layer dielectric material layer 630.

[0016] Each dielectric material layer (601, 610, 620, 630, 641) may contain dielectric materials such as undoped silicate glass, doped silicate glass, organosilicate glass, amorphous fluorinated carbon, porous deformed forms thereof, or combinations thereof. Each metal wiring structure (612, 618, 622, 628, 632, 638) may contain at least one conductive material, which may be a combination of a metal liner (such as a metal nitride or metal carbide) and a metal filler. Each metal liner may contain TiN, TaN, WN, TiC, TaC, and WC, and each metal filler portion may contain W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and / or combinations thereof. In one embodiment, the first metal via structure 622 and the second metal wiring structure 628 may be formed as integrated wiring and via structures by a dual damascene process. In general, any adjacent set of metal wiring structures (628, 638) and at least one lower metal via structure (622, 632) may be formed as an integrated wiring and via structure.

[0017] Generally, semiconductor devices (such as field-effect transistors (701, 702)) may be formed on a substrate 8, and metal wiring structures (612, 618, 622, 628, 632, 638) and dielectric material layers (601, 610, 620, 630, 641) may be formed on top of the semiconductor device. The metal wiring structures (612, 618, 622, 628, 632, 638) may be formed within the dielectric material layers (601, 610, 620, 630, 641) and may be electrically connected to the semiconductor device.

[0018] A subset of metal wiring structures (612, 618, 622, 628, 632, 638) located within the dielectric material layers below the uppermost dielectric layer may include bottom electrodes 38 of subsequently formed phase-change memory cells (formed as part of the metal wiring structure 638). In exemplary embodiments, a subset of the third metal wiring structure 638 may include a two-dimensional array of bottom electrodes 38 for subsequently formed arrays of phase-change memory cells. The bottom electrodes 38 may be formed within the dielectric material layers (e.g., third wiring layer dielectric material layer 630) located below the uppermost dielectric material layer (e.g., lower fourth wiring layer dielectric material layer 641). The bottom electrodes 38 include at least one metal having high electrical conductivity. For example, the bottom electrodes 38 may include a metal portion containing copper, aluminum, or tungsten. Optionally, the bottom electrodes 38 may include a metal barrier liner containing a metal barrier material such as TiN, TaN, WN, and / or MoN.

[0019] In summary, the programming transistor 701 may be formed on the substrate 8. The metal wiring structures (612, 618, 622, 628, 632, 638) formed within the wiring layer dielectric material layers (601, 610, 620, 630, 641) may be formed on top of the programming transistor 701. The metal wiring structures (612, 618, 622, 628, 632, 638) may be configured to be electrically connected to the heater elements of the subsequently formed phase change memory cells.

[0020] According to one aspect of the present invention, the programming transistor 701 may be configured to program each corresponding phase-change memory cell to at least two different resistance states, preferably at least three different resistance states, and more preferably at least four different resistance states. Programming each phase-change memory cell to a different resistance state may be performed by selecting a pulse pattern from a set of pre-programmed pulse patterns that each programming transistor 701 can apply. The pulse patterns may differ from each other in terms of the duration of the pulse pattern and the peak voltage of the pulse pattern. In one embodiment, the total number of resistance states that a phase-change memory cell can program is in the range of 2 to 64, for example, 3 to 16 and / or 4 to 8, but more resistance states may be programmed as needed by changing the pulse patterns generated from each programming transistor 701.

[0021] Referring to Figure 2, the via openings 41 may be formed through the uppermost dielectric material layer (e.g., the lower fourth wiring layer dielectric material layer 641). Each via opening 41 may be formed on each of the underlying metal wiring structures (e.g., a subset of the third metal wiring structure 638), thereby physically exposing the top segment of the underlying metal wiring structure. The dielectric material layer on which the via openings 41 are formed includes a heat-resistant dielectric material such as undoped silicate glass or doped silicate glass. The thickness of the dielectric material layer may be in the range of 200 to 1,000 nm, but smaller or larger thicknesses may also be used. The lateral dimension (e.g., diameter) of the bottom of each via opening 41 may be in the range of 50 to 400 nm, but smaller or larger lateral dimensions may also be used.

[0022] Generally, the bottom electrode 38, the dielectric material layer (e.g., the lower fourth wiring layer dielectric material layer 641), and the via openings 41 extending through the dielectric material layer may be formed such that the top surface segment of each bottom electrode 38 is exposed directly below each via opening 41.

[0023] Referring to Figure 3, the dielectric spacer material may be conformally deposited within the peripheral region of the via opening 41 and on the dielectric material layer surrounding the via opening 41 (e.g., the lower fourth wiring layer dielectric material layer 641) to form the dielectric spacer material layer 42L. The dielectric spacer material of the dielectric spacer material layer 42L may have a thermal conductivity of less than 40 W / m·K. For example, the dielectric spacer material layer 42L may include silicon oxide, silicon nitride, aluminum oxide, silicon carbonitride, or a combination thereof. In one embodiment, the dielectric spacer material of the dielectric spacer material layer 42L may be composed of silicon oxide having a thermal conductivity substantially in the range of 1.1 to 1.4 W / m·K. Generally, the dielectric spacer material layer 42L may have the same material composition as the dielectric material layer to which the via opening 41 extends vertically, or it may have a different material composition. The dielectric spacer material layer 42L may be deposited by a conformal deposition process such as a chemical vapor deposition process. The top surface of the dielectric spacer material layer 42L may include an annular convex segment formed around the top edge of the via opening 41 due to the isotropic nature of the deposition process that forms the dielectric spacer material layer 42L.

[0024] According to one aspect of the present invention, the thickness of the dielectric spacer material layer 42L is selected such that the difference between the width of the bottom of each via opening 41 and twice the thickness of the dielectric spacer material layer 42L falls within the target range of the width of the bottom of each vertical extension of the subsequently formed heater liner layer. In an exemplary embodiment, if the width of the bottom of each via opening 41 is in the range of 50 to 400 nm and the target range of the width of the bottom of each vertical extension of the subsequently formed heater liner layer is in the range of 20 to 100 nm, the thickness of the dielectric spacer material layer 42L may be in the range of 15 to 150 nm, for example, in the range of 30 to 80 nm, but smaller or larger thicknesses may also be used.

[0025] Referring to Figure 4, an anisotropic etching process may be performed to anisotropically etch the horizontally stretched portions of the dielectric spacer material layer 42L. Each remaining vertically stretched portion of the dielectric spacer material layer 42L remaining in the peripheral region of each via opening 41 constitutes a tubular dielectric spacer 42 having a tubular structure. According to one aspect of the present invention, the central portion of the top surface segment of the lower bottom electrode 38 may be exposed below each void laterally surrounded by each tubular dielectric spacer 42.

[0026] Each tubular dielectric spacer 42 may include an outer cylindrical sidewall having an outer taper angle in the range of 0 to 15 degrees with respect to the vertical, for example, in the range of 1 to 5 degrees. As used herein, “cylindrical sidewall” means any sidewall that has a closed perimeter in a horizontal section view and extends perpendicularly with or without a taper angle with respect to the vertical. Each tubular dielectric spacer 42 may include an inner cylindrical sidewall having an inner taper angle in the range of 0 to 15 degrees with respect to the vertical, for example, in the range of 1 to 5 degrees. The inner taper angle may be the same as or substantially the same as the outer taper angle. In one embodiment, each tubular dielectric spacer 42 includes an annular convex segment adjacent to the top periphery of the inner cylindrical sidewall of the via opening 41.

[0027] Referring to Figure 5, the metal heater material may be deposited in a void laterally surrounded by a tubular dielectric spacer 42, and on top of a dielectric material layer (such as the lower fourth wiring layer dielectric material layer 641) on which the via openings 41 extend vertically. The deposited metal heater material forms a heater liner layer 52L, which is a liner layer containing the metal heater material. The metal heater material has higher electrical conductivity than the metal material of the bottom electrode 38. In one embodiment, the heater liner layer 52L includes a first metal nitride material, which may be a stoichiometric or stoichiometrically close metal nitride material. For example, the heater liner layer 52L may include TaN, TiN, WN, and / or MoN. In one embodiment, the electrical conductivity of the metal material of the heater liner layer 52L is 1.0 × 10⁻¹⁰ 3 ~1.0×10 5The temperature may be in the range of S / cm. The metal heater material may be deposited by chemical vapor deposition or physical vapor deposition. In one embodiment, the metal heater material may include stoichiometric or nearly stoichiometric metal nitride materials, such as stoichiometric or nearly stoichiometric TiN, TaN, WN, and / or MoN.

[0028] In one embodiment, the metal heater material for the heater liner layer 52L may be deposited using a conformal deposition process such as chemical vapor deposition. According to one aspect of the present invention, the duration of the deposition process for depositing the heater liner layer 52L may be selected so that the major portion and / or all of the volume of each void within the range of the via openings 41 is filled with the deposited material for the heater liner layer 52L. The thickness of the horizontally stretched portion of the heater liner layer 52L is selected so that the patterned portion of the heater liner layer 52L provides electrical resistance during the operation of the subsequently formed phase change memory cell. The thickness of the horizontally stretched portion of the heater liner layer 52L deposited on the top surface of the dielectric material layer over which the via openings 41 extend vertically may be in the range of 10 to 80 nm, for example, in the range of 20 to 50 nm, but smaller or larger thicknesses may also be used.

[0029] Generally, the heater liner layer 52L may be deposited within a portion of the volume of each via opening 41 penetrating the dielectric material layer (such as the lower fourth wiring layer dielectric material layer 641) and on the horizontal top surface of the dielectric material layer. During the deposition of the heater liner layer 52L, the heater liner layer 52L includes a planar horizontal surface segment PHSS that overlaps the dielectric material layer, and further includes an annular convex segment ACSS adjacent to the periphery of each opening within the planar horizontal surface segment PHSS and overlapping each via opening 41. The formation of the annular convex segment ACSS is due to the isotropic nature of the deposition process used to deposit the heater liner layer 52L.

[0030] The heater liner layer 52L includes vertically stretched portions deposited in the voids within the tubular dielectric spacer 42 and horizontally stretched portions deposited on the top surface of the dielectric material layer (such as the lower fourth wiring layer dielectric material layer 641). The heater liner layer 52L at least partially fills each void within the via opening 41. In one embodiment, the maximum width of each void (such as the width in the horizontal plane including the top surface of the dielectric material layer) may be less than half (1 / 2) of the thickness of the heater liner layer 52L measured in the horizontally stretched portion of the heater liner layer 52L overlapping the dielectric material layer. In one embodiment, a vertical stretch seam S is formed at the center of each void filled by each vertical stretch of the heater liner layer 52L. Each vertical stretch seam S may be formed at the center of each vertical stretch of the heater liner layer 52L. In one embodiment, the heater liner layer 52L is deposited on each physically exposed central portion of the top surface segment of the bottom electrode 38.

[0031] The phase change material layer 54L may be deposited on the entire physically exposed surface of the heater liner layer 52L. Thus, the phase change material layer 54L is deposited directly on the planar horizontal surface segment PHSS of the heater liner layer 52L that overlaps with a horizontal plane including the top surface of the dielectric material layer (such as the lower fourth wiring layer dielectric material layer 641), and is also deposited directly on each annular convex segment ACSS of the heater liner layer 52L.

[0032] The phase change material layer 54L contains a phase change material and / or consists essentially of a phase change material. As used herein, "phase change material" refers to a material having at least two different phases that provide different resistivity. A phase change material (PCM) can be used to store information by utilizing different resistivity states corresponding to different phases of the material. The different phases may include an amorphous state having a high resistivity and a crystalline state having a low resistivity (i.e., a resistivity lower than the amorphous state). The transition between the amorphous state and the crystalline state can be induced by controlling the cooling rate after applying an electrical pulse to make the phase change material amorphous in the first part of the programming process. The second part of the programming process includes controlling the cooling rate of the phase change material. In embodiments where rapid cooling occurs, the phase change material can be cooled to an amorphous high resistivity state. In embodiments where slow cooling occurs, the phase change material can be cooled to a crystalline low resistivity state.

[0033] Exemplary phase change materials include, but are not limited to, germanium antimony tellurium (GST) compounds such as Ge2Sb2Te5 or GeSb2Te4, germanium antimony compounds, indium germanium tellurium compounds, aluminum selenium tellurium compounds, indium selenium tellurium compounds, and aluminum indium selenium tellurium compounds. In one embodiment, the phase change material of the phase change material layer 54L may include a doped GST compound such as N-doped GST, Si-doped GST, C-doped GST, Ge-doped GST, Ru-doped GST, or Al-doped GST, or a doped GeTe compound such as N-doped GeTe, Si-doped GeTe, C-doped GeTe, or Ge-doped GeTe. The phase change material layer 54L may be deposited by physical vapor deposition. The thickness of the phase change material layer 54L may be in the range of 30 to 200 nm, such as 50 to 90 nm, although smaller or larger thicknesses may also be used. In one embodiment, the phase change material of the phase change material layer has an electrical conductivity of the amorphous phase of the phase change material in the range of 1.0×10 -8 ~1.0×10 -3 S / cm, while the electrical conductivity of the crystalline phase of the phase change material is 1.0×10-1 ~1.0×10 3 It may be selected to fall within the range of S / cm.

[0034] The top electrode material layer 56L contains a metallic material such as W, Ta, Ti, Mo, WN, TiN, WN, or MoN. The top electrode material layer 56L may have a thickness in the range of 100 to 200 nm, but smaller or larger thicknesses may also be used. The top electrode material layer 56L may be deposited by chemical vapor deposition or physical vapor deposition.

[0035] Generally, a continuous layer laminate (52L, 54L, 56L) including a heater liner layer 52L, a phase change material layer 54L containing a phase change material, and a top electrode material layer 56L may be deposited on a dielectric material layer (e.g., a lower fourth wiring layer dielectric material layer 641) and a tubular dielectric spacer 42. The heater liner layer 52L may be deposited directly on a dielectric material layer on which via openings 41 extend vertically, and may also be deposited directly on a tubular dielectric spacer 42 located in the peripheral region of the via openings 41.

[0036] Referring to Figure 6, a first patterning process may be performed to pattern a continuous layer stack (52L, 54L, 56L) onto an in-process layer stack (52', 54', 56'). Specifically, a first patterned etching mask layer 77 may be formed on the continuous layer stack (52L, 54L, 56L). For example, the first patterned etching mask layer 77 may be formed by coating a photoresist layer on the continuous layer stack (52L, 54L, 56L) and lithographically patterning the photoresist layer onto an array of discrete patterned photoresist material portions. In one embodiment, the first patterned etching mask layer 77 may include a two-dimensional array of patterned photoresist material portions located in the memory array region 100, such as a two-dimensional rectangular periodic array. In one embodiment, each patterned photoresist material portion may have a rectangular horizontal cross-sectional shape. In one embodiment, the lateral dimensions of each patterned photoresist material portion may be selected to provide patterning for at least two phase-change memory cells in a subsequent processing step. Alternatively, the lateral dimensions of each patterned photoresist material portion may be selected to provide patterning for a single phase-change memory cell in a subsequent processing step.

[0037] A first anisotropic etching process may be performed to etch portions of the continuous layer laminate (52L, 54L, 56L) that are not masked by the first patterned etching mask layer 77. The first anisotropic etching process has an etching chemistry that selectively etches the material of the continuous layer laminate (52L, 54L, 56L) with respect to the material of the dielectric material layer (e.g., the lower fourth wiring layer dielectric material layer 641) that embeds the tubular dielectric spacer 42. The continuous layer laminate (52L, 54L, 56L) is patterned on an in-process layer laminate (52', 54', 56') which includes an in-process heater liner 52', an in-process phase change material portion 54', and an in-process top electrode 56', respectively. As used herein, the “in-process” element refers to an element that is structurally and / or compositionally modified in a subsequent processing step. Each in-process heater liner 52' ​​may be a patterned portion of the heater liner layer 52L. Each in-process phase change material portion 54' may be a patterned portion of the phase change material layer 54L. Each in-process top electrode 56' may be a patterned portion of the top electrode material layer 56L. For each in-process layer laminate (52', 54', 56'), the sidewall of the in-process heater liner 52' ​​may coincide perpendicularly with the sidewall of the in-process phase change material portion 54', or perpendicularly with the sidewall of the in-process top electrode 56'. As used herein, "perpendicular to" the first surface means that the second surface overlaps or overlaps the first surface and the first and second surfaces are located within the same vertical plane, which may be planar or curved in a horizontal cross-sectional view. The first patterned etching mask layer 77 may be subsequently removed, for example, by ashing.

[0038] Referring to Figure 7, according to one aspect of the present invention, the sidewall liner layer 58L may be deposited on the physically exposed surface of the in-process layer laminate (52', 54', 56') and on the physically exposed top surface of the dielectric material layer (e.g., lower fourth wiring layer dielectric material layer 641) that embeds the bottom electrode 38 and the tubular dielectric spacer 42. In one embodiment, the sidewall liner layer 58L may include a metal nitride material layer deposited by a conformal deposition process such as a chemical vapor deposition process. In one embodiment, the sidewall liner layer 58L may include a second metal nitride material, which may include TiN, TaN, WN, and / or MoN, and / or be essentially composed of these. The thickness of the sidewall liner layer 58L may be in the range of 1 to 20 nm, for example, in the range of 2 to 4 nm, but smaller or larger thicknesses may also be used.

[0039] According to one aspect of the present invention, the electrical conductivity of the second metal nitride material may be reduced by incorporating carbon or nitrogen atoms into the metal nitride material layer by in-situ doping or ex-situ doping of carbon or nitrogen atoms, i.e., by introducing carbon or nitrogen atoms during or after the deposition of the sidewall liner layer 58L. For example, carbon or nitrogen atoms may be provided by a reactive carbon-containing gas (such as acetylene or ethylene) or a reactive nitrogen-containing gas (such as ammonia) during chemical vapor deposition of the sidewall liner layer 58L. Alternatively, the sidewall liner layer 58L may be exposed to an atmosphere containing reactive carbon-containing species or reactive nitrogen-containing species at high temperatures after the deposition process of the sidewall liner layer 58L. Yet another method is to perform an ion implantation process or a plasma doping process after the deposition process of the sidewall liner layer 58L.

[0040] Carbon atoms or nitrogen atoms may be incorporated into the second metal nitride material of the sidewall liner layer 58L at an atomic concentration such that the electrical conductivity of the doped metal nitride material of the sidewall liner layer 58L after the introduction of carbon atoms or nitrogen atoms is less than 1 / 3 of the electrical conductivity of the second metal nitride material before the introduction of carbon atoms or nitrogen atoms. In an exemplary embodiment, the electrical conductivity of the sidewall liner layer 58L after the introduction of carbon atoms or nitrogen atoms is 1.0 × 10⁻⁶. 1 ~1.0×10 5 It may also be within the range of S / cm.

[0041] Generally, the ratio of metal atoms to nitrogen atoms in a stoichiometric metal compound MN (where M is Ta, Ti, Mo, or W) is 1:1. In embodiments where nitrogen doping is used, when nitrogen atoms are doped into the stoichiometric metal compound to form the sidewall liner layer 58L of the present invention, the ratio of metal atoms to nitrogen atoms in the sidewall liner layer 58L may be in the range of 1:1.02 to 1:1.05. In embodiments where carbon doping is used, when carbon atoms are doped into the stoichiometric metal compound to form the sidewall liner layer 58L of the present invention, the ratio of metal atoms to nitrogen atoms to carbon atoms in the sidewall liner layer 58L may be in the range of 1:1:0.02 to 1:1:0.05. Generally, the atomic concentration of excess nitrogen atoms in a nitrogen-doped metal nitride material may be in the range of 0.02 times to 0.05 times the atomic concentration of metal atoms. Similarly, the atomic concentration of carbon atoms in a carbon-doped metal nitride material may be in the range of 0.02 times to 0.05 times the atomic concentration of metal atoms.

[0042] In one embodiment, the second metal nitride material of the sidewall liner layer 58L after the doping process may have an electrical conductivity of less than 1 / 3, preferably less than 1 / 10, of the electrical conductivity of the first metal nitride material of the in-process heater liner 52'. In other words, the in-process heater liner 52' ​​includes a material having an electrical conductivity at least 3 times, preferably at least 10 times, that of the sidewall liner material of the sidewall liner layer 58L.

[0043] Generally, the first metal nitride material of the heater liner layer 52L (and the in-process heater liner 52') and the second metal nitride material (doped metal nitride material) of the sidewall liner layer 58L may be selected such that the resistance of the heater liner patterned from the in-process heater liner 52' ​​and the resistance of the sidewall liner patterned from the sidewall liner layer 58L are dominant in the resistance of the phase-change memory material cell states having high resistance values, which include high-resistance states and first resistance states having relatively high resistance values. In this embodiment, the resistance of the amorphous volume of the phase-change material portion does not determine the resistance of the high-resistance state of the phase-change memory cell. Therefore, the phase-change memory cell can operate without being affected by any resistance drift of the phase-change material.

[0044] Referring to Figure 8, an anisotropic etching process may be performed to remove the horizontally stretched portion of the sidewall liner layer 58L. The anisotropic etching process may be selective for the material of the dielectric material layer (such as the lower fourth wiring layer dielectric material layer 641) that embeds the tubular dielectric spacer 42. Each remaining vertically stretched portion of the sidewall liner layer 58L constitutes an in-process sidewall liner 58' that laterally surrounds each in-process laminate (52', 54', 56'). Each in-process sidewall liner 58' contacts the sidewalls of the in-process heater liner 52', the in-process phase change material portion 54', and the in-process top electrode 56' of each in-process laminate (52', 54', 56'). In one embodiment, the upper surface segments of each sidewall of the in-process top electrode 56' may be physically exposed. Generally, the in-process sidewall liner 58' may be formed around each in-process laminate (52', 54', 56') by conformally depositing a layer of sidewall liner material and anisotropically etching it.

[0045] Referring to Figure 9, a second patterning process may be performed to pattern the in-process laminates (52', 54', 56') and the in-process sidewall liners 58'. The second patterned etching mask layer 79 may be formed on the in-process laminates (52', 54', 56') and the in-process sidewall liners 58' in such a way that it covers a first region of the in-process laminates (52', 54', 56') and the in-process sidewall liners 58', but does not cover a second region of the in-process laminates (52', 54', 56') and the in-process sidewall liners 58'. For example, a photoresist layer (not shown) may be coated on the in-process laminates (52', 54', 56') and the in-process sidewall liners 58', and a two-dimensional array of patterned photoresist material portions, such as a rectangular array, may be lithographically patterned. In one embodiment, the second patterned etching mask layer 79 may cover at least two discrete regions of each in-process laminate (52', 54', 56') that are not interconnected, i.e., separated by gaps not covered by the second patterned etching mask layer 79.

[0046] A second anisotropic etching process may be performed to etch the unmasked portions of the in-process laminate (52', 54', 56') and the in-process sidewall liner 58', i.e., portions of the in-process laminate (52', 54', 56') and the in-process sidewall liner 58' that are not masked by the second patterned etching mask layer 79. The second anisotropic etching process has an etching chemical composition that selectively etches the materials of the in-process laminate (52', 54', 56') and the in-process sidewall liner 58' with respect to the materials of the dielectric material layers (such as the lower fourth wiring layer dielectric material layer 641) that embed the tubular dielectric spacers 42.

[0047] In one embodiment, the second patterning process may pattern each adjacent combination of in-process laminates (52', 54', 56') and in-process sidewall liners 58' onto a plurality of discrete material portions that are not adjacent to each other. In one embodiment, each patterned portion of the in-process laminates (52', 54', 56') includes a respective laminate containing a heater liner 52, a phase change material portion 54, and a top electrode 56. Each patterned portion of the in-process sidewall liners 58' constitutes a sidewall liner 58 according to the embodiments of the present disclosure. The in-process laminates (52', 54', 56') may be patterned onto a plurality of laminates (52, 54, 56). The in-process sidewall liners 58' may be patterned onto a plurality of sidewall liners 58. For each laminate (52, 54, 56), the lateral distance between the side wall of the laminate (52, 54, 56) and the proximal side wall of the lower heater element 52 may be in the range of 30 to 200 nm, for example, in the range of 50 to 150 nm, but smaller or larger lateral distances may also be used.

[0048] Generally, at least one sidewall liner 58 may be formed by depositing and patterning a sidewall liner material on the sidewalls of each stack (52, 54, 56) which are patterned portions of a continuous stack (52L, 54L, 56L). The sidewall liner material of at least one sidewall liner 58 includes a material having higher electrical conductivity than the amorphous phase of the phase change material. The sidewall liner material may include a metal nitride material formed by incorporating carbon or nitrogen atoms therein, resulting in the metal nitride material having lower electrical conductivity than a stoichiometric metal nitride material. Therefore, in embodiments in which the amorphous phase portion of the phase change material and the sidewall liner 58 provide two parallel electrical conduction paths, the sidewall liner 58 provides a lower resistance path, which primarily determines the total resistance of the two parallel electrical conduction paths during the operation of the phase change memory cell of this disclosure. This embodiment is particularly useful for the operation of phase-change memory cells for computation-in-memory (CIM) applications because the resistive drift effect of the phase-change material is suppressed during the operation of the phase-change memory cell.

[0049] Referring to Figure 10, the second patterned etching mask layer 79 may be removed, for example, by ashing. Each adjacent combination of the bottom electrode 38, heater liner 52, phase change material portion 54, top electrode 56, and at least one sidewall liner 58 constitutes the phase change memory cell 50. The vertical extension of the heater liner 52 functions as a heater element of the phase change memory cell 50, and when an appropriate programming pulse, i.e., a current pulse, is applied between the bottom electrode 38 and the top electrode 56, it provides various types of thermal pulses necessary to program the phase change material portion 54 to a target resistance state.

[0050] In one embodiment, each phase change memory cell 50 includes a tubular dielectric spacer 42 located within a via opening 41 within the range of a dielectric material layer (such as the lower fourth wiring layer dielectric material layer 641), a heater liner 52 including a vertically extended portion laterally surrounded by the tubular dielectric spacer 42 and a horizontally extended portion overlapping the top surface segment of the dielectric material layer (such as the lower fourth wiring layer dielectric material layer 641), a phase change material portion 54 including a phase change material that contacts the top surface of the heater liner layer 52L, and a top electrode 56 that contacts the top surface of the phase change material portion 54.

[0051] In one embodiment, the heater liner 52 includes a planar horizontal surface segment PHSS that overlaps a dielectric material layer (such as the lower fourth wiring layer dielectric material layer 641), and further includes an annular convex segment ACSS adjacent to the periphery of an opening in the planar horizontal surface segment PHSS and overlapping a via opening 41, wherein the phase change material portion 54 is in contact with the annular convex segment ACSS.

[0052] In one embodiment, the vertically extended portion of the heater liner 52 includes a vertically extended seam S, and the top surface of the heater liner 52 includes an annular convex segment ACSS having a bottom tip adjacent to the top end of the vertically extended seam S. In one embodiment, the phase change material portion 54 includes a vertically extended portion located within the central region of the via opening 41, and the vertically extended portion of the heater liner 52 includes a cylindrical inner side wall in contact with the vertically extended portion of the phase change material portion 54.

[0053] In one embodiment, the phase change memory cell 50 includes at least one sidewall liner 58 located on at least one sidewall of the phase change material portion 54. The at least one sidewall liner 58 is in contact with the sidewall of the horizontally extended portion of the heater liner 52 and includes a material having higher electrical conductivity than the amorphous phase of the phase change material.

[0054] In general, the first patterning process described with reference to Figure 8 and the second patterning process described with reference to Figure 11 can use various combinations of patterns to provide arrays of phase-change memory cells 50 having different configurations. Figures 11A to 11C show sequential top views of the regions of the first configuration of the embodiment structure during the processing steps of Figures 8 to 10. Figures 12A to 12C show sequential top views of the regions of the second configuration of the embodiment structure during the processing steps of Figures 8 to 10. Figures 13A to 13C show sequential top views of the regions of the third configuration of the embodiment structure during the processing steps of Figures 8 to 10. Figure 14 shows a top view of the region of the fourth configuration of the embodiment structure after the processing step of Figure 8. The various configurations shown in Figures 11A to 14 are merely illustrative examples illustrating specific configurations and do not limit the scope of this disclosure.

[0055] Referring to Figure 11A, the region of the first configuration of the embodiment structure, including the in-process layered bodies (52', 54', 56') and the in-process sidewall liner 58', is illustrated in the processing step of Figure 8. The in-process layered bodies (52', 54', 56') may include a first sidewall parallel to the first horizontal direction hd1 and a second sidewall parallel to the second horizontal direction hd2. The second horizontal direction hd2 may be perpendicular to the first horizontal direction hd1.

[0056] Referring to Figure 11B, the region of the first configuration of the embodiment's structure is shown after the formation of the second patterned etching mask layer 79 and before the execution of the second anisotropic etching process. The second patterned etching mask layer 79 may include a two-dimensional array, such as a 2 × N array of patterned discrete etching mask material portions (such as patterned photoresist material portions), covering 2N segments of the first sidewall of the in-process layer stack (52', 54', 56'). In the illustrated example, the integer N is 4. In general, the integer N may be any positive integer. As described above, the in-process layer stack (52', 54', 56') includes a first sidewall extending laterally along the first horizontal direction hd1 and a second sidewall extending laterally along the second horizontal direction hd2. The masking material portions of the second patterned etching mask layer 79 may extend laterally along the second horizontal direction hd2 and be spaced laterally apart from each other along the first horizontal direction hd1.

[0057] Referring to Figure 11C, the second anisotropic etching process may be carried out as described with reference to Figure 9. The second anisotropic etching process removes unmasked portions of the in-process layer laminates (52', 54', 56') that are not covered by the second patterning etching mask layer 79. Each patterned portion of the in-process layer laminates (52', 54', 56') includes a laminate (52, 54, 56) containing its respective heater liner 52, its respective phase change material portion 54, and its respective top electrode 56. Generally, the multiple patterned portions of each in-process layer laminate (52', 54', 56') may include at least one row of patterned portions arranged along the first horizontal direction hd1. In the first configuration shown in Figure 11C, at least one patterned portion may include two rows of patterned portions of two in-process layer stacks (52', 54', 56'), i.e., two rows of stacks (52, 54, 56) that constitute a 2×N array stack (52, 54, 56). Generally, P×Q array in-process layer stacks (52', 54', 56') may be used, and a 2P×QN array phase change memory cell 50 may be formed by using the first configuration shown in Figures 11A to 11C.

[0058] Generally speaking, at least one sidewall liner 58 may be formed on each stack (52, 54, 56) within the range of each phase-change memory cell 50. In the first configuration, at least one sidewall liner 58 within the range of each phase-change memory cell 50 may consist of a single sidewall liner 58 directly formed on the sidewall of the stack (52, 54, 56) of the phase-change memory cell 50, which is a patterned portion of the continuous layer stack (52L, 54L, 56L).

[0059] Referring to Figure 12A, a region of the second configuration of the embodiment structure, which includes two in-process layered bodies (52', 54', 56') and two in-process sidewall liners 58', is illustrated in the processing step of Figure 8. Each in-process layered body (52', 54', 56') may include a first sidewall parallel to a first horizontal direction hd1 and a second sidewall parallel to a second horizontal direction hd2. The second horizontal direction hd2 may be perpendicular to the first horizontal direction hd1.

[0060] Referring to Figure 12B, the region of the second configuration of the embodiment structure is shown after the formation of the second patterned etching mask layer 79 and before the execution of the second anisotropic etching process. The second patterned etching mask layer 79 may include a 1 × N array of patterned discrete etching mask material portions (such as patterned photoresist material portions) covering 2N segments of the first sidewall of each in-process layer stack (52', 54', 56'). Each patterned discrete etching mask material portion may include a photoresist material strip extending laterally along the second horizontal direction hd2 and having a uniform width along the first horizontal direction hd1. In the illustrated example, the integer N is 4. Generally, the integer N may be any positive integer. As described above, each in-process layer stack (52', 54', 56') includes a first sidewall extending laterally along the first horizontal direction hd1 and a second sidewall extending laterally along the second horizontal direction hd2. The masking material portion of the second patterned etching mask layer 79 may extend laterally along the second horizontal direction hd2 and be spaced apart laterally from each other along the first horizontal direction hd1.

[0061] Referring to Figure 12C, the second anisotropic etching process may be carried out as described with reference to Figure 9. The second anisotropic etching process removes unmasked portions of the in-process layered stacks (52', 54', 56') that are not covered by the second patterned etching mask layer 79. Each patterned portion of the in-process layered stacks (52', 54', 56') includes a layered stack (52, 54, 56) containing its respective heater liner 52, its respective phase change material portion 54, and its respective top electrode 56. Generally, the multiple patterned portions of each in-process layered stack (52', 54', 56') may include at least one row of patterned portions arranged along a first horizontal direction hd1. In the second configuration shown in Figure 12C, at least one column of the patterned portion may include a column of patterned portions of an in-process layered stack (52', 54', 56'), i.e., a column of layered stacks (52, 54, 56) that constitutes a 1×N array of layered stacks (52, 54, 56). Generally, a P×Q array of in-process layered stacks (52', 54', 56') may be used, and a P×QN array of phase-change memory cells 50 may be formed by using the second configuration shown in Figures 12A to 12C.

[0062] Generally speaking, at least one sidewall liner 58 may be formed on each layer stack (52, 54, 56) within the range of each phase-change memory cell 50. In a second configuration, at least one sidewall liner 58 within the range of each phase-change memory cell 50 may include two sidewall liners 58 formed directly on a pair of sidewalls of the layer stack (52, 54, 56) of the phase-change memory cell 50, which is a patterned portion of the continuous layer stack (52L, 54L, 56L). The pair of sidewalls may be parallel to each other, and the two sidewall liners 58 are spaced laterally apart from each other along a horizontal direction such as a second horizontal direction hd2.

[0063] Referring to Figure 13A, a region of the third configuration of the embodiment structure, including the in-process layered structures (52', 54', 56') and the in-process sidewall liner 58', is illustrated in the processing step of Figure 10. Each in-process layered structure (52', 54', 56') may include a first sidewall parallel to the first horizontal direction hd1 and a second sidewall parallel to the second horizontal direction hd2. The second horizontal direction hd2 may be perpendicular to the first horizontal direction hd1.

[0064] Referring to Figure 13B, the region of the third configuration of the embodiment structure is shown after the formation of the second patterned etching mask layer 79 and before the execution of the second anisotropic etching process. The second patterned etching mask layer 79 may include a pair of patterned discrete etching mask material portions (such as patterned photoresist material portions) that cover all second sidewalls of the in-process layer stacks (52', 54', 56') and each first sidewall segment adjacent to each second sidewall of the in-process layer stacks (52', 54', 56'). Each first sidewall of the in-process layer stacks (52', 54', 56') includes a central segment not covered by the second patterned etching mask layer 79. As described above, each in-process layer stack (52', 54', 56') includes a first sidewall extending laterally along a first horizontal direction hd1 and a second sidewall extending laterally along a second horizontal direction hd2. The two masking material portions of the second patterned etching mask layer 79 may extend laterally along the second horizontal direction hd2 and be spaced laterally apart from each other along the first horizontal direction hd1 so that the central segments of each first sidewall of the in-process layer laminate (52', 54', 56') are not covered by the second patterned etching mask layer 79.

[0065] Referring to Figure 13C, the second anisotropic etching process may be carried out as described with reference to Figure 9. The second anisotropic etching process removes unmasked portions of the in-process layered stacks (52', 54', 56') that are not covered by the second patterned etching mask layer 79. Each patterned portion of the in-process layered stacks (52', 54', 56') includes a layered stack (52, 54, 56) containing a heater liner 52, a phase change material portion 54, and a top electrode 56. Generally, the multiple patterned portions of each in-process layered stack (52', 54', 56') may include at least one row of patterned portions arranged along a first horizontal direction hd1. In the third configuration shown in Figure 13C, at least one patterned column may include a column containing two patterned columns of in-process layer stacks (52', 54', 56'), i.e., a column of layer stacks (52, 54, 56) constituting a 1×2 array of layer stacks (52, 54, 56). Generally, in-process layer stacks (52', 54', 56') of a P×Q array may be used, and a phase change memory cell 50 of a P×2Q array may be formed by using the third configuration shown in Figures 13A to 13C.

[0066] Generally speaking, at least one sidewall liner 58 may be formed on each layer stack (52, 54, 56) within the range of each phase-change memory cell 50. In a third configuration, at least one sidewall liner 58 within the range of each phase-change memory cell 50 may consist of a single sidewall liner 58 formed directly on the three sidewalls of the layer stack (52, 54, 56) of the phase-change memory cell 50, which is a patterned portion of a continuous layer stack (52L, 54L, 56L).

[0067] Referring to Figure 14, a fourth configuration of the embodiment structure is illustrated after the processing step in Figure 8. In the fourth configuration, the masking pattern of the first patterned etching mask layer 77 used in the processing step in Figure 8 is changed so that the pattern of the first patterned etching mask layer 77 is the same as the target pattern of the array of layer stacks (52, 54, 56) for the array of phase change memory cells 50. In this embodiment, the first anisotropic etching process described with reference to Figure 6 directly patterns the continuous layer stacks (52L, 54L, 56L) into the array of layer stacks (52, 54, 56). Furthermore, the sidewall liner layer 58L may be directly patterned into the sidewall liner 58 by performing the processing steps described with reference to Figures 7 and 8. Therefore, when the fourth configuration of the embodiment structure is used, the processing steps described with reference to Figures 9 and 10 may be omitted.

[0068] Generally speaking, at least one sidewall liner 58 may be formed on each layer stack (52, 54, 56) within the range of each phase-change memory cell 50. In a fourth configuration, at least one sidewall liner 58 within the range of each phase-change memory cell 50 may have an annular configuration. In other words, at least one sidewall liner 58 within the range of each phase-change memory cell 50 may consist of a single sidewall liner 58 that is topologically in phase with a torus, i.e., it may be continuously deformed into a torus without forming new holes and without removing existing holes. The single sidewall liner 58 may be formed directly on each sidewall of each layer stack (52, 54, 56), which is the patterned portion of the continuous layer stack (52L, 54L, 56L).

[0069] Referring to Figure 15, a sealing dielectric layer 643 and additional metal wiring structures (62, 642, 648) may be formed on the phase change memory cell 50. The sealing dielectric layer 643 includes at least one interlayer dielectric material such as silicon oxide, silicon nitride, and / or silicon carbide nitride. The sealing dielectric layer 643 constitutes the upper fourth wiring layer dielectric material layer. The combination of the lower fourth wiring layer dielectric material layer 641 and the sealing dielectric layer 643 constitutes the fourth wiring layer dielectric material layer 640. The additional metal wiring structures (62, 642, 648) may include a top contact via structure 62 that contacts the top surface of each of the top electrodes 56, a third metal via structure 642 formed through the lower part of the fourth wiring layer dielectric material layer 640, and a fourth metal wiring structure 648 formed on the top contact via structure 62 and the third metal via structure 642 on the upper part of the fourth wiring layer dielectric material layer 640. The top surface of the fourth metal wiring structure 648 may be coplanar with the horizontal top surface of the sealing dielectric layer 643. Additional dielectric material layers (not shown) and additional metal wiring structures may be formed as needed to provide electrical connections between the top electrode 56 of the phase change memory cell 50 and various semiconductor devices 700 that are underlying the dielectric material layers (601, 610, 620, 630, 640).

[0070] Generally, the programming transistor 701 may be provided on the substrate 8. Metal wiring structures (612, 618, 622, 628, 632, 638) embedded within the wiring layer dielectric material layers (601, 610, 620, 630, 641) may be formed on the programming transistor 701. The bottom electrode 38 and the tubular dielectric spacer 42 may be formed within the dielectric material layers such as the lower fourth wiring layer dielectric material layer 641. Each heater liner 52 may be electrically connected to an electrical node such as the output node of each programming transistor 701. A continuous layer laminate (52L, 54L, 56L) including a heater liner layer 52L, a phase change material layer 54L containing a phase change material, and a top electrode material layer 56L may be deposited and patterned to form a laminate (52, 54, 56) of the heater liner 52, the phase change material portion 54, and the top electrode 56. The sidewall liner layer 58L may be formed and patterned to form a sidewall liner 58. At least one sidewall liner 58 may be formed on at least one sidewall of each laminate (52, 54, 56).

[0071] Each sidewall liner 58 contains a material having higher electrical conductivity than the amorphous phase of the phase change material in the phase change material portion 54. For each phase change memory cell 50, the sealing dielectric layer 643 may be deposited directly on at least one sidewall of the laminate (52, 54, 56) (which is a patterned portion of the continuous layer laminate (52L, 54L, 56L)), directly on each outer sidewall of at least one sidewall liner 58, and directly on the top surface of the laminate (52, 54, 56). Thus, for each phase change memory cell 50, the sealing dielectric layer 643 is in contact with at least one sidewall of the laminate, each outer sidewall of at least one sidewall liner 58, and the top surface of the laminate (52, 54, 56).

[0072] For each phase-change memory cell 50 electrically connected to the programming transistor 701, the programming transistor 701 is configured to program the phase-change memory cell 50 to at least three different resistance states by applying at least three different programming pulse patterns to the heater liner 52. Figures 16A to 16D show various configurations of the phase-change material section 54 in various programmed resistance states according to embodiments of the present invention.

[0073] Referring to Figure 16A, a phase-change memory cell 50 in a low-resistance state is illustrated. In this embodiment, at least 99% of the total volume of the phase-change material portion 54 is a polycrystalline phase. In one embodiment, the entire phase-change material portion 54 may be a crystalline phase-change material portion 54C containing a polycrystalline phase-change material. The electrical conductivity of the crystalline phase-change material is higher than that of the materials of the heater liner 52 and at least one sidewall liner 58. Therefore, the main electrical conduction path extends perpendicularly between the heater liner 52 and the top electrode 56.

[0074] Referring to Figure 16B, a phase-change memory cell 50 in a first intermediate state is illustrated. In this embodiment, the phase-change material portion 54 includes a first volume having an amorphous phase and a second volume having a crystalline phase. The first volume includes the amorphous phase-change material portion 54A, and the second volume includes the crystalline phase-change material portion 54C. The first volume is not in direct contact with at least one sidewall liner 58. The electrical conductivity of the amorphous phase-change material is lower than that of the heater liner 52 and at least one sidewall liner 58. Therefore, the main electrical conduction paths extend laterally within the range of the heater liner 52 directly below the amorphous phase-change material portion 54A, and extend at an angle to the vertical through the crystalline phase-change material portion 54C between the periphery of the heater liner 52 and the top electrode 56.

[0075] Referring to Figure 16C, a phase-change memory cell 50 in a second intermediate state that provides a higher resistance than the first intermediate state is illustrated. In this embodiment, the phase-change material portion 54 includes a first volume having an amorphous phase and a second volume having a crystalline phase. The first volume includes the amorphous phase-change material portion 54A, and the second volume includes the crystalline phase-change material portion 54C. The first volume is in direct contact with at least one sidewall liner 58 but not with the top electrode 56. The electrical conductivity of the amorphous phase-change material is lower than that of the heater liner 52 and the materials of at least one sidewall liner 58. Therefore, the main electrical conduction paths extend laterally within the range of the heater liner 52 directly below the amorphous phase-change material portion 54A, extend vertically through the lower part of each sidewall liner 58, and extend at an angle to the vertical through the crystalline phase-change material portion 54C between the middle of each sidewall liner 58 and the top electrode 56.

[0076] Referring to Figure 16D, a phase-change memory cell 50 in a high-resistance state is illustrated. In this embodiment, at least 99% of the total volume of the phase-change material portion 54 is in the amorphous phase.

[0077] The four resistance states of the phase-change memory cell 50 are illustrated in Figures 16A to 16D, but the pulse pattern of the programming pulse from the programming transistor 701 may be pre-programmed to be selected from a plurality of programming pulse patterns stored in the programming circuit for the phase-change memory cell 50. The total number of pre-programmed pulse patterns may be in the range of 2 to 210, for example, in the range of 3 to 28 and / or in the range of 4 to 26. The total number of resistance states that can be programmed for each phase-change memory cell 50 may be the same as the total number of pre-programmed pulse patterns. In one embodiment, each programming transistor 701 may be configured to apply at least four different programming pulse patterns to each heater liner 52. The programming pulses may have a duration and / or voltage ramp-down rate to provide a controlled cooling rate for the molten region of the phase-change material 54. The duration of the programming pulses may be in the range of 10 to 500 nanoseconds, and longer programming pulses generally correspond to the formation of larger crystallized regions of the phase-change material 54.

[0078] Referring to Figure 17, a second embodiment structure according to one embodiment of the present invention is illustrated. The second embodiment structure may be derived from the first embodiment structure shown in Figure 1 by forming via openings 41 having larger lateral dimensions, performing the processing steps described with reference to Figures 3 and 4, and depositing a heater liner layer 52L having a greater thickness than the heater liner layer 52L described with reference to Figure 5.

[0079] For example, the lateral dimension (such as diameter) of the bottom of each via opening 41 formed in the processing step corresponding to the processing step in Figure 2 may be in the range of 80 to 400 nm, but smaller or larger lateral dimensions may also be used. The thickness of the dielectric spacer material layer 42L deposited in the processing step corresponding to the processing step in Figure 3 is selected such that the difference between the width of the bottom of each via opening 41 and twice the thickness of the dielectric spacer material layer 42L is greater than the target range of the width of the bottom of each vertical extension of the heater liner layer that is later formed. In an exemplary embodiment, if the width of the bottom of each via opening 41 is in the range of 80 to 400 nm and the target range of the width of the bottom of each vertical extension of the heater liner layer 52L is in the range of 20 to 100 nm, the thickness of the dielectric spacer material layer 42L may be in the range of 15 to 150 nm, for example, in the range of 30 to 80 nm, but smaller or larger thicknesses may also be used. Thus, the lateral distance between the inner cylindrical sidewall and the outer cylindrical sidewall of each tubular dielectric spacer 42 may be in the range of approximately 15 to 150 nm, for example, in the range of 30 to 80 nm, but smaller or larger lateral distances may also be used.

[0080] The heater liner layer 52L may be deposited to a thickness sufficient to fill the main portion and / or all of the volume of each void within the range of the via opening 41 with the deposited material of the heater liner layer 52L. The thickness of the horizontally stretched portion of the heater liner layer 52L formed on the top surface of the dielectric material layer (such as the lower fourth wiring layer dielectric material layer 641) may be in the range of 25 to 120 nm, for example, in the range of 50 to 80 nm, but smaller or larger thicknesses may also be used.

[0081] Similar to the structure of the first embodiment, vertically stretched seams S may be formed within the range of each vertically stretched portion of the heater liner layer 52L deposited within a portion of the volume of each via opening 41. Another portion of the volume of each via opening 41 may be occupied by tubular dielectric spacers 42. Similar to the structure of the first embodiment, the heater liner layer 52L is formed having a planar horizontal surface segment PHSS and an annular convex segment ACSS that overlaps a dielectric material layer (such as the lower fourth wiring layer dielectric material layer 641), and each annular convex segment ACSS includes each bottom tip point adjacent to the periphery of each opening in the planar horizontal surface segment PHSS and adjacent to the top end of the vertically stretched seam S.

[0082] Referring to Figure 18, the heater liner layer 52L may be vertically recessed by performing an etch-back process, which is a recess etching process that etches the material of the heater liner layer 52L. The etch-back process vertically recesses the horizontally extended portion of the heater liner layer 52L. The etch-back process vertically recesses the annular convex segment ACSS of the heater liner layer 52L at the same time. In other words, the etch-back process simultaneously etches the annular convex segment ACSS and the planar horizontal surface segment PHSS of the heater liner layer 52L.

[0083] The etch-back process may include a wet etching process or a reactive ion etching process. The time of the etch-back process may be selected so that the horizontally stretched portion of the thinned heater liner layer 52L has a thickness within a target thickness range, which may be in the range of 1 to 50 nm, for example, 3 to 20 nm, but smaller or larger thicknesses may also be used. In general, the thickness of the horizontally stretched portion of the heater liner layer 52L formed through the processing steps described with reference to Figures 17 and 18 may be smaller than the thickness of the horizontally stretched portion of the heater liner layer 52L within the range of the first embodiment structure, and the horizontally stretched portion of the heater liner layer 52L of the second embodiment structure may provide higher electrical resistance than the horizontally stretched portion of the heater liner layer 52L of the first embodiment structure.

[0084] Referring to Figure 19, a subset of the processing steps described with reference to Figure 5 may be performed to deposit the phase change material layer 54L and the top electrode material layer 56L on the horizontally stretched portion of the heater liner layer 52L.

[0085] Referring to Figure 20, the processing steps described with reference to Figure 6 may be performed to pattern the continuous layered structure (52L, 54L, 56L) onto a two-dimensional array of in-process layered structures (52', 54', 56').

[0086] Referring to Figure 21, the processing steps described with reference to Figures 7 to 15 may be performed to form a two-dimensional array of phase-change memory devices 50. Each phase-change memory cell 50 in the second embodiment structure may have a larger bottom width with respect to the vertical extension of the heater liner 52 and / or a smaller thickness with respect to the horizontal extension of the heater liner 52, which may be advantageously used to provide enhanced resistance distribution characteristics for various program states of the phase-change memory cell 50.

[0087] Referring to Figure 22, a third embodiment structure according to an embodiment of the present invention is shown after the formation of the heater liner layer 52L. The third embodiment structure may be derived from the first embodiment structure shown in Figure 1 by forming via openings 41 having larger lateral dimensions, performing the processing steps described with reference to Figures 3 and 4, and depositing a heater liner layer 52L having the same thickness range as the heater liner layer 52L described with reference to Figure 5. The heater liner layer 52L may be deposited by a conformal deposition process.

[0088] As described above, voids may exist within the range of each volume laterally enclosed by the tubular dielectric spacer 42. In the third embodiment structure, the maximum width of each void within the volume of the via opening 41 is greater than half the thickness of the heater liner layer 52L. Therefore, the voids within the volume of the via opening 41 are not completely filled by the heater liner layer 52L. In other words, after the formation of the heater liner layer 52L, there may be unfilled voids within the range of each volume of the via opening 41. In one embodiment, the inner cylindrical sidewall of the tubular portion of the heater liner layer 52L and the top surface segment of the horizontally extended portion of the heater liner layer 52L that contacts the bottom electrodes 38 of the respective lower layers may be physically exposed to each unfilled void located within the range of each via opening 41 that penetrates the dielectric material layer (such as the lower fourth wiring layer dielectric material layer 641).

[0089] Similar to the structure of the first embodiment, the heater liner layer 52L is formed having a planar horizontal surface segment PHSS that overlaps the dielectric material layer (such as the lower fourth wiring layer dielectric material layer 641), and annular convex segment ACSS adjacent to the periphery of each opening in the planar horizontal surface segment PHSS and including each bottom tip point adjacent to the apex of the vertically stretched seam S.

[0090] Referring to Figure 23, a subset of the processing steps described with reference to Figure 5 may be performed to deposit the phase change material layer 54L and the top electrode material layer 56L. In the third embodiment structure, the phase change material layer 54L includes vertically extended portions having cylindrical sidewalls that contact the inner cylindrical sidewalls of each tubular dielectric spacer 42, within the volume of each via opening 41 that vertically penetrates the dielectric material layer (such as the lower fourth wiring layer dielectric material layer 641). Each vertically extended portion of the phase change material layer 54L may be deposited within the unfilled portion of each void laterally surrounded by each tubular portion of the heater liner layer 52L. The top electrode material layer 56L is then deposited on top of the phase change material layer 54L.

[0091] Referring to Figure 24, the processing steps described with reference to Figure 6 may be performed to pattern the continuous layer laminate (52L, 54L, 56L) onto a two-dimensional array of in-process laminates (52', 54', 56').

[0092] Referring to Figure 25, the processing steps described with reference to Figures 7 to 15 may be performed to form a two-dimensional array of phase-change memory devices 50. Each phase-change memory cell 50 in the third embodiment structure may have a tubular vertical extension of the heater liner 52. In one embodiment, the lateral thickness of the tubular vertical extension of the heater liner 52 (measured between the cylindrical inner sidewall and the cylindrical outer sidewall) and the vertical thickness of the horizontal extension of the heater liner 52 that overlaps the dielectric material layer on which the via openings 41 extend vertically may be the same.

[0093] Referring comprehensively to Figures 1 to 25, various embodiments of the present invention provide a device structure comprising: a tubular dielectric spacer 42 located within the range of via openings 41 in a dielectric material layer (such as the lower fourth wiring layer dielectric material layer 641); a heater liner 52 including a vertically extended portion laterally surrounded by the tubular dielectric spacer 42 and a horizontally extended portion overlapping the top surface segment of the dielectric material layer (such as the lower fourth wiring layer dielectric material layer 641); a phase change material portion 54 including a phase change material in contact with the top surface of the heater liner layer 52L; and a top electrode 56 in contact with the top surface of the phase change material portion 54.

[0094] In one embodiment, the heater liner 52 includes a planar horizontal surface segment PHSS that overlaps a dielectric material layer (such as the lower fourth wiring layer dielectric material layer 641), and further includes an annular convex segment ACSS adjacent to the periphery of an opening in the planar horizontal surface segment PHSS and overlapping a via opening 41, and the phase change material portion 54 is in contact with the annular convex segment ACSS.

[0095] In one embodiment, the vertically extended portion of the heater liner 52 includes a vertically extended seam S, and the top surface of the heater liner 52 includes an annular convex segment ACSS having a bottom tip adjacent to the top end of the vertically extended seam S.

[0096] In one embodiment, the phase change material portion 54 includes a vertically extended portion located within the central region of the via opening 41, and the vertically extended portion of the heater liner 52 includes a cylindrical inner side wall that contacts the vertically extended portion of the phase change material portion 54.

[0097] In one embodiment, the device structure includes at least one sidewall liner 58, the at least one sidewall liner 58 located on at least one sidewall of the phase change material portion 54, in contact with the sidewall of the horizontally extended portion of the heater liner 52, and comprising a material having higher electrical conductivity than the amorphous phase of the phase change material.

[0098] Figure 26 is a first flowchart showing a general process for manufacturing a device structure according to an embodiment of the present invention.

[0099] Referring to step 2610 and Figures 1-2, 17, and 22, a bottom electrode 38, a dielectric material layer (such as the lower fourth wiring layer dielectric material layer 641), and a via opening 41 extending through the dielectric material layer (such as the lower fourth wiring layer dielectric material layer 641) are formed, thereby exposing the top surface segment of the bottom electrode 38 directly below the via opening 41.

[0100] Referring to step 2620 and Figures 3, 4, 17, and 22, a tubular dielectric spacer 42 is formed in the peripheral region of the via opening 41, and the central part of the top segment is exposed below the gap laterally surrounded by the tubular dielectric spacer 42.

[0101] Referring to step 2630 and Figures 5, 17, and 16, and Figures 22 and 23, a continuous layer laminate (52L, 54L, 56L) including a heater liner layer 52L, a phase change material layer 54L containing a phase change material, and a top electrode material layer 56L is formed on a dielectric material layer (such as the lower fourth wiring layer dielectric material layer 641) and a tubular dielectric spacer 42.

[0102] Referring to step 2640 and Figures 16D, 19, 21, 24, and 25, a continuous layer laminate (52L, 54L, 56L) is patterned onto a laminate (52, 54, 56) that includes a heater liner 52, a phase change material section 54, and a top electrode 56.

[0103] Figure 27 is a second flowchart showing a general process for manufacturing a device structure according to an embodiment of the present invention.

[0104] Referring to step 2710 and Figures 1, 2, and 17, a bottom electrode 38, a dielectric material layer (such as the lower fourth wiring layer dielectric material layer 641), and a via opening 41 extending through the dielectric material layer (such as the lower fourth wiring layer dielectric material layer 641) are formed, thereby exposing the top surface segment of the bottom electrode 38 directly below the via opening 41.

[0105] Referring to step 2720 and Figures 5 and 17, the heater liner layer 52L is deposited within a portion of the volume of the via opening 41 and on top of the dielectric material layer (such as the lower fourth wiring layer dielectric material layer 641).

[0106] Referring to step 2730 and Figure 18, the horizontally extended portion of the heater liner layer 52L is recessed in the vertical direction.

[0107] Referring to step 2740 and Figure 19, a phase change material layer 54L containing the phase change material and a top electrode material layer 56L are deposited on the horizontally stretched portion of the heater liner layer 52L.

[0108] Referring to step 2750 and Figures 6 to 16D, 20, and 21, the top electrode material layer 56L, the phase change material layer 54L, and the heater liner layer 52L are patterned onto a laminate (52, 54, 56) including the heater liner 52, the phase change material portion 54, and the top electrode 56.

[0109] Within each phase-change memory cell, the heater liner 52 and sidewall liner 58 are used to set the resistance level of the high-resistance state of the phase-change memory cell. The combination of the heater liner 52 and sidewall liner 58 suppresses the effects of resistance drift of the phase-change material portion 54, reduces the power consumption of the phase-change memory cell, reduces the error rate during operation of the phase-change memory cell, and provides a reduction in the cell size of the phase-change memory cell. Generally, the thickness of the heater liner 52 and the thickness of the sidewall liner 58 are optimized to provide a wide variation in the resistance of the various resistance states of the phase-change memory cell, facilitating efficient multilevel cell (MLC) operation, i.e., cell operation in which the cell is programmed to have three or more resistance states. Thus, a large programming window is provided for the use of the phase-change memory cell 50 for MLC operation.

[0110] Embodiments of the present invention provide an advance in processing techniques for manufacturing phase-change memory devices by eliminating the need for a chemical mechanical polishing (CMP) process during the formation of heater elements, including the vertically extended portion of the heater liner 52. In one embodiment, each heater liner 52 is formed within the range of a via opening 41 and laterally surrounded by a tubular dielectric spacer 42. The horizontally extended portion of the heater liner 52 overlaps the via opening 41 on a dielectric material layer that extends vertically. The phase-change material portion 54 is positioned on the heater liner 52, and the top electrode 56 is in contact with the top surface of the phase-change material portion 54. The sequence of processing steps used to form the phase-change memory cell 50 reduces manufacturing complexity while improving thermal and cost efficiency. The phase-change memory cell 50 of the present invention minimizes heat loss by using a low thermal conductivity material for the tubular dielectric spacer 42 that laterally surrounds the vertically extended portion of the heater liner 52, which functions as a heater element. Enhanced thermal insulation for the heater element improves device performance for in-memory computing (CIM) applications.

[0111] The foregoing outlines the features of several embodiments so that those skilled in the art may better understand aspects of the present invention. Each embodiment described using the term "comprises" also essentially discloses that, unless expressly disclosed otherwise herein, the term "comprises" may be replaced with the terms "consists essentially of" or "consists of" in some embodiments. Whenever two or more elements are listed as alternatives in the same paragraph or in different paragraphs, a Markush group containing a list of two or more elements may also be implicitly disclosed. Whenever the auxiliary verb "can" is used in this disclosure to describe the formation of an element or the execution of a processing step, embodiments in which such an element or processing step is not performed are also expressly contemplated, insofar as the resulting apparatus or device can provide an equivalent result. Therefore, the auxiliary verb “can” applied to the formation of an element or the execution of a processing step should also be interpreted as “may” or “may, or may not” whenever the omission of the formation of such element or processing step can provide the same or equivalent result, and equivalent results include slightly better and slightly worse results. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to accomplish the same objectives and / or achieve the same advantages of the embodiments presented herein. Those skilled in the art will also recognize that such equivalent configurations do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention. [Industrial applicability]

[0112] This invention provides a novel method for forming a device structure and a device structure. [Explanation of Symbols]

[0113] 8: Circuit board 9: Semiconductor material layer 38:Bottom electrode 41: Via opening 42: Tubular dielectric spacer 42L: Dielectric spacer material layer 50: Phase-change memory cell 52: Heater liner 52': In-process heater liner 52L: Heater liner layer 54: Phase change material section 54': In-process phase change material section 54A: Amorphous phase change material section 54C: Crystalline phase change material section 54L: Phase change material layer 56:Top electrode 56': In-process top electrode 56L: Top electrode material layer 58: Side wall liner 58': In-process sidewall liner 58L: Sidewall liner layer 62: Top contact via structure 77: First patterned etching mask layer 79: Second patterned etching mask layer 100: Memory array area 300: Peripheral region 601: First dielectric material layer 610: First wiring layer dielectric material layer 612: Device Contact Via Structure 618: 1st metal wiring structure 620: Second wiring layer dielectric material layer 622: First Metal Via Structure 628:Second metal wiring structure 630: Third wiring layer dielectric material layer 632: Second Metal Via Structure 638:Third metal wiring structure 640: Fourth wiring layer dielectric material layer 641: Lower fourth wiring layer dielectric material layer 642: Third Metal Via Structure 643: Sealing dielectric layer 648: 4th metal wiring structure 700: Semiconductor Equipment 701: Programmable Transistor 702: Peripheral Transistors 720: Shallow trench separation structure 2610, 2620, 2630, 2640, 2710, 2720, 2730, 2740, 2750: Process ACSS: Annular convex segment hd1: 1st horizontal direction hd2: 2nd horizontal direction PHSS: Planar horizontal surface segment S: Vertical stretching seam

Claims

1. A method for forming a device structure, A bottom electrode, a dielectric material layer, and a via opening extending through the dielectric material layer are formed, and the top surface segment of the bottom electrode is exposed directly below the via opening. A tubular dielectric spacer is formed in the peripheral region of the via opening, so that the central part of the top surface segment is exposed below the gap laterally surrounded by the tubular dielectric spacer. A continuous layer laminate including a heater liner layer, a phase change material layer containing a phase change material, and a top electrode material layer is deposited on the dielectric material layer and the tubular dielectric spacer. The continuous layer laminate is patterned to form a laminate including a heater liner, a phase change material portion, and a top electrode. Methods that include...

2. The heater liner layer is A vertically extended portion deposited in the void within the range of the tubular dielectric spacer, Including a horizontally stretched portion deposited on the top surface of the dielectric material layer, The method according to claim 1.

3. A vertical stretch seam is formed at the center of the vertical stretch portion of the heater liner layer. The method according to claim 2.

4. The phase change material layer includes a vertically stretched portion, and the vertically stretched portion has a cylindrical side wall that contacts the inner cylindrical side wall of the tubular dielectric spacer. The method according to claim 2.

5. A dielectric spacer material layer is deposited within the peripheral region of the via opening and on the dielectric material layer. The dielectric spacer material layer is anisotropically etched, It further includes, The remaining vertically stretched portion of the dielectric spacer material layer filling the peripheral region of the via opening constitutes the tubular dielectric spacer. The method according to claim 1.

6. The heater liner layer is deposited on the central portion of the top surface segment of the bottom electrode, The phase change material layer is deposited on the planar horizontal surface segment of the heater liner layer, and the planar horizontal surface segment of the heater liner layer overlaps with a horizontal plane including the top surface of the dielectric material layer. The method according to claim 1.

7. When the heater liner layer is deposited, the heater liner layer Includes a planar horizontal surface segment that overlaps the dielectric material layer, The invention further includes an annular convex segment adjacent to the periphery of the opening within the planar horizontal surface segment and overlapping the via opening, The phase change material layer is deposited directly on the annular convex segment. The method according to claim 1.

8. The aforementioned heater liner layer is deposited by a conformal deposition process. The maximum width of the void is less than half the thickness of the heater liner layer. The vertically stretched seam is formed in the center of the void filled by the vertically stretched portion of the heater liner layer. The method according to claim 7.

9. The aforementioned heater liner layer is deposited by a conformal deposition process. The maximum width of the aforementioned void is greater than half the thickness of the heater liner layer. After the formation of the heater liner layer, the unfilled portion of the void exists within the volume of the via opening. The vertically extended portion of the phase-change material layer is deposited within the range of the unfilled portion of the void. The method according to claim 7.

10. The method further includes forming at least one sidewall liner by depositing and patterning a sidewall liner material, At least one of the sidewall liners is formed on at least one sidewall of the laminate, At least one of the sidewall liners includes a material having higher electrical conductivity than the amorphous phase of the phase change material. The method according to claim 1.

11. A method for forming a device structure, A bottom electrode, a dielectric material layer, and a via opening extending through the dielectric material layer are formed so that the top surface segment of the bottom electrode is exposed directly below the via opening. A heater liner layer is deposited within a portion of the volume of the via opening and on the dielectric material layer. The horizontally extended portion of the heater liner layer is recessed in the vertical direction, A phase change material layer containing a phase change material and a top electrode material layer are deposited on the horizontally extended portion of the heater liner layer, The top electrode material layer, the phase change material layer, and the heater liner layer are patterned onto a laminate including the heater liner, the phase change material portion, and the top electrode. Methods that include...

12. The method further includes forming a tubular dielectric spacer in the peripheral region of the via opening, such that the central portion of the top surface segment is exposed below the gap laterally surrounded by the tubular dielectric spacer, A portion of the volume of the via opening includes the volume of the void within the range of the tubular dielectric spacer. The method according to claim 11.

13. Recessing the horizontally stretched portion of the heater liner layer in the vertical direction includes performing an etch-back process to etch the material of the heater liner layer. The method according to claim 11.

14. A vertical extension seam is formed within the range of the vertical extension portion of the heater liner layer deposited within the range of a portion of the volume of the via opening. The method according to claim 11.

15. The heater liner layer is A planar horizontal surface segment overlapping the dielectric material layer, An annular convex segment including a bottom tip point adjacent to the periphery of the opening in the planar horizontal surface segment and adjacent to the apex of the vertically extending seam, It is formed to have, Recessing the horizontally extended portion of the heater liner layer in the vertical direction includes performing an etch-back process that simultaneously recesses the horizontally extended portion of the heater liner layer in the vertical direction and the annular convex segment of the heater liner layer in the vertical direction. The method according to claim 14.

16. A tubular dielectric spacer located within the range of via openings in the dielectric material layer, A heater liner including a vertically stretched portion surrounded laterally by the tubular dielectric spacer, and a horizontally stretched portion overlapping the top surface segment of the dielectric material layer, A phase change material portion including a phase change material that contacts the top surface of the heater liner, The top electrode in contact with the top surface of the phase change material portion, A device structure that includes this.

17. The heater liner is, Includes a planar horizontal surface segment that overlaps the dielectric material layer, The invention further includes an annular convex segment adjacent to the periphery of the opening within the planar horizontal surface segment and overlapping the via opening, The phase change material portion is in contact with the annular convex segment. The device structure according to claim 16.

18. The vertically extended portion of the heater liner includes a vertically extended seam. The top surface of the heater liner includes an annular convex segment having a bottom tip adjacent to the top end of the vertically extending seam. The device structure according to claim 16.

19. The phase change material portion includes a vertically extended portion located within the central region of the via opening, The vertically extended portion of the heater liner includes a cylindrical inner side wall that contacts the vertically extended portion of the phase change material portion. The device structure according to claim 16.

20. Further including at least one sidewall liner, The at least one sidewall liner is located on at least one sidewall of the phase change material portion and is in contact with the sidewall of the horizontally extended portion of the heater liner. The at least one sidewall liner comprises a material having higher electrical conductivity than the amorphous phase of the phase change material. The device structure according to claim 16.

Images