Semiconductor equipment

Abstract

We provide semiconductor devices capable of high-speed operation. We also provide highly reliable semiconductor devices. ru. [Solution] A crystalline oxide semiconductor is used for the semiconductor layer of the transistor, and the semiconductor layer It forms a channel-forming region, a source region and a drain region. The formation of the region involves using a channel protection layer as a mask and applying one of either a noble gas or hydrogen to the semiconductor layer. Alternatively, multiple elements can be added by ion doping or ion implantation. conduct.

Description

Technical Field

[0001] Relates to a semiconductor device having a circuit including semiconductor elements such as transistors and a method of manufacturing the same . For example, a power device mounted on a power supply circuit, a memory, a thyristor, a converter, an image sensor, and other semiconductor integrated circuits, an electro-optical device typified by a liquid crystal display panel, a light-emitting display device having a light-emitting element, and other electronic devices mounted with such components as parts .

[0002] In addition, in this specification, a semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. An electro-optical device, a light-emitting display device, a semiconductor circuit, and an electronic device are all semiconductor devices .

Background Art

[0003] As typified by a liquid crystal display device, transistors formed on a glass substrate or the like are composed of amorphous silicon, polycrystalline silicon, or the like. Although a transistor using amorphous silicon has a low field-effect mobility, it can cope with the enlargement of the area of the glass substrate . In addition, a transistor using polycrystalline silicon has a high field-effect mobility but has a drawback that it is not suitable for the enlargement of the area of the glass substrate .

[0004] ​​​​​​​​​​​​​​Patent Document 3 describes a staggered transistor using an oxide semiconductor, and the source region and A highly conductive nitrogen is used as a buffer layer between the drain region and the source and drain electrodes. An oxide semiconductor containing an element is provided, and the oxide semiconductor and the source electrode and drain electrode are connected. A technology for reducing resistance has been disclosed.

[0006] Furthermore, Non-Patent Document 1 describes a self-treatment method in which exposed oxide semiconductors are subjected to argon plasma treatment. The matching process reduces the resistivity of the oxide semiconductor in that area, thereby reducing the source region and drain. An oxide semiconductor transistor with an in-region is disclosed.

[0007] However, this method exposes the oxide semiconductor surface and performs argon plasma treatment. By doing so, the oxide semiconductor in the source and drain regions is also simultaneously processed. The material is thinned, and the source and drain regions are reduced in thickness (see Figure 8 in Non-Patent Document 1). As a result, the resistance of the source and drain regions increases, and over-aging occurs due to the thinning of the layer. The probability of defective products occurring due to the manufacturing process also increases.

[0008] This phenomenon occurs when the ion species used in plasma treatment of oxide semiconductors have a large atomic radius. This becomes particularly noticeable.

[0009] Of course, this is not a problem if the oxide semiconductor layer is of sufficient thickness, but the channel When the length is 200 nm or less, in order to prevent short channel effects, the channel portion The thickness of the oxide semiconductor layer is required to be 20 nm or less, preferably 10 nm or less. When dealing with such thin oxide semiconductor layers, the plasma treatment described above is preferred. That's not good. [Prior art documents] [Patent Documents]

[0010] [Patent Document 1] Japanese Patent Publication No. 2007-123861 [Patent Document 2] Japanese Patent Publication No. 2007-96055 [Patent Document 3] Japanese Patent Publication No. 2010-135774 [Non-patent literature]

[0011] [Non-Patent Document 1] S. Jeon et al. “180nm Gate Length Amorphous InGaZnO Thin Film Transistor for High Density Image Sensor Application”, IEDM Tech. Dig., p.504, 2010. [Overview of the Initiative] [Problems that the invention aims to solve]

[0012] One of the objectives is to provide a semiconductor device capable of high-speed operation.

[0013] We propose a semiconductor device using transistors that are less susceptible to fluctuations in electrical characteristics due to short-channel effects. One of the objectives is to provide it.

[0014] Furthermore, the source and drain regions are formed through a self-aligning process, making it easier to miniaturize the semiconductor. One of the objectives is to provide a conductive device.

[0015] Furthermore, by forming a source region and drain region with lower resistance than the channel region, This reduces the contact resistance between the source and drain electrodes, improving the on-current. One of the objectives is to provide a semiconductor device.

[0016] One of our objectives is to provide highly reliable semiconductor devices. [Means for solving the problem]

[0017] One aspect of the present invention comprises a gate electrode, a gate insulating layer, and a crystalline oxide semiconductor layer. It has a channel protection layer, a gate insulating layer is formed on the gate electrode, and oxidation is present on the gate insulating layer. A material semiconductor layer is formed, a channel protection layer is formed on the oxide semiconductor layer, and the oxide semiconductor layer It has a first oxide semiconductor region and a pair of second oxide semiconductor regions, and a pair of second oxide The oxide semiconductor region is formed sandwiching the first oxide semiconductor region. It is characterized by being superimposed on the gate electrode via a gate insulating layer and in contact with the channel protection layer. This is a semiconductor device.

[0018] Furthermore, one aspect of the present invention comprises a crystalline oxide semiconductor layer, a gate insulating layer, and a gate electric The oxide semiconductor layer has electrodes and comprises a first oxide semiconductor region and a pair of second oxide semiconductor regions. The region has a pair of second oxide semiconductor regions, which are formed flanking the first oxide semiconductor region. The first oxide semiconductor region is superimposed on the gate electrode via a gate insulating layer. It is a semiconductor device that is characterized by its features.

[0019] A non-single-crystal semiconductor is used for the oxide semiconductor layer.

[0020] The first oxide semiconductor region is CAAC-OS (C Axis Aligned Crystal talline Oxide Semiconductor). CAAC-OS The c-axis is parallel to the normal vector of the surface being formed on the CAAC-OS or the normal vector of the surface. The atoms are aligned in a particular direction and have a triangular or hexagonal arrangement when viewed from a direction perpendicular to the ab plane. When viewed from a direction perpendicular to the c-axis, the metal atoms are arranged in layers, or the metal atoms and oxygen atoms are arranged in layers. It has a crystalline portion.

[0021] The second oxide semiconductor region contains at least one element from among noble gases or hydrogen (H). 5 x 10 19 atoms / cm 3 The above is 1 x 10 22 atoms / cm 3 Contains at the following concentrations nothing.

[0022] Oxide semiconductors can contain two or more elements selected from In, Ga, Sn, and Zn. Cut.

[0023] The first oxide semiconductor region becomes the channel formation region of the transistor, and a pair of second oxides The semiconductor region consists of the source and drain regions of the transistor.

[0024] In a bottom-gate transistor, the source region and drain region maintain the channel. This can be formed by using a protective layer as a mask and adding a dopant to the oxide semiconductor layer. The Nel protective layer is formed to protect the back channel portion of the active layer, and contains silicon oxide. Materials selected from silicon nitride, aluminum oxide, aluminum nitride, etc., are used in single layers. It is preferable to use them in a stacked manner.

[0025] In a top-gate transistor, the source region and drain region are the gate electrode. It can be formed by using a mask and adding a dopant to an oxide semiconductor layer.

[0026] The addition of dopants to form the source and drain regions of a transistor is ion Doping methods or ion implantation methods can be used. The method involves using one or more elements from among noble gases or hydrogen (H). This can be done. In addition, oxides can be produced by ion doping or ion implantation. When dopants are added to a semiconductor layer, the dopant passes through the insulating layer to the oxide semiconductor layer. By adding it, excessive damage to the oxide semiconductor layer during dopant doping is reduced. This is possible. Also, the interface between the oxide semiconductor layer and the insulating layer is kept clean, so transient The characteristics and reliability of the stan are improved. Furthermore, the dopant doping depth (doping region) becomes easier to control. This allows for precise dopant addition to the oxide semiconductor layer.

[0027] Increasing the concentration of the added dopant increases the carrier density in the oxide semiconductor region. This is possible, but if the concentration of the added dopant is too high, it will inhibit carrier movement and conduction. This will lead to a decrease in sexual performance.

[0028] By using an oxide semiconductor with a dopant added in the source and drain regions, This reduces the bending of the band edge in the channel-forming region where the dopant is not added. It is effective. On the other hand, when the source region and drain region are made of a metallic material, oxide semiconductor The bending at the band edge of the channel becomes non-negligible, resulting in a shorter effective channel length. This can happen. This tendency is more pronounced when the transistor channel length is shorter. ru.

[0029] An acid with reduced impurities such as moisture or hydrogen that serves as an electron donor and has been purified to a high purity The purified oxide semiconductor (purified OS) is then supplied with oxygen to reduce oxygen vacancies in the oxide semiconductor, thereby obtaining a type-i (intrinsic semiconductor) or an oxide semiconductor that is as close as possible to type-i (substantially type-i). Therefore, a transistor using an oxide semiconductor that is type-i or substantially type-i formed in the semiconductor layer where the channel is formed has the characteristic that the off-current is extremely low. Specifically, the purified oxide semiconductor has a hydrogen concentration measured by secondary ion mass spectrometry (SIMS) of less than 5×10 / cm , preferably less than 1×10 / cm , more preferably less than 5×10 / cm , and even more preferably less than 1×10 18 / cm 3 . Also, the carrier density of the type-i or substantially type-i oxide semiconductor layer that can be measured by Hall effect measurement is less than 1×10 / cm 18 , preferably less than 1×10 3 / cm 17 , and even more preferably less than 1×10 3 [[ID=​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​Here, let's discuss SIMS analysis of hydrogen concentration in oxide semiconductors. SIMS analysis In principle, it is possible to accurately obtain data near the sample surface and near the lamination interface with films of different materials. It is known to be difficult to do so. Therefore, the fraction of hydrogen concentration in the film in the thickness direction When analyzing fabric with SIMS, extreme fluctuations in values ​​occur within the range where the target membrane exists. In the region where a nearly constant value is obtained, the average value is adopted as the hydrogen concentration. When the thickness of the film being measured is small, it is affected by the hydrogen concentration in the adjacent film, and is almost In some cases, it may not be possible to find a region where a consistent value can be obtained. In this case, in the region where the film exists... The maximum or minimum hydrogen concentration in the film is adopted as the hydrogen concentration in the film. In the region where the film exists, there is a mountain-shaped peak with a maximum value and a valley-shaped peak with a minimum value. If no peak is present, the value at the inflection point is used as the hydrogen concentration. [Effects of the Invention]

[0031] According to one aspect of the present invention, an oxide semiconductor having good electrical properties and being easily miniaturized is used. We can provide semiconductor devices.

[0032] Furthermore, the present invention provides a semiconductor device that is less susceptible to fluctuations in electrical characteristics due to short-channel effects.

[0033] Furthermore, by adding a dopant to the oxide semiconductor through the insulating layer, This prevents the body from becoming thin and keeps the interface between the oxide semiconductor and the insulating layer clean, thus providing a special feature for semiconductor devices. It can enhance reliability and trustworthiness. [Brief explanation of the drawing]

[0034] [Figure 1] A top view and a cross-sectional view illustrating one aspect of the present invention. [Figure 2] A top view and a cross-sectional view illustrating one aspect of the present invention. [Figure 3] A cross-sectional view illustrating one aspect of the present invention. [Figure 4] A cross-sectional view illustrating one aspect of the present invention. [Figure 5] A top view and a cross-sectional view illustrating one aspect of the present invention. [Figure 6] A top view and a cross-sectional view illustrating one aspect of the present invention. [Figure 7] A cross-sectional view illustrating one aspect of the present invention. [Figure 8] A cross-sectional view illustrating one aspect of the present invention. [Figure 9] A diagram illustrating the band structure of oxide semiconductors and metallic materials. [Figure 10] A circuit diagram illustrating one aspect of the present invention. [Figure 11] A circuit diagram illustrating one aspect of the present invention. [Figure 12] A circuit diagram illustrating one aspect of the present invention. [Figure 13] A circuit diagram illustrating one aspect of the present invention. [Figure 14] This is a block diagram and a partial circuit diagram showing a specific example of a CPU. [Figure 15] A diagram illustrating the crystal structure of oxide materials. [Figure 16] A diagram illustrating the crystal structure of oxide materials. [Figure 17] A diagram illustrating the crystal structure of oxide materials. [Figure 18] A diagram illustrating the crystal structure of oxide materials. [Modes for carrying out the invention]

[0035] Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is described below. The present invention is not limited to any particular form or detail and may be described in any way without departing from the spirit and scope of the present invention. Those skilled in the art will readily understand that the invention can be modified in various ways. Therefore, the present invention is as shown below. This is not to be interpreted as being limited to the description of the form of application. Furthermore, the present invention described below... In the configuration, the same reference numeral is used for identical parts or parts with similar functions across different drawings. This is used in common, and its repeated explanation will be omitted.

[0036] Furthermore, the position, size, and scope of each component shown in the drawings, etc., are for ease of understanding. The position, size, and range of the edges may not be shown. Therefore, the disclosed invention is not necessarily However, this is not limited to the location, size, and scope disclosed in drawings, etc.

[0037] Furthermore, the terms "first," "second," "third," etc. used in this specification are used to avoid confusion of constituent elements. This is attached to the number and does not limit it numerically. Therefore, for example, "the first" can be written as " This can be explained by replacing it with "the second" or "the third," etc., as appropriate.

[0038] A transistor is a type of semiconductor device used to amplify current and voltage, and to control conduction or non-conductivity. It is possible to realize controlled switching operations, etc. Transistors in this specification are , IGFET(Insulated Gate Field Effect Trans istors and thin-film transistors (TFTs) ) includes.

[0039] Furthermore, the "source" and "drain" functions of transistors are related to transistors with different polarities. When adopting a circuit, or when the direction of current changes during circuit operation, the configuration may be reversed. Therefore, in this specification, the terms "source" and "drain" are interchangeable. It may be used.

[0040] Furthermore, in this specification, the terms "electrode" and "wiring" do not limit the functionality of these components. It is not fixed. For example, "electrode" can be used as part of "wiring". The reverse is also true. Furthermore, the terms "electrode" and "wiring" can refer to multiple "electrodes" and "wiring". This also includes cases where the "lines" are formed as a single unit.

[0041] (Embodiment 1) This embodiment describes a transistor using an oxide semiconductor as the channel and a method for manufacturing the same. Next, we will explain using Figures 1 to 4.

[0042] Figure 1(A) illustrates the structure of a transistor 100, which is one form of semiconductor device configuration. This is a top view, and Figure 1(B) explains the layered structure of the area indicated by the dashed line A1-A2 in Figure 1(A). This is a cross-sectional view. Note that the substrate and insulating layer are omitted in Figure 1(A). .

[0043] The transistor 100 shown in Figure 1 has a base layer 102 formed on the substrate 101, and the base layer 10 An oxide semiconductor layer 103 is formed on 2. Also, a gate is formed on the oxide semiconductor layer 103. An insulating layer 104 is formed, and a gate electrode 105 is formed on the gate insulating layer 104. Furthermore, insulating layers 107 and 108 are formed on the gate electrode 105, and on the insulating layer 108 Source electrode 110a and drain electrode 110b are formed. The drain electrode 110b is provided in the gate insulating layer 104, insulating layer 107, and insulating layer 108. The oxide semiconductor layer 103 is electrically connected through the provided contact hole 109. Yes, they are.

[0044] The oxide semiconductor layer 103 is superimposed on the gate electrode 105 via the gate insulating layer 104. The flannel-forming region 103c and the source region 103a which is electrically connected to the source electrode 110a It has a drain region 103b that is electrically connected to the drain electrode 110b.

[0045] Furthermore, the gate electrode 105 consists of a gate electrode 105a that is in contact with the gate insulating layer 104, and the gate It has a gate electrode 105b stacked on the electrode 105a.

[0046] In Figure 1(A), the contact hole 109 is located in the source region 103a and the drain region. The example shows multiple units provided on each of the region 103b, but the source region 103a and drain are also shown. Alternatively, one may be provided on each region 103b. Contact resistance of drain region 103a, and contact between drain electrode 110b and drain region 103b To reduce resistance, the contact hole 109 is made as large as possible, and the contact hole 1 It is preferable to increase the number of 09s.

[0047] The transistor 140 shown in Figure 2 has the same configuration as transistor 100, plus a gate electrode 10 The side of 5 has a sidewall 111, and the oxide semiconductor layer 103 has a sidewall 111 The region overlapping with it has low-concentration region 103d and low-concentration region 103e. Region 103d is formed between the channel-forming region 103c and the source region 103a, and is a low-concentration region Region 103e is formed between the channel-forming region 103c and the drain region 103b. Figure 2(A) is a top view illustrating the configuration of transistor 140, and Figure 2(B) is a top view illustrating the configuration of transistor 140. (A) is a cross-sectional view illustrating the layered structure of the region indicated by the dashed line B1-B2.

[0048] By providing low-concentration regions 103d and 103e, the transistor characteristics are improved. This can reduce the negative shift in threshold voltage caused by short-channel effects.

[0049] Transistors 100 and 140 are forms of top-gate transistors. It is a state.

[0050] Next, the method for fabricating the transistor 100 shown in Figure 1 will be explained using Figures 3 and 4. Figures 3 and 4 correspond to the cross-section of the area indicated by the dashed line A1-A2 in Figure 1(A). ru.

[0051] First, a base layer 102 is applied to the substrate 101 with a thickness of 50 nm to 300 nm, preferably 100 nm. It is formed with a thickness of m or more and 200 nm or less. The substrate 101 is a glass substrate, a ceramic substrate In addition, a plastic substrate or the like with sufficient heat resistance to withstand the processing temperature of this manufacturing process is used. This is possible. Furthermore, if light transmission is not required for the substrate, a metal substrate such as stainless steel alloy can be used. A material with an insulating layer on its surface may also be used. As a glass substrate, for example, barium glass Alkaline glass such as borosilicate glass, aluminoborosilicate glass, or aluminosilicate glass It is recommended to use a re-glass substrate. Other substrates such as quartz and sapphire can also be used. Also, single-crystal semiconductor substrates such as silicon and silicon carbide, polycrystalline semiconductor substrates, and silicon It is also possible to apply compound semiconductor substrates such as germanium, SOI substrates, etc. A substrate 101 may be one on which semiconductor elements are provided.

[0052] Substrate 102 consists of aluminum nitride, aluminum oxide, aluminum nitride oxide, and nitrate oxide. Aluminum oxide, silicon nitride, silicon oxide, silicon nitride or silicon oxide nitride The selected material can be formed as a single layer or in layers, and the material from the substrate 101 It has the function of preventing the diffusion of pure elements. In this specification, nitride oxides refer to: Its composition is such that the nitrogen content is higher than the oxygen content, and oxidized nitrides are composed of such compounds. This refers to substances in which the oxygen content is greater than the nitrogen content. Note that the content of each element is, for example, Rutherford Backscattering (RBS) Measurements can be taken using methods such as ng Spectrometry.

[0053] The base layer 102 can be prepared using methods such as sputtering, CVD, coating, or printing, as appropriate. In this embodiment, a laminate of silicon nitride and silicon oxide is used as the base layer 102. Specifically, silicon nitride is formed on the substrate 101 to a thickness of 50 nm, and the silicon nitride A layer of silicon oxide is formed on the concrete to a thickness of 150 nm. Note that phosphorus (P) is present in the base layer 102. It is also acceptable for the material to be doped with ) or boron (B).

[0054] Furthermore, by including halogen elements such as chlorine and fluorine in the base layer 102, the substrate 101 The function of preventing the diffusion of impurity elements from the substrate can be further enhanced. The concentration of halogen elements is obtained by analysis using SIMS (Secondary Ion Mass Spectrometer). At the concentration peak, 1 × 10 15 / cm 3 The above 1 x 10 20 / cm 3 The following Yes.

[0055] Furthermore, the base layer 102 may be made of a material that releases oxygen when heated. "Emitted as primary" means TDS (Thermal Desorption Spectrometer) In scopy (temperature-induced desorption gas spectroscopy) analysis, the amount of oxygen released, converted to oxygen atoms, was 1. 0 x 10 18 atoms / cm 3 Preferably 3.0 × 10 20 atoms / cm 3 This means that it is as described above.

[0056] Here, we will explain the method for measuring the amount of oxygen released in terms of oxygen atoms using TDS analysis, as follows: I will explain it to them.

[0057] The amount of gas released during TDS analysis is proportional to the integral value of the spectrum. Therefore, insulation The amount of gas released is calculated by comparing the integral value of the layer spectrum with the ratio to the reference value of the standard sample. It is possible. The reference value of a standard sample is the integral of the spectrum of a sample containing a given atom. This is the ratio of the atomic density to the value.

[0058] For example, the TDS analysis results of a silicon wafer containing hydrogen of a predetermined density, which is a standard sample, and From the TDS analysis results of the insulating layer, the amount of oxygen molecules released from the insulating layer (N O2 ) can be found using formula 1. This is possible. Here, all of the spectra detected at mass number 32 obtained by TDS analysis Let's assume it originates from an oxygen molecule. CH3OH is an example with a mass number of 32, but is it possible that it exists? Acids with low acidity will not be considered here. Also, acids with a mass number of 17, which are isotopes of the oxygen atom. Regarding elementary atoms and oxygen molecules containing oxygen atoms with a mass number of 18, the abundance ratio in nature is It is too small to be considered.

[0059] N O2 =N H2 / SH2 ×S O2 ×α (Equation 1)

[0060] N H2 This value represents the density of hydrogen molecules detached from the standard sample. H2 The standard test This is the integral value of the spectrum when the sample is analyzed using TDS. Here, the reference value of the standard sample is N H2 / S H2 Let's assume that. S O2 This is the integral value of the spectrum obtained when the insulating layer is analyzed by TDS. α is a coefficient that affects the spectral intensity in TDS analysis. (See details of Equation 1.) For further information, see Japanese Patent Publication No. 6-275697. The amount of oxygen released from the insulating layer is Using the EMD-WA1000S / W temperature-controlled desorption analyzer manufactured by Denshi Kagaku Co., Ltd., a standard sample and and 1 x 10 16 atoms / cm 3 Measurements were taken using a silicon wafer containing hydrogen atoms. .

[0061] Furthermore, in TDS analysis, some oxygen is detected as oxygen atoms. Oxygen molecules and oxygen atoms The ratio of these can be calculated from the ionization rate of oxygen molecules. Note that α above represents the oxygen component. Because it includes the ionization rate of the oxygen atom, by evaluating the amount of oxygen molecule released, the amount of oxygen atom released can be determined. Even if it's there, it can still be estimated.

[0062] Note N O2 This is the amount of oxygen molecules released. In the insulating layer, when converted to oxygen atoms, The amount of oxygen released is twice the amount of oxygen molecules released.

[0063] In the above configuration, the insulating layer that releases oxygen upon heating is silicon oxide (S) with an excess of oxygen. iO X (X>2)) is also acceptable. Silicon oxide (SiO2) has an excess of oxygen.X (X>2)) This refers to a material that contains more than twice the number of oxygen atoms per unit volume compared to the number of silicon atoms. The number of silicon atoms and oxygen atoms per unit volume was measured using the Rutherford backscattering method. It is a value.

[0064] Oxygen is supplied from the underlying layer to the oxide semiconductor, which affects the interface state between the underlying layer and the oxide semiconductor. This can reduce the amount of charge that may be generated due to the operation of transistors, etc. This can suppress the trapping of the underlying layer and oxide semiconductor interface, resulting in inferior electrical properties. This allows us to obtain transistors with less oxidation.

[0065] Furthermore, electric charge can be generated due to oxygen vacancies in oxide semiconductors. Generally speaking, oxide semiconductors When the body experiences oxygen deficiency, some oxygen acts as a donor, generating electrons that act as carriers. As a result, transients occur. The threshold voltage of the sta is shifted in the negative direction. This tendency is observed on the back channel side. This is particularly evident in the resulting oxygen deficiency. Note that in this specification, back channels refer to oxidation In semiconductor materials, this refers to the vicinity of the interface between the underlying layers. This occurs when sufficient oxygen is released from the underlying layer into the oxide semiconductor. As a result, the oxide semiconductor, which is a factor that causes the threshold voltage to shift in the negative direction, It can compensate for oxygen deficiency.

[0066] In other words, when an oxygen vacancy occurs in the oxide semiconductor, the charge at the interface between the underlying layer and the oxide semiconductor... Since it becomes difficult to suppress the capture of these organisms, the underlying layer is an insulating layer that releases oxygen when heated. By providing this, the interface states between the oxide semiconductor and the underlying layer, as well as the oxygen vacancies in the oxide semiconductor, are maintained. This reduces the effect of charge trapping at the interface between the oxide semiconductor and the underlying layer. Cut.

[0067] Furthermore, the base layer 102 uses an insulating material containing the same components as the oxide semiconductor to be formed later. It may be. If the base layer 102 is a stack of different layers, the layer in contact with the oxide semiconductor is An insulating material containing the same components as an oxide semiconductor would suffice. Such a material is an oxide semiconductor. It has good compatibility with it, and by using it in the base layer 102, the state of the interface with the oxide semiconductor is improved. This is because it can be kept in good condition. Here, "components of the same type as oxide semiconductors" refers to oxides. This refers to one or more elements selected from the constituent elements of a semiconductor. For example, an oxide semiconductor. When it is composed of an In-Ga-Zn oxide semiconductor material, an aqueous semiconductor containing the same type of component is used. Examples of edge materials include gallium oxide.

[0068] Next, an oxide semiconductor is formed on the underlayer 102. As a pretreatment, the oxide semiconductor is treated In order to minimize the presence of hydrogen, hydroxyl groups, and water, in the preheating chamber of the film deposition apparatus The substrate 101 is preheated to remove impurities such as hydrogen and moisture adsorbed on the substrate 101 and the underlying layer 102. It is preferable to detach and exhaust the fluid. The exhaust means provided in the preheating chamber is a cryopump. This is preferable. However, this preheating process can be omitted. Also, this preheating is The same procedure may be performed on the substrate 101 before the deposition of the underlayer 102.

[0069] The oxide semiconductor must contain at least indium (In) or zinc (Zn). It is preferable that it contains In and Zn. Furthermore, a tra As a stabilizer to reduce variations in the electrical characteristics of the generators, in addition to those, It is preferable to have lium (Ga). It is also preferable to have tin (Sn) as a stabilizer. It is preferable to have hafnium (Hf) as a stabilizer. It is preferable to have aluminum (Al) as a stabilizer.

[0070] Also, other stabilizers include lanthanides such as lanthanum (La) and cerium ( Ce, praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Mium (Ho), Erbium (Er), Thulium (Tm), Ytterbium (Yb), Lu It may contain one or more types of tecium (Lu).

[0071] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and the oxide of binary metals. These are In-Zn oxides, Sn-Zn oxides, Al-Zn oxides, and Zn-Mg oxides. Oxides, Sn-Mg oxides, In-Mg oxides, In-Ga oxides, ternary metals In-Ga-Zn oxides (also written as IGZO), In-Al-Zn oxides Oxides, In-Sn-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn acids oxides, Sn-Al-Zn oxides, In-Hf-Zn oxides, In-La-Zn oxides Materials, In-Ce-Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides In-Sm-Zn oxides, In-Eu-Zn oxides, In-Gd-Zn oxides, In-Tb-Zn oxides, In-Dy-Zn oxides, In-Ho-Zn oxides, I n-Er-Zn oxides, In-Tm-Zn oxides, In-Yb-Zn oxides, In -Lu-Zn ​​oxides, In-Sn-Ga-Zn oxides which are oxides of quaternary metals, I n-Hf-Ga-Zn oxides, In-Al-Ga-Zn oxides, In-Sn-Al- Using Zn-based oxides, In-Sn-Hf-Zn-based oxides, and In-Hf-Al-Zn-based oxides It is possible to be there.

[0072] The oxide semiconductor layer is preferably an oxide semiconductor containing In, more preferably In, It is an oxide semiconductor containing Ga.

[0073] Here, for example, In-Ga-Zn oxides are composed of indium (In) and gallium (Ga ), it means an oxide containing zinc (Zn), and the ratio of In, Ga, and Zn is not specified. Furthermore, it may contain metallic elements other than In, Ga, and Zn.

[0074] Furthermore, the oxide semiconductor layer has the chemical formula InMO3(ZnO) m Thin films denoted as (m>0) It can be used. Here, M is selected from Sn, Zn, Ga, Al, Mn, and Co. It shows one or more metallic elements. Also, as an oxide semiconductor, In3SnO5(Zn O) n Materials denoted as (n>0) may also be used.

[0075] For example, In:Ga:Zn = 1:1:1 (= 1 / 3:1 / 3:1 / 3) or In:G In-Ga-Zn acid with an atomic ratio of a:Zn = 2:2:1 (= 2 / 5:2 / 5:1 / 5) Oxides or oxides with a similar composition can be used. Alternatively, In:Sn:Zn=1 :1:1(=1 / 3:1 / 3:1 / 3), In:Sn:Zn=2:1:3(=1 / 3:1 / 6:1 / 2) or In:Sn:Zn=2:1:5 (=1 / 4:1 / 8:5 / 8) It is preferable to use In-Sn-Zn oxides with a specific atomic ratio or oxides with a similar composition.

[0076] However, this is not limited to these, and depends on the required semiconductor characteristics (mobility, threshold, variability, etc.) A suitable composition should be used accordingly. Furthermore, in order to obtain the required semiconductor properties, Carrier density, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic bond distance, density It is preferable to make the following appropriate.

[0077] For example, high mobility can be obtained relatively easily with In-Sn-Zn oxides. However, Furthermore, even with In-Ga-Zn oxides, mobility can be increased by reducing the bulk defect density. It is possible to do so.

[0078] For example, if the atomic ratio of In, Ga, and Zn is In:Ga:Zn=a:b:c(a+b+ The composition of an oxide with c=1 is such that the atomic ratio is In:Ga:Zn=A:B:C(A+B+C The composition of the oxide in the vicinity of =1) is such that a, b, and c are (a-A) 2 +(b-B) 2 +(c―C) 2 ≤r 2 This means that the following conditions are met, and r can be set to, for example, 0.05. The same applies to other oxides. .

[0079] Oxide semiconductors can be single crystals or non-single crystals. In the latter case, they can be amorphous or polycrystalline. But that's fine too. Also, even if the structure contains crystalline parts within the amorphous material, it can be non-amorphous. But that's fine.

[0080] Amorphous oxide semiconductors can be made relatively easily to obtain a flat surface, This can reduce interfacial scattering when fabricating transistors, and it can be done relatively easily and relatively high You can obtain a high degree of mobility.

[0081] Furthermore, in crystalline oxide semiconductors, bulk defects can be reduced even further, and surface By improving the flatness, it is possible to obtain mobility higher than that of an amorphous oxide semiconductor. To improve surface flatness, it is preferable to form an oxide semiconductor on a flat surface. Specifically, the average surface roughness (Ra) is 1 nm or less, preferably 0.3 nm or less, more preferably Alternatively, it is preferable to form it on a surface with a wavelength of 0.1 nm or less. Note that Ra is measured using an atomic force microscope (AFM). It can be evaluated using an Atomic Force Microscope.

[0082] As an oxide semiconductor with crystalline properties, CAAC-OS (C Axis Aligned) Crystalline Oxide Semiconductor is preferred. AAC-OS is neither a perfect single crystal nor a perfect amorphous material. CAAC-OS is non This oxide semiconductor has a crystalline-amorphous multiphase structure with a crystalline portion in the crystalline phase. These are often small enough to fit within a cube with sides less than 100 nm. Microscope (TEM: Transmission Electron Microscope) In the observation image by e), the boundary between the amorphous and crystalline parts contained in CAAC-OS is not clear. No. Also, TEM indicates that CAAC-OS has grain boundaries (also called grain boundaries). ) cannot be confirmed. Therefore, CAAC-OS suppresses the decrease in electron mobility caused by grain boundaries. They are controlled.

[0083] The crystalline portion contained in CAAC-OS has a c-axis that is aligned with the normal vector of the surface formed in CAAC-OS. Alternatively, they are aligned in a direction parallel to the surface normal vector and form a triangular shape when viewed from a direction perpendicular to the ab plane. Alternatively, it has a hexagonal atomic arrangement, and when viewed from a direction perpendicular to the c-axis, the metal atoms are layered or metal. Atoms and oxygen atoms are arranged in layers. Furthermore, between different crystalline regions, the a-axis and The orientation of the b-axis may differ. In this specification, when it is simply described as perpendicular, it means 85°. The range of 95° or less is also included. Furthermore, when simply described as parallel, the range of -5° or less is included. This will include the range of 5° or less above the baseline.

[0084] Furthermore, in CAAC-OS, the distribution of the crystalline regions does not need to be uniform. For example, CAAC -In the formation process of OS, when crystal growth is performed from the surface side of the oxide semiconductor film, the surface to be formed The proportion of the crystalline portion may be higher near the surface compared to the vicinity of the crystalline portion. Also, CAAC -By adding impurities to OS, the crystalline region becomes amorphous in the impurity-added region. Sometimes that happens.

[0085] The c-axis of the crystalline portion contained in CAAC-OS is the normal vector of the surface formed in CAAC-OS. Alternatively, they align in a direction parallel to the surface normal vector, thus the shape of CAAC-OS (cross section of the formed surface) Depending on the surface shape or cross-sectional shape of the surface, they may face in different directions. The direction of the c-axis of the crystal portion is the normal vector of the formed surface when CAAC-OS is formed or The direction is parallel to the surface normal vector. The crystalline portion is formed by film deposition or after film deposition. It is formed by performing crystallization treatments such as heat treatment.

[0086] CAAC-OS can be a conductor, a semiconductor, or an insulator, depending on its composition. And so on. Also, depending on its composition, it can be transparent or opaque to visible light. It may exist. Furthermore, a portion of CAAC-OS may be replaced with nitrogen.

[0087] Transistors using CAAC-OS exhibit changes in electrical characteristics due to irradiation with visible light and ultraviolet light. It is possible to reduce this. Therefore, the transistor is highly reliable.

[0088] An example of the crystal structure contained in CAAC-OS is explained in detail using Figures 15 to 17. In addition, unless otherwise specified, in Figures 15 to 17, the upward direction is the c-axis direction. Let the plane perpendicular to it be called plane ab. Note that when we simply refer to the upper half and the lower half, we mean the plane with plane ab as the boundary. This refers to the upper and lower halves of a case. Also, in Figure 15, the circled O represents O in 4-coordinate. Furthermore, the O enclosed in a double circle indicates a 3-coordinate O.

[0089] Figure 15(A) shows one 6-coordinate In atom and six 4-coordinate oxygen atoms adjacent to the In atom (hereinafter referred to as 4 The structure shows a coordinated O) and a nearby oxygen atom. Here, for each metal atom, A structure showing only the children is called a small group. The structure in Figure 15(A) takes the form of an octahedron, but For simplicity, it is shown as a planar structure. Note that the upper and lower halves of Figure 15(A) are respectively There are 4-coordinate oxygen atoms, 3 in each group. The small group shown in Figure 15(A) has a charge of 0.

[0090] Figure 15(B) shows one 5-coordinate Ga atom and three 3-coordinate oxygen atoms adjacent to the Ga atom (hereinafter referred to as 3 The structure shows a coordinated oxygen atom and two 4-coordinate oxygen atoms adjacent to Ga. The 3-coordinate oxygen atom is All of them are located on the ab plane. There is one in the upper half and one in the lower half of Figure 15(B), for a total of four. There is a coordinate oxygen atom. Also, since In can take on a 5-coordinate state, it can take on the structure shown in Figure 15(B). The small group shown in Figure 15(B) has a charge of 0.

[0091] Figure 15(C) shows a structure having one 4-coordinate Zn and four 4-coordinate O adjacent to the Zn. The structure is shown. The upper half of Figure 15(C) has one 4-coordinate oxygen atom, and the lower half has three 4-coordinate oxygen atoms. There is an O. Alternatively, there are three 4-coordinate Os in the upper half of Figure 15(C) and one in the lower half There may be oxygen atoms with 4 coordination. The small group shown in Figure 15(C) has a charge of 0.

[0092] Figure 15(D) shows a structure having one 6-coordinate Sn and six 4-coordinate O adjacent to the Sn. The structure is shown. The upper half of Figure 15(D) has 3 four-coordinate oxygen atoms, and the lower half has 3 four-coordinate oxygen atoms. There is an O. The small group shown in Figure 15(D) has a charge of +1.

[0093] Figure 15(E) shows a small group containing two Zn molecules. The upper half of Figure 15(E) shows one There is a 4-coordinate oxygen atom, and the lower half has one 4-coordinate oxygen atom. The small group shown in Figure 15(E) The charge becomes -1.

[0094] Here, a collection of multiple small groups is called a medium group, and a collection of multiple medium groups is This is called a large group (also known as a unit cell).

[0095] Here, we will explain the rules by which these subgroups combine. These rules are shown in Figure 15(A). The three oxygen atoms in the upper half of the 6-coordinate In each have three adjacent In atoms below them, and the lower half The three oxygen atoms each have three adjacent in atoms in the upward direction. Figure 15(B) shows a five-coordinate G One O in the upper half of a has one adjacent Ga in the downward direction, and one O in the lower half has an upward direction It has one adjacent Ga. The one O in the upper half of the four-coordinate Zn shown in Figure 15(C) is below It has one adjacent Zn in the direction, and the three O in the lower half each have three adjacent Zn in the upward direction. It possesses. In this way, the number of 4-coordinate oxygen atoms above the metal atom and the number of nearby oxygen atoms below that oxygen The number of group atoms is equal, and similarly, the number of oxygen atoms in the 4-coordinate downward direction of the metal atom and the number of oxygen atoms above that oxygen atom The number of neighboring metal atoms is equal. Since O is 4-coordinate, the number of neighboring metal atoms below and above are equal. The sum of the number of neighboring metal atoms in that direction is 4. Therefore, the 4-coordinate atoms above the metal atom When the sum of the number of oxygen atoms and the number of 4-coordinate oxygen atoms below another metal atom is 4, the metal atom Two subgroups possessing the same properties can bond together. For example, a 6-coordinate metal atom (In Alternatively, if Sn) is bonded via the lower half of the 4-coordinate oxygen atoms, there are three 4-coordinate oxygen atoms. It bonds with either a 5-coordinate metal atom (Ga or In) or a 4-coordinate metal atom (Zn). They will merge.

[0096] Metal atoms with these coordination numbers are bonded in the c-axis direction via 4-coordinate oxygen atoms. In addition, multiple small groups combine such that the total charge of the layered structure becomes 0. It forms a middle group.

[0097] Figure 16(A) shows a model diagram of the intermediate groups that constitute the layer structure of In-Sn-Zn oxides. Figure 16(B) shows the large group, which is composed of three medium groups. (C) shows the atomic arrangement when the layer structure of Figure 16(B) is observed from the c-axis direction.

[0098] In Figure 16(A), for simplicity, three-coordinate oxygen atoms are omitted, and only the number of four-coordinate oxygen atoms is shown. For example, the upper and lower halves of Sn each contain three 4-coordinate oxygen atoms (indicated by the circle). It is shown as 3. Similarly, in Figure 16(A), the upper half and lower half of In are Each of these has one 4-coordinate oxygen atoms, which are shown as "1" in the circle. Similarly, Figure 16 In (A), the lower half has one 4-coordinate oxygen atom, and the upper half has three 4-coordinate oxygen atoms. Zn has one 4-coordinate oxygen atom in the upper half and three 4-coordinate oxygen atoms in the lower half. This indicates that.

[0099] In Figure 16(A), the middle group constituting the layer structure of the In-Sn-Zn oxide is the upper Starting from there, there are three 4-coordinate oxygen atoms in the upper half and three 4-coordinate oxygen atoms in the lower half of the Sn atom, and one 4-coordinate oxygen atom in each half. It is bonded to In in the upper and lower halves, and that In has three 4-coordinate oxygen atoms in the upper half. It is bonded to Zn, and through one 4-coordinate oxygen atom in the lower half of the Zn, three 4-coordinate oxygen atoms are bonded to the upper half. In is bonded to the In in the lower half, and that In has one 4-coordinate O in the upper half of the Zn It binds to a small group consisting of two atoms, via one 4-coordinate oxygen atom in the lower half of this small group. This configuration consists of 4-coordinate oxygen atoms bonded to Sn atoms in the upper and lower halves, with three oxygen atoms bonded to each other. Multiple groups combine to form a larger group.

[0100] Here, for 3-coordinate oxygen and 4-coordinate oxygen, the charge per bond is -0.6, respectively. 67, -0.5 can be considered. For example, In (6-coordinate or 5-coordinate), Zn (4 The charges of (5-coordinate) and Sn (5-coordinate or 6-coordinate) are +3, +2, and +4, respectively. Therefore Therefore, the small group containing Sn has a charge of +1. As a result, it forms a layered structure containing Sn. For this to work, a charge of -1 is needed to cancel out the charge of +1. Figure 1 shows a structure that takes on a charge of -1. As shown in 5(E), a small group containing two Zn elements is an example. If there is one small group and one small group containing two Zn atoms, the charges cancel each other out. Therefore, the total charge of the layered structure can be set to 0.

[0101] Specifically, the large groups shown in Figure 16(B) are repeated, resulting in In-Sn-Zn Crystals of the In-S oxide (In2SnZn3O8) can be obtained. The layer structure of n-Zn oxides is In2SnZn2O7(ZnO) m (m is 0 or a natural number) It can be represented by the following empirical formula: .

[0102] In addition, there are other oxides of quaternary metals, such as In-Sn-Ga-Zn oxides, and ternary metal oxides. In-Ga-Zn oxides (also written as IGZO), which are oxides of the original metal, Al-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides, Sn-A l-Zn oxides, In-Hf-Zn oxides, In-La-Zn oxides, In-C e-Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides, In-Sm -Zn oxides, In-Eu-Zn oxides, In-Gd-Zn oxides, In-Tb- Zn oxides, In-Dy-Zn oxides, In-Ho-Zn oxides, In-Er-Z n-based oxides, In-Tm-Zn-based oxides, In-Yb-Zn-based oxides, In-Lu-Zn-based oxides In-Zn oxides, Sn-Zn oxides, and Al oxides are examples of oxides of binary metals. -Zn oxides, Zn-Mg oxides, Sn-Mg oxides, In-Mg oxides, and I The same applies when using n-Ga-based oxides, etc.

[0103] For example, Figure 17(A) shows the middle group that constitutes the layer structure of the In-Ga-Zn oxide. A diagram is shown.

[0104] In Figure 17(A), the middle group constituting the layer structure of the In-Ga-Zn oxide is the upper In order from there, the ion has three 4-coordinate oxygen atoms in the upper half and three in the lower half, and one 4-coordinate oxygen atom in the upper half. It bonds with Zn in the middle, and via the three 4-coordinate oxygen atoms in the lower half of that Zn, the 4-coordinate oxygen atoms are connected. Each atom bonds with the Ga atoms in the upper and lower halves, and one of the four-coordinate O atoms in the lower half of that Ga atom... Through this, the structure consists of three 4-coordinate oxygen atoms bonded to the in atoms in the upper and lower halves, respectively. These smaller groups combine to form larger groups.

[0105] Figure 17(B) shows the large group, which is composed of three medium groups. Figure 17(C) is Figure 17(B) shows the atomic arrangement when the layered structure is observed from the c-axis direction.

[0106] Here, the charges of In (6-coordinate or 5-coordinate), Zn (4-coordinate), and Ga (5-coordinate) are as follows: Since they are +3, +2, and +3 respectively, small groups containing any of In, Zn, and Ga Therefore, the charge becomes 0. The charge of the sum is always 0.

[0107] Furthermore, the intermediate groups constituting the layer structure of the In-Ga-Zn oxide are shown in Figure 17(A). Not limited to the same intermediate group, but combining intermediate groups with different arrangements of In, Ga, and Zn. Large groups could also be targeted.

[0108] Specifically, the large groups shown in Figure 17(B) are repeated, resulting in In-Ga-Zn Crystals of the In-Ga-Zn system oxide can be obtained. The layer structure of the obtained In-Ga-Zn system oxide is also shown. InGaO3(ZnO) n It can be expressed by the empirical formula (where n is a natural number).

[0109] For n=1 (InGaZnO4), for example, it can take the crystal structure shown in Figure 18(A). Furthermore, in the crystal structure shown in Figure 18(A), as explained in Figure 15(B), Ga and Since in takes a 5-coordinate state, it can also take a structure in which Ga is replaced by in.

[0110] Furthermore, in the case of n=2(InGaZn2O5), for example, the crystal structure shown in Figure 18(B) is It is possible. Furthermore, in the crystal structure shown in Figure 18(B), as explained in Figure 15(B) Since Ga and In can form a 5-coordinate structure, a structure in which Ga is replaced by In is also possible.

[0111] In this embodiment, first, a layer of 1 nm to 10 nm is applied to the base layer 102 by sputtering. A first oxide semiconductor with a value of m or less is formed. The substrate temperature when forming the first oxide semiconductor is The temperature should be between 200°C and 400°C.

[0112] Here, we will explain in detail the sputtering apparatus used to form oxide semiconductors.

[0113] The deposition chamber for forming oxide semiconductors has a leak rate of 1 × 10⁻⁶ -10 Pa·m 3 / second or less It is preferable to do so, as this will prevent impurities from entering the film when the film is formed by sputtering. Contamination can be reduced.

[0114] To reduce the leak rate, it is necessary to reduce not only external leaks but also internal leaks. External leakage refers to the inflow of gas from outside the vacuum system due to tiny holes or faulty seals. Internal leaks refer to leaks from valves or other partitions within a vacuum system, or leaks from internal components. It is caused by the emitted gas. The leak rate is 1 × 10⁻⁶. -10Pa·m 3 To be below [value] per second, it is necessary to take measures against both external leakage and internal leakage.

[0115] To reduce external leakage, the opening and closing parts of the film forming chamber may be sealed with a metal gasket. The metal gasket is preferably made of a metal material coated with iron fluoride, aluminum oxide, or chromium oxide. The metal gasket has higher adhesion compared to an O-ring and can reduce external leakage. Also, by using a metal material coated with a passivation such as iron fluoride, aluminum oxide, chromium oxide, etc., the release gas containing hydrogen generated from the metal gasket can be suppressed, and internal leakage can also be reduced.

[0116] As a member constituting the inner wall of the film forming chamber, use aluminum, chromium, titanium, zirconium, nickel, or vanadium with less release gas containing hydrogen. Also, the above materials may be coated with an alloy material containing iron, chromium, nickel, etc. and used. Alloy materials containing iron, chromium, nickel, etc. are rigid, heat-resistant, and suitable for processing. Here, if the surface unevenness of the member is reduced by polishing or the like to reduce the surface area, the release gas can be reduced. Alternatively, the members of the above film forming apparatus may be coated with a passivation such as iron fluoride, aluminum oxide, chromium oxide, etc.

[0117] Furthermore, it is preferable to provide a purifier for the sputter gas immediately before introducing the sputter gas into the film forming chamber. At this time, the length of the piping from the purifier to the film forming chamber is set to 5 m or less, preferably 1 m or less. By setting the length of the piping to 5 m or less or 1 m or less, the influence of the release gas from the piping can be reduced according to the length.

[0118] The evacuation of the film formation chamber is preferably carried out by appropriately combining a rough pump such as a dry pump and a high-vacuum pump such as a sputter ion pump, a turbomolecular pump, and a cryopump. Also, in order to remove residual moisture in the film formation chamber, it is preferable to use an adsorption-type vacuum pump, for example, a cryopump, an ion pump, or a titanium sublimation pump. While a turbomolecular pump is excellent in evacuating large-sized molecules, it has a low evacuation ability for hydrogen and water. Therefore, it is effective to combine a cryopump with a high water evacuation ability and a sputter ion pump with a high hydrogen evacuation ability. Also, a cold trap may be added to the turbomolecular pump. The film formation chamber evacuated using an adsorption-type vacuum pump such as a cryopump can exhaust, for example, compounds containing hydrogen atoms such as hydrogen atoms and water (H2O) (more preferably compounds containing carbon atoms as well), so that the concentration of impurities contained in the oxide semiconductor layer formed in the film formation chamber can be reduced. The adsorbates present inside the film formation chamber are adsorbed on the inner wall and do not affect the pressure of the film formation chamber, but they cause gas release when the film formation chamber is evacuated. Therefore, although there is no correlation between the leak rate and the evacuation speed, it is important to use a pump with a high evacuation ability to desorb as much as possible the adsorbates present in the film formation chamber and evacuate it in advance. In addition, in order to promote the desorption of the adsorbates, the film formation chamber may be baked. By baking, the desorption rate of the adsorbates can be increased by about 10 times. The baking may be carried out at 100°C or higher and 450°C or lower. At this time, if the adsorbates are removed while adding an inert gas, the desorption rate of water, which is difficult to desorb by simply evacuating,

[0119] can be further increased. can be further increased. The film formation chamber evacuated using an adsorption-type vacuum pump such as a cryopump can exhaust, for example, compounds containing hydrogen atoms such as hydrogen atoms and water (H2O) (more preferably compounds containing carbon atoms as well), so that the concentration of impurities contained in the oxide semiconductor layer formed in the film formation chamber can be reduced. The adsorbates present inside the film formation chamber are adsorbed on the inner wall and do not affect the pressure of the film formation chamber, but they cause gas release when the film formation chamber is evacuated. Therefore, although there is no correlation between the leak rate and the evacuation speed, it is important to use a pump with a high evacuation ability to desorb as much as possible the adsorbates present in the film formation chamber and evacuate it in advance. In addition, in order to promote the desorption of the adsorbates, the film formation chamber may be baked. By baking, the desorption rate of the adsorbates can be increased by about 10 times. The baking may be carried out at 100°C or higher and 450°C or lower. At this time, if the adsorbates are removed while adding an inert gas, the desorption rate of water, which is difficult to desorb by simply evacuating,

[0120] In the sputtering method, the power supply for generating plasma is an RF power supply, A A C power supply, a DC power supply, etc., can be used as appropriate.

[0121] For forming In-Ga-Zn oxide materials as oxide semiconductors using the sputtering method In-Ga-Zn oxide targets are, for example, In2O3:Ga2O3:ZnO=1 A target having a composition ratio of 1:1 [molar ratio] can be used. A target having a composition ratio of 2O3:Ga2O3:ZnO=1:1:2 [molar ratio] Alternatively, a composition ratio of In2O3:Ga2O3:ZnO = 1:1:4 [molar ratio] - Get, has a composition ratio of In2O3:Ga2O3:ZnO = 2:1:8 [molar ratio] It is also possible to use a target with an atomic ratio of In:Ga:Zn=1:1:1. In- A Ga-Zn oxide target can be used. In-G having the aforementioned atomic ratio By forming an oxide semiconductor using an α-Zn oxide target, polycrystalline or CA (carbonated) semiconductors can be formed. AC-OS is more likely to form.

[0122] Furthermore, when forming an In-Sn-Zn oxide as an oxide semiconductor using the sputtering method... Preferably, the atomic ratio is In:Sn:Zn = 1:1:1, 2:1:3, 1:2:2, Alternatively, an In-Sn-Zn oxide target represented by 20:45:35 is used. Forming oxide semiconductors using In-Sn-Zn oxide targets with specific atomic ratios. This makes it easier for polycrystalline or CAAC-OS to form.

[0123] In addition, the relative density of the metal oxide target for forming the oxide semiconductor is 90% or more and 10 0% or less, preferably 95% or more and 99.9% or less. By using a metal oxide target with a high relative density, the formed oxide semiconductor layer can be made into a dense film.

[0124] The sputtering gas is appropriately selected from an inert gas (typically argon) atmosphere, an oxygen atmosphere, a mixed gas of an inert gas and oxygen. Further, it is preferable to use a high purity gas from which impurities such as hydrogen, water, hydroxyl groups, or hydrides have been removed. For example, when using argon as the sputtering gas, a purity of 9N, a dew point of -121 °C, an H2O content of 0.1 ppb or less, and an H2 content of 0.5 ppb or less are preferable. When using oxygen, a purity of 8N, a dew point of -112 °C, an H2O content of 1 ppb or less, and an H2 content of 1 ppb or less are preferable. .

[0125] In addition, the substrate temperature during film formation is 150 °C or more and 450 °C or less, preferably 200 °C or more and 350 °C or less. By forming the film while heating the substrate to 150 °C or more and 450 °C or less, preferably 200 °C or more and 350 °C or less, it is possible to prevent the incorporation of moisture (including hydrogen) and the like into the film.

[0126] By forming the film while heating the substrate, it is possible to reduce the concentration of impurities such as hydrogen, moisture, hydrides, or hydroxides contained in the formed oxide semiconductor. Further, the damage due to sputtering is reduced. Then, while removing the residual moisture in the film formation chamber, a sputtering gas from which hydrogen and moisture have been removed is added, and using the above target, 1 nm or more and 10 nm or less, Preferably, a first oxide semiconductor film is formed with a thickness of 2 nm to 5 nm.

[0127] In this embodiment, an In-Ga-Zn oxide semiconductor is used as the target for the oxide semiconductor. Using a target (In2O3:Ga2O3:ZnO=1:1:2 [molar ratio]) The distance between the substrate and the target was 170 mm, the substrate temperature was 250°C, the pressure was 0.4 Pa, and the direct current was set. DC power supply power 0.5kW, sputtering gas can be oxygen only, argon only, or argon. A first oxide semiconductor film with a thickness of 5 nm is deposited using gon and oxygen.

[0128] Next, the chamber atmosphere in which the substrate is placed is changed to nitrogen or dry air, and the first heat treatment is performed. The following steps are performed. The temperature of the first heat treatment shall be between 400°C and 750°C. Therefore, the first oxide semiconductor crystallizes and becomes the first crystalline oxide semiconductor.

[0129] Depending on the temperature of the first heat treatment, crystallization occurs from the film surface as a result of the first heat treatment. Crystal growth occurs from the surface of the film toward the interior, resulting in crystals oriented along the C axis. By principle, zinc and oxygen accumulate in large quantities on the film surface, and the upper plane is made up of zinc and oxygen forming a hexagon. A graphene-type two-dimensional crystal is formed in one or more layers on the outermost surface, and this is in the direction of film thickness It grows and overlaps, forming layers. When the heat treatment temperature is increased, it starts from the surface, then the inside, and then from the inside. Crystal growth progresses at the bottom.

[0130] The first heat treatment brings oxygen in the underlying layer 102 to the interface with the first crystalline oxide semiconductor. Alternatively, diffuse it in its vicinity (plus or minus 5 nm from the interface) to form the first crystalline oxide semiconductor. It reduces oxygen deficiency in the body. Therefore, the base layer 102 is in the base layer 102 (in the bulk), and At least one of the interfaces between the first crystalline oxide semiconductor and the underlying layer 102 is present in a stoichiometric ratio. It is preferable that an amount of oxygen exceeding a certain value is present.

[0131] Next, a second oxide semiconductor thicker than 10 nm is formed on the first crystalline oxide semiconductor. The second oxide semiconductor is formed using the sputtering method, and the substrate temperature during film formation is... The temperature shall be between 200°C and 400°C. By doing the following, an oxide semiconductor film is formed in contact with the surface of the first crystalline oxide semiconductor. The precursors in the body align, creating what is known as order.

[0132] In this embodiment, an In-Ga-Zn oxide semiconductor is used as the target for the oxide semiconductor. Using a target (In2O3:Ga2O3:ZnO=1:1:2 [molar ratio]) The distance between the substrate and the target was 170 mm, the substrate temperature was 400°C, the pressure was 0.4 Pa, and the direct current was set. DC power supply power 0.5kW, sputtering gas can be oxygen only, argon only, or argon. A second oxide semiconductor film with a thickness of 25 nm is deposited using gon and oxygen.

[0133] Next, the chamber atmosphere in which the substrate is placed is changed to nitrogen or dry air, followed by a second heat treatment. The second heat treatment temperature shall be between 400°C and 750°C. Therefore, a second crystalline oxide semiconductor is formed. The second heat treatment is carried out under a nitrogen atmosphere, oxygen By performing the process under a specific atmosphere, or under a mixed atmosphere of nitrogen and oxygen, a second crystalline oxide semiconductor can be produced. The aim is to increase the density of the material and reduce the number of defects. The second heat treatment is performed on the first crystalline oxide semiconductor. Crystal growth proceeds in the direction of film thickness, i.e., from the bottom inward, with the conductor as the nucleus, forming a second crystalline oxide semiconductor. A conductor is formed. At this time, the first crystalline oxide semiconductor and the second crystalline oxide semiconductor are the same The process of being composed of only one element is called homogeneous growth. Alternatively, it refers to the first crystalline oxide semiconductor and the second The crystalline oxide semiconductor is composed of at least one different element. This is called growth.

[0134] Thus, in the oxide semiconductor formation process, the pressure in the deposition chamber and the leak rate in the deposition chamber are In this process, by minimizing the inclusion of impurities, hydrogen and moisture are prevented from entering the oxide semiconductor. This can reduce the inclusion of various impurities. Hydrogen contained in oxide semiconductors interacts with metal atoms. It reacts with the oxygen it binds to to form water, and at the same time, the lattice from which the oxygen has been removed (or the lattice from which the oxygen has been removed) Defects will form in the area.

[0135] Therefore, in the oxide semiconductor formation process, by drastically reducing impurities, It is possible to reduce defects in semiconductors. Therefore, it is possible to remove impurities as much as possible. Furthermore, an oxide semiconductor made of highly purified CAAC-OS is used in the channel region. Therefore, the change in threshold voltage before and after light irradiation and BT testing of the transistor is small. Therefore, it can have stable electrical characteristics.

[0136] Furthermore, after the second heat treatment, the atmosphere is changed to an oxidizing atmosphere while maintaining the temperature, and further heating is performed. Heat treatment is preferable. Heat treatment in an oxidizing atmosphere removes oxygen vacancies in oxide semiconductors. This can be reduced.

[0137] Furthermore, metal oxides that can be used in oxide semiconductors have a band gap of 2 eV or more. Preferably, it is 2.5 eV or more, more preferably 3 eV or more. In this way, the bandgap By using metal oxides with a wide top, the off-current of the transistor can be reduced. .

[0138] Furthermore, the process from the formation of the base layer 102 to the second heat treatment is carried out continuously without exposure to the atmosphere. It is preferable to carry it out precisely. The process from the formation of the base layer 102 to the second heat treatment involves hydrogen and And under an atmosphere that contains almost no moisture (inert atmosphere, reduced pressure atmosphere, dry air atmosphere, etc.) It is preferable to control the dew point to be -40°C or lower for moisture, preferably the dew point Maintain a dry nitrogen atmosphere at -50°C or below.

[0139] Next, an oxide semiconductor consisting of a first crystalline oxide semiconductor and a second crystalline oxide semiconductor The stacked layers are processed to form island-shaped oxide semiconductor layers 103 (see Figure 3(A)).

[0140] The processing of oxide semiconductors involves forming a mask of the desired shape on the oxide semiconductor, and then processing the oxide This can be done by etching the semiconductor. The mask mentioned above is photolithographic It can be formed using methods such as roughing. Alternatively, it can be formed using inkjet or printing methods. Any method can be used to form the mask.

[0141] Furthermore, etching of oxide semiconductors can be done using either dry etching or wet etching methods. That's fine. Of course, you can also use them in combination.

[0142] Furthermore, the first crystalline oxide semiconductor and the second crystalline oxide obtained by the above manufacturing method One of the characteristics of semiconductors is that they have a C-axis orientation. However, the first crystalline acid The oxide semiconductor and the second crystalline oxide semiconductor are neither single-crystal nor amorphous in structure. It is a crystalline oxide semiconductor (CAAC-OS) with a C-axis orientation.

[0143] Furthermore, this is limited to a two-layer structure in which a second crystalline oxide semiconductor is formed on a first crystalline oxide semiconductor. It is not determined, and the third crystalline oxide semiconductor is formed after the formation of the second crystalline oxide semiconductor. The film deposition and heat treatment processes can be repeated to create a laminated structure of three or more layers.

[0144] Like oxide semiconductor layer 103, a first crystalline oxide semiconductor and a second crystalline oxide semiconductor By using this stacked structure in transistors, stable electrical characteristics and high reliability are achieved. It is possible to create a transistor.

[0145] Next, a gate insulating layer 104 is formed on the oxide semiconductor layer 103. Aluminum nitride, aluminum oxide, aluminum nitride oxide, aluminum oxide nitride , silicon nitride, silicon oxide, silicon nitride oxide, silicon oxide nitride, tantalum oxide, Alternatively, materials selected from lanthanum oxide can be formed in a single layer or in layers. .

[0146] Furthermore, as the gate insulating layer 104, hafnium silicate (HfSiO x (x>0), Nitrogen-added hafnium silicate (HfSi x O y N z (x>0, y>0, z>0 )), nitrogen-added hafnium aluminate (HfAl x O y N z (x>0, y>0 (z>0), high-k materials such as hafnium oxide and yttrium oxide are used. So, without changing the actual thickness of the gate insulating film (for example, in terms of silicon oxide), the physical By increasing the thickness of the gate insulating film, gate leakage can be reduced. Furthermore, hig HK materials, silicon oxide, silicon oxide nitride, silicon nitride, silicon oxide nitride, acid Laminated structure with one or more of aluminum oxide, aluminum oxide nitride, and gallium oxide It can be constructed. The thickness of the gate insulating layer 104 is 1 nm or more and 300 nm or less. Preferably, the wavelength should be between 5 nm and 50 nm.

[0147] The gate insulating layer 104 is formed by sputtering, CVD, or the like. O4 can be formed using methods such as sputtering and plasma CVD, as well as with μ-wave (e.g., frequency 2. Film deposition methods such as high-density plasma CVD using 45 GHz can be applied. Furthermore, the gate insulating layer 104 is not limited to a single layer; it may also be a lamination of different layers. Preferably, the portion of 104 that is in contact with the oxide semiconductor layer 103 is an insulating layer containing oxygen. Particularly preferred is an oxide insulating layer that releases oxygen upon heating. For example, a gate insulating layer. By using silicon oxide for 104, oxygen is diffused into the oxide semiconductor layer 103, causing oxidation. This reduces oxygen vacancies in the semiconductor layer 103, improving the characteristics of the transistor. It is possible.

[0148] In the structure shown in this embodiment, the structure that creates irregularities on the substrate is the oxide semiconductor layer 103 This reduces leakage current caused by the gate insulating layer 104, and the gate insulating layer 1 The breakdown voltage of 04 can be increased. Therefore, the gate insulating layer 104 can be thinned to nearly 5 nm. The transistor can be operated even when it is modified. By forming a film, the short-channel effect is reduced, and the operating speed of the transistor is increased. To play.

[0149] Before forming the gate insulating layer 104, the surface of the oxide semiconductor layer 103 is treated with oxygen and ozoite. The surface of the oxide semiconductor layer 103 is oxidized by exposing it to a plasma of oxidizing gases such as nitrous oxide. This may reduce oxygen deficiency. In this embodiment, the gate insulating layer 104 is an oxide A silicon oxide layer with a thickness of 100 nm is formed on the semiconductor layer 103.

[0150] Next, on the gate insulating layer 104, using sputtering, vacuum deposition, or plating methods A conductive layer is formed, a mask is formed on the conductive layer, and the conductive layer is selectively etched. A conductive electrode 105 is formed. The mask formed on the conductive layer is created by printing, inkjet, or Photolithography can be used as appropriate. The gate electrode 105 is connected to the gate insulating layer 10 A gate electrode 105a that is in contact with 4, and a gate electrode 105 stacked on top of the gate electrode 105a It is formed by b.

[0151] The material used to form the gate electrode 105a is indium gallium zinc oxide containing nitrogen. (In-Ga-Zn-O), indium tin oxide containing nitrogen (In-Sn-O), and nitrogen Indium gallium oxide (In-Ga-O) containing nitrogen, and indium zinc acid containing nitrogen. Indiene compounds (In-Zn-O), nitrogen-containing tin oxide (Sn-O), and nitrogen-containing indium acid It is preferable to use an oxide (In-O) or a metal nitride (InN, ZnN, etc.).

[0152] These materials have a work function of 5 eV, preferably 5.5 eV or more, and gate electrode 105 a is provided between the gate electrode 105b and the gate insulating layer 104, and the gate electrode 105a By superimposing the oxide semiconductor layer 103 with the gate insulating layer 104, the transistor The threshold voltage of the electrical characteristics can be made positive, resulting in so-called normally-off switching. This allows for the realization of the device. For example, if the gate electrode 105a is made of In-Ga-Zn-O containing nitrogen... If present, the nitrogen concentration should be at least higher than that of the oxide semiconductor layer 103, specifically a nitrogen concentration of 7 Use in-Ga-Zn-O in atomic percent or more.

[0153] The materials used to form the gate electrode 105b include aluminum (Al), chromium (Cr), Copper (Cu), tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten ( Metal elements selected from W, neodymium (Nd), and scandium (Sc), as mentioned above Alloys containing the element, alloys combining the above-mentioned metal elements, nitrides of the above-mentioned metal elements It can be formed using the following: manganese (Mn), magnesium (Mg), A metal selected from one or more of the following: zirconium (Zr) and beryllium (Be). Elements may also be used.

[0154] Furthermore, the gate electrode 105b may have a single-layer structure or a stacked structure of two or more layers. A single-layer structure using silicon-containing aluminum, and a two-layer structure with titanium laminated on aluminum. Layered structure, two-layer structure with titanium laminated on titanium nitride, tungsten laminated on titanium nitride Two-layer structure, two-layer structure with tungsten laminated on tantalum nitride, Cu-Mg-Al alloy A two-layer structure with Cu layered on top of gold, titanium, and aluminum layered on top of that titanium, and further This includes a three-layer structure in which titanium is formed on top of it.

[0155] Furthermore, the gate electrode 105b contains indium tin oxide and tungsten oxide. Indium zinc oxide containing oxides, tungsten oxide, and indium acid containing titanium oxide Adds indium tin oxide containing titanium dioxide, indium zinc oxide, and silicon dioxide. It is also possible to apply transparent conductive materials such as indium tin oxide. Alternatively, a laminated structure of the above-mentioned light-transmitting conductive material and the above-mentioned metal element can be used.

[0156] In this embodiment, the gate electrode 105a is an indium gallium zinc oxide containing nitrogen. Materials are used. In addition, tungsten is laminated on titanium nitride as the gate electrode 105b. A two-layer structure is used (see Figure 3(B)). The ends of the formed gate electrode 105 are taped. A perforated shape is preferable because it improves the coverage of the layers that are formed later.

[0157] Next, a self-alignment process forms the source region 103a and the drain region 103b. Specifically, gate electrode 105 is used as a mask for ion doping or ion injection. Dopant 106 is added to the oxide semiconductor layer 103 by the plantation method. The dopant 106 added to the semiconductor layer 103 is a noble gas or hydrogen (H), One or more types of elements can be used.

[0158] Hydrogen acts as an electron donor in oxide semiconductors, causing them to become n-type. Furthermore, noble gas elements create defects in oxide semiconductors, causing them to become n-type. Hydrogen diffuses easily, and when hydrogen diffuses into the channel formation region, the transistor characteristics deteriorate. There is a risk that this may occur. For this reason, using a noble gas element as dopant 106 is preferable for semiconductor devices. Its reliability is good and desirable.

[0159] Furthermore, in the region where the oxide semiconductor layer 103 overlaps with the gate electrode 105, the gate electrode 105 It acts as a mask, preventing the addition of dopant 106, and resulting in the channel-forming region 103c.

[0160] The source region 103a and drain region 103b to which dopant 106 is added are of type n. It becomes an oxide semiconductor, and its resistivity decreases compared to the channel formation region 103c. Therefore, The resistance values ​​of the drain region 103a and the drain region 103b decrease, and transistor 100 This makes it possible to operate at high speed. In addition, the source area 103a and drain area 10 There is almost no overlap between 3b and the gate electrode 105, which reduces the parasitic capacity. Therefore, it becomes possible to operate transistor 100 at an even higher speed.

[0161] Furthermore, using the gate electrode 105 as a mask, the oxide semiconductor that forms the source and drain regions... The gate insulating layer 104 on the body layer 103 is removed to expose the oxide semiconductor layer 103. A dopant 106 is added to the oxide semiconductor layer 103, and the source region 103a and drain are added. Region 103b may be formed. Removal of the gate insulating layer 104 on the oxide semiconductor layer 103 is The process is carried out under conditions that make it difficult for the oxide semiconductor layer 103 to be etched.

[0162] The addition of dopant 106 to the exposed oxide semiconductor layer 103 is performed by ion doping or This can be done by ion implantation. Note that the addition of dopant 106 is A plasma is generated in a gas atmosphere containing the added element, exposing the oxide semiconductor layer 103. This can also be done by performing plasma treatment on the affected area. However, Adding oxides using lazma processing carries the risk of etching and thinning the oxide semiconductor layer. Therefore, the addition of dopant 106 to oxide semiconductor layer 103 is ion doping. It is preferable to perform this procedure using either the ion implantation method or the ion implantation method.

[0163] Furthermore, the addition of dopant 106 to oxide semiconductor layer 103 is performed by ion doping or When performed by the on-plantation method, the oxide semiconductor layer 103 is not exposed. It is preferable to leave the gate insulating layer 104 intact. Dopant 106 is applied to the gate insulating layer 1 By passing through 04 and adding it to the oxide semiconductor layer 103, the addition of dopant 106 This reduces excessive damage to the oxide semiconductor layer 103. The interface between the body layer 103 and the gate insulating layer 104 is also kept clean, thus preserving the characteristics and reliability of the transistor. Reliability is increased. Also, the depth of dopant 106 addition (addition region) becomes easier to control, and oxidation The dopant 106 can be precisely added to the semiconductor layer 103.

[0164] In this embodiment, xenon (Xe) is used as dopant 106, and xenon is ionized By the implantation method, the oxide semiconductor layer 103 is passed through the gate insulating layer 104. It is added to the source region 103a and drain region formed by the addition of xenon. The xenon concentration in region 103b is 5 × 10⁻⁶ 19 atoms / cm 3 The above is 1 x 10 22 a toms / cm 3The following should be achieved (see Figure 3(C)).

[0165] After adding dopant 106, under a reduced pressure atmosphere and an inert gas atmosphere such as nitrogen or a noble gas, Heat treatment may be performed at a temperature of 300°C to 600°C. In this embodiment, heat treatment Using an electric furnace, one of the devices, heat treatment is performed at 450°C for 1 hour under a nitrogen atmosphere.

[0166] Furthermore, the heat treatment device is not limited to electric furnaces, but also includes heat conduction or heat from heat-generating elements such as resistance heating elements. The device may include an apparatus that heats the object to be processed by radiation. For example, GRTA(Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Angle) for Thermal Annealing devices, etc. A neal device can be used. The LRTA device uses halogen lamps and metal halide lamps. Lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, high pressure A device that heats an object to be processed by radiation of light (electromagnetic waves) emitted from lamps such as mercury lamps. The GRTA device is a device that performs heat treatment using high-temperature gas. This involves using noble gases such as argon, or nitrogen, which do not react with the material being treated by heat treatment. An inert gas is used.

[0167] For example, as a heat treatment, the substrate is moved into an inert gas heated to a high temperature and subjected to heat for several minutes. After heating, you can also perform GRTA by moving the substrate and removing it from a high-temperature heated inert gas. stomach.

[0168] The above heat treatment can be performed at any time after the addition of dopant 106.

[0169] Furthermore, dopant 10 can be added by ion doping or ion implantation. When adding 6, the substrate may be heated during the process.

[0170] Next, the oxide semiconductor layer 103 and the gate electrode 105 are covered by sputtering and CVD. In accordance with the law, insulating layer 107 and insulating layer 108 are formed. This includes aluminum nitride, aluminum oxide, aluminum nitride oxide, and aluminum oxide nitride. Selected from silicon nitride, silicon oxide, silicon nitride-oxide, or silicon oxide-nitride. It can be formed using the following materials. In addition, the insulating layer 107 and the insulating layer 108 are each This can be used as a single layer or in multiple layers.

[0171] In this case, at least the insulating layer 107 should be made of a material that does not easily release oxygen when heated. This is preferable. This reduces the conductivity of the source region 103a and the drain region 103b. This is because there is no such thing. Specifically, the CVD method uses silane gas as the main material and nitrogen oxide gas The film can be formed by mixing appropriate source gases from nitrogen gas, hydrogen gas, and noble gases. The substrate temperature should be between 300°C and 550°C. By using the CVD method, heating is It is possible to create a material that does not easily release oxygen. Also, by using silane gas as the main material... Hydrogen remains in the insulating layer, and as this hydrogen diffuses, the source region 103a and the drain region The conductivity of 103b can be further increased. The hydrogen concentration in the insulating layer 107 is 0.1 It should be between 25% and 25% atomic percentage.

[0172] The film thickness of insulating layer 107 and insulating layer 108 is 50 nm or more, preferably 200 nm or more. The thickness shall be 0 nm or less. In this embodiment, the insulating layer 107 is made of silica oxide with a film thickness of 300 nm. A cone is formed, and an aluminum oxide layer with a thickness of 100 nm is formed as an insulating layer 108.

[0173] The insulating layer 108 is made of silicon nitride or aluminum oxide to prevent the intrusion of impurities from the outside. It is preferable to form it using nium. In this embodiment, the insulating layer 108 is, A 100 nm aluminum oxide layer is formed (see Figure 3(D)). In addition, the insulating layer 107 and the insulating layer are formed. The marginal layer 108 may be omitted, either one or both of them.

[0174] After the formation of the insulating layer 108, heat treatment may be performed if necessary (temperature range 150°C to 650°C). You may also perform the procedure at temperatures between 200°C and 500°C.

[0175] Next, a mask is formed on the insulating layer 108, and the gate insulating layer 104 is used with the mask. A portion of layer 107 and the insulating layer 108 is selectively etched to create the source region 103a and Dre A portion of the in-region 103b is exposed to form a contact hole 109 (see Figure 4(A)). (see).

[0176] Next, a conductive layer is formed on the insulating layer 108, a mask is formed on the conductive layer, and the conductive layer is selected. The source electrode 110a and drain electrode 110b are formed by etching (Figure 4(B) (See reference). The conductive layer for forming the source electrode 110a and the drain electrode 110b is made of The same material as that used for electrode 105b can be applied.

[0177] In this embodiment, conductive materials are used to form the source electrode 110a and the drain electrode 110b. As a layer, a conductive layer is used, in which Cu is laminated on a Cu-Mg-Al alloy. By providing a Cu-Mg-Al alloy material, the adhesion of the conductive layer can be improved. ru.

[0178] The channel length of transistor 100 is as shown in Figure 1(B), with respect to the source region 103a. This corresponds to the length of the channel-forming region 103c, which is sandwiched between the drain region 103b. The channel length of transistor 100 is approximately equal to the width of gate electrode 105.

[0179] Through the above process, even when the transistor is miniaturized and the channel length is reduced, the electrical characteristics remain good. A transistor 100 can be fabricated using a good and highly reliable oxide semiconductor. ru.

[0180] Transistor 140 has a low-concentration region 103d and a low-concentration region 1 in the oxide semiconductor layer 103. It has 03e. Transistor 140 is a side step in the manufacturing process of transistor 100. The process for fabricating the foil 111 is added, and the dopant 106 is added to the oxide semiconductor layer 103. It can be produced by doing it in two separate steps.

[0181] Low-concentration regions 103d and 103e use gate electrode 105 as a mask. It can be formed by a self-aligning process. Specifically, after the gate electrode 105 is formed, Using the gate electrode 105 as a mask, dopant 1 is created in the same manner as transistor 100. 06 is added to the oxide semiconductor layer 103 (also called the first doping step). The dopant 106 added to the oxide semiconductor layer 103 is used in the transistor 100. The same elements as those used in dopant 106 can be used. In the first doping step, acid The concentration of dopant 106 in the ion semiconductor layer 103 is 5 × 1018 atoms / cm 3 That's all. , 5×10 19 atoms / cm 3 Add so that the total amount is less than the specified value.

[0182] Next, a sidewall 111 is formed on the side of the gate electrode 105. 1 can be prepared by known methods.

[0183] Next, using the gate electrode 105 and sidewall 111 as a mask, the dopant 106 The oxide semiconductor layer 103 is doped (also called the second doping step). The dopant 106 added to the synthetic semiconductor layer 103 is used in the transistor 100. Similar elements to those used in dopant 106 can be used. In the second doping step, oxide semi-oxides are used. The concentration of dopant 106 in the conductive layer 103 is 5 × 10 19 atoms / cm 3 The above is 1× 10 22 atoms / cm 3 The following should be achieved.

[0184] In this way, transistor 140 has a source region 103a, a drain region 103b, and low A concentration region 103d and a low concentration region 103e can be formed. Low concentration region 103 d, and the low-concentration region 103e are greater than the source region 103a and the drain region 103b. The dopant concentration is low, and the resistivity is high.

[0185] By providing low-concentration regions 103d and 103e, the transistor characteristics are improved. This can reduce the negative shift in threshold voltage due to short-channel effects, and further... Highly reliable transistors can be manufactured.

[0186] Furthermore, the channel length of transistor 140 is shown in Figure 2(B) as low concentration region 103d and This corresponds to the length of the channel-forming region 103c, which is sandwiched between the low-concentration region 103e. The channel length of the transistor 140 is approximately equal to the width of the gate electrode 105.

[0187] This embodiment can be implemented in appropriate combination with other embodiments.

[0188] (Embodiment 2) In this embodiment, a transistor having a different configuration from the transistor disclosed in Embodiment 1 is used. Let's explain the example of ZISTA.

[0189] Figure 5(A) is a top view illustrating the configuration of transistor 150, and Figure 5(B) is a top view illustrating the configuration of transistor 150. (A) is a cross-sectional view illustrating the layered structure of the region indicated by the dashed line C1-C2. Note that Figure 5 In (A), the description of the substrate and insulating layer has been omitted.

[0190] The transistor 150 shown in Figure 5(B) is the same as the transistor 100 disclosed in Embodiment 1. In comparison, the stacking positions of the source electrode 110a and the drain electrode 110b are different. The lampistor 150 has a source electrode 110a and a drain electrode 110b on the base layer 102. An oxide semiconductor is formed on the underlayer 102, source electrode 110a, and drain electrode 110b. Body layer 103 is formed.

[0191] In transistor 150, the source electrode 110a and the drain electrode 110b are contacts. The source region 103a and drain region 10 of the oxide semiconductor layer 103 without passing through hole 109 Because it is configured to connect to 3b, it is easy to increase the connection area and reduce contact resistance. .

[0192] The channel length of transistor 150 is as shown in Figure 5(B) with respect to the source region 103a. This corresponds to the length of the channel-forming region 103c, which is sandwiched between the drain region 103b. The channel length of transistor 150 is approximately equal to the width of gate electrode 105.

[0193] The transistor 160 shown in Figure 6 has the same configuration as transistor 150, plus the gate electrode 10 The side of 5 has a sidewall 111, and the oxide semiconductor layer 103 has a sidewall 111 The region overlapping with it has low-concentration region 103d and low-concentration region 103e. Region 103d is formed between the channel-forming region 103c and the source region 103a, and is a low-concentration region Region 103e is formed between the channel-forming region 103c and the drain region 103b. Figure 6(A) is a top view illustrating the configuration of transistor 160, and Figure 6(B) is a top view illustrating the configuration of transistor 160. (A) is a cross-sectional view illustrating the layered structure of the region indicated by the dashed line D1-D2.

[0194] By providing a low-concentration region 103d or a low-concentration region 103e in the oxide semiconductor layer 103, Between the channel formation region 103c and the source region 103a or drain region 103b This can mitigate the resulting electric field and reduce the degradation of transistor characteristics. In particular, channel Relaxation of the electric field generated in the formation region 103c and the drain region 103b results in inferior transistor characteristics. It is effective in reducing oxidation. In addition, a low-concentration region 103d or a low-concentration region 103e is provided. This makes it possible to suppress the short-channel effect associated with the miniaturization of transistors.

[0195] Furthermore, the channel length of transistor 160 is shown in Figure 6(B) as low concentration region 103d and This corresponds to the length of the channel-forming region 103c, which is sandwiched between the low-concentration region 103e. The channel length of the transistor 160 is approximately equal to the width of the gate electrode 105.

[0196] The transistor 170 shown in Figure 7(A) is a form of bottom-gate transistor. ru.

[0197] Figure 7(A) shows the cross-sectional structure of transistor 170. Transistor 170 is based A gate electrode 105 is formed on the plate 101, and a gate insulating layer 104 is formed on the gate electrode 105. It is formed. The gate electrode 105 has gate electrode 105a stacked on gate electrode 105b. It has a layered structure. Between the substrate 101 and the gate electrode 105, as described in Embodiment 1 A base layer may be provided.

[0198] Furthermore, an oxide semiconductor layer 103 is formed on the gate insulating layer 104, and the oxide semiconductor layer 103 A channel protection layer 112, a source electrode 110a, and a drain electrode 110b are formed on top of it. The oxide semiconductor layer 103 is superimposed on the channel protection layer 112 in a channel formation region 1 03c, source region 103a electrically connected to source electrode 110a, and drain electrode It has a drain region 103b that is electrically connected to 110b.

[0199] The channel protection layer 112 is formed using the same materials and methods as the gate insulation layer 104. This is possible. The thickness of the channel protection layer 112 is preferably between 10 nm and 500 nm. The wavelength should be between 100 nm and 300 nm.

[0200] The source region 103a and the drain region 103b use the channel protection layer 112 as a mask. It can be used and formed in the same way as transistor 100.

[0201] Furthermore, an insulating layer is applied to the channel protection layer 112, the source electrode 110a, and the drain electrode 110b. An edge layer 108 is formed. The insulating layer 108 may be a lamination of multiple insulating layers.

[0202] The channel length of transistor 170 is as shown in Figure 7(A) with respect to the source region 103a. This corresponds to the length of the channel-forming region 103c, which is sandwiched between the drain region 103b. The channel length of transistor 170 is approximately equal to the width of the channel protection layer 112.

[0203] Figure 7(B) shows the cross-sectional structure of transistor 180. Transistor 180 is The transistor 100 has a structure in which a back gate electrode 115 and an insulating layer 113 are provided. Transistor 180 has a back gate electrode 115 formed on the base layer 102, and An insulating layer 113 is formed on the electrode 115. Also, the oxide of the transistor 180 The semiconductor layer 103 is formed superimposed on the back gate electrode 115 via the insulating layer 113. It is.

[0204] The back gate electrode 115 is connected to the gate electrode 105 and the back gate electrode 115, forming an oxide semiconductor. It is positioned so as to sandwich the channel formation region 103c of layer 103. The back gate electrode 115 is It is formed of a conductive layer and can function similarly to the gate electrode 105. By changing the potential of electrode 115, the threshold voltage of the transistor can be changed. It is possible.

[0205] The back gate electrode 115 can be formed using the same material and method as the gate electrode 105b. Yes, it is possible. Also, between the back gate electrode 115 and the insulating layer 113, the gate electrode 105a and You may create layers for different types of classifications.

[0206] The insulating layer 113 can be formed using the same materials and methods as the gate insulating layer 104. Alternatively, the underlying layer 102 may not be formed, and the insulating layer 113 may serve as the underlying layer 102. Cut.

[0207] The channel length of transistor 180 is as shown in Figure 7(B) with respect to the source region 103a. This corresponds to the length of the channel-forming region 103c, which is sandwiched between the drain region 103b. The channel length of transistor 180 is approximately equal to the width of gate electrode 105.

[0208] This embodiment can be implemented in appropriate combination with other embodiments.

[0209] (Embodiment 3) In this embodiment, a method for forming an oxide semiconductor film made of CAAC-OS is described. Methods other than those disclosed in Form 1 are described below.

[0210] First, an oxide semiconductor film with a thickness of 1 nm to 50 nm is formed on the base layer 102.

[0211] The substrate temperature during film formation is 150°C to 450°C, preferably 200°C to 350°C. Yes. The substrate is heated to a temperature of 150°C to 450°C, preferably 200°C to 350°C. By performing film formation while simultaneously preventing contamination of the film with water (including hydrogen), etc., it is possible to prevent contamination of the film. It is possible to form CAAC-OS, which is an oxide semiconductor film containing crystalline properties. .

[0212] Furthermore, after oxide semiconductor formation, the substrate 101 is subjected to heat treatment to further remove the oxide semiconductor In addition to releasing hydrogen, a portion of the oxygen contained in the base layer 102 is absorbed by the oxide semiconductor and the base layer It is preferable to diffuse the heat treatment near the interface of the oxide semiconductor in layer 102. By performing this process, an oxide semiconductor with a higher crystalline CAAC-OS is formed. It is possible.

[0213] The temperature of this heat treatment causes hydrogen to be released from the oxide semiconductor and is contained in the underlying layer 102. A temperature that releases some of the oxygen and further diffuses it into the oxide semiconductor is preferred, and typically... The temperature is 200°C or higher but below the strain point of the substrate 101, preferably 250°C or higher and 450°C or lower. By diffusing oxygen into the oxide semiconductor, the oxygen vacancies in the oxide semiconductor can be reduced. It is possible.

[0214] Furthermore, this heat treatment uses an RTA (Rapid Thermal Annealing) device. This is possible. By using RTA, heat treatment can be performed at a temperature above the substrate's strain point for a short period of time. This allows for the following: oxide semiconductors with a high proportion of crystalline regions compared to amorphous regions. This can shorten the time required to form it.

[0215] Heat treatment can be carried out in an inert gas atmosphere, typically using helium, neon, or aluminum. It is preferable to carry out the process in a noble gas such as gon, xenon, or krypton, or in a nitrogen atmosphere. The procedure may also be carried out in an oxygen atmosphere or a reduced pressure atmosphere. The processing time should be 3 minutes to 24 hours. The longer the interval, the more crystalline the oxide semiconductor is formed compared to the amorphous region. While this is possible, heat treatment exceeding 24 hours is undesirable as it leads to a decrease in productivity.

[0216] Using the above method, an oxide semiconductor made of CAAC-OS can be formed.

[0217] This embodiment can be implemented in appropriate combination with other embodiments.

[0218] (Embodiment 4) In this embodiment, the transistor using the oxide semiconductor shown in Embodiment 1 and Embodiment 2 is used. The effect of the zista on the electrical characteristics will be explained using a band diagram.

[0219] Figure 8 is a cross-sectional view of a transistor having a stacked structure equivalent to that of transistor 100 shown in Figure 1. Figure 9 shows the energy band diagram (schematic diagram) in the X1-X2 section shown in Figure 8. Furthermore, Figure 9(B) shows the case where the voltage between the source and drain is at equipotential (VD=0V). Figure 8 shows the first oxide semiconductor region (referred to as OS1) and a pair of second acids. An oxide semiconductor layer consisting of an oxide semiconductor region (referred to as OS2), and a source electrode and a drain electrode. It is a transistor formed by electrodes (referred to as metal).

[0220] The channel formation region of the transistor in Figure 8 is formed by OS1, and OS1 This process involves removing and desorbing as much impurities as possible, such as water (including hydrogen), from the membrane to achieve high purity. Furthermore, by reducing oxygen deficiency in the membrane, it is made true (type i), or as close to true as possible. It is formed from an oxide semiconductor that is close to the property. By doing so, the Fermi level ( Ef) can be brought to the same level as the true Fermi level (Ei).

[0221] Furthermore, the source and drain regions of the transistor in Figure 8 are defined by a pair of OS2. OS2 is formed, and like OS1 above, it absorbs moisture (including hydrogen) and other impurities from within the membrane. The goal is to remove and desorb as much of the pure material as possible to achieve high purity, and further reduce oxygen deficiency in the membrane. To make it more intrinsic (type i), or to make it as close to intrinsic as possible, an oxide semiconductor is used, and then, Adding an element selected from at least one of hydrogen or a noble gas. It is formed by causing a donor or oxygen deficiency. As a result, OS2 is O Compared to S1, the carrier density is higher, and the Fermi level is located closer to the conduction band.

[0222] Figure 9(A) shows the vacuum level (referred to as Evac) and the first oxide semiconductor region (referred to as OS1). , a second oxide semiconductor region (referred to as OS2), and source and drain electrodes (met This is the relationship of the band structures (let's call it al). Here, IP is the ionization potential, and Ea is Electron affinity, Eg represents the energy gap, and Wf represents the work function. Also, Ec represents the conduction band. The lower end, Ev, and Fermi level are indicated. Note that the notation at the end of each symbol indicates the lower end, upper end of the valence band, and Fermi level. The numbers 1, 2, and m represent OS1, OS2, and metal, respectively. This assumes a Wf_m of 4.1 eV (for titanium, etc.).

[0223] OS1 is an i-type or substantially i-type oxide semiconductor with an extremely low carrier density. Therefore, we assume that Ef_1 is roughly in the middle of Ec and Ev. Also, OS2 is the carrier density These are highly n-type oxide semiconductors, and their Ec₂ and Ef₂ values ​​are approximately the same. (OS1 and OS2) The oxide semiconductor shown has an energy gap (Eg) of 3.15 eV and an electron affinity (Ea The reading is said to be 4.3 eV.

[0224] As shown in Figure 9(B), the channel formation region is OS1, and the source region and drain region are... When the OS2 region comes into contact, carrier movement occurs so that the Fermi levels match. The band edges of OS1 and OS2 are bent. Furthermore, OS2, the source electrode and the drain electrode Even when metal contacts occur, carrier movement occurs so that the Fermi levels match. This causes the band end of the OS2 to bend.

[0225] Thus, the channel-forming region is OS1, and the source and drain electrodes are met. The formation of OS2, an n-type oxide semiconductor, between al and the oxide semiconductor, results in the formation of an oxide semiconductor. This allows for ohmic contact with metal and reduces contact resistance. This is possible. As a result, the on-current of the transistor can be increased.

[0226] This embodiment can be implemented in appropriate combination with other embodiments.

[0227] (Embodiment 5) Figure 10(A) shows the circuit diagram of a memory element (hereinafter also referred to as a memory cell) that constitutes a semiconductor device. Here is an example. The memory cell uses a transistor that uses a material other than an oxide semiconductor in the channel formation region. The transistor 1162 uses a zista 1160 and an oxide semiconductor as the channel formation region. It is composed of [this].

[0228] The transistor 1162, which uses an oxide semiconductor in the channel formation region, is described in Embodiment 1. It can be manufactured by [this method].

[0229] As shown in Figure 10(A), the gate electrode of transistor 1160 and transistor 116 It is electrically connected to either the source electrode or the drain electrode of the two. What are the wiring (1st Line: also called the source line) and the source electrode of the transistor 1160? Electrically connected, the second line (also called the bit line) and the transistor The drain electrode of the TA1160 is electrically connected. And the third wiring (3rd Line (also called the first signal line) and the source electrode or drain of transistor 1162 The other electrode is electrically connected to the fourth wire (4th Line: also called the second signal line). The gate electrode of transistor 1162 is electrically connected to the gate electrode.

[0230] Transitions using materials other than oxide semiconductors, such as single-crystal silicon, in the channel formation region Because transistor 1160 is capable of sufficiently high-speed operation, by using transistor 1160, It is possible to perform tasks such as reading stored data at high speed. Furthermore, oxide semiconductors are used as channels. The transistor 1162 used in the formation region has a smaller off-current compared to the transistor 1160. It has the characteristic of being such that by turning off transistor 1162 This makes it possible to maintain the potential of the gate electrode of transistor 1160 for an extremely long period of time. It is Noh.

[0231] By taking advantage of the characteristic that the potential of the gate electrode can be maintained, information can be written as follows: It can be held and read.

[0232] First, we will explain how to write and retain information. First, the potential of the fourth wire is... The potential at which transistor 1162 turns on is set to turn on transistor 1162. This allows the potential of the third wire to be applied to the gate electrode of transistor 1160. (Writing). Then, the potential of the fourth wire is set to the potential at which transistor 1162 is in the off state. By turning off transistor 1162, the gate of transistor 1160 is The potential of the electrode is maintained (held).

[0233] The off-current of transistor 1162 is smaller than that of transistor 1160, so The potential of the gate electrode of the 1160 is maintained for a long time. For example, a transistor If the potential of the gate electrode of transistor 1160 is the potential that turns on transistor 1160, then The transistor 1160 will remain in the ON state for an extended period of time. The potential of the gate electrode of transistor 1160 is the potential that turns transistor 1160 off. If transistor 1160 remains in the off state for an extended period of time, this will be achieved.

[0234] Next, we will explain how to read the information. As mentioned above, when transistor 1160 is ON When the state is maintained as either the "on" or "off" state, a predetermined potential (low potential) is applied to the first wiring. When this occurs, the potential of the second wiring depends on whether transistor 1160 is on or off. It takes different values. For example, when transistor 1160 is ON, the first wiring The potential of the second wiring will decrease relative to the potential of the first wiring. Also, transistor 1160 When the device is in the off state, the potential of the second wire does not change.

[0235] In this way, while the information is retained, the potential of the second wiring is compared with a predetermined potential. By doing so, information can be extracted.

[0236] Next, we will explain how to rewrite information. Rewriting information involves writing and saving the above information. This is done in the same way as holding. In other words, the potential of the fourth wire is set when transistor 1162 is ON. To achieve this potential, transistor 1162 is turned ON. This allows the power of the third wiring to be turned ON. A potential (related to new information) is applied to the gate electrode of transistor 1160. Next, the potential of the fourth wire is set to the potential at which transistor 1162 is in the off state. By turning off STA1162, the new information will be retained.

[0237] Thus, the memory cell relating to the disclosed invention directly generates information through subsequent writing. It is possible to rewrite the information. Therefore, it is necessary in flash memory and other applications. This eliminates the need for an erase operation, thus suppressing the decrease in operating speed caused by the erase operation. In other words, high-speed operation of semiconductor devices containing memory cells is achieved.

[0238] Furthermore, Figure 10(B) shows an example of a memory cell circuit diagram that is an extension of Figure 10(A).

[0239] The memory cell 1100 shown in Figure 10(B) has a first wiring SL (source line) and a second wiring BL (bit line), third wiring S1 (first signal line), and fourth wiring S2 (second signal line) And the fifth wiring WL (word wire), and transistor 1164 (the first transistor), Transistor 1161 (second transistor) and transistor 1163 (third transistor) It consists of a transistor 1164 and a transistor 1163. Other materials than oxide semiconductors are used in the channel formation region, and transistor 1161 is oxide A monocrystalline semiconductor is used in the channel formation region.

[0240] Here, the gate electrode of transistor 1164 and the source electrode of transistor 1161 It is electrically connected to one of the drain electrodes. Also, the first wiring SL and the transistor The source electrode of transistor 1164 is electrically connected to the drain of transistor 1164. The electrode and the source electrode of transistor 1163 are electrically connected. Wiring BL 2 and the drain electrode of transistor 1163 are electrically connected, and the third The wiring S1 and the other of the source electrode or drain electrode of transistor 1161 are electrically connected. The fourth wiring S2 is connected to the gate electrode of transistor 1161, and the gate electrode of transistor 1161 is electrically connected to it. Furthermore, the fifth wiring WL and the gate electrode of transistor 1163 are electrically connected. ru.

[0241] Next, I will explain the operation of the circuit in detail.

[0242] When writing to memory cell 1100, set the first wiring SL to 0V and the fifth wiring WL to Set the voltage to 0V, the second wire BL to 0V, and the fourth wire S2 to 2V. Write data "1" to this location. In this case, set the third wire S1 to 2V, and when writing data "0", set the third wire S1 to 0V. At this time, transistor 1163 is in the off state and transistor 1161 is in the on state. Yes. Furthermore, when writing is complete, before the potential of the third wiring S1 changes, the fourth Set wiring S2 to 0V and turn off transistor 1161.

[0243] As a result, after writing data "1", the gate electrode of transistor 1164 is connected to the Node.js. The potential of node A (hereinafter referred to as node A) is approximately 2V, and after writing data "0", the potential of node A is approximately The voltage becomes 0V. Node A accumulates a charge corresponding to the potential of the third wiring S1, but the transistor The off-current of the ZISTA 1161 is a transistor that uses single-crystal silicon in the channel formation region. Compared to that, it is small, and the potential of the gate electrode of transistor 1164 is maintained for a long time. ru.

[0244] Next, when reading the memory cell, set the first wiring SL to 0V and the fifth wiring WL to 2V. V, the fourth wire S2 is set to 0V, the third wire S1 is set to 0V, and it is connected to the second wire BL. The read circuit is set to the operating state. At this time, transistor 1163 is ON, The STA1161 will be turned off.

[0245] If the data is "0," meaning node A is at approximately 0V, then transistor 1164 is in the off state. Therefore, the resistance between the second wiring BL and the first wiring SL is high. On the other hand, data If node A is at approximately 2V, then transistor 1164 is ON. Therefore, the resistance between the second wiring BL and the first wiring SL will be low. The readout circuit is memo The data "0" and "1" can be read from the difference in the resistance state of the recell. The second wiring BL was set to 0V when connected, but it is charged to a floating state or a potential above 0V. It's okay if it's floating. The third wire S1 was set to 0V during reading, but it's floating. It is also acceptable if it is charged to a potential of 0V or higher.

[0246] Note that the definitions of data "1" and data "0" are for convenience only, and they could be reversed. Furthermore, the operating voltages mentioned above are just examples. The operating voltage is such that when the data is "0", transistor 1 Transistor 164 is in the off state, and transistor 1164 is in the on state when the data is "1". Also, transistor 1161 is ON during writing and OFF at other times. If you select it so that the transistor 1163 turns ON when reading out, That's fine. In particular, instead of 2V, you can use the power supply potential VDD of the surrounding logic circuits.

[0247] In this embodiment, for the sake of ease of understanding, we will explain the smallest memory unit (1 bit) memory cell. As revealed, the configuration of memory cells is not limited to this. Multiple memory cells can be appropriately configured. They can also be connected to form more advanced semiconductor devices. For example, multiple of the above memory cells can be connected. Using these, it is possible to construct NAND and NOR type semiconductor devices. Wiring configuration Furthermore, the figures are not limited to Figure 10(A) or Figure 10(B), and can be modified as appropriate.

[0248] Figure 11 shows a block of a semiconductor device according to one embodiment of the present invention having an m × n bit memory capacity. The circuit diagram is shown.

[0249] The semiconductor device shown in Figure 11 has m fifth and fourth wirings, and n second wirings and A third wiring and multiple memory cells 1100(1,1)~1100(m,n) arranged in m rows. Memory cell array 11 arranged in a matrix of ) × n columns (where m and n are natural numbers) 10, and the second wiring and third wiring drive circuits 1111, and the fourth wiring and fifth wiring drive It is composed of peripheral circuits such as circuit 1113 and read circuit 1112. A refresh circuit or the like may be provided as an edge circuit.

[0250] Let's consider memory cell 1100(i, j) as a representative of each memory cell. Here, memory cells Lu1100(i, j) (where i is an integer between 1 and m, and j is an integer between 1 and n) is the second Wiring BL(j), third wiring S1(j), fifth wiring WL(i), and fourth wiring S2(i ), and the first wiring are connected respectively. The first wiring is given the first wiring potential Vs. It is obtained. Also, the second wiring BL(1)~BL(n) and the third wiring S1(1)~S 1(n) is connected to the second wiring and the third wiring drive circuit 1111 and the read circuit 1112, and the fifth The wiring WL(1)~WL(m) and the fourth wiring S2(1)~S2(m) are the fourth wiring and Each is connected to the fifth wiring drive circuit 1113.

[0251] The operation of the semiconductor device shown in Figure 11 will be explained. In this configuration, line-by-line writing and reading are performed. Perform the dispensing.

[0252] When writing to memory cells 1100(i,1) to 1100(i,n) in the i-th row, Set the wiring potential Vs of wire 1 to 0V, the fifth wiring WL(i) to 0V, and the second wiring BL(1)~BL( Let n) be 0V and the fourth wiring S2(i) be 2V. At this time, transistor 1161 is The state is as follows. The third wiring S1(1)~S1(n) is the column where data "1" is written, which is 2V The column to which the data "0" is written will be set to 0V. Furthermore, when writing is complete, the third distribution Before the potential of lines S1(1) to S1(n) changes, set the fourth wire S2(i) to 0V, Turn off transistor 1161. Also, the unselected fifth wire WL is 0V, unselected. The fourth wire S2 is set to 0V.

[0253] As a result, the gate voltage of transistor 1164 of the memory cell that wrote data "1" The potential of the node connected to the pole (hereinafter referred to as Node A) is approximately 2V, and the data "0" is written. The potential at node A of the selected memory cell is approximately 0V. The ranking remains unchanged.

[0254] To read memory cells 1100(i,1) to 1100(i,n) in the i-th row, Set the potential of the first wiring Vs to 0V, the fifth wiring WL(i) to 2V, and the fourth wiring S2(i) to 0V. The third wiring S1(1)~S1(n) is set to 0V, and the second wiring BL(1)~BL(n) The connected read circuit is put into operation. In the read circuit, for example, the resistance of the memory cell is... Based on the difference in the resistance state, the data "0" or "1" can be read. Note that the 5th non-selected state The wiring WL is set to 0V, and the unselected fourth wiring S2 is also set to 0V. Note that the second wiring during writing... Although BL is set to 0V, it is acceptable for it to be in a floating state or charged to a potential above 0V. The third wiring S1 was set to 0V during reading, but it may be in a floating state or at a potential of 0V or higher. It's okay if it's electrified.

[0255] Note that the definitions of data "1" and data "0" are for convenience only, and they could be reversed. Furthermore, the operating voltages mentioned above are just examples. The operating voltage is such that when the data is "0", transistor 1 Transistor 164 is in the off state, and transistor 1164 is in the on state when the data is "1". Also, transistor 1161 is ON during writing and OFF at other times. If you select it so that the transistor 1163 turns ON when reading out, That's fine. In particular, instead of 2V, you can use the power supply potential VDD of the surrounding logic circuits.

[0256] This embodiment can be implemented in appropriate combination with other embodiments.

[0257] (Embodiment 6) In this embodiment, an example of a circuit diagram of a memory cell having a capacitive element is shown. Figure 12(A) shows The memory cell 1170 shown has a first wiring SL, a second wiring BL, a third wiring S1, and a fourth wiring BL Wiring S2, the fifth wiring WL, transistor 1171 (the first transistor), and It consists of a transistor 1172 (the second transistor) and a capacitive element 1173. Transistor 1171 uses a material other than an oxide semiconductor in the channel formation region, The Rangista 1172 uses an oxide semiconductor in the channel formation region.

[0258] Here, the gate electrode of transistor 1171 and the source electrode of transistor 1172 One of the drain electrodes and one of the electrodes of the capacitive element 1173 are electrically connected. Furthermore, the first wiring SL and the source electrode of transistor 1171 are electrically connected. The second wiring BL and the drain electrode of transistor 1171 are electrically connected, The wiring S1 of 3 and the other of the source electrode or drain electrode of transistor 1172 are connected by electricity. The fourth wire S2 and the gate electrode of transistor 1172 are electrically connected. The fifth wiring WL and the other electrode of the capacitive element 1173 are electrically connected. Yes, they are.

[0259] Next, I will explain the operation of the circuit in detail.

[0260] When writing to memory cell 1170, set the first wiring SL to 0V and the fifth wiring WL to Set the voltage to 0V, the second wire BL to 0V, and the fourth wire S2 to 2V. Write data "1" to this location. In this case, set the third wire S1 to 2V, and when writing data "0", set the third wire S1 to 0V. At this time, transistor 1172 will be in the ON state. Then, before the potential of the third wiring S1 changes, the fourth wiring S2 is set to 0V, and the transistor Turn off the Ta1172.

[0261] As a result, after writing data "1", it is connected to the gate electrode of transistor 1171. The potential of node A (hereinafter referred to as node A) is approximately 2V, and after writing data "0", the potential of node A The voltage becomes approximately 0V.

[0262] When reading from memory cell 1170, set the first wiring SL to 0V and the fifth wiring WL to With 2V, the fourth wire S2 set to 0V, the third wire S1 set to 0V, and connected to the second wire BL. The readout circuit is set to the operating state. At this time, transistor 1172 is in the off state. .

[0263] The state of transistor 1171 when the fifth wiring WL is set to 2V will be explained. The potential of node A, which determines the state of the generator 1171, is the capacitance between the fifth wiring WL and node A. C1, the gate electrode of transistor 1171, and the capacitance C between the source electrode and the drain electrode. It depends on 2.

[0264] Note that the third wiring S1 was set to 0V during reading, but it may be floating or at a potential of 0V or higher. It's fine if it's charged. Data "1" and data "0" are definitions for convenience, and the opposite is true. That's fine.

[0265] The potential of the third wire S1 during writing is such that transistor 1172 is in the off state after writing. Furthermore, in the range where transistor 1171 is in the off state when the fifth wiring potential is 0V Then, you just need to select the potentials for data "0" and "1" respectively. The potential of the fifth wiring when reading is When the data is "0", transistor 1171 is turned off, and when the data is "1", the transistor You should select the transistor 1171 so that it turns on. Also, the transistor 1171 The key voltage is just one example. As long as it does not change the state of the transistor 1171 as described above. Any threshold value is fine.

[0266] Furthermore, a select transistor having a first gate electrode and a second gate electrode, and a capacitive element An example of a NOR-type semiconductor memory device using a memory cell having the following characteristics is shown in Figure 12(B). I will explain.

[0267] A semiconductor device according to one aspect of the present invention, shown in Figure 12(B), has an I row (where I is a natural number greater than or equal to 2) J A memory cell array with multiple memory cells arranged in a matrix in columns (where J is a natural number) It possesses the characteristics of (i).

[0268] The memory cell array shown in Figure 12(B) has i rows (where i is a natural number greater than or equal to 3) and j columns (where j is greater than or equal to 3). Multiple memory cells 1180 arranged in a matrix (a natural number of ), and i word lines W L (word line WL_1 to word line WL_i) and i capacitance lines CL (capacitance line CL_1 to To the capacity line CL_i) and i gate lines BGL (gate line BGL_1 to gate line BGL _i), j bit lines BL (bit line BL_1 to bit line BL_j), and source line It is equipped with an SL (steam locomotive).

[0269] Furthermore, each of the multiple memory cells 1180 (memory cell 1180(M,N)(however A transistor (also called a transistor) is a natural number between 1 and i (M is a natural number between 1 and j) 1181(M,N), capacitive element 1183(M,N), and transistor 1182(M,N ) and are provided.

[0270] In addition, in semiconductor memory devices, the capacitive element comprises a first capacitive electrode, a second capacitive electrode, and It is composed of a dielectric layer superimposed on a first capacitive electrode and a second capacitive electrode. Charge is accumulated in accordance with the voltage applied between the first capacitive electrode and the second capacitive electrode.

[0271] Transistor 1181(M,N) is an N-channel transistor, and has a source electrode and a dotted It has a rain electrode, a first gate electrode, and a second gate electrode. In semiconductor memory devices, transistor 1181 is not necessarily an N-channel transistor. You don't have to.

[0272] One of the source and drain electrodes of transistor 1181(M,N) is connected to the bit line BL. The first gate electrode of transistor 1181(M,N) is connected to the word line WL. The second gate electrode of transistor 1181(M,N) is connected to _M, and the gate wire BG Connected to L_M. Source and drain electrodes of transistor 1181(M,N) By configuring one side to be connected to the bit line BL_N, each memory cell can be selectively bitten. The data can be read.

[0273] Transistor 1181(M,N) is a selected transistor in memory cell 1180(M,N). It functions as a zista (radioactive marker).

[0274] As for transistor 1181(M,N), an oxide semiconductor is used in the channel formation region. A transistor can be used.

[0275] Transistor 1182(M,N) is a P-channel transistor. In the form of semiconductor memory, transistor 1182 is not necessarily a P-channel type transistor You don't have to make it a standard.

[0276] One of the source and drain electrodes of transistor 1182(M,N) is connected to the source wire SL The source electrode and the other drain electrode of transistor 1182(M,N) are connected to the other, The bit line BL_N is connected, and the gate electrode of transistor 1182(M,N) is connected to the transistor It is connected to the source electrode and the other of the drain electrode of the ZISTA 1181(M,N).

[0277] Transistor 1182(M,N) is an output transistor in memory cell 1180(M,N). It functions as a transistor. For example, the transistor 1182(M,N) can be used in single-phase configuration. A transistor can be used that uses crystalline silicon in the channel formation region.

[0278] The first capacitance electrode of the capacitance element 1183(M,N) is connected to the capacitance line CL_M, and the capacitance element The second capacitive electrode of transistor 1183(M,N) is the source electrode of transistor 1181(M,N). And it is connected to the other side of the drain electrode. Note that the capacitive element 1183(M,N) is a retaining capacitance It functions as such.

[0279] The voltages of each word line WL_1 through WL_i are, for example, controlled by a decoder. It is controlled by a dynamic circuit.

[0280] The voltages of bit lines BL_1 through BL_j are, for example, controlled by a decoder. It is controlled by a dynamic circuit.

[0281] The voltages of capacitance lines CL_1 to CL_i are, for example, the number of times a decoder is used for driving. It is controlled by the road.

[0282] The voltages of gate lines BGL_1 through BGL_i are, for example, the gate line drive cycle. It is controlled using roads.

[0283] The gate line drive circuit includes, for example, a diode and a first capacitive electrode which is the anode and of the diode. It consists of a circuit equipped with a capacitive element electrically connected to the gate line BGL.

[0284] By adjusting the voltage of the second gate electrode of transistor 1181, The threshold voltage of 181 can be adjusted. Therefore, it functions as a selector transistor. Adjust the threshold voltage of transistor 1181 and the off state of transistor 1181 The current flowing between the drain electrode and the drain electrode can be minimized. Therefore, memory The data retention period in the circuit can be extended. Also, data writing and reading can be improved. Because the voltage required for output can be lower than that of conventional semiconductor devices, power consumption is reduced. It is possible.

[0285] This embodiment can be implemented in appropriate combination with other embodiments.

[0286] (Embodiment 7) In this embodiment, an example of a semiconductor device using the transistor shown in the previous embodiment is described below. This will be explained with reference to Figure 13.

[0287] Figure 13(A) shows what is known as DRAM (Dynamic Random Access). An example of a semiconductor device with a configuration equivalent to memory is shown. Figure 13(A) shows the memory The Luar Array 1120 has a configuration in which multiple memory cells 1130 are arranged in a matrix. Furthermore, the memory cell array 1120 has m first wirings and n second wirings. It has. In this embodiment, the first wiring is called the bit line BL, and the second wiring The line is called the word line (WL).

[0288] The memory cell 1130 is composed of a transistor 1131 and a capacitive element 1132. The gate electrode of transistor 1131 is connected to the first wiring (word line WL). It is. Also, one of the source electrode or drain electrode of transistor 1131 is the second distribution It is connected to the line (bit line BL) and the source electrode or drain of transistor 1131. The other electrode of the capacitor is connected to one of the electrodes of the capacitive element. It is connected to the capacitance line CL and a constant potential is applied. Transistor 1131 has the The transistor shown in the embodiment is applied.

[0289] The transistor that uses an oxide semiconductor as the channel formation region as shown in the previous embodiment is Compared to transistors using single-crystal silicon in the channel formation region, the off-current is smaller. It has the following characteristics. For this reason, it is recognized as a so-called DRAM, as shown in Figure 13(A). When this transistor is applied to a semiconductor device, it is possible to obtain a substantially non-volatile memory. It is possible.

[0290] Figure 13(B) shows what is known as SRAM (Static Random Access Module). An example of a semiconductor device with a configuration equivalent to a memory cell is shown. Figure 13(B) shows a memory cell. The array 1140 has a configuration in which multiple memory cells 1150 are arranged in a matrix. This is possible. In addition, the memory cell array 1140 has a first wiring (word line WL), a second It has multiple wires for the first wiring (bit line BL) and multiple wires for the second wiring (inverting bit line / BL).

[0291] Memory cell 1150 consists of a first transistor 1151, a second transistor 1152, and Transistor 3 1153, Transistor 4 1154, Transistor 5 1155 , and the sixth transistor 1156. The first transistor 1151 and the second Transistor 1152 functions as a selection transistor. Also, the third transistor Of transistors 1153 and the fourth transistor 1154, one is an n-channel type transistor (here So, the fourth transistor is 1154), and the other is a p-channel transistor (here This is the third transistor 1153). In other words, the third transistor 1153 and the fourth The CMOS circuit is formed by transistor 1154. Similarly, the fifth transistor The CMOS circuit is composed of transistor 1155 and the sixth transistor 1156.

[0292] First transistor 1151, second transistor 1152, fourth transistor 115 4. The sixth transistor 1156 is an n-channel type transistor, and is in the form of the previous implementation. The transistor shown in the diagram can be applied. The third transistor 1153 and The fifth transistor, 1155, is a p-channel type transistor, and is made of a material other than oxide semiconductors. The material (for example, single-crystal silicon) is used in the channel formation region.

[0293] The configurations and methods shown in this embodiment may be combined with the configurations and methods shown in other embodiments as appropriate. They can be used together.

[0294] This embodiment can be implemented in appropriate combination with other embodiments.

[0295] (Embodiment 8) A CPU that uses at least a portion of transistors with oxide semiconductors in the channel formation region. A Central Processing Unit (Central Processing Unit) can be configured.

[0296] Figure 14(A) is a block diagram showing the specific configuration of the CPU. The PU has an arithmetic logic unit (ALU) on board 1190. nit)1191, ALU controller 1192, instruction decoder 1193 Interrupt controller 1194, timing controller 1195, register 11 96, Register Controller 1197, Bus Interface (Bus I / F) 119 8. Rewritable ROM 1199 and ROM interface (ROM I / F) 1 It has 189. The substrate 1190 is a semiconductor substrate, SOI substrate, glass substrate, etc. The ROM 1199 and ROM interface 1189 may be provided on separate chips. Of course, the CPU shown in Figure 14(A) is merely one example of a simplified configuration, and the actual configuration is different. CPUs have a wide variety of configurations depending on their intended use.

[0297] Instructions input to the CPU via the bus interface 1198 are instructions The signal is input to decoder 1193, decoded, and then processed by ALU controller 1192, interface Raptor controller 1194, register controller 1197, timing controller It is entered into 1195.

[0298] ALU controller 1192, interrupt controller 1194, register controller R1197 and timing controller 1195 control various commands based on the decoded instructions. To perform the operation. Specifically, the ALU controller 1192 controls the operation of the ALU 1191. It generates a signal for that purpose. Also, the interrupt controller 1194 is the CPU programmer. During execution, interrupt requests from external input / output devices and peripheral circuits are prioritized and masked. The state is judged and processed. The register controller 1197 adds register 1196 It generates a response and reads or writes to register 1196 depending on the CPU state.

[0299] Furthermore, the timing controller 1195 is connected to the ALU 1191 and the ALU controller 119 2. Instruction decoder 1193, interrupt controller 1194, and It generates a signal that controls the timing of the operation of the zista controller 1197. For example, The ming controller 1195 uses the reference clock signal CLK1 to generate the internal clock signal C It is equipped with an internal clock generation unit that generates LK2, and the clock signal CLK2 is used in the various cycles described above. To supply to the road.

[0300] In the CPU shown in Figure 14(A), a memory element is provided in register 1196. The memory element of STA 1196 can be the memory element described in Embodiment 5. Cut.

[0301] In the CPU shown in Figure 14(A), the register controller 1197 is ALU1191 Following the instructions, select a hold operation in register 1196. That is, register In the memory element of Ta 1196, data retention is performed by a phase inversion element, or capacity Select whether to retain data using an element. Selecting data retention using a phase inversion element. If this is the case, power voltage is supplied to the memory elements in register 1196. If data retention in the element is selected, data will be rewritten to the capacitive element. This allows the supply of power voltage to the memory elements in register 1196 to be stopped.

[0302] Regarding power shutdown, as shown in Figure 14(B) or Figure 14(C), the memory element group and the power A switching element is installed between nodes where the source potential VDD or power supply potential VSS is provided. This can be done by doing so. The circuits in Figures 14(B) and 14(C) are explained below. conduct.

[0303] Figures 14(B) and 14(C) show a switch that controls the supply of power potential to the memory element. The memory circuit configuration includes a transistor in which an oxide semiconductor is used as the channel formation region. Here is an example.

[0304] The memory device shown in Figure 14(B) consists of a switching element 1141 and multiple memory elements 1142. It has a group of memory elements 1143. Specifically, each memory element 1142 has an embodiment The memory elements described in Form 5 can be used. Each of the memory element group 1143 The memory element 1142 receives a high-level power supply potential VD via the switching element 1141. D is supplied. Furthermore, each memory element 1142 of the memory element group 1143 has a signal The potential of point IN and the potential of the low-level power supply (VSS) are given.

[0305] In Figure 14(B), the switching element 1141 is an oxide semiconductor channel formation region. It uses a transistor, and the signal given to the gate electrode of the transistor Switching is controlled by SigA.

[0306] Note that in Figure 14(B), the switching element 1141 has only one transistor. While it indicates a configuration, it is not particularly limited and may have multiple transistors. When element 1141 has multiple transistors that function as switching elements The above-mentioned transistors may be connected in parallel or in series. Furthermore, a combination of series and parallel connections is also acceptable.

[0307] Furthermore, in Figure 14(B), the switching element 1141 controls the memory element group 1143. The supply of a high-level power supply potential VDD to each memory element 1142 is controlled, Even when the supply of a low-level power supply potential VSS is controlled by the switching element 1141, good.

[0308] Furthermore, Figure 14(C) shows that each memory element 1142 of the memory element group 1143 has a switch. A low-level power supply potential VSS is supplied to the memory device via the 1141 element. Here is an example. The switching element 1141 controls each memory element of the memory element group 1143. The supply of a low-level power potential VSS to 1142 can be controlled.

[0309] Between the memory element group and the node to which the power supply potential VDD or power supply potential VSS is provided, When a switching element is installed to temporarily stop the CPU's operation and cut off the power supply voltage, It is possible to retain data even while power consumption is reduced. Specifically In terms of this, for example, when a personal computer user uses an input device such as a keyboard, Even when you stop inputting information, you can stop the CPU from operating, thereby consuming It can reduce power consumption.

[0310] Here, we used the CPU as an example, but DSP (Digital Signal Processor) Processor), custom LSI, FPGA (Field Programmable) It can also be applied to LSIs such as e Gate Arrays.

[0311] This embodiment can be implemented in appropriate combination with other embodiments. [Explanation of Symbols]

[0312] 100 transistors 101 circuit board 102 Base layer 103 Oxide semiconductor layer 104 Gate Insulation Layer 105 Guard Station 106 Dopant 107 Insulating layer 108 Insulating layer 109 Contact Holes 111 Sidewall 112 channel protection layer 113 Insulating layer 115 Back gate 140 transistors 150 transistors 160 transistors 170 transistors 180 transistors 190 transistors 1100 cell cells 1110 memory cell array 1111 Wiring drive circuit 1112 Circuit 1113 Wiring drive circuit 1120 memory cell array 1130 memory cells 1131 Transistors 1132 Capacitive element 1140 memory cell array 1141 Switching element 1142 memory element 1143 Memory element group 1150 memory cells 1151 Transistors 1152 Transistors 1153 Transistors 1154 Transistors 1155 Transistor 1156 Transistors 1160 transistors 1161 transistors 1162 transistors 1163 Transistors 1164 transistors 1170 cell cells 1171 transistors 1172 transistors 1173 Capacitive element 1180 memory cells 1181 Transistors 1182 transistors 1183 Capacitive element 1189 ROM Interface 1190 circuit board 1191 ALU 1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Register 1197 Register Controller 1198 Bus Interface 1199 ROM 103a Source area 103b Drain area 103c Channel formation region 103d Low concentration area 103e Low concentration area 105a Gridgate 105b Guard gate 110a Source electrode 110b Drain electrode

Claims

[Claim 1] It comprises a gate electrode, a gate insulating layer, a crystalline oxide semiconductor layer, and a channel protection layer. The gate insulating layer is formed on the gate electrode, The oxide semiconductor layer is formed on the gate insulating layer, The channel protection layer is formed on the oxide semiconductor layer, The oxide semiconductor layer has a first oxide semiconductor region and a pair of second oxide semiconductor regions. The pair of second oxide semiconductor regions are formed sandwiching the first oxide semiconductor region. The first oxide semiconductor region is superimposed on the gate electrode via the gate insulating layer and is in contact with the channel protective layer. The second oxide semiconductor region comprises at least one element selected from noble gases or hydrogen, with a concentration of 5 × 10⁻⁶. １９ atoms / cm ３ The above is 1 x 10 ２２ atoms / cm ３ It contains the following concentrations: The semiconductor device is characterized in that the oxide semiconductor layer has indium oxide.

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