Motherboard for display device, and method for manufacturing a display device.
The mother substrate for display devices, featuring a specific configuration with inorganic layers and island-like portions, addresses yield challenges in OLED manufacturing, resulting in improved reliability and efficiency.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- MAGNOLIA WHITE CORP
- Filing Date
- 2024-10-29
- Publication Date
- 2026-05-15
Smart Images
Figure 2026078885000001_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present invention relate to a mother substrate for a display device and a method of manufacturing a display device.
Background Art
[0002] In recent years, display devices applying organic light-emitting diodes (OLEDs) as display elements have been put into practical use. In this type of display device, technologies for improving the yield are required.
Prior Art Documents
Patent Documents
[0003]
Patent Document 1
Patent Document 2
Patent Document 3
Patent Document 4
Patent Document 5
Patent Document 6
Patent Document 7
Summary of the Invention
Problems to be Solved by the Invention
[0004] One object of the present invention is to provide a mother substrate for a display device capable of improving the yield and a method of manufacturing a display device.
Means for Solving the Problems
[0005] Generally, according to the embodiment, the mother board for a display device comprises a display area for displaying an image, a margin area outside a cut line for cutting out the display area, an inorganic insulating layer disposed in the display area and the margin area, a display element disposed in the display area, a first partition wall disposed above the inorganic insulating layer in the margin area, a first sealing layer made of an inorganic insulating material and disposed above the display element and the first partition wall, and a first resin layer disposed on the first sealing layer in the margin area.
[0006] According to another embodiment, the mother board for a display device includes a display area for displaying an image, a margin area outside a first cut line for cutting out the display area, a display element disposed in the display area, a first partition wall disposed in the margin area, a first sealing layer made of an inorganic insulating material and disposed above the display element and the first partition wall, a first resin layer disposed on the first sealing layer in the margin area, and a second resin layer disposed on the first sealing layer in the display area. The margin area has a plurality of island-like portions including the first partition wall, the first sealing layer, and the first resin layer. In a plan view, the island-like portions are arranged around the first cut line, away from the second resin layer.
[0007] Furthermore, according to the embodiment, the method for manufacturing a display device includes preparing a substrate including a display area for displaying an image and a margin area outside a first cut line for cutting out the display area; forming an inorganic insulating layer in the display area and the margin area; forming a first partition wall including a lower part and an upper part having an end protruding from the side surface of the lower part on the inorganic insulating layer in the margin area; forming a display element in the display area; forming a first sealing layer above the display element and the first partition wall; and forming a first resin layer on the first sealing layer in the margin area. [Brief explanation of the drawing]
[0008] [Figure 1] Figure 1 shows an example of the configuration of a display device according to one embodiment. [Figure 2] FIG. 2 is a schematic plan view showing an example of the layout of sub-pixels. [Figure 3] FIG. 3 is a schematic cross-sectional view of the display panel along line III-III in FIG. 2. [Figure 4] FIG. 4 is a schematic plan view of the mother substrate according to the present embodiment. [Figure 5] FIG. 5 is a schematic plan view of a part of the mother substrate. [Figure 6] FIG. 6 is a schematic cross-sectional view of the panel portion along line VI-VI in FIG. 5. [Figure 7] FIG. 7 is a schematic enlarged view of part VII in FIG. 6. [Figure 8] FIG. 8 is a flowchart showing an example of a method for manufacturing a display device. [Figure 9A] FIG. 9A is a schematic cross-sectional view showing the manufacturing process of the display device. [Figure 9B] FIG. 9B is a schematic cross-sectional view showing the process following FIG. 9A. [Figure 9C] FIG. 9C is a schematic cross-sectional view showing the process following FIG. 9B. [Figure 9D] FIG. 9D is a schematic cross-sectional view showing the process following FIG. 9C. [Figure 9E] FIG. 9E is a schematic cross-sectional view showing the process following FIG. 9D. [Figure 9F] FIG. 9F is a schematic cross-sectional view showing the process following FIG. 9E. [Figure 9G] FIG. 9G is a schematic cross-sectional view showing the process following FIG. 9F. [Figure 9H] FIG. 9H is a schematic cross-sectional view showing the process following FIG. 9G. [Figure 9I] FIG. 9I is a schematic cross-sectional view showing the process following FIG. 9H. [Figure 9J] FIG. 9J is a schematic cross-sectional view showing the process following FIG. 9I. [Figure 10A] FIG. 10A is a schematic cross-sectional view showing the partition wall of the island portion and the surrounding structure in the manufacturing process of the display device. [Figure 10B]FIG. 10B is a schematic cross-sectional view showing the process following FIG. 10A. [Figure 10C] FIG. 10C is a schematic cross-sectional view showing the process following FIG. 10B10B. [Figure 10D] FIG. 10D is a schematic cross-sectional view showing the process following FIG. 10C. [Figure 11A] FIG. 11A is a schematic cross-sectional view of a terminal portion for explaining the process of providing openings in the rib layer and the sealing layer of the terminal portion. [Figure 11B] FIG. 11B is a schematic cross-sectional view showing the process following FIG. 11A. [Figure 11C] FIG. 11C is a schematic cross-sectional view showing the process following FIG. 11B. [Figure 11D] FIG. 11D is a schematic cross-sectional view showing the process following FIG. 11C. [Figure 12] FIG. 12 is a schematic plan view of a mother board according to a comparative example. [Figure 13] FIG. 13 is a schematic plan view of a mother board according to an embodiment. [Figure 14] FIG. 14 is a plan view showing another shape example of the panel body.
DETAILED DESCRIPTION OF THE INVENTION
[0009] Hereinafter, embodiments will be described with reference to the drawings. It should be noted that the disclosure is merely an example, and for those that can be easily conceived by those skilled in the art with appropriate modifications while maintaining the gist of the invention, they are naturally included in the scope of the present invention. Also, the drawings may be schematically represented in terms of the width, thickness, shape, etc. of each part compared to the actual aspect for the sake of clearer explanation, but this is merely an example and does not limit the interpretation of the present invention. Further, in this specification and each figure, components that exhibit the same or similar functions as those described above with respect to the already presented figures may be given the same reference numerals, and detailed descriptions that are redundant may be omitted as appropriate.
[0010] Furthermore, the drawings will include mutually orthogonal X, Y, and Z axes as needed to facilitate understanding. The direction along the X axis will be referred to as the first direction X, the direction along the Y axis as the second direction Y, and the direction along the Z axis as the third direction Z. Viewing the various elements parallel to the third direction Z is called a plan view.
[0011] The display device according to this embodiment is an organic electroluminescent display device equipped with an organic light-emitting diode (OLED) as a display element, and can be mounted on various electronic devices such as televisions, personal computers, in-vehicle equipment, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.
[0012] Figure 1 shows an example configuration of a display device DSP according to this embodiment. The display device DSP includes a display panel PNL including an insulating substrate 10. The display panel PNL has a display area DA for displaying an image and a peripheral area SA around the display area DA. The substrate 10 may be glass or a flexible resin film.
[0013] In this embodiment, the shape of the substrate 10 and the display area DA in plan view is circular. Here, the circular shape is not limited to a perfect circle, but includes shapes such as a circle with a part missing, an ellipse, or an oblong shape. Furthermore, the shape of the substrate 10 and the display area DA in plan view is not limited to a circle, but may be other shapes such as a rectangle, square, or ellipse.
[0014] In the example shown in Figure 1, an annular dam structure DS is positioned in the surrounding region SA. The dam structure DS encloses the display region DA. The shape of the dam structure DS in plan view is, for example, circular, but is not limited to this example. The dam structure DS can be formed, for example, by an organic insulating layer 12 (see Figure 3), which will be described later.
[0015] The display area DA comprises a plurality of pixels PX arranged in a matrix in a first direction X and a second direction Y. Each pixel PX includes a plurality of sub-pixels SP that display different colors. In this embodiment, it is assumed that each pixel PX includes a sub-pixel SP1 of a first color, a sub-pixel SP2 of a second color, and a sub-pixel SP3 of a third color. For example, the first color is blue, the second color is green, and the third color is red, but this is not an example. Each pixel PX may include sub-pixels SP of other colors, such as white, together with sub-pixels SP1, SP2, and SP3, or in place of any one of sub-pixels SP1, SP2, and SP3.
[0016] The display device DSP further includes a terminal section T located in the peripheral region SA. A flexible circuit board, for example, that supplies voltage and signals for driving the display device DSP, is connected to the terminal section T.
[0017] The sub-pixel SP comprises a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 comprises a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements composed of, for example, thin-film transistors.
[0018] The display area DA is arranged with multiple scan lines GL that supply scan signals to the pixel circuit 1 of each sub-pixel SP, multiple signal lines SL that supply video signals to the pixel circuit 1 of each sub-pixel SP, and multiple power lines PL. In the example in Figure 1, the scan lines GL and power lines PL extend in the first direction X, and the signal lines SL extend in the second direction Y.
[0019] The gate electrode of pixel switch 2 is connected to the scan line GL. One of the source and drain electrodes of pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of drive transistor 3 and capacitor 4. In drive transistor 3, one of the source and drain electrodes is connected to the power line PL and capacitor 4, and the other is connected to display element DE.
[0020] Note that the configuration of the pixel circuit 1 is not limited to the example shown. For example, the pixel circuit 1 may include more thin-film transistors and capacitors.
[0021] Figure 2 is a schematic plan view showing an example of the layout of sub-pixels SP1, SP2, and SP3. In the example in Figure 2, sub-pixels SP2 and SP3 are aligned with sub-pixel SP1 in the first direction X. Furthermore, sub-pixels SP2 and SP3 are aligned in the second direction Y.
[0022] When sub-pixels SP1, SP2, and SP3 are arranged in this manner, the display area DA forms columns in which sub-pixels SP2 and SP3 are alternately arranged in the second direction Y, and columns in which multiple sub-pixels SP1 are repeatedly arranged in the second direction Y. These columns are arranged alternately in the first direction X. Note that the layout of sub-pixels SP1, SP2, and SP3 is not limited to the example in Figure 2.
[0023] A rib layer 5 is arranged in the display area DA. In this embodiment, the rib layer 5 is an example of an inorganic insulating layer. The rib layer 5 has pixel apertures AP1, AP2, and AP3 in the sub-pixels SP1, SP2, and SP3, respectively. In the example in Figure 2, pixel aperture AP1 is larger than pixel aperture AP2, and pixel aperture AP2 is larger than pixel aperture AP3. That is, among the sub-pixels SP1, SP2, and SP3, sub-pixel SP1 has the largest aperture ratio, and sub-pixel SP3 has the smallest aperture ratio. However, the sizes of pixel apertures AP1, AP2, and AP3 are not limited to this example.
[0024] Sub-pixel SP1 comprises a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, which overlap with the pixel aperture AP1. Sub-pixel SP2 comprises a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, which overlap with the pixel aperture AP2. Sub-pixel SP3 comprises a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, which overlap with the pixel aperture AP3.
[0025] The portion of the lower electrode LE1, upper electrode UE1, and organic layer OR1 that overlaps with the pixel aperture AP1 constitutes the display element DE1 of the sub-pixel SP1. The portion of the lower electrode LE2, upper electrode UE2, and organic layer OR2 that overlaps with the pixel aperture AP2 constitutes the display element DE2 of the sub-pixel SP2. The portion of the lower electrode LE3, upper electrode UE3, and organic layer OR3 that overlaps with the pixel aperture AP3 constitutes the display element DE3 of the sub-pixel SP3. The display elements DE1, DE2, and DE3 may further include a cap layer, which will be described later. The rib layer 5 surrounds each of these display elements DE1, DE2, and DE3.
[0026] A conductive partition wall 6 (second partition wall) is positioned above the rib layer 5. The partition wall 6 serves as wiring that supplies a common voltage to the upper electrodes UE1, UE2, and UE3. The partition wall 6 overlaps with the rib layer 5 overall and has a similar planar shape to the rib layer 5.
[0027] Specifically, partition wall 6 has partition opening 601A in sub-pixel SP1, partition opening 602A in sub-pixel SP2, and partition opening 603A in sub-pixel SP3. Partition openings 601A, 602A, and 603A overlap with the entirety of pixel openings AP1, AP2, and AP3, respectively. Furthermore, partition openings 601A, 602A, and 603A overlap with the entirety of display elements DE1, DE2, and DE3, respectively. In other words, partition wall 6 surrounds display elements DE1, DE2, and DE3.
[0028] Figure 3 is a schematic cross-sectional view of the display panel PNL along the line III-III in Figure 2. A circuit layer 11 is placed on the substrate 10 described above. The circuit layer 11 includes various circuits and wiring, such as the pixel circuit 1, scan line GL, signal line SL, and power line PL shown in Figure 1. The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that flattens the irregularities caused by the circuit layer 11.
[0029] The lower electrodes LE1, LE2, and LE3 are positioned on top of the organic insulating layer 12. The rib layer 5 is positioned on top of the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the rib layer 5. Although not shown in the cross-section of Figure 3, the lower electrodes LE1, LE2, and LE3 are each connected to the pixel circuit 1 of the circuit layer 11 through contact holes provided in the organic insulating layer 12.
[0030] The partition wall 6 includes a conductive lower part 61 positioned on the rib layer 5 and an upper part 62 positioned on the lower part 61. In this embodiment, the lower part 61 of the partition wall 6 corresponds to the second lower part, and the upper part 62 of the partition wall 6 corresponds to the second upper part.
[0031] The upper section 62 has a greater width than the lower section 61. As a result, both ends of the upper section 62 protrude beyond the sides of the lower section 61. This shape of the partition wall 6 is called an overhang.
[0032] In the example shown in Figure 3, the lower section 61 has a bottom layer 63 positioned on top of the rib layer 5 and an axial layer 64 positioned on top of the bottom layer 63. For example, the bottom layer 63 is formed to be thinner than the axial layer 64. Also, in the example shown in Figure 3, both ends of the bottom layer 63 protrude from the sides of the axial layer 64.
[0033] Furthermore, in the example shown in Figure 3, the upper section 62 comprises a first top layer 65 and a second top layer 66 positioned on top of the first top layer 65. For example, the width of the second top layer 66 is slightly smaller than the width of the first top layer 65. However, it is not limited to this, and the first top layer 65 and the second top layer 66 may have equivalent widths.
[0034] The organic layer OR1 covers the lower electrode LE1 through the pixel aperture AP1. The upper electrode UE1 covers the organic layer OR1 and faces the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel aperture AP2. The upper electrode UE2 covers the organic layer OR2 and faces the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel aperture AP3. The upper electrode UE3 covers the organic layer OR3 and faces the lower electrode LE3. The upper electrodes UE1, UE2, and UE3 are in contact with the side surface of the lower part 61 of the partition wall 6.
[0035] Display element DE1 includes a cap layer CP1 placed on top of the upper electrode UE1. Display element DE2 includes a cap layer CP2 placed on top of the upper electrode UE2. Display element DE3 includes a cap layer CP3 placed on top of the upper electrode UE3. The cap layers CP1, CP2, and CP3 each serve as optical adjustment layers that improve the efficiency of light extraction from the organic layers OR1, OR2, and OR3, respectively.
[0036] In the following explanation, a multilayer containing an organic layer OR1, an upper electrode UE1, and a cap layer CP1 will be referred to as multilayer film FL1, a multilayer containing an organic layer OR2, an upper electrode UE2, and a cap layer CP2 will be referred to as multilayer film FL2, and a multilayer containing an organic layer OR3, an upper electrode UE3, and a cap layer CP3 will be referred to as multilayer film FL3.
[0037] Sub-pixels SP1, SP2, and SP3 are each fitted with sealing layers SE11, SE12, and SE13, respectively. Sealing layer SE11 continuously covers the laminated film FL1 and the partition wall 6 surrounding sub-pixel SP1. Sealing layer SE12 continuously covers the laminated film FL2 and the partition wall 6 surrounding sub-pixel SP2. Sealing layer SE13 continuously covers the laminated film FL3 and the partition wall 6 surrounding sub-pixel SP3.
[0038] In the example shown in Figure 3, the sealing layer SE11 on the partition wall 6 between sub-pixels SP1 and SP2 is separated from the sealing layer SE12 on the same partition wall 6. Also, the sealing layer SE11 on the partition wall 6 between sub-pixels SP1 and SP3 is separated from the sealing layer SE13 on the same partition wall 6. However, any two of the sealing layers SE11, SE12, and SE13 may be in contact above the partition wall 6.
[0039] For example, gaps are formed between the sealing layers SE11, SE12, SE13 and the upper part 62 of the partition wall 6. The laminated films FL1, FL2, FL3 may be placed in at least a portion of these gaps.
[0040] The sealing layers SE11, SE12, and SE13 are covered by the resin layer RS1. The resin layer RS1 is covered by the sealing layer SE2. The sealing layer SE2 is covered by the resin layer RS2. The resin layers RS1, RS2, and the sealing layer SE2 are provided continuously over at least the entire display area DA, with a portion of them extending into the peripheral area SA.
[0041] In the example shown in Figure 3, the touch panel electrode TP is placed on the sealing layer SE2. The touch panel electrode TP is covered by a resin layer RS2. The touch panel electrode TP can be formed by metal wiring. This wiring may face the partition wall 6 in the third direction Z. Furthermore, this wiring may have a planar shape similar to that of the partition wall 6.
[0042] A cover member, such as a polarizing plate, protective film, or cover glass, may be further placed above the resin layer RS2. Such a cover member may be bonded to the resin layer RS2 via an adhesive layer, such as OCA (Optical Clear Adhesive).
[0043] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The rib layer 5 and the sealing layers SE11, SE12, SE13, SE2 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON). In one example, the rib layer 5 is formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, SE2 are formed of silicon nitride. The resin layers RS1, RS2 are formed of a resin material (organic insulating material) such as epoxy resin or acrylic resin.
[0044] The lower electrodes LE1, LE2, and LE3 each have a reflective layer made of, for example, silver, and a pair of conductive oxide layers covering the upper and lower surfaces of this reflective layer, respectively. Each conductive oxide layer can be made of a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).
[0045] The upper electrodes UE1, UE2, and UE3 are formed from a metallic material such as a magnesium-silver alloy (MgAg). For example, the lower electrodes LE1, LE2, and LE3 correspond to the anode, and the upper electrodes UE1, UE2, and UE3 correspond to the cathode.
[0046] The organic layers OR1, OR2, and OR3 are composed of multiple thin films including an emissive layer. In one example, the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, an emissive layer, a hole blocking layer, an electron transport layer, and an electron injection layer are stacked in the third direction Z in sequence. However, the organic layers OR1, OR2, and OR3 may have other structures, such as a so-called tandem structure including multiple emissive layers.
[0047] The cap layers CP1, CP2, and CP3 have a laminated structure in which multiple transparent layers are stacked, for example. These transparent layers may include layers formed from inorganic materials and layers formed from organic materials. Furthermore, these transparent layers have different refractive indices. For example, the refractive indices of these transparent layers are different from those of the upper electrodes UE1, UE2, and UE3 and the sealing layers SE11, SE12, and SE13. Note that at least one of the cap layers CP1, CP2, and CP3 may be omitted.
[0048] The bottom layer 63 and axial layer 64 of the partition wall 6 are formed of a metallic material. For example, the metallic material for the bottom layer 63 can be molybdenum, titanium, titanium nitride (TiN), molybdenum-tungsten alloy (MoW), or molybdenum-niobium alloy (MoNb). For example, the metallic material for the axial layer 64 can be aluminum, aluminum-neodymium alloy (AlNd), aluminum-yttrium alloy (AlY), or aluminum-silicon alloy (AlSi). The axial layer 64 may also be formed of an insulating material.
[0049] The first top layer 65 of the partition wall 6 is formed of, for example, a metallic material. The second top layer 66 of the partition wall 6 is formed of, for example, a conductive oxide. As the metallic material forming the first top layer 65, for example, titanium, titanium nitride, molybdenum, tungsten, molybdenum-tungsten alloy, or molybdenum-niobium alloy can be used. As the conductive oxide forming the second top layer 66, for example, ITO or IZO can be used. The upper part 62 may consist of three or more layers, or it may be formed of a single layer. Furthermore, the upper part 62 may include a layer formed of an insulating material.
[0050] A common voltage is supplied to the partition wall 6. This common voltage is supplied to the upper electrodes UE1, UE2, and UE3, which are in contact with the sides of the lower part 61. The lower electrodes LE1, LE2, and LE3 are supplied with pixel voltages corresponding to the video signal on the signal line SL through the pixel circuits 1 of the sub-pixels SP1, SP2, and SP3, respectively.
[0051] The organic layers OR1, OR2, and OR3 emit light in response to the application of voltage. Specifically, when a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of organic layer OR1 emits light in the wavelength range of the first color. When a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of organic layer OR2 emits light in the wavelength range of the second color. When a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of organic layer OR3 emits light in the wavelength range of the third color.
[0052] During the manufacturing of a display device (DSP), a large motherboard is created in which multiple areas corresponding to the display panel PNL are formed. The following describes the configurations that can be applied to this motherboard.
[0053] Figure 4 is a schematic plan view of the motherboard MB (display device motherboard) according to this embodiment. The motherboard MB is rectangular in shape as shown in the figure, but it may also be circular or have other shapes.
[0054] The motherboard MB has multiple panel sections PP arranged in a matrix. In the example shown in Figure 4, the multiple panel sections PP are arranged continuously in the first direction X and the second direction Y. However, the arrangement of the multiple panel sections PP on the motherboard MB is not limited to this example.
[0055] Figure 5 is a schematic plan view of a portion of the motherboard (MB). In Figure 5, we focus on one of the panel sections (PP) shown in Figure 4.
[0056] In the example shown in Figure 5, the shape of the panel PP in plan view is square. However, the shape of the panel PP in plan view may also be a rectangle that is elongated in the first direction X, or a rectangle that is elongated in the second direction Y. Furthermore, the shape of the panel PP in plan view may include multiple straight and curved sections.
[0057] The outline of each panel section PP corresponds to the cut line CL1 (second cut line) used to cut each panel section PP from the motherboard MB. The cut line CL1 is formed in a grid pattern. Focusing on a single panel section PP, the cut line CL1 is formed in a square shape.
[0058] Furthermore, a cut line CL2 (first cut line) is formed on the panel portion PP. Cut line CL2 corresponds to the outer shape of the display panel PNL shown in Figure 1. Cut line CL2 is formed in a circular shape. Cut line CL2 corresponds to the cut line for cutting out a portion of the display area DA and the surrounding area SA from the panel portion PP. Hereinafter, the area inside cut line CL2 may be referred to as the panel body PNLB.
[0059] The panel section PP has the display area DA and the peripheral area SA described above. The peripheral area SA includes the margin area FA outside the cut line CL2. The margin area FA corresponds, for example, to the area between cut line CL1 and cut line CL2. Cut line CL1 corresponds to the cut line for cutting out the display area DA and the margin area FA from the motherboard MB.
[0060] The cut line CL2 divides the panel section PP into a portion including the display area DA and a portion including the margin area FA. Between the cut line CL1 and the cut line CL2, several inspection pads (not shown) are placed to check the operation of the display panel PNL.
[0061] In this embodiment, a partition wall 7 (first partition wall) is positioned in the peripheral region SA, which includes the margin region FA. In Figure 5, a dot pattern is shown in the region where the partition wall 7 may be positioned. The partition wall 7 can be positioned in the region between the display region DA and the cut line CL2, the margin region FA, etc. However, the partition wall 7 does not have to be positioned in at least one of these regions. Furthermore, the position and planar shape of the partition wall 7 in these regions can be determined as appropriate.
[0062] From the viewpoint of efficiently cutting out the panel portion PP, it is preferable that a partition wall 7 is not provided at the cut line CL1. Similarly, it is preferable that a partition wall 7 is not provided at the cut line CL2.
[0063] The margin area FA has multiple island-shaped portions IP. Specifically, the multiple island-shaped portions IP are arranged around the cut line CL2 in a plan view. More specifically, the multiple island-shaped portions IP are arranged between the cut line CL1 and the cut line CL2 in a plan view. In addition, the multiple island-shaped portions IP are arranged away from the cut line CL2.
[0064] In the example shown in Figure 5, each island-shaped IP is positioned at a corner CN of the cut line CL1. The corner CN is formed by a straight section extending in the first direction X and a straight section extending in the second direction Y of the cut line CL1. In Figure 5, each island-shaped IP is given a diagonal pattern.
[0065] In this embodiment, four island-shaped IPs are arranged for one panel section PP. The number and position of island-shaped IPs arranged for one panel section PP can be appropriately changed according to the shape of the panel body PNLB.
[0066] The island-shaped IP protrudes in the third direction Z more than the rest of the area within the margin region FA. In other words, the island-shaped IP has a greater thickness than the rest of the area within the margin region FA. The island-shaped IP is formed by laminating multiple layers (for example, sealing layers SE1x, SE2 and resin layer RS3, which will be described later) above the partition wall 7.
[0067] Each island-shaped IP has a similar shape, for example, centered around the display area DA. Here, we will focus on one island-shaped IP (island-shaped IP1 in Figure 5) and describe its shape in plan view.
[0068] The island-shaped portion IP1 has sides M1, M2, and M3. In other words, the island-shaped portion IP1 has a side surface that includes sides M1, M2, and M3. This side surface extends upward from the substrate 10. Side M1 extends in the first direction X. Side M2 extends in the second direction Y. The length of side M1 is, for example, approximately equal to the length of side M2.
[0069] Side M3 extends in directions different from the first direction X and the second direction Y. Specifically, side M3 is formed along the cut line CL2. Side M3 may be formed in a curved shape or a straight shape.
[0070] These edges M1, M2, and M3 are connected by shorter edges SM, which are shorter than the edges M1, M2, and M3. Note that edges M1, M2, and M3 may also be directly connected. Furthermore, the shape of the island-like portion IP1 in plan view is not limited to the example in Figure 5.
[0071] Figure 6 is a schematic cross-sectional view of the panel section PP along the line VI-VI in Figure 5. In Figure 6, the panel section PP is viewed in the direction opposite to the first direction X. In Figure 6, the panel body PNLB represents the peripheral region SA.
[0072] The aforementioned organic insulating layer 12 and rib layer 5 are also formed in the surrounding region SA, including the margin region FA. In Figure 6, elements below the organic insulating layer 12 are omitted.
[0073] The partition wall 7 is positioned on top of the rib layer 5. The multilayer film FLx is positioned on top of the partition wall 7. The multilayer film FLx is formed using the same process and materials as any of the multilayer films FL1, FL2, or FL3 shown in Figure 3. In other words, the multilayer film FLx is composed of the same layers as any of the multilayer films FL1, FL2, or FL3. The multilayer film FLx is formed using the same process and materials as, for example, the multilayer film FL3. Therefore, the cap layer CP3 is also positioned in the margin region FA.
[0074] A sealing layer SE1x is placed on top of the multilayer film FLx. The sealing layer SE1x is formed using the same process and materials as any of the sealing layers SE11, SE12, or SE13 shown in Figure 3. For example, the sealing layer SE1x is formed using the same process and materials as the sealing layer SE13. In this embodiment, sealing layers SE11, SE12, SE13, and SE1x correspond to the first sealing layer.
[0075] A resin layer is placed on top of the sealing layer SE1x. Both the sealing layer SE1x and the resin layer are covered by a sealing layer SE2 (second sealing layer). In addition, other layers (e.g., an overcoat layer) may be formed above the sealing layer SE2 of the panel body PNLB.
[0076] Here, we will describe the resin layer positioned above the sealing layer SE1x. First, focusing on the panel body PNLB, the resin layer RS1 shown in Figure 3 is placed on top of the sealing layer SE1x. In this embodiment, the resin layer RS1 corresponds to the second resin layer.
[0077] The resin layer RS1 is formed by, for example, multiple layers. The resin layer RS1 includes resin layers RS11, RS12, and RS13. The resin layers RS11, RS12, and RS13 are stacked in this order in the third direction Z. In the example in Figure 6, an example in which the resin layer RS1 is formed by three layers is disclosed, but the resin layer RS1 may be formed by two or fewer layers, or by four or more layers.
[0078] Next, focusing on the island-shaped IP, a resin layer RS3 (first resin layer) is formed on top of the sealing layer SE1x. The resin layer RS3 is formed as a single layer. The resin layer RS3 is formed using the same process and the same material as the resin layer RS11 of the panel body PNLB. The island-shaped IP includes a partition wall 7, a laminated film FLx, a sealing layer SE1x, a resin layer RS3, and a sealing layer SE2.
[0079] The thickness T1 of resin layer RS3 (shown in Figure 6) is smaller than the thickness T2 of resin layer RS1 (shown in Figure 6). In other words, resin layer RS3 is thinner than resin layer RS1. Here, the thickness corresponds to the distance in the third direction Z from the upper surface of sealing layer SE1x to the lower surface of sealing layer SE2.
[0080] From another perspective, the upper surface SF1 of the panel body PNLB of the sealing layer SE2 is located above the upper surface SF2 of the island-shaped IP. Furthermore, the upper surface SF2 is located above the upper surface of the sealing layer SE2 located in areas other than the island-shaped IP.
[0081] Furthermore, the island-shaped IP (resin layer RS3) is separated from resin layer RS1. In other words, resin layer RS3 is separated from resin layer RS1.
[0082] The difference in thickness between the island-shaped IP and the panel body PNLB is due to differences in the thickness of the resin layers located in the island-shaped IP and the panel body PNLB. For example, the thickness of resin layers RS11, RS12, RS13, and RS3 is approximately 5 μm each, the thickness of sealing layer SE1x is approximately 2.2 μm, and the thickness of sealing layer SE2 is approximately 1 μm.
[0083] Figure 7 is a schematic enlarged view of section VII in Figure 6. In Figure 7, the vicinity of edge M3 (the end of the island-shaped section IP1) is shown.
[0084] The partition wall 7, like the partition wall 6, includes a lower section 61 and an upper section 62. In this embodiment, the lower section 61 of the partition wall 7 corresponds to the first lower section, and the upper section 62 of the partition wall 7 corresponds to the first upper section. The upper section 62 has a greater width than the lower section 61. The lower section 61 of the partition wall 7, like the partition wall 6, includes a bottom layer 63 and an axial layer 64. The upper section 62 of the partition wall 7, like the partition wall 6, includes a first top layer 65 and a second top layer 66.
[0085] The bottom layer 63, axial layer 64, first top layer 65, and second top layer 66 of partition wall 7 are formed of the same material as the bottom layer 63, axial layer 64, first top layer 65, and second top layer 66 of partition wall 6.
[0086] The laminated film FLx covers the rib layer 5 and the partition walls 7, respectively. Specifically, the laminated film FLx is positioned over the upper part 62 of the partition walls 7 and over the rib layer 5 between adjacent partition walls 7. The sealing layer SE1x continuously covers each segmented portion of the laminated film FLx and the partition walls 7. Focusing on the partition walls 7, the sealing layer SE1x is in contact with the lower part 61 and upper part 62 of the partition walls 7. Therefore, the partition walls 7 are not exposed from the sealing layer SE1x.
[0087] As described above, the resin layer RS3 and the sealing layer SE2 are placed on top of the sealing layer SE1x. Focusing on the edge S1E of the sealing layer SE1x, the edge R3E of the resin layer RS3 is located on top of the edge S1E of the sealing layer SE1x.
[0088] In other words, the resin layer RS3 does not protrude beyond the edge S1E of the encapsulating layer SE1x. In other words, a portion of the encapsulating layer SE1x is not covered by the resin layer RS3, but is covered by the encapsulating layer SE2.
[0089] Note that the position of the end R3E of the resin layer RS3 is not limited to the example in Figure 7. For example, the end R3E may be located further inside the island-shaped portion IP1 than in the example in Figure 7. Also, although the end R3E is located above the partition wall 7, it does not have to be located above the partition wall 7.
[0090] Next, an example of a method for manufacturing a display device DSP will be described. Figure 8 is a flowchart of an example of a method for manufacturing a display device DSP. Figures 9A to 9J are schematic cross-sectional views showing the manufacturing process of a display device DSP. In Figures 9A to 9J, the focus is mainly on the display area DA, and elements below the organic insulating layer 12 are omitted.
[0091] In forming the panel portion PP, first a mother board MB substrate 10 is prepared, and a circuit layer 11 and an organic insulating layer 12 are formed on it (step PR1 in Figure 8). Next, as shown in Figure 9A, lower electrodes LE1, LE2, and LE3 are formed on the organic insulating layer 12 (step PR2 in Figure 8).
[0092] Next, as shown in Figure 9B, a rib layer 5 covering the lower electrodes LE1, LE2, and LE3 is formed over the entire motherboard MB (step PR3 in Figure 8). At this point, the pixel apertures AP1, AP2, and AP3 are not yet provided on the rib layer 5. The rib layer 5 can be formed by CVD (Chemical Vapor Deposition).
[0093] After the formation of the rib layer 5, a process for forming the partition wall 6 is carried out (process PR4 in Figure 8). In process PR4, as shown in Figure 9C, a first layer L1 for processing into the bottom layer 63, a second layer L2 for processing into the axial layer 64, a third layer L3 for processing into the first top layer 65, and a fourth layer L4 for processing into the second top layer 66 are sequentially formed over the entire motherboard MB. Furthermore, a resist R1 is placed on top of the fourth layer L4. The resist R1 is patterned to the shape of the partition wall 6. The first layer L1, second layer L2, third layer L3, and fourth layer L4 can be formed, for example, by sputtering.
[0094] Subsequently, the first layer L1, second layer L2, third layer L3, and fourth layer L4 are patterned using the resist R1 as a mask. In one example, the first layer L1 is formed of titanium nitride, the second layer L2 is formed of aluminum, the third layer L3 is formed of titanium, and the fourth layer L4 is formed of ITO. In this case, the patterning may include wet etching to remove the portion of the fourth layer L4 exposed from the resist R1, dry etching to remove the portions of the first layer L1, second layer L2, and third layer L3 exposed from the resist R1, and wet etching to reduce the width of the second layer L2.
[0095] After step PR4, a partition wall 6 is formed in the display area DA, as shown in Figure 9D. After the formation of the partition wall 6, the resist R1 is removed (peeled off). In the wet etching process described above, which reduces the width of the second layer L2, the second top layer 66 (fourth layer L4) may also be slightly eroded. If this erosion occurs, the width of the second top layer 66 becomes smaller than the width of the first top layer 65.
[0096] Next, a process is carried out to create pixel apertures AP1, AP2, and AP3 (process PR5 in Figure 8). In this process PR5, a resist R2 is formed to cover the partition wall 6, as shown in Figure 9E. Furthermore, dry etching is performed on the rib layer 5 using the resist R2 as a mask. As a result, pixel apertures AP1, AP2, and AP3 that expose the lower electrodes LE1, LE2, and LE3 are formed on the rib layer 5, as shown in Figure 9F. After the dry etching, the resist R2 is removed (peeled off).
[0097] After step PR5, a process is performed to remove the rib layer 5 from the inspection pad located in the margin area FA (step PR6 in Figure 8). In step PR6, the resist that has been opened in the inspection pad is placed on top of the rib layer 5, and dry etching is performed on the rib layer 5.
[0098] After step PR6, a process for forming the display element DE1 is carried out (step PR7 in Figure 8). In forming the display element DE1, first, as shown in Figure 9G, a multilayer film FL1 and a sealing layer SE11 are formed. As shown in Figure 3, the multilayer film FL1 includes an organic layer OR1 that contacts the lower electrode LE1 through the pixel aperture AP1, an upper electrode UE1 that covers the organic layer OR1, and a cap layer CP1 that covers the upper electrode UE1. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 can be formed, for example, by vapor deposition. The sealing layer SE11 can be formed, for example, by CVD.
[0099] The laminated film FL1 and the sealing layer SE11 are formed on the entire motherboard MB, including not only the display area DA of each panel PP but also the surrounding area SA. The laminated film FL1 is divided into multiple parts by overhanging partition walls 6. The sealing layer SE11 continuously covers each divided part of the laminated film FL1 and the partition walls 6.
[0100] Next, the multilayer film FL1 and the sealing layer SE11 are patterned. In this patterning process, as shown in Figure 9G, a resist R3 is placed on top of the sealing layer SE11. The resist R3 covers the subpixel SP1 and a portion of the surrounding partition wall 6.
[0101] Subsequently, an etching process is performed using resist R3 as a mask. As a result, as shown in Figure 9H, the portions of the multilayer film FL1 and the sealing layer SE11 that are exposed from resist R3 are removed. In other words, the portions of the multilayer film FL1 and the sealing layer SE11 that overlap with the lower electrode LE1 are left, and the other portions are removed. This forms the display element DE1 on the sub-pixel SP1. For example, in the peripheral region SA, the multilayer film FL1 and the sealing layer SE11 are removed by this etching process. This etching process may include wet etching or dry etching performed sequentially on the sealing layer SE11, the cap layer CP1, the upper electrode UE1, and the organic layer OR1. After these etchings, resist R3 is removed (peeled off).
[0102] After step PR7, a process for forming the display element DE2 is carried out (step PR8 in Figure 8). The display element DE2 can be formed using the same procedure as the display element DE1. That is, in forming the display element DE2, the multilayer film FL2 and the sealing layer SE12 are formed over the entire mother substrate MB. As shown in Figure 3, the multilayer film FL2 includes an organic layer OR2 that contacts the lower electrode LE2 through the pixel aperture AP2, an upper electrode UE2 that covers the organic layer OR2, and a cap layer CP2 that covers the upper electrode UE2.
[0103] The organic layer OR2, the upper electrode UE2, and the cap layer CP2 can be formed, for example, by vapor deposition. The sealing layer SE12 can be formed, for example, by CVD. The multilayer film FL2 is divided into multiple parts by overhanging partition walls 6. The sealing layer SE12 continuously covers each divided part of the multilayer film FL2 and the partition walls 6. By patterning the multilayer film FL2 and the sealing layer SE2, a display element DE2 is formed on the sub-pixel SP2, as shown in Figure 9I. For example, in the peripheral region SA, the multilayer film FL2 and the sealing layer SE12 are removed by etching during the patterning process.
[0104] After step PR8, a process for forming the display element DE3 is carried out (step PR9 in Figure 8). The display element DE3 can be formed using the same procedure as for the display elements DE1 and DE2. That is, in forming the display element DE3, the multilayer film FL3 and the sealing layer SE13 are formed over the entire mother substrate MB. As shown in Figure 3, the multilayer film FL3 includes an organic layer OR3 that contacts the lower electrode LE3 through the pixel aperture AP3, an upper electrode UE3 that covers the organic layer OR3, and a cap layer CP3 that covers the upper electrode UE3.
[0105] The organic layer OR3, the upper electrode UE3, and the cap layer CP3 can be formed, for example, by vapor deposition. The sealing layer SE13 can be formed, for example, by CVD. The multilayer film FL3 is divided into multiple parts by overhanging partition walls 6. The sealing layer SE13 continuously covers each divided part of the multilayer film FL3 and the partition walls 6. By patterning the multilayer film FL3 and the sealing layer SE13, a display element DE3 is formed on the sub-pixel SP3, as shown in Figure 9J. For example, in the peripheral region SA, a portion of the multilayer film FL3 and the sealing layer SE13 is removed by etching during the patterning process.
[0106] However, in the areas within the margin region FA where multiple island-shaped IPs are formed, the laminated film FL3 and the sealing layer SE13 remain without being removed by etching. These remaining laminated film FL3 and sealing layer SE13 correspond to the laminated film FLx and sealing layer SE1x shown in Figure 6, respectively.
[0107] Note that, while this example assumes that the display elements DE1, DE2, and DE3 are formed in this order, they may be formed in any other order.
[0108] Figures 10A to 10D are schematic cross-sectional views showing the partition wall 7 of the island-shaped IP and its surrounding structure during the manufacturing process of the display device DSP.
[0109] The partition wall 7 in the margin area FA is formed together with the partition wall 6 in process PR4. After process PR4, an overhang-shaped partition wall 7 with a lower part 61 and an upper part 62 is formed, as shown in Figure 10A. The bottom layer 63, axial layer 64, first top layer 65, and second top layer 66 of this partition wall 7 are processed from the first layer L1, second layer L2, third layer L3, and fourth layer L4 described above, respectively.
[0110] After step PR9, a laminated film FLx and a sealing layer SE1x are formed on the island-shaped IP, as shown in Figure 10B. The laminated film FLx is formed on top of the partition wall 7 and between adjacent partition walls 7, as explained using Figure 7.
[0111] In other words, the multilayer film FLx is finely divided by the partition wall 7. This prevents the divided multilayer film FLx and the sealing layer SE1x covering them from peeling off from the substrate.
[0112] After process PR9, a process for forming the resin layer RS1 is carried out (process PR10 in Figure 8). The resin layer RS1 can be formed inside the dam structure DS (shown in Figure 1), for example, by an inkjet method. The dam structure DS serves to contain the resin layer RS1 before it hardens. Process PR10 includes multiple coating steps (for example, three times).
[0113] In the panel body PNLB, for example, a resin layer RS11 (shown in Figure 6) is formed by the first coating process, a resin layer RS12 (shown in Figure 6) is formed on top of resin layer RS11 by the subsequent second coating process, and a resin layer RS13 (shown in Figure 6) is formed on top of resin layer RS12 by the subsequent third coating process. In other words, forming resin layer RS1 includes forming multiple layers.
[0114] Furthermore, in step PR10 shown in Figure 8, a resin layer RS3 is formed on the sealing layer SE1x of the island-shaped IP, as shown in Figure 10C. The resin layer RS3 is formed between the margin region FA (cut line CL1 and cut line CL2). Specifically, the resin layer RS3 is formed at the corner CN of the cut line CL1 (shown in Figure 5).
[0115] For example, in the first coating step of process PR10, a resin layer RS3 is formed on the sealing layer SE1x of the island-shaped IP, along with the resin layer RS11, as shown in Figure 10C. In the second and third coating steps of process PR10, no resin layer is formed on the sealing layer SE1x of the island-shaped IP. As a result, the resin layer RS3 is formed thinner than the resin layer RS1. Specifically, the resin layer RS3 is formed by creating fewer layers than the resin layer RS1.
[0116] As shown in Figure 7, by placing the resin layer RS3 on top of the sealing layer SE1x, the resin layer RS3 is positioned at the edge S1E of the sealing layer SE1x due to surface tension, and the resin layer RS3 can be positioned in the intended location.
[0117] Here, an example is disclosed in which the resin layer RS3 of the island-shaped IP is formed simultaneously with the resin layer RS11 of the panel body PNLB. However, the resin layer RS3 of the island-shaped IP may also be formed simultaneously with the resin layer RS12 of the panel body PNLB, or simultaneously with the resin layer RS13 of the panel body PNLB.
[0118] After step PR10, a sealing layer SE2 is formed over the entire motherboard MB, for example by CVD (step PR11 in Figure 8). After step PR11, the resin layer RS1 of the panel body PNLB is covered with the sealing layer SE2.
[0119] Furthermore, the sealing layer SE1x and resin layer RS3 of the island-shaped IP are covered by the sealing layer SE2, as shown in Figures 7 and 10D. If a partition wall 7 is located in the marginal area FA in addition to the island-shaped IP, this partition wall 7 is covered by the sealing layer SE2.
[0120] After step PR11, a step is performed to remove the rib layer 5 and sealing layer SE2 covering the terminal portion T (step PR12 in Figure 8). Furthermore, a step is performed to remove the sealing layer SE2 around the terminal portion T (step PR13 in Figure 8).
[0121] Figures 11A to 11D are schematic cross-sectional views of the terminal section T for illustrating processes PR12 and PR13.
[0122] As shown in these figures, the terminal portion T is equipped with a conductive pad PD. The pad PD is placed on an insulating layer 110, which is made of, for example, an inorganic insulating material. The pad PD and the insulating layer 110 are included in the circuit layer 11 shown, for example, in Figure 3. For example, the periphery of the pad PD is covered with an organic insulating layer 12.
[0123] At the completion of step PR11, the pad PD is covered by the rib layer 5 and the sealing layer SE2, as shown in Figure 11A. In step PR12, a resist R4 with an opening above the pad PD is placed on top of the sealing layer SE2. Furthermore, dry etching is performed on the rib layer 5 and the sealing layer SE2 using the resist R4 as a mask.
[0124] As a result, as shown in Figure 11B, an opening APt that exposes the pad PD is formed in the rib layer 5 and the sealing layer SE2. After the dry etching described above, the resist R4 is removed (peeled off). For example, in Figure 11B, the edge E1 of the rib layer 5 surrounding the opening APt and the edge E2 of the sealing layer SE2 surrounding the opening APt are roughly aligned.
[0125] In step PR13, as shown in Figure 11C, a resist R5 with a shape larger than the opening APt is placed on top of the encapsulation layer SE2 above the pad PD. Furthermore, dry etching of the encapsulation layer SE2 is performed using the resist R5 as a mask. As a result, as shown in Figure 11D, the edge E2 of the encapsulation layer SE2 recedes away from the opening APt. In addition, the edge E2 becomes a gently sloping tapered shape.
[0126] By giving the edge portion E2 this shape, it is possible to suppress connection problems with the flexible circuit board etc. to the terminal portion T, compared to the case where the edges E1 and E2 form steep walls as shown in Figure 11C. After dry etching of the sealing layer SE2, the resist R5 is removed (peeled off).
[0127] In steps PR12 and PR13, contact openings for connecting the touch panel electrode TP (shown in Figure 3) and the wiring of the circuit layer 11 may be formed in the rib layer 5 and the sealing layer SE2.
[0128] After step PR13, the touch panel electrode TP is formed on the sealing layer SE2 (step PR14 in Figure 8). Specifically, first, a conductive layer for processing into the touch panel electrode TP is formed over the entire mother substrate MB. Next, a resist in the shape corresponding to the touch panel electrode TP is placed, and the conductive layer is etched using this resist as a mask. After this etching, the resist is removed (peeled off).
[0129] After step PR14, a resin layer RS2 is formed (step PR15 in Figure 8). The resin layer RS2 can be formed inside the dam structure DS, for example, by an inkjet method. The dam structure DS plays the role of blocking the resin layer RS2 before it hardens.
[0130] The resin layer RS2 may be formed by a photolithography process. In this case, first, a photosensitive resin for processing into the resin layer RS2 is formed over the entire motherboard MB. Then, the resin layer RS2 is formed on each panel portion PP through the processes of pre-baking, exposure, development, and firing of the photosensitive resin.
[0131] After step PR15, each panel section PP is cut out from the motherboard MB along the cut line CL1 (step PR16 in Figure 8). Furthermore, the margin area FA is cut along the cut line CL2 (step PR17 in Figure 8). This completes the display panel PNL.
[0132] According to this embodiment, it is possible to improve the yield of the display device DSP. Here, we assume the case where resist R5 is applied in process PR13.
[0133] Figure 12 is a schematic plan view of a motherboard MB10 according to a comparative example with this embodiment. The motherboard MB10 according to the comparative example differs from the motherboard MB according to this embodiment in that the island-shaped IP is not arranged in the margin area FA.
[0134] In the example shown in Figure 12, the resist R5 is applied in the direction of arrow A1 (opposite to the first direction X). For example, resist R5 is dripped from a nozzle (not shown) located above the motherboard MB10, and the entire motherboard MB10 is coated with resist R5 by moving the motherboard MB10 in the first direction X.
[0135] Focusing on the panel section PP located in the center on the right side of Figure 12, the resist R5 dropped from the nozzle first collides with the edge E10 of the panel body PNLB. A portion of the impacted resist R5 flows towards the panel body PNLB along the direction of arrow A1, while the other portion flows towards the panel body PNLB, wrapping around the outer surface of the panel body PNLB from the outside.
[0136] Furthermore, a gap G1 is formed between adjacent panel sections PP and the panel body PNLB. The island-shaped section IP in this embodiment is not located in the gap G1. The resist R5 flowing through the gap G1 flows towards the panel body PNLB, with a portion of it wrapping around from the gap G1 as indicated by arrow A2.
[0137] In such cases, differences in the velocity of the resist R5 flowing through the panel section PP tend to occur depending on the position in the second direction Y. Specifically, the velocity of the resist R5 increases as you move away from the center of the panel body PNLB in the second direction Y.
[0138] In Figure 12, arrows V1, V2, and V3 indicate the resist R5 flowing through the panel section PP, moving away from the center of the second direction Y in the panel body PNLB. The resist R5 flowing through the gap G1 corresponds to arrow V3.
[0139] The sizes of these arrows V1, V2, and V3 indicate the velocity of the resist R5. Arrow V2 is larger than arrow V1, and arrow V3 is larger than arrow V2. In other words, the velocity of resist R5 flowing through the center of the second direction Y in the panel body PNLB is the slowest, and the velocity of resist R5 flowing through the gap G1 is the fastest.
[0140] Thus, there is a significant difference in flow velocity between the resist R5 flowing through the center of the panel body PNLB in the second direction Y and the resist R5 flowing through the gap G1. Since the resist R5 flowing through the gap G1 has the highest velocity, it does not flow easily toward the edge E10 of the panel body PNLB, as indicated by arrow A2. As a result, a thin-walled section P10 is formed on the edge E10 side where the thickness of the resist R5 is smaller than in other parts. In Figure 12, a dot pattern is applied to the thin-walled section P10.
[0141] As described above, the resist R5 applied to the panel body PNLB is prone to uneven coating. Here, uneven coating refers to variations in the thickness of the resist R5. If uneven coating occurs in the resist R5, it can cause malfunctions in the manufactured display device DSP. Specifically, when the resist R5 is used as a mask, the thin-walled portion P10 may not function adequately as a mask, and layers located beneath the resist R5 may be removed more than necessary. This can lead to a decrease in the yield of the display device DSP.
[0142] Figure 13 is a schematic plan view of the motherboard MB according to this embodiment. The resist R5 is applied in the direction of arrow A1, similar to the example in Figure 12. Focusing on the panel section PP located in the center on the right side of Figure 13, the resist R5 dropped from the nozzle collides with the edge E10 of the panel body PNLB.
[0143] In this embodiment, island-shaped IP portions are arranged at each of the four corners of the panel portion PP. Therefore, the resist R5 also collides with these island-shaped IP portions (for example, the side including side M2 in Figure 4). The island-shaped IP portions have the function of reducing the speed of the resist R5 by colliding with them.
[0144] In this case, the difference in the velocity of the resist R5 at the position in the second direction Y of the panel body PNLB becomes smaller than in the comparative example. Specifically, since the resist R5 collides not only with the edge E10 but also with the island-shaped IP, there is less difference in the flow velocity of the resist R5 between the central part of the second direction Y of the panel body PNLB and the vicinity of the island-shaped IP.
[0145] Furthermore, by arranging the island-shaped IPs at the four corners of the panel section PP, the gap G1 shown in Figure 12 is divided into the gap G2 between the panel body PNLB and the island-shaped IP (side M3), the gap G3 between adjacent island-shaped IPs, and the gap G4 between adjacent panel body PNLBs. These gaps G2, G3, and G4 are smaller than the gap G1 in the comparative example.
[0146] As a result, the velocity of the resist R5 flowing through gaps G2, G3, and G4 is reduced, making it less likely for a velocity difference to occur in the resist R5 flowing at the second direction Y position in the panel body PNLB.
[0147] A portion of the resist R5 flowing through gap G2 flows towards the panel body PNLB. The resist R5 flowing through gap G3 proceeds along the edge M1 of the island-shaped IP in the direction of arrow A1, and a portion of it flows towards the panel body PNLB while circling around the island-shaped IP, as shown by arrow A2. It can be said that the island-shaped IP has a function to control the flow direction of the resist R5.
[0148] By arranging island-shaped IP portions in the margin area FA in this way, and reducing the difference in the speed of the flowing resist R5, the resist R5 flows more easily toward the panel body PNLB, and uneven coating of resist R5 can be suppressed compared to the comparative example.
[0149] In other words, by arranging island-shaped IP portions, the formation of the thin-walled portion P10 shown in Figure 12 can be suppressed. As a result, the resist R5 functions reliably as a mask, preventing the removal of the layer placed beneath the resist R5, which reduces the likelihood of defects in the manufactured display device DSP and improves the yield of the display device DSP.
[0150] In this embodiment, the island-shaped IP portions are arranged at the corners CN of the cut line CL1. This reduces the gaps between adjacent panel portions PP in the first direction X and the second direction Y, respectively, and between the panel bodies PNLB. As a result, the difference in the application speed of the resist R5 in each panel portion PP placed on the motherboard MB is reduced, and uneven application can be suppressed.
[0151] Furthermore, in this embodiment, the island-shaped IP has a thinner resin layer than the panel body PNLB. For example, if sufficient space cannot be secured at the four corners of the panel PP, the size of the island-shaped IP may not be able to be increased. Even in such cases, by reducing the thickness of the resin layer RS3, the resin layer RS3 can be reliably placed on the sealing layer SE1x. The size of the island-shaped IP can be changed as appropriate.
[0152] The suppression of resist coating unevenness by island-shaped IP in this embodiment is not limited to process PR13 in Figure 8. For example, resist coating unevenness can also be suppressed by arranging island-shaped IP in processes performed after process PR11, such as processes PR12 and PR14 in Figure 8. For example, in process PR14, a touch panel electrode TP of a desired shape can be obtained by suppressing resist coating unevenness.
[0153] With the manufacturing method for the motherboard MB and display device DSP configured as described above, the yield can be improved. In addition, various other desirable effects can be obtained from this embodiment.
[0154] Note that the shape of the panel body PNLB (display panel PNL) is not limited to the example described above. Figure 14 is a plan view showing another example of the shape of the panel body PNLB.
[0155] The panel body PNLB may be rectangular in shape. The corners C1 of the panel body PNLB may be rounded, as shown in Figure 14. The radius of curvature of the corners C1 can be changed as appropriate.
[0156] Even in such cases, the yield of the display device DSP can be improved by placing island-shaped IP at the corner CN of the panel PP. The shape of the island-shaped IP in plan view is not limited to the example shown.
[0157] Furthermore, although this embodiment discloses an example in which the thickness of resin layer RS3 is smaller than the thickness of resin layer RS1, the thickness of resin layer RS3 may be the same as the thickness of resin layer RS1. For example, the thickness of resin layer RS3 can be increased in step PR10 of Figure 8 by increasing the number of coating steps in the island-shaped IP.
[0158] All display devices, motherboards, and manufacturing methods that can be implemented by those skilled in the art by appropriately modifying the design based on the display devices, motherboards, and manufacturing methods described above as embodiments of the present invention also fall within the scope of the present invention insofar as they encompass the gist of the present invention.
[0159] Within the scope of the concept of the present invention, a person skilled in the art can conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, any modifications made by a person skilled in the art to add, delete, or change the design of any of the above-described embodiments, or to add, omit, or change the conditions of any process, are also included within the scope of the present invention, as long as they retain the essence of the present invention.
[0160] Furthermore, any other effects and advantages brought about by the embodiments described above that are obvious from the description herein or that can be appropriately conceived by those skilled in the art are naturally considered to be brought about by the present invention. [Explanation of Symbols]
[0161] 5...Rib layer, 6,7...Partition wall, 10...Substrate, 11...Circuit layer, 12...Organic insulating layer, 61...Lower part, 62...Upper part, AP1,AP2,AP3...Pixel aperture, CL1,CL2...Cut line, CP1,CP2,CP3...Cap layer, DA...Display area, DE1,DE2,DE3...Display element, DS...Dumb structure, DSP...Display device, FA...Margin area, FL1,FL2,FL3,FLx...Laminated film, GL...Scan line, IP...Island part, LE1,LE2,LE3...Lower electrode, MB...Mother substrate, OR1,OR2,OR3...Organic layer, PNL...Display panel, PP...Panel part, PX...Pixel, RS1,RS2,RS3...Resin layer, SA...Peripheral area, SE1x,SE2,SE11,SE12,SE13...Sealing layer, SL...Signal line, SP1,SP2,SP3...Sub-pixel, UE1,UE2,UE3...Upper electrode.
Claims
1. The display area for displaying the image, The margin area outside the cut line for cutting out the aforementioned display area, An inorganic insulating layer arranged in the display area and the margin area, A display element arranged in the aforementioned display area, In the margin region, a first partition wall is positioned above the inorganic insulating layer, A first sealing layer formed of an inorganic insulating material and positioned above the display element and the first partition wall, The margin region comprises a first resin layer disposed on the first sealing layer, Motherboard for display devices.
2. The first partition wall is, A first lower part disposed on the inorganic insulating layer, It has a first upper part positioned on the first lower part and protruding from the side surface of the first lower part, Mother board for display device according to claim 1.
3. The display area further comprises a second resin layer disposed on the first sealing layer, The first resin layer has a smaller thickness than the second resin layer. Mother board for display device according to claim 1.
4. It further comprises a second sealing layer formed of an inorganic insulating material and covering the first resin layer and the second resin layer, Motherboard for display device according to claim 3.
5. The first resin layer is formed by a single layer, The second resin layer is formed by a plurality of layers. Motherboard for display device according to claim 3.
6. The first resin layer is separated from the second resin layer. Motherboard for display device according to claim 3.
7. The display area is further provided with a second partition wall that surrounds the display element, The aforementioned second partition wall is A second lower part disposed on the inorganic insulating layer, It has a second upper part positioned above the second lower part and protruding from the side surface of the second lower part, Mother board for display device according to claim 1.
8. The display element further comprises a laminated film including an organic layer and an upper electrode, The laminated film is positioned between the first partition and the first sealing layer in the margin region. Mother board for display device according to any one of claims 1 to 7.
9. The laminated film is arranged between adjacent first partitions, Mother board for display device according to claim 8.
10. The laminated film further includes a cap layer disposed on the upper electrode, The cap layer is also placed in the margin area. Motherboard for display device according to claim 9.
11. The display area for displaying the image, The margin area outside the first cut line for cutting out the aforementioned display area, A display element arranged in the aforementioned display area, The first partition wall is positioned in the aforementioned margin area, A first sealing layer formed of an inorganic insulating material and positioned above the display element and the first partition wall, In the margin region, a first resin layer is disposed on the first sealing layer, The display area comprises a second resin layer disposed on the first sealing layer, The margin region has a plurality of island-like portions including the first partition wall, the first sealing layer, and the first resin layer. The island-shaped portion is, in a plan view, positioned around the first cut line, away from the second resin layer. Motherboard for display devices.
12. The island-shaped portion is positioned between the first cut line and the second cut line for cutting out the display area and the margin area. Mother board for display device according to claim 11.
13. The first cut line is formed in a circular shape, The second cut line is formed in a square shape. Mother board for display device according to claim 12.
14. The island-shaped portions are each located at the corners of the second cut line. Mother board for display device according to claim 13.
15. A substrate is prepared that includes a display area for displaying an image and a margin area outside the first cut line for cutting out the display area. An inorganic insulating layer is formed in the display area and the margin area. A first partition wall is formed on the inorganic insulating layer in the margin region, including a lower part and an upper part having an end protruding from the side surface of the lower part. A display element is formed in the display area. A first sealing layer is formed above the display element and the first partition wall. This includes forming a first resin layer on the first sealing layer in the margin region. A method for manufacturing a display device.
16. The further step is to form a second sealing layer covering the first resin layer with an inorganic insulating material. A method for manufacturing a display device according to claim 15.
17. The display area further includes forming a second resin layer disposed on the first sealing layer, Forming the first resin layer includes forming the first resin layer which is thinner than the second resin layer. A method for manufacturing a display device according to claim 15.
18. Forming the second resin layer includes forming a plurality of layers. Forming the first resin layer includes forming fewer layers than the second resin layer. A method for manufacturing a display device according to claim 17.
19. The display area and the margin area are cut out from the substrate along the second cut line. The method further includes cutting out the display area along the first cut line, Forming the first resin layer includes forming the first resin layer between the first cut line and the second cut line. A method for manufacturing a display device according to claim 17.
20. The first cut line is formed in a circular shape, The second cut line is formed in a square shape, Forming the first resin layer includes forming the first resin layer at the corner of the second cut line. A method for manufacturing a display device according to claim 19.