Semiconductor package structure and method for manufacturing a semiconductor package structure

Abstract

To provide a semiconductor package structure that enables further finer electrode pitch and further space saving on the surface of connecting components, thereby suppressing substrate warping. [Solution] The semiconductor package structure 1 comprises a semiconductor package 12 having a semiconductor chip 2 and a first redistribution layer 4 having a larger area than the semiconductor chip 2 in a plan view in the thickness direction, a cured resin layer 5 made of a cured product of an anisotropic conductive film 14 in which conductors 10 are aligned at predetermined intervals in an insulating resin layer, and another substrate 6. The first redistribution layer 4 has a semiconductor chip 2 mounted on one surface 4A and a first electrode 7 on the other surface 4B that connects to the other substrate 6. The other substrate 6 has a second electrode 11 on one surface 6A that connects to the first electrode 7. In the semiconductor package structure 1, the first electrode 7 and the second electrode 11 are connected by the conductors 10 in the cured resin layer 5.

Description

Technical Field

[0001] This technology relates to a semiconductor package structure and a method for manufacturing a semiconductor package structure.

Background Art

[0002] In FOWLP, a redistribution layer (RDL) is formed on the electrode surface of a semiconductor chip (die) by a wafer process, so that electrode formation for substrate connection is performed outside the semiconductor chip. In FOWLP, it is possible to minimize the wiring inside the semiconductor chip, enabling miniaturization and high performance of the semiconductor chip.

[0003] FIG. 1 is a cross-sectional view showing an example of FOWLP (Fan out Wafer Level Package). FIG. 2 is a cross-sectional view showing an example of a semiconductor package structure 100 in which FOWLP and a substrate are connected.

[0004] As shown in FIGS. 1 and 2, in a conventional semiconductor package structure 100, an electrode 102 drawn out by FOWLP 101 is connected (bonded) to an electrode 105 of a substrate 104 by a solder joint 103A composed of solder balls (solder bumps) (see, for example, Patent Document 1). FOWLP 101 includes, for example, a semiconductor chip 106, a redistribution layer 107 having a larger area than the semiconductor chip 106 in a plan view in the thickness direction, and a sealing material 108.

[0005] As semiconductor chips become more high-performance, for example, if the line space (L / S) of the redistribution layer 107 in FOWLP101 is reduced, the risk of short circuits is expected to increase. Therefore, when reducing the line space of the redistribution layer 107, it is desirable to also reduce the size of the solder balls 103. Similarly, as semiconductor chips 106 become more high-performance, if the pitch of the electrodes 105 is narrowed, it is desirable to also reduce the size of the solder balls 103. However, due to the characteristics of the solder balls 103, the pitch of the electrodes 105 using solder joints 103A is considered to be industrially limited to several tens of micrometers.

[0006] Furthermore, when connecting the FOWLP101 and the substrate 104 using solder balls 103, a pad for the solder balls 103 is required. Therefore, it is considered difficult to reduce the space on the electrode side surface of the redistribution layer 107 of the FOWLP101.

[0007] Furthermore, when connecting the FOWLP101 and the substrate 104 with solder balls 103, it is necessary to raise the bonding temperature, and this high temperature may cause, for example, warping of the substrate 104. [Prior art documents] [Patent Documents]

[0008] [Patent Document 1] Patent No. 6443893 [Overview of the project] [Problems that the invention aims to solve]

[0009] This technology was proposed in light of the conventional situation, and provides a semiconductor package structure that enables further finer pitch of electrodes, further space saving on the surface of connecting components, and suppresses substrate warping. [Means for solving the problem]

[0010] The semiconductor package structure according to this technology comprises a semiconductor chip, a first redistribution layer having a larger area than the semiconductor chip in a plan view in the thickness direction, a cured resin layer made of a cured product of an anisotropic conductive film in which conductors are aligned at predetermined intervals in an insulating resin layer, and another substrate, wherein the first redistribution layer has a semiconductor chip mounted on one side and a first electrode on the other side that connects to the other substrate, and the other substrate has a second electrode on one side that connects to the first electrode, and the first electrode and the second electrode are connected by the conductors in the cured resin layer.

[0011] A method for manufacturing a semiconductor package structure according to this technology includes a semiconductor package comprising a semiconductor chip and a first redistribution layer having a larger area than the semiconductor chip in a plan view in the thickness direction, on which the semiconductor chip is mounted on one side and which has a first electrode on the other side for connecting to another substrate, and the semiconductor package is arranged on the other substrate having a second electrode that connects to the first electrode, and the first electrode and the second electrode are connected via an anisotropic conductive film in which conductors are aligned at predetermined intervals in an insulating resin layer. [Effects of the Invention]

[0012] According to this technology, the first electrode and the second electrode are connected by a conductor in the cured resin layer, which allows for even finer pitches of the first and second electrodes compared to the case where solder bumps are used.

[0013] Furthermore, according to this technology, since the first electrode and the second electrode are connected by a conductor in the cured resin layer, it becomes possible to further reduce the space on the surface of the first electrode side of the first redistribution layer, for example.

[0014] Furthermore, this technology allows for connection of semiconductor chips to other substrates at lower temperatures compared to using solder bumps, and suppresses warping of the other substrates. [Brief explanation of the drawing]

[0015] [Figure 1] FIG. 1 is a cross-sectional view showing an example of FOWLP. [Figure 2] FIG. 2 is a cross-sectional view showing an example of a semiconductor package structure in which FOWLP and a substrate are connected. [Figure 3] FIG. 3 is a cross-sectional view showing an example of the semiconductor package structure according to the present technology. [Figure 4] FIG. 4 is an exploded cross-sectional view for explaining an example of a method for manufacturing the semiconductor package structure according to the present technology. [Figure 5] FIG. 5 is an exploded cross-sectional view for explaining an example of a method for manufacturing the semiconductor package structure according to the present technology. [Figure 6] FIG. 6 is an exploded cross-sectional view for explaining an example of a method for manufacturing the semiconductor package structure according to the present technology. [Figure 7] FIG. 7 is an exploded cross-sectional view for explaining an example of a method for manufacturing the semiconductor package structure according to the present technology. [Figure 8] FIG. 8 is an exploded cross-sectional view for explaining an example of a method for manufacturing the semiconductor package structure according to the present technology. [Figure 9] FIG. 9 is an exploded cross-sectional view for explaining an example of a method for manufacturing the semiconductor package structure according to the present technology.

BEST MODE FOR CARRYING OUT THE INVENTION

[0016] Hereinafter, a semiconductor package structure and a method for manufacturing the semiconductor package structure to which the present technology is applied will be described in detail with reference to the drawings. Note that the present technology is not limited to the following embodiments, and various modifications can be made without departing from the gist of the present technology. Also, the drawings are schematic, and the ratios of each dimension etc. may be different from the actual ones. Specific dimensions etc. should be determined in consideration of the following description. Also, it is needless to say that there are portions where the relationships and ratios of the dimensions to each other are different among the drawings.

[0017] <Semiconductor Package Structure> [First Embodiment] Figure 3 is a cross-sectional view showing an example of a semiconductor package structure 1 related to this technology. The semiconductor package structure 1 comprises a semiconductor chip 2, an encapsulant 3, a first redistribution layer 4, a cured resin layer 5, and another substrate 6. In the semiconductor package structure 1, a first electrode 7 and a second electrode 11 are connected by a conductor 10 in the cured resin layer 5. In the semiconductor package structure 1, the FOWLP (semiconductor package 12) composed of the semiconductor chip 2, the encapsulant 3, and the first redistribution layer 4 is connected to the other substrate 6 by the conductor 10 in the cured resin layer 5.

[0018] The semiconductor chip 2 is made of a semiconductor such as silicon, and a circuit is formed inside it. The semiconductor chip 2 has a cubic shape, for example, having one surface 2A, another surface 2B opposite to the surface 2A, and a side surface 2C between the surface 2A and the other surface 2B. One surface 2A of the semiconductor chip 2 is in contact with the first redistribution layer 4, and at least the side surface 2C is in contact with the encapsulating material 3.

[0019] The encapsulant 3 is in contact with both the semiconductor chip 2 and the first redistribution layer 4, for example. The encapsulant 3 can be made of an insulating resin, such as epoxy resin. The encapsulant 3 may be a single layer or a multilayer. If the encapsulant 3 is a multilayer, the composition of each layer may be the same or different.

[0020] The first redistribution layer 4 has a semiconductor chip 2 mounted on one side 4A. The first redistribution layer 4 has a first electrode 7 on the other side 4B that connects to another substrate 6. The first redistribution layer 4 is a wiring layer for drawing the circuit of the semiconductor chip 2 to the first electrode 7. The area of ​​the first redistribution layer 4 is larger than that of the semiconductor chip 2 in a plan view in the thickness direction D of the semiconductor package structure 1.

[0021] The first redistribution layer 4 comprises, for example, a first wiring 8 connected to the semiconductor chip 2 and an insulating layer 9 in contact with the first wiring 8. The first redistribution layer 4 can be configured as a laminate of the first wiring 8 and the insulating layer 9. The first redistribution layer 4 may be a single layer or may consist of two or more layers. The first wiring 8 may be made of a highly conductive material (metal), such as copper. The insulating layer 9 is for preventing unintended conductivity between the first wirings 8. The insulating layer 9 is in contact with, for example, the semiconductor chip 2 and the encapsulating material 3. The thickness of the first redistribution layer 4 is not particularly limited and can be, for example, 10 to 100 μm.

[0022] The first electrode 7 can be made of, for example, a metal. Examples of metals that can be used include gold, silver, and copper. The first electrode 7 may be made of two or more metals. For example, the first electrode 7 may be made of a first metal and a second metal whose surface is different from that of the first metal.

[0023] The first electrode 7 is, for example, a planar electrode. The external shape and size of the first electrode 7 are not particularly limited, and examples include a rectangular shape with a length of 3 to 20 μm, a width of 3 to 20 μm, and a height of 0.1 to 10 μm. From the viewpoint of enabling further fine pitch and further space saving on the surface of the connecting member, the length and width of the first electrode 7 are preferably 20 μm or less, but may also be 15 μm or less, 10 μm or less, or 5 μm or less. The space between the first electrodes 7 (the distance between adjacent first electrodes 7) is preferably 20 μm or less, but may also be 15 μm or less, 10 μm or less, or 5 μm or less, from the viewpoint of achieving fine pitch.

[0024] The other substrate 6 has a second electrode 11 on one side 6A that connects to the first electrode 7. The second electrode 11 is, for example, a planar electrode. The material of the second electrode 11, the external shape and size of the second electrode 11, and the space between the second electrodes 11 (the distance between adjacent second electrodes 11) are not particularly limited and can be, for example, the same as that of the first electrode 7. The other substrate 6 may or may not have an electrode on the other side 6B, which is not shown.

[0025] The other substrate 6 is not particularly limited and can be, for example, a package substrate or an interposer. As an interposer, the substrate may be silicon, resin, glass, or a combination of two or more of these. Specifically, examples include silicon interposers, organic interposers, and glass interposers. For example, if the other substrate 6 is an organic interposer, a silicon bridge may be embedded in the organic substrate. The other substrate 6 may be, for example, a combination of an interposer and a package substrate. The other substrate 6 may, for example, have a passive element array called an IPD (Integrated Passive Device) embedded in it, from the viewpoint of further improving signal quality.

[0026] The thickness of the other substrate 6 is not particularly limited and can be, for example, 50 to 200 μm.

[0027] The cured resin layer 5 consists of a cured insulating resin in which conductors 10 are aligned at predetermined intervals. For example, the cured resin layer 5 is made of a cured anisotropic conductive film 14 in which conductors 10 are aligned at predetermined intervals in an insulating resin layer 13. This makes it easier to stabilize the trapping of conductors 10 between the first electrode 7 and the second electrode 11, thereby improving conductivity and insulation. The anisotropic conductive film 14 will be described in detail later.

[0028] The conductors 10 in the cured resin layer 5 are aligned at predetermined intervals. For example, the arrangement of the conductors 10 may have a repeating regularity, and they may be aligned in the cured resin layer 5 but not uniform. For example, the cured resin layer 5 may have a region where the conductors 10 are aligned at predetermined intervals at positions corresponding to the first electrode 7 and the second electrode 11 (between the first electrode 7 and the second electrode 11), and other regions of the cured resin layer 5 other than this region where the conductors 10 are substantially absent. The shape of the arrangement of the conductors 10 is not particularly limited, and examples include grid arrangements such as a square grid, hexagonal grid, rhombic grid, and rectangular grid in a plan view.

[0029] The shape of the conductor 10 is not particularly limited, and examples include spherical and columnar shapes. Below, we will explain using the case where conductive particles are used as the conductor 10 as an example. The particle diameter of the conductor 10 is not particularly limited, but from the viewpoint of fine pitching of the first electrode 7 and the second electrode 11 in the semiconductor package structure 1 and the capture efficiency of the conductor 10, it is preferable to set it to, for example, 20 μm or less, but it may also be 15 μm or less, 10 μm or less, or 5 μm or less. Furthermore, the particle diameter of the conductor 10 can be, for example, 1 μm or more, 3 μm or more, or 5 μm or more. The particle diameter of the conductor 10 can be, for example, the value measured by an image-type particle size analyzer (for example, FPIA-3000: manufactured by Malvern). In this case, the number of conductor 10 measured can be, for example, 1000 or more.

[0030] The conductor 10 can be appropriately selected from conductive particles used in known anisotropic conductive films. The conductor 10 can be a material that enables conductivity with other substrates 6 even when solder bumps are not provided as connection points on the semiconductor chip 2. For example, metal particles such as nickel, cobalt, silver, copper, gold, and palladium; alloy particles such as solder; and metal-coated resin particles in which the surface of resin particles such as polyamide and polybenzoguanamine is coated with a metal such as nickel. The conductor 10 may be used alone or in combination of two or more types. For example, metal-coated resin particles are preferred as the conductor 10 makes it easier to maintain contact between the first electrode 7 and the second electrode 11 due to the repulsion of the resin particles after connection, resulting in more stable conductivity. Furthermore, the surface of the conductor 10 may be insulated by known techniques to the extent that it does not impair the conductivity characteristics.

[0031] The thickness of the cured resin layer 5 is not particularly limited and can be, for example, 60% or more of the particle diameter of the conductor 10. Alternatively, the thickness of the cured resin layer 5 may be, for example, 1.3 times or more of the particle diameter of the conductor 10, or 3 μm or more. The upper limit of the thickness of the cured resin layer 5 may be, for example, 3 times or less of the particle diameter of the conductor 10, or 20 μm or less.

[0032] From the viewpoint of further improving the thermal conductivity of the cured resin layer 5, for example, the cured resin layer 5 may further contain thermally conductive fillers in areas other than the conductive paths. Examples of the shape of the thermally conductive filler include spherical, fibrous, flaky, powdery, and granular forms. Examples of materials for the thermally conductive filler include aluminum oxide (alumina, sapphire), aluminum nitride, aluminum, aluminum hydroxide, and boron nitride. The thermally conductive filler may be used alone or in combination of two or more types.

[0033] As described above, in the semiconductor package structure 1, the first electrode 7 and the second electrode 11 are connected by a conductor 10 in the cured resin layer 5, so it is not necessary to introduce solder bumps on the semiconductor chip 2 side, for example. Therefore, it becomes possible to further finen the pitch of the first electrode 7 and the second electrode 11. For example, in the semiconductor package structure 1, the width between the first electrode 7 and the second electrode 11 can be set to 20 μm or less, the space between multiple first electrodes 7 and the space between multiple second electrodes 11 can be set to 20 μm or less, and the average particle diameter of the conductor 10 can be set to 5 μm or less.

[0034] Furthermore, since the semiconductor package structure 1 does not require solder bumps, for example, it does not require solder bump pads. Therefore, for example, it becomes possible to further reduce the space on the surface of the first electrode 7 side of the first redistribution layer 4. Also, since the semiconductor package structure 1 does not require solder bump pads, for example, it becomes possible to mount it at an even lower profile. Therefore, the semiconductor package structure 1 makes it possible to achieve higher performance at the package level (for example, semiconductor package 12).

[0035] <Manufacturing method for semiconductor package structures> Figure 4 is an exploded cross-sectional view illustrating an example of a method for manufacturing a semiconductor package structure according to this technology. The method for manufacturing the semiconductor package structure 1 (hereinafter also referred to as the first manufacturing method) includes, for example, the following steps A, B, and C, and may further include other steps.

[0036] In step A, for example, an anisotropic conductive film 14 is attached to the surface of the semiconductor package 12 on the stage that is on the side of the first electrode 7, using an attachment device. The semiconductor package 12 comprises a semiconductor chip 2 and a first redistribution layer 4 that has a larger area than the semiconductor chip 2 in a plan view in the thickness direction D, with the semiconductor chip 2 mounted on one surface 4A and the first electrode 7 on the other surface 4B. The anisotropic conductive film 14 has conductors 10 aligned at predetermined intervals on an insulating resin layer 13. In step A, instead of attaching the anisotropic conductive film 14 to the surface of the semiconductor package 12 that is on the side of the first electrode 7, the anisotropic conductive film 14 may be attached to the surface of another substrate 6 that is on the side of the second electrode 11.

[0037] In step B, for example, the second electrode 11 of the other substrate 6 is aligned with the first electrode 7 of the semiconductor package 12, and the semiconductor package 12 is mounted on the other substrate 6.

[0038] In step C, the first electrode 7 of the semiconductor package 12 and the second electrode 11 of the other substrate 6 are connected via the anisotropic conductive film 14. In step C, for example, the semiconductor package 12 side is pressed with a crimping tool via a buffer material. Also in step C, depending on the curing type of the anisotropic conductive film 14, heating, light irradiation, etc., are performed to cure the anisotropic conductive film 14. As a result, the conductor 10 is sandwiched between the first electrode 7 and the second electrode 11, connecting the first electrode 7 and the second electrode 11. For example, the thermocompression bonding conditions can be a temperature of 150 to 260°C, a pressure of 1 to 60 MPa, and a time of 5 to 300 seconds.

[0039] Thus, in the first manufacturing method, a semiconductor package structure 1, as shown in Figure 3, is obtained by connecting the first electrode 7 and the second electrode 11 via an anisotropic conductive film 14 while the semiconductor package 12, comprising the semiconductor chip 2 and the first redistribution layer 4, is arranged on another substrate 6.

[0040] Next, an example of the configuration of the anisotropic conductive film 14 will be described. The anisotropic conductive film 14 refers to a film that is provided on a release film, for example, and is attached to an object to be connected, so that the anisotropic conductive film 14 itself can be separated. The anisotropic conductive film 14 is, for example, a particle-aligned film in which conductors 10 are arranged in the planar direction. The arrangement of the conductors 10 can be, for example, one that has a repeating regularity. The shape of the arrangement of the conductors 10 is not particularly limited, and examples include grid arrangements such as a square grid, a hexagonal grid, an orthorhombic grid, etc. Because the conductors 10 are arranged in the planar direction of the anisotropic conductive film 14, it becomes easier to stabilize the capture by the first electrode 7 and the second electrode 11, and the conductivity and insulation can be further improved.

[0041] Furthermore, the anisotropic conductive film 14 may have a segregated region where the conductor 10 is concentrated at positions corresponding to the first electrode 7 and the second electrode 11, and may be configured so that the conductor 10 is not present in areas other than this segregated region. From the viewpoint of capturing the conductor 10, the segregated region can be, for example, 0.8 times or more the size of the first electrode 7 and the second electrode 11. Also, from the viewpoint of reducing the amount of conductor 10, the segregated region can be, for example, 1.2 times or less the size of the first electrode 7 and the second electrode 11.

[0042] The anisotropic conductive film 14 is formed in a film shape with the arrangement direction of the first electrode 7 and the second electrode 11 as the longitudinal direction, and the conductors 10 may be sparsely arranged in the longitudinal direction and densely arranged in the width direction, or the conductors 10 may be densely arranged in the longitudinal direction and sparsely arranged in the width direction.

[0043] The particle surface density of the conductor 10 in the anisotropic conductive film 14 can be appropriately designed, for example, according to the size of the first electrode 7 and the second electrode 11. The lower limit of the particle surface density of the anisotropic conductive film 14 is, for example, 500 particles / mm², from the viewpoint of obtaining excellent conductivity and insulation even when the electrode size is small. 2 This can be increased to 20,000 pieces / mm 2 It may be more than 40,000 pieces / mm 2It may be more than 50,000 pieces / mm 2 The above is also acceptable. Furthermore, the upper limit of particle surface density is, for example, 1,500,000 particles / mm², from the viewpoint of obtaining excellent conductivity and insulation even when the electrode size is small. 2 It can be as follows: 1,000,000 pieces / mm 2 The following may also apply: 500,000 pieces / mm 2 The following may also be true: 100,000 pieces / mm 2 The following is also acceptable.

[0044] The thickness of the anisotropic conductive film 14 may be, for example, the same as the particle diameter of the conductor 10, 1.3 times or more the particle diameter of the conductor 10, 2 μm or more, or 10 μm or more. Alternatively, the thickness of the anisotropic conductive film 14 may be, for example, 200 μm or less, 50 μm or less, or 2 times or less the particle diameter of the conductor 10.

[0045] The anisotropic conductive film 14 may have adhesive layers or tack layers that do not contain the conductor 10 laminated onto it, and the number of layers and the lamination surface can be appropriately selected according to the target and purpose.

[0046] The conductor 10 is the same as the conductor 10 in the cured resin layer 5 described above, and the preferred range is also the same.

[0047] A known insulating resin (insulating binder) can be used for the insulating resin layer 13. Examples of curing types include thermosetting, photocuring, and photothermal combined curing. Examples include a photoradical polymerization resin composition containing a (meth)acrylate compound and a photoradical polymerization initiator, a thermal radical polymerization resin composition containing a (meth)acrylate compound and a thermal radical polymerization initiator, a thermal cationic polymerization resin composition containing an epoxy compound and a thermal cationic polymerization initiator, and a thermal anionic polymerization resin composition containing an epoxy compound and a thermal anionic polymerization initiator.

[0048] The following explanation will use a specific example: a thermal radical polymerization type insulating binder containing a film-forming resin, an elastomer, a (meth)acrylic monomer, a polymerization initiator, and a silane coupling agent. Note that "(meth)acrylic monomer" includes both acrylic monomer and methacrylic monomer.

[0049] There are no particular restrictions on the film-forming resin, and examples include phenoxy resin, unsaturated polyester resin, saturated polyester resin, urethane resin, butadiene resin, polyimide resin, polyamide resin, and polyolefin resin. The film-forming resin may be used alone or in combination of two or more types. Among these, phenoxy resin is preferred in terms of film-forming properties, processability, and connection reliability. Phenoxy resin is a resin synthesized from bisphenol A and epichlorohydrin, and may be synthesized as appropriate or commercially available. The content of the film-forming resin can be, for example, 10 to 60% by mass.

[0050] There are no particular restrictions on the elastomer used; examples include polyurethane resin (polyurethane-based elastomer), acrylic rubber, silicone rubber, and butadiene rubber.

[0051] There are no particular restrictions on the (meth)acrylic monomer; for example, it may be a monofunctional (meth)acrylic monomer or a bifunctional or polyfunctional (meth)acrylic monomer. From the viewpoint of stress relaxation of the polymer, it is preferable that 80% by mass or more of the (meth)acrylic monomers in the insulating binder are monofunctional (meth)acrylic monomers. Furthermore, from the viewpoint of adhesion, it is preferable that the monofunctional (meth)acrylic monomer has a carboxylic acid. The molecular weight of the monofunctional (meth)acrylic monomer having a carboxylic acid can be, for example, 100 to 500. Furthermore, the content of the monofunctional (meth)acrylic monomer having a carboxylic acid in the insulating binder can be, for example, 3 to 20% by mass.

[0052] The polymerization initiator is not particularly limited as long as it can cure the (meth)acrylic monomer at a predetermined temperature during thermocompression bonding, and examples include organic peroxides. Examples of organic peroxides include lauroyl peroxide, butyl peroxide, benzyl peroxide, dilauroyl peroxide, dibutyl peroxide, peroxydicarbonate, and benzoyl peroxide. These may be used individually or in combination of two or more. The content of the polymerization initiator in the insulating binder is not particularly limited and can be, for example, 0.5 to 15% by mass.

[0053] There are no particular restrictions on the silane coupling agent, and examples include epoxy-based silane coupling agents, acrylic-based silane coupling agents, thiol-based silane coupling agents, and amine-based silane coupling agents. There are no particular restrictions on the content of the silane coupling agent in the insulating binder, and it can be, for example, 0.1 to 5.0% by mass.

[0054] Thus, in the first manufacturing method of the semiconductor package structure, the first electrode 7 and the second electrode 11 are connected via an anisotropic conductive film 14. Therefore, solder bumps are not required to connect the semiconductor package 12 to the other substrate 6, allowing the semiconductor chip 2 to be connected to the other substrate 6 at a lower temperature and suppressing warping of the other substrate 6. This suppresses adverse effects (assembly misalignment) caused by warping of the other substrate 6, for example. In particular, when the interface between the semiconductor package 12 and the other substrate 6 is made of an organic material, for example, when the other substrate 6 is an organic interposer, warping of the encapsulant of the semiconductor package 12 and the other substrate 6 can be effectively suppressed.

[0055] Furthermore, in the first method for manufacturing the semiconductor package structure, solder bumps are not required to connect the semiconductor package 12 to other substrates 6, and therefore underfill material is not required. This further reduces the manufacturing process and prevents the risk of incomplete underfilling.

[0056] <Other Embodiments> The semiconductor package structure relating to this technology is not limited to the semiconductor package structure 1 described above, but may take other forms. For example, the semiconductor package structure may further include multiple semiconductor chips, including the semiconductor package 12 (FOWLP) constituting the semiconductor package structure 1, mounted on another substrate 6.

[0057] [Second Embodiment] Figure 5 is an exploded cross-sectional view illustrating an example of a method for manufacturing a semiconductor package structure 20 according to this technology. The semiconductor package structure 20 is, for example, a semiconductor package 12 which is FOWLP, a group of semiconductor chips 21 which is a combination of small pieces (chiplets) 21a and 21b of semiconductor chips fabricated according to function, and HBM (High Bandwidth Memory) 22, which are mounted on a silicon interposer 23 which is another substrate 6 along direction A, which is the arrangement direction of these components. The group of semiconductor chips 21 has a third electrode 24 on one side 21A. The HBM 22 has a fourth electrode 25 on one side 22A. The group of semiconductor chips 21 and the HBM 22 may also have a redistribution layer similar to the first redistribution layer 4 of the semiconductor package 12.

[0058] The silicon interposer 23 includes, for example, a wiring layer and a through-silicon electrode (TSV) 26. The through-silicon electrode 26 is for connecting from the wiring layer to the other surface 23B. On one surface 23A of the silicon interposer 23, an electrode (hereinafter also referred to as a fifth electrode) is formed for connecting to the first electrode 7, the third electrode 24, and the fourth electrode 25. This fifth electrode corresponds to the second electrode 11 described above and can have the same configuration as the second electrode 11. The semiconductor package structure 20 is connected to the first electrode 7, the third electrode 24, and the fourth electrode 25 and the fifth electrode of the silicon interposer 23 (corresponding to the second electrode 11 described above) by a conductor 10 in the cured resin layer 5 which is made of the cured product of the anisotropic conductive film 14 described above.

[0059] Such a semiconductor package structure 20 does not require the introduction of solder bumps on the semiconductor package 12, semiconductor chip group 21, and HBM 22 side. Therefore, for example, it becomes possible to further finen the pitch of the first electrode 7, third electrode 24, and fourth electrode 25. For example, in the semiconductor package structure 20, the width of the first electrode 7, third electrode 24, and fourth electrode 25 can be set to 20 μm or less, the space between multiple first electrodes 7, the space between multiple third electrodes 24, and the space between multiple fourth electrodes 25 can be set to 20 μm or less, and the average particle diameter of the conductor 10 can be set to 5 μm or less.

[0060] Furthermore, since the semiconductor package structure 20 does not require solder bumps, it does not require solder bump pads. Therefore, for example, it is possible to further reduce the surface space of the first electrode 7, the third electrode 24, and the fourth electrode 25.

[0061] On the other side 23B of the silicon interposer 23, electrodes 27 are formed for connection to, for example, another package substrate 28. The semiconductor package structure 20 can be mounted on the package substrate 28 via the electrodes 27. For example, solder bumps can be used for the electrodes 27. The package substrate 28 can be, for example, a printed circuit board.

[0062] The method for manufacturing the semiconductor package structure 20 (hereinafter also referred to as the second manufacturing method) includes, for example, the following steps A1, B1, and C1, and may further include other steps.

[0063] In step A1, for example, an anisotropic conductive film 14 is attached to the surfaces of the first electrode 7, the third electrode 24, and the fourth electrode 25 on the stage using an attachment device. The anisotropic conductive film 14 has conductors 10 aligned at predetermined intervals on an insulating resin layer 13. In step A1, instead of attaching the anisotropic conductive film 14 to the surfaces of the first electrode 7, the third electrode 24, and the fourth electrode 25, the anisotropic conductive film 14 may be attached to the surface of the silicon interposer 23 on the side of the fifth electrode (corresponding to the second electrode 11 described above).

[0064] In step B1, for example, the fifth electrode of the silicon interposer 23 (corresponding to the second electrode 11 mentioned above) is aligned with the first electrode 7, the third electrode 24, and the fourth electrode 25, and the semiconductor package 12, the semiconductor chip group 21, and the HBM 22 are mounted on the silicon interposer 23.

[0065] In step C1, the first electrode 7, the third electrode 24, and the fourth electrode 25 are connected to the fifth electrode of the silicon interposer 23 via the anisotropic conductive film 14. As a result, the conductor 10 is sandwiched between the first electrode 7, the third electrode 24, and the fourth electrode 25 and the fifth electrode of the silicon interposer 23, thereby connecting the first electrode 7, the third electrode 24, and the fourth electrode 25 to the fifth electrode of the silicon interposer 23. In step C1, the anisotropic conductive film 14 can be cured according to the curing type of the anisotropic conductive film 14, similar to step C described above.

[0066] In the second manufacturing method, solder bumps are not required to connect the first electrode 7, the third electrode 24, and the fourth electrode 25 to the fifth electrode of the silicon interposer 23 (corresponding to the second electrode 11 described above). As a result, the semiconductor package 12, the semiconductor chip group 21, and the HBM 22 can be connected to the silicon interposer 23 at a lower temperature, and warping of the silicon interposer 23 can be suppressed.

[0067] Furthermore, in the second manufacturing method, solder bumps are not required to connect the first electrode 7, the third electrode 24, and the fourth electrode 25 with the fifth electrode. Therefore, underfill material is also not required, further reducing the manufacturing process and preventing the risk of incomplete underfilling.

[0068] [Third Embodiment] Figure 6 is an exploded cross-sectional view illustrating an example of a manufacturing method for the semiconductor package structure 30 according to this technology. The semiconductor package structure 30 has the same configuration as the semiconductor package structure 20, except that the silicon interposer 23 in the semiconductor package structure 20 is replaced with an interposer 32 having a silicon bridge 31 (corresponding to the other substrate 6 mentioned above).

[0069] The interposer 32 includes, for example, a silicon bridge 31 and a silicon through-electrode 33. The interposer 32 has, for example, a silicon bridge 31 embedded in an organic substrate. The semiconductor package structure 20 includes, for example, a silicon bridge 31A for connecting a first electrode 7 and a third electrode 24, and a silicon bridge 31B for connecting a third electrode 24 and a fourth electrode 25, as the silicon bridge 31.

[0070] On one side 32A of the interposer 32, an electrode (not shown, corresponding to the second electrode 11 described above) is formed for connecting to the first electrode 7, the third electrode 24, and the fourth electrode 25. The electrode on one side 32A of the interposer 32 can have the same configuration as the second electrode 11 described above. The semiconductor package structure 30 is connected to the electrode on one side 32A of the interposer 32 (corresponding to the second electrode 11 described above) by a conductor 10 in a cured resin layer 5 made of a cured product of an anisotropic conductive film 14. On the other side 32B of the interposer 32, an electrode 27 is formed for connecting to another package substrate 28.

[0071] Such a semiconductor package structure 30 can achieve the same effects as the semiconductor package structure 20 described above. Furthermore, the semiconductor package structure 30 can be manufactured in the same manner as the second manufacturing method. Therefore, the manufacturing method of the semiconductor package structure 30 can also achieve the same effects as the second manufacturing method described above.

[0072] [Fourth Embodiment] Figure 7 is an exploded cross-sectional view illustrating an example of a method for manufacturing a semiconductor package structure 40 according to this technology. The semiconductor package structure 40 has the same configuration as the semiconductor package structure 20, except that the silicon interposer 23 in the semiconductor package structure 20 is replaced with an organic interposer 41 (corresponding to the other substrate 6 mentioned above). As the organic interposer 41, for example, one in which a thin film wiring layer is formed on the surface of a build-up substrate can be used.

[0073] On one side 41A of the organic interposer 41, an electrode (not shown, corresponding to the second electrode 11 described above) is formed for connecting to the first electrode 7, the third electrode 24, and the fourth electrode 25. The electrode on one side 41A of the organic interposer 41 can have the same configuration as the second electrode 11 described above. The semiconductor package structure 40 is connected to the electrode on one side 41A of the organic interposer 41 (corresponding to the second electrode 11 described above) by a conductor 10 in a cured resin layer 5 made of a cured product of an anisotropic conductive film 14. On the other side 41B of the organic interposer 41, an electrode 27 is formed for connecting to another package substrate 28.

[0074] Such a semiconductor package structure 40 can achieve the same effects as the semiconductor package structure 20 described above. Furthermore, the semiconductor package structure 40 can be manufactured in the same manner as the second manufacturing method. Therefore, the manufacturing method of the semiconductor package structure 40 can also achieve the same effects as the second manufacturing method described above.

[0075] [Fifth Embodiment] Figure 8 is an exploded cross-sectional view illustrating an example of a method for manufacturing a semiconductor package structure 50 according to this technology. The semiconductor package structure 50 has the same configuration as the semiconductor package structure 20, except that the silicon interposer 23 in the semiconductor package structure 20 is replaced with a glass interposer 51 (corresponding to the other substrate 6 mentioned above). As the glass interposer 51, for example, one can be used in which a thin film wiring layer is formed on the surface of a glass substrate, fine through-holes are formed inside the glass substrate, and through-electrodes 52 called TGV (Through Glass via) are arranged in these through-holes filled with a conductive material.

[0076] On one side 51A of the glass interposer 51, electrodes (corresponding to the second electrode 11 described above) are formed for connecting to the first electrode 7, the third electrode 24, and the fourth electrode 25. The electrodes on one side 51A of the glass interposer 51 can have the same configuration as the second electrode 11 described above. The semiconductor package structure 50 is connected to the electrodes on one side 51A of the glass interposer 51 by a conductor 10 in a cured resin layer 5 made of a cured product of an anisotropic conductive film 14. On the other side 51B of the glass interposer 51, electrodes 27 are formed for connecting to other package substrates 28.

[0077] Such a semiconductor package structure 50 can achieve the same effects as the semiconductor package structure 20 described above. Furthermore, the semiconductor package structure 50 can be manufactured in the same manner as the second manufacturing method. Therefore, the manufacturing method of the semiconductor package structure 50 can also achieve the same effects as the second manufacturing method described above.

[0078] [Sixth Embodiment] Figure 9 is an exploded cross-sectional view illustrating an example of a method for manufacturing a semiconductor package structure 60 according to this technology. The semiconductor package structure 60 has the same configuration as the semiconductor package structure 20, except that the silicon interposer 23 in the semiconductor package structure 20 is replaced with an interposer 64 (corresponding to the other substrate 6 mentioned above) on which an organic resin wiring layer 63 is formed on a silicon substrate 62 having a Si through electrode 61 (TSV: Through Silicon via).

[0079] One side 64A of the interposer 64 has electrodes (corresponding to the second electrode 11 described above) formed thereon for connecting to the first electrode 7, the third electrode 24, and the fourth electrode 25. The electrodes on one side 64A of the interposer 64 can have the same configuration as the second electrode 11 described above. The semiconductor package structure 60 is connected to the electrodes on one side 64A of the interposer 64 by a conductor 10 in a cured resin layer 5 made of a cured product of an anisotropic conductive film 14. The other side 64B of the interposer 64 has electrodes 27 formed thereon for connecting to other package substrates 28.

[0080] Such a semiconductor package structure 60 can achieve the same effects as the semiconductor package structure 20 described above. Furthermore, the semiconductor package structure 60 can be manufactured in the same manner as the second manufacturing method. Therefore, the manufacturing method of the semiconductor package structure 60 can also achieve the same effects as the second manufacturing method described above. [Explanation of Symbols]

[0081] 1. Semiconductor package structure, 2. Semiconductor chips, 2A One side, 2B The other side, 2C side, 3. Sealing agent, 4. First redistribution layer, 4A One side, 4B The other side, 5 Cured resin layer, 6 Other boards, 6A One side, 6B The other side, 7. First electrode, 8. First wiring, 9. First insulating layer, 10 Conductors, 11. Second electrode, 12 Semiconductor packages, 13. Insulating resin layer, 14 Anisotropic conductive film, 20 Semiconductor package structures, 21 semiconductor chip group, 21A One side, 21a Small pieces of semiconductor chips, 21b Small pieces of semiconductor chips, 22 HBM, 22A One side, 23 Silicon interposers, 23A One side, 23B The other side, 24. Third electrode, 25. The fourth electrode, 26 Through-silicon electrodes, 27 electrodes, 28 Package substrates, 30 Semiconductor package structures, 31. Silicon bridges, 32 Interposers, 32A One side, 32B The other side, 33 Through-silicon electrodes, 40 Semiconductor package structures, 41 Organic interposer, 41A One side, 41B The other side, 50 Semiconductor package structures, 51 Glass interposer, 51A One side, 51B The other side, 52 Through electrode, 60 semiconductor package structure, 61 Si through electrode, 62 silicon substrates, 63 Redistribution layer of organic resin, 64 Interposer, 64A One side, 64B The other side, 100 semiconductor package structures, 101 FOWLP, 102 electrodes, 103 Solder ball, 103A Solder joint, 104 circuit boards, 105 electrodes, 106 semiconductor chips, 107 redistribution layer, 108 Sealant

Claims

1. A semiconductor package comprising a semiconductor chip and a first redistribution layer having a larger area than the semiconductor chip in a plan view in the thickness direction, A cured resin layer consisting of a cured anisotropic conductive film in which conductors are arranged at predetermined intervals in an insulating resin layer, Other boards and Equipped with, The first redistribution layer has the semiconductor chip mounted on one side and a first electrode on the other side for connecting to the other substrate. The other substrate has a second electrode on one side that connects to the first electrode. A semiconductor package structure in which the first electrode and the second electrode are connected by the conductor in the cured resin layer.

2. The widths of the first electrode and the second electrode are 20 μm or less. The space between the multiple first electrodes and the space between the multiple second electrodes are 20 μm or less. The semiconductor package structure according to claim 1, wherein the average particle diameter of the conductor is 5 μm or less.

3. The semiconductor package structure according to claim 1 or 2, wherein the first electrode is a planar electrode.

4. The semiconductor package structure according to claim 1 or 2, wherein the other substrate is an interposer or a package substrate.

5. The semiconductor package structure according to claim 1 or 2, wherein the other substrate is an interposer, and the base material is silicon, resin, glass, or a combination of two or more of these.

6. The semiconductor package structure according to claim 1 or 2, wherein the cured resin layer further comprises a thermally conductive filler.

7. A method for manufacturing a semiconductor package structure, comprising: a semiconductor package comprising a semiconductor chip and a first redistribution layer having a larger area than the semiconductor chip in a plan view in the thickness direction, with the semiconductor chip mounted on one side and a first electrode on the other side for connecting to another substrate, arranged on the other substrate having a second electrode that connects to the first electrode, and the step of connecting the first electrode and the second electrode via an anisotropic conductive film in which conductors are aligned at predetermined intervals in an insulating resin layer.

Images