Semiconductor package structure and method for manufacturing a semiconductor package structure

Abstract

To provide a semiconductor package structure that enables further finer electrode pitch and further space saving on the surface of connecting components, thereby suppressing substrate warping. [Solution] The semiconductor package structure 1 comprises a plurality of chiplets 2A to 2C having a first electrode 6 on its surface, an intermediate substrate 3 having a second electrode 7 connected to the first electrode 6 on one side 3A and a wiring layer 9 for wiring input / output signals from one of the plurality of chiplets 2A to 2C to other chiplets, and a cured resin layer 5 made of a cured product of an anisotropic conductive film 13 in which conductors 11 are aligned at predetermined intervals in an insulating resin layer 12. In the semiconductor package structure 1, the first electrode 6 and the second electrode 7 are connected by the conductors 11 in the cured resin layer 5.

Description

Technical Field

[0001] The present technology relates to a semiconductor package structure and a method for manufacturing the semiconductor package structure.

Background Art

[0002] In recent years, SiP (System in Package) technology has attracted attention. The SiP technology is, for example, a technology that realizes performance equivalent to or higher than that of a monolithic SoC (System on Chip) by mounting and integrating a group of semiconductor chips individually designed and manufactured at an optimal node for each function on an interposer. Such a concept of SiP technology and each semiconductor chip manufactured by function are also referred to as chiplets.

[0003] For connection between a chiplet and an interposer for input / output, for example, solder bumps (solder balls) are used (see, for example, Patent Document 1).

[0004] With the chipletization, the opportunity for interconnection tends to increase more. In 2.1D mounting and 2.5D mounting, in comparison with a monolithic SoC, in order to achieve more miniaturization and smaller area, for example, it is necessary to narrow the pitch of electrodes (connection pitch). For example, when trying to make the pitch of electrodes of a semiconductor chip narrower, it is considered desirable to make the solder bumps as electrodes smaller as well. However, due to the characteristics of solder bumps, the pitch of solder bumps is considered to be limited to several tens of μm industrially.

[0005] Also, when connecting a chiplet and an interposer with solder bumps, pads for solder bumps are required. Therefore, for example, it is considered difficult to save space on the surface on the electrode side of the chiplet.

[0006] Furthermore, when connecting a chiplet and an interposer with solder bumps, it is necessary to raise the bonding temperature, and due to this high temperature, for example, there is a risk of warpage of the interposer.

Prior Art Documents

[0007] [Patent Document 1] Special Publication No. 2022-539010 [Overview of the project] [Problems that the invention aims to solve]

[0008] This technology was proposed in light of the conventional situation, and provides a semiconductor package structure that enables further finer pitch of electrodes, further space saving on the surface of connecting components, and suppresses substrate warping. [Means for solving the problem]

[0009] The semiconductor package structure according to this technology comprises a plurality of chiplets having a first electrode on its surface, an intermediary substrate having a wiring layer that has a second electrode on one side connected to the first electrode and that wires input / output signals from one of the plurality of chiplets to the other chiplets, and a cured resin layer made of a cured product of an anisotropic conductive film in which conductors are aligned at predetermined intervals in an insulating resin layer, and the first electrode and the second electrode are connected by the conductors in the cured resin layer.

[0010] A method for manufacturing a semiconductor package structure according to this technology includes the step of connecting the first electrode and the second electrode via an anisotropic conductive film in which conductors are aligned at predetermined intervals in an insulating resin layer, with the intermediate substrate having a plurality of chiplets having a first electrode on its surface and a second electrode on one side for connecting to the first electrode, and on the one side on which the plurality of chiplets are mounted, and a wiring layer for wiring input / output signals from one of the plurality of chiplets to the other chiplets, in an arranged state. [Effects of the Invention]

[0011] According to this technology, the first electrode and the second electrode are connected by a conductor in the cured resin layer, which allows for even finer pitches of the first and second electrodes compared to the case where solder bumps are used.

[0012] Furthermore, according to this technology, since the first electrode and the second electrode are connected by a conductor in the cured resin layer, it becomes possible to further reduce the space required on the surface of the chiplet on the first electrode side, for example.

[0013] Furthermore, this technology allows for connection between the chiplet and the intermediary substrate at a lower temperature compared to using solder bumps, and suppresses warping of the intermediary substrate. [Brief explanation of the drawing]

[0014] [Figure 1] Figure 1 is a cross-sectional view showing an example of a semiconductor package structure related to this technology. [Figure 2] Figure 2 is an exploded cross-sectional view illustrating an example of a method for manufacturing a semiconductor package structure related to this technology. [Figure 3] Figure 3 is a cross-sectional view showing an example of a semiconductor package structure related to this technology. [Figure 4] Figure 4 is an exploded cross-sectional view illustrating an example of a method for manufacturing a semiconductor package structure related to this technology. [Figure 5] Figure 5 is a cross-sectional view illustrating an example of a semiconductor package, specifically a Fan-Out Wafer Level Package (FOWLP). [Figure 6] Figure 6 is an exploded cross-sectional view illustrating an example of a method for manufacturing a semiconductor package structure related to this technology. [Figure 7] Figure 7 is an exploded cross-sectional view illustrating an example of a method for manufacturing a semiconductor package structure related to this technology. [Figure 8] Figure 8 is an exploded cross-sectional view illustrating an example of a method for manufacturing a semiconductor package structure related to this technology. [Figure 9]FIG. 9 is an exploded cross-sectional view for explaining an example of a method for manufacturing a semiconductor package structure according to the present technology.

Embodiments for Carrying Out the Invention

[0015] Hereinafter, a semiconductor package structure and a method for manufacturing a semiconductor package structure to which the present technology is applied will be described in detail with reference to the drawings. Note that the present technology is not limited to the following embodiments, and various modifications can be made without departing from the gist of the present technology. Also, the drawings are schematic, and the ratios of each dimension etc. may be different from the actual ones. Specific dimensions etc. should be determined in consideration of the following description. Also, it is a matter of course that there are portions where the relationships and ratios of the dimensions are different between the drawings.

[0016] <Semiconductor Package Structure> [First Embodiment] FIG. 1 is a cross-sectional view showing an example of a semiconductor package structure 1 according to the present technology. The semiconductor package structure 1 includes a semiconductor chip group 2 composed of a plurality of semiconductor chips (chiplets), an interposer substrate 3, a cured resin layer 4, and may further include another substrate 5.

[0017] The semiconductor chip group 2 is composed of, for example, semiconductor chips 2A (chiplet 2A), semiconductor chips 2B (chiplet 2B), and semiconductor chips 2C (chiplet 2C), which are small pieces of a plurality of semiconductor chips manufactured by function. The semiconductor chip group 2 is composed of a semiconductor such as silicon, for example, and a circuit is formed inside thereof. The semiconductor chip group 2 has a first electrode 6 on its surface. For example, in FIG. 1, the first electrode 6 is composed of first electrodes 6A to 6C. Specifically, the semiconductor chip 2A has the first electrode 6A on its surface, the semiconductor chip 2B has the first electrode 6B on its surface, and the semiconductor chip 2C has the first electrode 6C on its surface.

[0018] The first electrode 6 can be made of, for example, a metal. Examples of metals that can be used include gold, silver, and copper. The first electrode 6 may be made of two or more metals. For example, the first electrode may be made of a first metal and a second metal whose surface is different from that of the first metal.

[0019] The first electrode 6 is, for example, a planar electrode. The external shape and size of the first electrode 6 are not particularly limited, and examples include a rectangular shape with a length of 3 to 20 μm, a width of 3 to 20 μm, and a height of 0.1 to 10 μm. From the viewpoint of enabling further fine pitch and further space saving on the surface of the connecting member, the length and width of the first electrode 6 are preferably, for example, 20 μm or less, but may also be 15 μm or less, 10 μm or less, or 5 μm or less. The space between the first electrodes 6, for example, the distance between adjacent first electrodes 6A and 6B, or between 6B and 6C, is preferably 20 μm or less, for example, from the viewpoint of achieving fine pitch, but may also be 15 μm or less, 10 μm or less, or 5 μm or less.

[0020] The intermediary substrate 3 has a semiconductor chip group 2 mounted on one side 3A. The intermediary substrate 3 has a wiring layer 9 on one side 3A that wires input / output signals from the terminals of one semiconductor chip (e.g., semiconductor chip 2A) of the semiconductor chip group 2 to another semiconductor chip (e.g., semiconductor chip 2B). The intermediary substrate 3 has a second electrode 7 on one side 3A that connects to the first electrode 6.

[0021] The second electrode 7 is, for example, a planar electrode. The material of the second electrode 7, the external shape and size of the second electrode 7, and the space between the second electrodes 7 (the distance between adjacent second electrodes 7) are not particularly limited and can be, for example, the same as the first electrode 6.

[0022] The wiring layer 9 comprises, for example, wiring connected to the semiconductor chip group 2 and an insulating layer in contact with this wiring. The wiring layer 9 includes, for example, a wiring layer that wires input / output signals from semiconductor chip 2A to an adjacent semiconductor chip 2B, and a wiring layer that wires input / output signals from semiconductor chip 2B to an adjacent semiconductor chip 2C. The wiring layer 9 has, for example, a second electrode 7 on one surface. The wiring layer 9 can be configured as a laminate of wiring and an insulating layer. The wiring layer 9 may be a single layer or may consist of two or more layers. The wiring may be made of a highly conductive material (metal), such as copper. The insulating layer is for preventing unintended conductivity between the wirings. The thickness of the wiring layer 9 is not particularly limited and can be, for example, 5 to 50 μm.

[0023] The intermediary substrate 3 is, for example, an interposer. The intermediary substrate 3 may be, for example, a base material of silicon, resin, glass, or a combination of two or more of these, and specifically, examples include silicon interposers, organic interposers, and glass interposers. The intermediary substrate 3 is a silicon interposer having a wiring layer 9 and silicon through-electrodes 10, as shown in Figure 1, for example. Also, for example, if the intermediary substrate 3 is an organic interposer, silicon bridges as the wiring layer 9 may be embedded in the organic substrate. The intermediary substrate 3 may be, for example, a combination of an interposer and a package substrate. The intermediary substrate 3 may have a passive element array called an IPD (Integrated Passive Device) embedded in it, for example, from the viewpoint of further improving signal quality.

[0024] The intermediary substrate 3 has, for example, a third electrode 8 connected to another substrate 5 on its other side 3B. The other substrate 5 is, for example, a package substrate. A printed circuit board can be used as the other substrate 5. The third electrode 8 is, for example, a solder joint consisting of a solder bump.

[0025] The thickness of the intermediary substrate 3 is not particularly limited and can be, for example, 50 to 200 μm.

[0026] The cured resin layer 4 consists of a cured insulating resin in which conductors 11 are aligned at predetermined intervals. For example, the cured resin layer 4 is made of a cured anisotropic conductive film 13 in which conductors 11 are aligned at predetermined intervals in an insulating resin layer 12. This makes it easier to stabilize the trapping of conductors 11 between the first electrode 6 and the second electrode 7, thereby improving conductivity and insulation. The anisotropic conductive film 13 will be described in detail later.

[0027] The conductors 11 in the cured resin layer 4 are aligned at predetermined intervals. For example, the arrangement of the conductors 11 may have a repeating regularity, and they may be aligned in the cured resin layer 4 but not uniform. For example, the cured resin layer 4 may have a region where the conductors 11 are aligned at predetermined intervals at positions corresponding to the first electrode 6 and the second electrode 7 (between the first electrode 6 and the second electrode 7), and other regions of the cured resin layer 4 other than this region where the conductors 11 are substantially absent. The shape of the arrangement of the conductors 11 is not particularly limited, and examples include grid arrangements such as a square grid, hexagonal grid, rhombic grid, and rectangular grid in a plan view.

[0028] The shape of the conductor 11 is not particularly limited, and examples include spherical and columnar shapes. Below, we will explain using the case where conductive particles are used as the conductor 11 as an example. The particle diameter of the conductor 11 is not particularly limited, but from the viewpoint of fine pitching of the first electrode 6 and the second electrode 7 in the semiconductor package structure 1 and the capture efficiency of the conductor 11, it is preferable to set it to, for example, 20 μm or less, but it may also be 15 μm or less, 10 μm or less, or 5 μm or less. Furthermore, the particle diameter of the conductor 11 can be, for example, 1 μm or more, 3 μm or more, or 5 μm or more. The particle diameter of the conductor 11 can be, for example, the value measured by an image-type particle size analyzer (for example, FPIA-3000: manufactured by Malvern). In this case, the number of conductors 11 measured can be, for example, 1000 or more.

[0029] The conductor 11 can be appropriately selected from conductive particles used in known anisotropic conductive films. The conductor 11 can be made of a material that enables conductivity with the intermediary substrate 3 even when solder bumps are not provided as connection points for the semiconductor chip group 2. For example, metal particles such as nickel, cobalt, silver, copper, gold, and palladium; alloy particles such as solder; or metal-coated resin particles in which the surface of resin particles such as polyamide and polybenzoguanamine is coated with a metal such as nickel. The conductor 11 may be used alone or in combination of two or more types. For example, metal-coated resin particles are preferred as the conductor 11 makes it easier to maintain contact between the first electrode 6 and the second electrode 7 due to the repulsion of the resin particles after connection, resulting in more stable conductivity. Furthermore, the surface of the conductor 11 may be insulated by known techniques to the extent that it does not impair the conductivity characteristics.

[0030] The thickness of the cured resin layer 4 is not particularly limited and can be, for example, 60% or more of the particle diameter of the conductor 11. Alternatively, the thickness of the cured resin layer 4 may be, for example, 1.3 times or more of the particle diameter of the conductor 11, or 3 μm or more. The upper limit of the thickness of the cured resin layer 4 may be, for example, 3 times or less of the particle diameter of the conductor 11, or 20 μm or less.

[0031] From the viewpoint of further improving the thermal conductivity of the cured resin layer 4, for example, the cured resin layer 4 may further contain thermally conductive fillers in areas other than the conductive paths. Examples of the shape of the thermally conductive filler include spherical, fibrous, flaky, powdery, and granular forms. Examples of materials for the thermally conductive filler include aluminum oxide (alumina, sapphire), aluminum nitride, aluminum, aluminum hydroxide, and boron nitride. The thermally conductive filler may be used alone or in combination of two or more types.

[0032] As described above, in the semiconductor package structure 1, the first electrode 6 and the second electrode 7 are connected by a conductor 11 in the cured resin layer 4, so it is not necessary to introduce solder bumps on the semiconductor chip group 2 side, for example. Therefore, it becomes possible to further finen the pitch of the first electrode 6 and the second electrode 7. For example, in the semiconductor package structure 1, the width between the first electrode 6 and the second electrode 7 can be 20 μm or less, the space between multiple first electrodes 6 and the space between multiple second electrodes 7 can be 20 μm or less, and the average particle diameter of the conductor 11 can be 5 μm or less.

[0033] Furthermore, since the semiconductor package structure 1 does not require solder bumps, for example, it does not require solder bump pads. Therefore, for example, further space saving is possible on the surface on the first electrode 6 side. Also, since the semiconductor package structure 1 does not require solder bump pads, for example, it is possible to mount it at an even lower profile. Therefore, the semiconductor package structure 1 can achieve higher performance at the package level.

[0034] <Manufacturing method for semiconductor package structures> Figure 2 is an exploded cross-sectional view illustrating an example of a method for manufacturing a semiconductor package structure according to this technology. The method for manufacturing the semiconductor package structure 1 (hereinafter also referred to as the first manufacturing method) includes, for example, the following steps A, B, and C, and may further include other steps.

[0035] In step A, for example, an anisotropic conductive film 13 is attached to the surface of the semiconductor chips 2A to 2C on the first electrode side 6A to 6C using a bonding device. The anisotropic conductive film 13 has conductors 11 aligned at predetermined intervals on an insulating resin layer 12. In step A, instead of attaching the anisotropic conductive film 13 to the surface of the semiconductor chips 2A to 2C on the first electrode side 6A to 6C, the anisotropic conductive film 13 may be attached to the surface of the intermediary substrate 3 on the second electrode side 7. Note that the intermediary substrate 3 shown in Figure 2 is an example configuration in the case of an organic interposer, and the silicon through-electrode 10 shown in Figure 1 is not shown, but it may have a configuration similar to the intermediary substrate 3 shown in Figure 1.

[0036] In step B, for example, the second electrode 7 of the intermediary substrate 3 is aligned with the first electrodes 6A to 6C of the semiconductor chips 2A to 2C, and the semiconductor chips 2A to 2C are mounted on the intermediary substrate 3.

[0037] In step C, the first electrodes 6A to 6C of the semiconductor chips 2A to 2C and the second electrode 7 of the intermediary substrate 3 are connected via the anisotropic conductive film 13. In step C, for example, the semiconductor chips 2A to 2C are pressed with a compression tool via a buffer material. Also in step C, depending on the curing type of the anisotropic conductive film 13, heating, light irradiation, etc., are performed to cure the anisotropic conductive film 13. As a result, the conductor 11 is sandwiched between the first electrodes 6A to 6C and the second electrode 7, connecting the first electrodes 6A to 6C and the second electrode 7. For example, the thermocompression bonding conditions can be a temperature of 150 to 260°C, a pressure of 1 to 60 MPa, and a time of 5 to 300 seconds.

[0038] Thus, in the first manufacturing method, with the semiconductor chips 2A to 2C arranged on the intermediary substrate 3, a semiconductor package structure 1 shown in Figure 1 is obtained by connecting the first electrodes 6A to 6C and the second electrode 7 via an anisotropic conductive film 13. In addition to steps A, B, and C, the first manufacturing method may further include a step of connecting the third electrode 8 of the intermediary substrate 3 to another substrate 5. Furthermore, in step A, one anisotropic conductive film 13 is attached to the entire surface of the first electrodes 6A to 6C of the semiconductor chips 2A to 2C on the stage, but the method is not limited to this example, and anisotropic conductive films 13 of a size corresponding to each semiconductor chip 2A to 2C may be prepared and attached to each semiconductor chip 2A to 2C. Figure 3 is a cross-sectional view showing an example of a semiconductor package structure according to this technology. In step A, when anisotropic conductive films 13 of a size corresponding to each semiconductor chip 2A to 2C are attached to the semiconductor chips 2A to 2C, fillets (overhangs) 4A are formed in the cured resin layer 4 near the edges of the semiconductor chips 2A to 2C, as shown in Figure 3, for example.

[0039] Next, an example of the configuration of the anisotropic conductive film 13 will be described. The anisotropic conductive film 13 refers to a film that is provided on a release film, for example, and adheres to an object to be connected, so that the anisotropic conductive film 13 itself can be separated. The anisotropic conductive film 13 is, for example, a particle-aligned film in which conductors 11 are arranged in the planar direction. The arrangement of the conductors 11 can be, for example, one that has a repeating regularity. The shape of the arrangement of the conductors 11 is not particularly limited, and examples include grid arrangements such as a square grid, hexagonal grid, orthorhombic grid, etc. Because the conductors 11 are arranged in the planar direction of the anisotropic conductive film 13, it becomes easier to stabilize the capture by the first electrodes 6A to 6C and the second electrode 7, and the conductivity and insulation can be further improved.

[0040] Furthermore, the anisotropic conductive film 13 may have a segregated region in which the conductor 11 is concentrated at positions corresponding to the first electrodes 6A to 6C and the second electrode 7, and may be configured so that the conductor 11 is not present in areas other than this segregated region. From the viewpoint of capturing the conductor 11, the segregated region can be, for example, 0.8 times or more the size of the first electrodes 6A to 6C and the second electrode 7. Also, from the viewpoint of reducing the amount of conductor 11, the segregated region can be, for example, 1.2 times or less the size of the first electrodes 6A to 6C and the second electrode 7.

[0041] The anisotropic conductive film 13 is formed in a film shape with the arrangement direction of the first electrodes 6A to 6C and the second electrode 7 as the longitudinal direction, and the conductors 11 may be sparsely arranged in the longitudinal direction and densely arranged in the width direction, or the conductors 11 may be densely arranged in the longitudinal direction and sparsely arranged in the width direction.

[0042] The particle surface density of the conductor 11 in the anisotropic conductive film 13 can be appropriately designed according to the size of the first electrodes 6A to 6C and the second electrode 7, for example. The lower limit of the particle surface density of the anisotropic conductive film 13 is 500 particles / mm², for example, from the viewpoint of obtaining excellent conductivity and insulation even when the electrode size is small. 2 This can be increased to 20,000 pieces / mm 2 It may be more than 40,000 pieces / mm 2 It may be more than 50,000 pieces / mm 2 The above is also acceptable. Furthermore, the upper limit of particle surface density is, for example, 1,500,000 particles / mm², from the viewpoint of obtaining excellent conductivity and insulation even when the electrode size is small. 2 It can be as follows: 1,000,000 pieces / mm 2 The following may also apply: 500,000 pieces / mm 2 The following may also be true: 100,000 pieces / mm 2 The following is also acceptable.

[0043] The thickness of the anisotropic conductive film 13 may be, for example, the same as the particle diameter of the conductor 11, 1.3 times or more the particle diameter of the conductor 11, 2 μm or more, or 10 μm or more. Alternatively, the thickness of the anisotropic conductive film 13 may be, for example, 200 μm or less, 50 μm or less, or 2 times or less the particle diameter of the conductor 11.

[0044] The anisotropic conductive film 13 may have adhesive layers or tack layers that do not contain the conductor 11 laminated over it, and the number of layers and the lamination surface can be appropriately selected according to the target and purpose.

[0045] The conductor 11 is the same as the conductor 11 in the cured resin layer 4 described above, and the preferred range is also the same.

[0046] A known insulating resin (insulating binder) can be used for the insulating resin layer 12. Examples of curing types include thermosetting, photocuring, and photothermal combined curing. Examples include a photoradical polymerization resin composition containing a (meth)acrylate compound and a photoradical polymerization initiator, a thermal radical polymerization resin composition containing a (meth)acrylate compound and a thermal radical polymerization initiator, a thermal cationic polymerization resin composition containing an epoxy compound and a thermal cationic polymerization initiator, and a thermal anionic polymerization resin composition containing an epoxy compound and a thermal anionic polymerization initiator.

[0047] The following explanation will use a specific example: a thermal radical polymerization type insulating binder containing a film-forming resin, an elastomer, a (meth)acrylic monomer, a polymerization initiator, and a silane coupling agent. Note that "(meth)acrylic monomer" includes both acrylic monomer and methacrylic monomer.

[0048] There are no particular restrictions on the film-forming resin, and examples include phenoxy resin, unsaturated polyester resin, saturated polyester resin, urethane resin, butadiene resin, polyimide resin, polyamide resin, and polyolefin resin. The film-forming resin may be used alone or in combination of two or more types. Among these, phenoxy resin is preferred in terms of film-forming properties, processability, and connection reliability. Phenoxy resin is a resin synthesized from bisphenol A and epichlorohydrin, and may be synthesized as appropriate or commercially available. The content of the film-forming resin can be, for example, 10 to 60% by mass.

[0049] There are no particular restrictions on the elastomer used; examples include polyurethane resin (polyurethane-based elastomer), acrylic rubber, silicone rubber, and butadiene rubber.

[0050] There are no particular restrictions on the (meth)acrylic monomer; for example, it may be a monofunctional (meth)acrylic monomer or a bifunctional or polyfunctional (meth)acrylic monomer. From the viewpoint of stress relaxation of the polymer, it is preferable that 80% by mass or more of the (meth)acrylic monomers in the insulating binder are monofunctional (meth)acrylic monomers. Furthermore, from the viewpoint of adhesion, it is preferable that the monofunctional (meth)acrylic monomer has a carboxylic acid. The molecular weight of the monofunctional (meth)acrylic monomer having a carboxylic acid can be, for example, 100 to 500. Furthermore, the content of the monofunctional (meth)acrylic monomer having a carboxylic acid in the insulating binder can be, for example, 3 to 20% by mass.

[0051] The polymerization initiator is not particularly limited as long as it can cure the (meth)acrylic monomer at a predetermined temperature during thermocompression bonding, and examples include organic peroxides. Examples of organic peroxides include lauroyl peroxide, butyl peroxide, benzyl peroxide, dilauroyl peroxide, dibutyl peroxide, peroxydicarbonate, and benzoyl peroxide. These may be used individually or in combination of two or more. The content of the polymerization initiator in the insulating binder is not particularly limited and can be, for example, 0.5 to 15% by mass.

[0052] There are no particular restrictions on the silane coupling agent, and examples include epoxy-based silane coupling agents, acrylic-based silane coupling agents, thiol-based silane coupling agents, and amine-based silane coupling agents. There are no particular restrictions on the content of the silane coupling agent in the insulating binder, and it can be, for example, 0.1 to 5.0% by mass.

[0053] Thus, in the first manufacturing method of the semiconductor package structure, the first electrodes 6A to 6C and the second electrode 7 are connected via an anisotropic conductive film 13. Therefore, solder bumps are not required to connect the semiconductor chips 2A to 2C and the intermediary substrate 3, allowing the semiconductor chips 2A to 2C and the intermediary substrate 3 to be connected at a lower temperature and suppressing warping of the intermediary substrate 3. This suppresses adverse effects (assembly misalignment) caused by warping of the intermediary substrate 3, for example. In particular, when the interface between the semiconductor chips 2A to 2C and the intermediary substrate 3 is made of an organic material, for example, when the intermediary substrate 3 is an organic interposer as shown in Figure 2, warping of the intermediary substrate 3 can be effectively suppressed.

[0054] Furthermore, in the first method for manufacturing the semiconductor package structure, solder bumps are not required to connect the semiconductor chips 2A to 2C and the intermediary substrate 3. Therefore, underfill material is also not required, which further reduces the manufacturing process and prevents the risk of incomplete underfilling.

[0055] <Other Embodiments> The semiconductor package structure relating to this technology is not limited to the semiconductor package structure 1 described above, but may take other forms. For example, the semiconductor package structure may have other semiconductor chips besides semiconductor chips 2A to 2C further mounted on the intermediary substrate 3.

[0056] [Second Embodiment] Figure 4 is an exploded cross-sectional view illustrating an example of a method for manufacturing a semiconductor package structure 20 according to this technology. The semiconductor package structure 20 is, for example, a semiconductor chip group 21 made up of small pieces (chiplets) 21a and 21b of semiconductor chips, an HBM (High Bandwidth Memory) 22, and a FOWLP semiconductor package 14, which are mounted on a silicon interposer 23 (corresponding to the intermediary substrate 3 described above) along direction A, which is the arrangement direction of these components. The semiconductor chip group 21 has a fourth electrode 24 (corresponding to the first electrode 6 described above) on one side 21A. This fourth electrode 24 is synonymous with the first electrode 6 described above, and its preferred range is also the same. The HBM 22 has a fifth electrode 25 on one side 22A.

[0057] The silicon interposer 23 shown in Figure 4 has, for example, a wiring layer (corresponding to the wiring layer 9 described above) and a silicon through-silicon (TSV) 26. The wiring layer (corresponding to the wiring layer 9 described above) has the function of wiring input / output signals from a chiplet 21a to an adjacent chiplet 21b. The silicon through-silicon 26 is for connecting from the wiring layer to the other surface 23B. On one surface 23A of the silicon interposer 23, an electrode (not shown, hereinafter also referred to as a seventh electrode) is formed for connecting to the fourth electrode 24, the fifth electrode 25, and the sixth electrode 29. This seventh electrode corresponds to the second electrode 7 described above and can have the same configuration as the second electrode 7. The semiconductor package structure 20 is connected to the conductor 11 in the cured resin layer 4, which is made of the cured product of the anisotropic conductive film 13 described above, by the conductor 11 in the conductor 11 in the conductor 24 (corresponding to the first electrode 6 described above), the 5th electrode 25, and the 6th electrode 29, and to the 7th electrode of the silicon interposer 23 (corresponding to the second electrode 7 described above).

[0058] Such a semiconductor package structure 20 does not require the introduction of solder bumps on the semiconductor package 14, semiconductor chip group 21, and HBM 22 side. Therefore, for example, it becomes possible to further finen the pitch of the fourth electrode 24, fifth electrode 25, and sixth electrode 29. For example, the semiconductor package structure 20 can have the width of the fourth electrode 24, fifth electrode 25, and sixth electrode 29 be 20 μm or less, the space between multiple fourth electrodes 24, the space between multiple fifth electrodes 25, and the space between multiple sixth electrodes 29 be 20 μm or less, and the average particle diameter of the conductor 11 be 5 μm or less.

[0059] Furthermore, since the semiconductor package structure 20 does not require solder bumps, it does not require solder bump pads. Therefore, for example, it is possible to further reduce the surface space of the fourth electrode 24, the fifth electrode 25, and the sixth electrode 29.

[0060] On the other side 23B of the silicon interposer 23, electrodes 27 (corresponding to the third electrode 8 described above) are formed for connection to another package substrate 28 (corresponding to the other substrate 5 described above). The semiconductor package structure 20 can be mounted on the package substrate 28 via the electrodes 27. For example, solder bumps can be used for the electrodes 27. For example, a printed circuit board can be used for the package substrate 28.

[0061] Figure 5 is a cross-sectional view illustrating an example of a FOWLP, which is an example of a semiconductor package. The semiconductor package 14 (fan-out type semiconductor package) is a FOWLP composed of a semiconductor chip 15, an encapsulant 16, and a redistribution layer 17. The semiconductor chip 15 is made of a semiconductor such as silicon, and a circuit is formed inside it. The semiconductor chip 15 has a cubic shape, for example, having one surface 15A, another surface 15B opposite to the surface 15A, and a side surface 15C between the surface 15A and the other surface 15B. One surface 15A of the semiconductor chip 15 is in contact with the redistribution layer 17, and at least the side surface 15C is in contact with the encapsulant 16.

[0062] The encapsulant 16 is in contact with both the semiconductor chip 15 and the redistribution layer 17, for example. The encapsulant 16 can be made of an insulating resin, such as epoxy resin. The encapsulant 16 may be a single layer or a multilayer. If the encapsulant 16 is multilayer, the composition of each layer may be the same or different.

[0063] The redistribution layer 17 has a semiconductor chip 15 mounted on one side 17A. The redistribution layer 17 has a sixth electrode 29 on the other side 17B that connects to the silicon interposer 23. The redistribution layer 17 is a wiring layer for drawing the circuit of the semiconductor chip 15 to the sixth electrode 29. The area of ​​the redistribution layer 17 is larger than that of the semiconductor chip 15 in a plan view in the thickness direction of the semiconductor package structure 20. Note that the chiplets 21a, 21b and HBM 22 that constitute the semiconductor chip group 21 may also have a redistribution layer similar to the redistribution layer 17. For example, at least one of the chiplets 21a and 21b may constitute a fan-out type semiconductor package that includes a redistribution layer with a larger area than that of the chiplets 21a and 21b in a plan view in the thickness direction, and the surface of this redistribution layer may have the sixth electrode 29.

[0064] The redistribution layer 17 comprises, for example, wiring 17a connected to the semiconductor chip 15 and an insulating layer 17b in contact with the wiring 17a. The redistribution layer 17 can be configured as a laminate of wiring 17a and insulating layer 17b. The redistribution layer 17 may be a single layer or may consist of two or more layers. The wiring 17a may be made of a highly conductive material (metal), such as copper. The insulating layer 17b is for preventing unintended conductivity between the wirings 17a. The insulating layer 17b is in contact with, for example, the semiconductor chip 15 and the encapsulating material 16. The thickness of the redistribution layer 17 is not particularly limited and can be, for example, 10 to 100 μm.

[0065] The method for manufacturing the semiconductor package structure 20 (hereinafter also referred to as the second manufacturing method) includes, for example, the following steps A1, B1, and C1, and may also include other steps.

[0066] In step A1, for example, an anisotropic conductive film 13 is attached to the surfaces of the fourth electrode 24, fifth electrode 25, and sixth electrode 29 on the stage using an attachment device. Alternatively, in step A1, instead of attaching the anisotropic conductive film 13 to the surfaces of the fourth electrode 24, fifth electrode 25, and sixth electrode 29, the anisotropic conductive film 13 may be attached to the surface of the silicon interposer 23 on the seventh electrode side.

[0067] In step B1, for example, the seventh electrode of the silicon interposer 23 (corresponding to the second electrode 7 mentioned above), the fourth electrode 24 (corresponding to the first electrode 6 mentioned above), the fifth electrode 25, and the sixth electrode 29 are aligned, and the semiconductor package 14, the semiconductor chip group 21, and the HBM 22 are mounted on the silicon interposer 23.

[0068] In step C1, the fourth electrode 24 (corresponding to the first electrode 6 described above), the fifth electrode 25, and the sixth electrode 29 are connected to the seventh electrode (corresponding to the second electrode 7 described above) via the anisotropic conductive film 13. As a result, the conductor 11 is sandwiched between the fourth electrode 24, the fifth electrode 25, and the sixth electrode 29 and the seventh electrode, thereby connecting the fourth electrode 24, the fifth electrode 25, and the sixth electrode 29 to the seventh electrode. In step C1, the anisotropic conductive film 13 can be cured according to the curing type of the anisotropic conductive film 13, similar to step C described above.

[0069] In the second manufacturing method, solder bumps are not required to connect the fourth electrode 24, the fifth electrode 25, and the sixth electrode 29 to the seventh electrode of the silicon interposer 23 (corresponding to the second electrode 7 described above). As a result, the semiconductor package 14, the semiconductor chip group 21, and the HBM 22 can be connected to the silicon interposer 23 at a lower temperature, and warping of the silicon interposer 23 can be suppressed.

[0070] Furthermore, in the second manufacturing method, solder bumps are not required to connect the fourth electrode 24, the fifth electrode 25, and the sixth electrode 29 to the seventh electrode of the silicon interposer 23. As a result, underfill material is not required, further reducing the manufacturing process and preventing the risk of incomplete underfilling.

[0071] [Third Embodiment] Figure 6 is an exploded cross-sectional view illustrating an example of a method for manufacturing a semiconductor package structure 30 according to this technology. The semiconductor package structure 30 has the same configuration as the semiconductor package structure 20, except that the silicon interposer 23 in the semiconductor package structure 20 is replaced with an interposer 32 (corresponding to the intermediary substrate 3) having a silicon bridge 31 (corresponding to the wiring layer 9 described above).

[0072] The interposer 32 includes, for example, a silicon bridge 31 and a silicon through-electrode 33. The interposer 32 has, for example, a silicon bridge 31 embedded in an organic substrate. The semiconductor package structure 20 includes, for example, a silicon bridge 31A for connecting the fourth electrode 24 and the sixth electrode 29, and a silicon bridge 31B for connecting the fourth electrode 24 and the fifth electrode 25, as silicon bridges 31.

[0073] On one side 32A of the interposer 32, an electrode (corresponding to the second electrode 7 described above) is formed for connecting to the fourth electrode 24, the fifth electrode 25, and the sixth electrode 29. The electrode on one side 32A of the interposer 32 can have the same configuration as the second electrode 7 described above. The semiconductor package structure 30 is connected to the electrode on one side 32A of the interposer 32 (corresponding to the second electrode 7 described above) by a conductor 11 in the cured resin layer 4, which is made of a cured product of the anisotropic conductive film 13. On the other side 32B of the interposer 32, an electrode 27 (corresponding to the third electrode 8 described above) is formed for connecting to another package substrate 28 (corresponding to the other substrate 5 described above).

[0074] Such a semiconductor package structure 30 can achieve the same effects as the semiconductor package structure 20 described above. Furthermore, the semiconductor package structure 30 can be manufactured in the same manner as the second manufacturing method. Therefore, the manufacturing method of the semiconductor package structure 30 can also achieve the same effects as the second manufacturing method described above.

[0075] [Fourth Embodiment] Figure 7 is an exploded cross-sectional view illustrating an example of a method for manufacturing a semiconductor package structure 40 according to this technology. The semiconductor package structure 40 has the same configuration as the semiconductor package structure 20, except that the silicon interposer 23 in the semiconductor package structure 20 is replaced with an organic interposer 41 (corresponding to the intermediary substrate 3 described above). As the organic interposer 41, for example, one in which a thin film wiring layer (corresponding to the wiring layer 9 described above) is formed on the surface of a build-up substrate can be used.

[0076] On one side 41A of the organic interposer 41, an electrode (corresponding to the second electrode 7 described above) is formed for connecting to the fourth electrode 24, the fifth electrode 25, and the sixth electrode 29. The electrode on one side 41A of the organic interposer 41 can have the same configuration as the second electrode 7 described above. The semiconductor package structure 40 is connected to the electrode on one side 41A of the organic interposer 41 (corresponding to the second electrode 7 described above) by a conductor 11 in the cured resin layer 4 made of the cured product of the anisotropic conductive film 13. On the other side 41B of the organic interposer 41, an electrode 27 (corresponding to the third electrode 8 described above) is formed for connecting to another package substrate 28 (corresponding to the other substrate 5 described above).

[0077] Such a semiconductor package structure 40 can achieve the same effects as the semiconductor package structure 20 described above. Furthermore, the semiconductor package structure 40 can be manufactured in the same manner as the second manufacturing method. Therefore, the manufacturing method of the semiconductor package structure 40 can also achieve the same effects as the second manufacturing method described above.

[0078] [Fifth Embodiment] Figure 8 is an exploded cross-sectional view illustrating an example of a method for manufacturing a semiconductor package structure 50 according to this technology. The semiconductor package structure 50 has the same configuration as the semiconductor package structure 20, except that the silicon interposer 23 in the semiconductor package structure 20 is replaced with a glass interposer 51 (corresponding to the intermediary substrate 3 described above). As the glass interposer 51, for example, one can be used in which a thin film wiring layer (corresponding to the wiring layer 9 described above) is formed on the surface of a glass substrate, fine through-holes are formed inside the glass substrate, and through-electrodes 52 called TGV (Through Glass via), which are filled with a conductive material, are arranged in these through-holes.

[0079] On one side 51A of the glass interposer 51, an electrode (corresponding to the second electrode 7 described above) is formed for connecting to the fourth electrode 24, the fifth electrode 25, and the sixth electrode 29. The electrode on this side 51A of the glass interposer 51 can have the same configuration as the second electrode 7 described above. The semiconductor package structure 50 is connected to the electrode on the side 51A of the glass interposer 51 by a conductor 11 in the cured resin layer 4 which is made of a cured product of the anisotropic conductive film 13, with respect to the fourth electrode 24, the fifth electrode 25, and the sixth electrode 29. On the other side 51B of the glass interposer 51, an electrode 27 (corresponding to the third electrode 8 described above) is formed for connecting to another package substrate 28 (corresponding to the other substrate 5 described above).

[0080] Such a semiconductor package structure 50 can achieve the same effects as the semiconductor package structure 20 described above. Furthermore, the semiconductor package structure 50 can be manufactured in the same manner as the second manufacturing method. Therefore, the manufacturing method of the semiconductor package structure 50 can also achieve the same effects as the second manufacturing method described above.

[0081] [Sixth Embodiment] Figure 9 is an exploded cross-sectional view illustrating an example of a method for manufacturing a semiconductor package structure 60 according to this technology. The semiconductor package structure 60 has the same configuration as the semiconductor package structure 20, except that the interposer 23 in the semiconductor package structure 20 is replaced with an interposer 64 (corresponding to the intermediary substrate 3 described above) on which an organic resin wiring layer 63 (corresponding to the wiring layer 9 described above) is formed on a silicon substrate 62 having a Si through-silicon via (TSV).

[0082] On one side 64A of the interposer 64, an electrode (corresponding to the second electrode 7 described above) is formed for connecting to the fourth electrode 24, the fifth electrode 25, and the sixth electrode 29. The electrode on one side 64A of the interposer 64 can have the same configuration as the second electrode 7 described above. The semiconductor package structure 60 is connected to the electrode on one side 64A of the interposer 64 by a conductor 11 in the cured resin layer 4, which is made of a cured product of the anisotropic conductive film 13. On the other side 64B of the interposer 64, an electrode 27 (corresponding to the third electrode 8 described above) is formed for connecting to another package substrate 28 (corresponding to the other substrate 5 described above).

[0083] Such a semiconductor package structure 60 can achieve the same effects as the semiconductor package structure 20 described above. Furthermore, the semiconductor package structure 60 can be manufactured in the same manner as the second manufacturing method. Therefore, the manufacturing method of the semiconductor package structure 60 can also achieve the same effects as the second manufacturing method described above. [Explanation of Symbols]

[0084] 1. Semiconductor package structure, 1A Semiconductor package structure, 2. Group of semiconductor chips, 2A~2C semiconductor chips (chiplets), 3. Intermediary substrate, 3A One side, 3B The other side, 4 cured resin layer, 4A fillet, 5 Other boards, 6. First electrode, 6A~6C First electrode, 7. Second electrode, 8. Third electrode, 9 wiring layer, 9A wiring layer, 9B wiring layer, 10 Through-silicon electrodes, 11 Conductors, 12 Insulating resin layer, 13 Anisotropic conductive film, 14. Semiconductor packages, 15 semiconductor chips, 15A One side, 15B The other side, 15C side, 16. Sealant, 17 redistribution layer, 17a Wiring, 17b Insulating layer, 17A One side, 17B The other side, 20 Semiconductor package structures, 21 semiconductor chip group, 21A One side, 21a Small pieces of semiconductor chips, 21b Small pieces of semiconductor chips, 22 HBM, 22A One side, 23 Silicon interposers, 23A One side, 23B The other side, 24. The fourth electrode, 25. The fifth electrode, 26 Through-silicon electrodes, 27 electrodes, 28 Package substrates, 29. The sixth electrode, 30 Semiconductor package structures, 31. Silicon bridges, 32 Interposers, 32A One side, 32B The other side, 33 Through-silicon electrodes, 40 Semiconductor package structures, 41 Organic interposer, 41A One side, 41B The other side, 50 Semiconductor package structures, 51 Glass interposer, 51A One side, 51B The other side, 52 Through electrode, 60 semiconductor package structure, 61 Si through electrode, 62 silicon substrates, 63 Redistribution layer of organic resin, 64 Interposer 64A One side, 64B The other side

Claims

1. Multiple chiplets having a first electrode on their surface, An intermediary substrate having a second electrode on one side that connects to the first electrode, and a wiring layer that wires input / output signals from one of the plurality of chiplets to other chiplets, A cured resin layer consisting of a cured anisotropic conductive film in which conductors are arranged at predetermined intervals in an insulating resin layer, and Equipped with, A semiconductor package structure in which the first electrode and the second electrode are connected by the conductor in the cured resin layer.

2. The widths of the first electrode and the second electrode are 20 μm or less. The space between the multiple first electrodes and the space between the multiple second electrodes are 20 μm or less. The semiconductor package structure according to claim 1, wherein the average particle diameter of the conductor is 5 μm or less.

3. The semiconductor package structure according to claim 1 or 2, wherein the first electrode is a planar electrode.

4. The semiconductor package structure according to claim 1 or 2, wherein the intermediary substrate is an interposer, and the base material is silicon, resin, glass, or a combination of two or more of these.

5. The semiconductor package structure according to claim 1 or 2, wherein the cured resin layer further comprises a thermally conductive filler.

6. At least one of the above-mentioned multiple chiplets comprises a fan-out type semiconductor package that includes a redistribution layer with a larger area than the chiplet in a plan view in the thickness direction. The semiconductor package structure according to claim 1 or 2, wherein the surface of the redistribution layer is the first electrode.

7. The present invention further comprises another substrate having a third electrode, The semiconductor package structure according to claim 1 or 2, wherein the second electrode and the third electrode are connected.

8. A method for manufacturing a semiconductor package structure, comprising the step of connecting the first electrode and the second electrode via an anisotropic conductive film in which conductors are aligned at predetermined intervals in an insulating resin layer, with the intermediate substrate having a plurality of chiplets having a first electrode on its surface and a second electrode on one side for connecting to the first electrode, and on the one side on which the plurality of chiplets are mounted and a wiring layer for wiring input / output signals from one of the plurality of chiplets to the other chiplets, in an arranged state.

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