Semiconductor structure integrating logic elements and memory elements

Abstract

The present invention provides a semiconductor structure that includes a substrate, logic elements, and memory elements, and integrates the logic elements and memory elements. [Solution] In the semiconductor structure 100, the substrate 110 has a first region 110A and a second region 110B that is laterally adjacent to the first region. A logic element 120 is arranged in the first region of the substrate, and a memory element 130 is arranged in the second region of the substrate. The logic element includes a plurality of transistors. The memory element includes an upper electrode 133, a lower electrode 132, and dielectric layers 134 and 135 arranged between the upper electrode and the lower electrode. The lower electrode includes a metal layer 1321 and a copper-phosphorus alloy layer 1322 that extends along the contour of the metal layer 1321 and surrounds the metal layer 1321. The upper electrode includes a metal layer 1331 and a copper-phosphorus alloy layer 1332 that extends along the contour of the metal layer 1331 and surrounds the metal layer 1331.

Description

Technical Field

[0001] Cross-reference This application claims the benefit of U.S. Patent Application No. 18 / 931,868, filed on October 30, 2024, which is hereby incorporated by reference in its entirety.

[0002] Field of the Disclosure The present disclosure relates to semiconductor structures, and more particularly to semiconductor structures integrating logic elements and memory elements.

Background Art

[0003] With the progress of technology, currently artificial intelligence and the high-performance computing (HPC) required therefor have become indispensable in the fields of science and technology. Although the computing speed of processors continues to improve, the access speed of memory cannot achieve the maintenance of that speed, resulting in the problem of the "memory wall". In other words, when the computing speed of the processor exceeds the access speed of the memory, the overall output speed is limited and the expected performance cannot be achieved.

[0004] In addition, since certain memories require a higher operating voltage and cannot be manufactured using the same manufacturing process as logic circuits, these memories and logic circuits need to be placed on different chips. In this case, the communication between the memory and the processor becomes complicated, which is disadvantageous for improving the access speed of the memory. Therefore, in this field, in order to promote the development of HPC, a complete integration solution is required by redesigning the structures of logic circuits and memory cells.

Summary of the Invention

[0005] According to one embodiment of the present disclosure, a semiconductor structure integrating logic elements and memory elements is provided. The semiconductor structure includes a substrate, logic elements, and memory elements. The substrate has a first region and a second region laterally adjacent to the first region. The logic elements are located in the first region of the substrate and include a plurality of transistors and are capable of operating as bit line and word line decoding circuits. The memory elements are located in the second region of the substrate and their manufacturing process is compatible with the manufacturing process of the logic elements located in the first region. Thus, both logic circuits and memory circuits can be manufactured on the same chip substrate (for example, forming a computing-in-memory (CIM) structure within a memory chip), thus mitigating the memory wall problem in the prior art. The memory elements include an upper electrode, a lower electrode, and a dielectric layer disposed between the upper electrode and the lower electrode. The lower electrode is located above the substrate and includes a first metal layer and a first copper-phosphorus alloy layer extending along the contour of the first metal layer and surrounding the first metal layer. The upper electrode is positioned above the substrate and the lower electrode and includes a second metal layer and a second copper-phosphorus alloy layer that extends along the contour of the second metal layer and surrounds it.

[0006] According to another aspect of this disclosure, an electronic device is provided. The electronic device comprises a circuit board, an electronic component, and an organic solderability preservative (OSP). The circuit board comprises a plurality of conductive wire layers, of which the surface conductive wire layer comprises a plurality of solder contacts. The electronic component comprises a semiconductor structure and a plurality of pins, the plurality of pins being soldered to a plurality of corresponding solder contacts. The OSP coats the surface conductive wire layer. The circuit board operates in a cooling gas or is immersed in a cooling fluid. The OSP does not cover all or at least some of the plurality of solder contacts of the surface conductive wire layer so that at least some of the other wires operate directly in the cooling gas or come into direct contact with the cooling fluid.

[0007] According to another aspect of the present disclosure, a semiconductor structure is provided. The semiconductor structure includes a substrate, logic elements, and memory elements. The substrate has a first region and a second region laterally adjacent to the first region. The logic elements are arranged in the first region of the substrate and include a plurality of transistors. The memory elements are arranged in the second region of the substrate. The memory elements include a source, a drain, a first oxide layer, a control gate, and a first copper-phosphorus alloy layer. The source and drain are located in the substrate. The first oxide layer is located in the substrate between the source and the drain. The control gate is located in the first oxide layer. The first copper-phosphorus alloy layer is located between the first oxide layer and the control gate. [Brief explanation of the drawing]

[0008] For a more comprehensive understanding of this disclosure, one can refer to the following embodiments, claims, and accompanying drawings. By standard practice in the art, various features in the drawings are not necessarily to scale. In fact, the dimensions of certain features may be intentionally enlarged or reduced for the sake of clarity.

[0009] [Figure 1] This is a schematic diagram of a semiconductor structure according to one embodiment of the present disclosure. [Figure 2] Figure 1 shows a partially enlarged schematic diagram of the barrier layer, copper-phosphorus alloy layer, and dielectric layer. [Figure 3] This is a cross-sectional view of the semiconductor structure in Figure 1. [Figure 4] This is a schematic diagram of a semiconductor structure according to another embodiment of the present disclosure. [Figure 5] This is a top view of the copper-phosphorus alloy layer in the semiconductor structure shown in Figure 4. [Figure 6] This is a schematic diagram of a semiconductor structure according to another embodiment of the present disclosure. [Figure 7] This is a schematic diagram of a memory element according to one embodiment of the present disclosure. [Figure 8] This is a cross-sectional view of the memory element in Figure 7. [Figure 9] This is a schematic diagram of a semiconductor structure according to another embodiment of the present disclosure. [Figure 10]This is a top view of the ferroelectric material layer. [Figure 11] This is a schematic diagram of a semiconductor structure according to another embodiment of the present disclosure. [Figure 12] This is a schematic diagram of a circuit board according to one embodiment of the present disclosure. [Modes for carrying out the invention]

[0010] To implement different features of the subject matter described herein, the following description of the disclosure provides numerous different embodiments or examples. Hereinafter, in order to simplify the disclosure, the following description provides specific examples of elements, arrangements, and configurations. This description is illustrative only and does not limit the disclosure. For example, in the following description, forming a first feature on / on or above a second feature may include embodiments in which the first and second features are formed in direct contact, or in which additional features are formed between the first and second features so that they do not directly contact. Furthermore, numbers and / or symbols may be repeatedly used for elements in the various embodiments of the disclosure. Such repetitions are for simplification and clarity and do not determine or represent relationships between the embodiments and / or configurations described herein.

[0011] Furthermore, for better explanation, relative spatial terms such as “below,” “below,” “lower,” “above,” and “upper” may be used to describe the relationship between one element or feature shown in the diagram and another element or feature. In addition to the directions depicted in the diagram, these relative spatial terms are intended to include different orientations of the device in use or operation. The device may be configured in other orientations (e.g., rotated 90 degrees or otherwise oriented), and the relative spatial terms may be interpreted accordingly.

[0012] While all numerical ranges and parameters defined herein are approximations, relevant values ​​in specific embodiments are reported as accurately as possible herein. However, any value inherently includes a standard deviation as a result of the respective test method. Therefore, unless otherwise specified, the numerical parameters described herein and in the appended claims may be approximations that vary depending on the requirements. These numerical parameters should be understood as values ​​obtained by applying at least a specified number of significant figures and a standard rounding method. Here, numerical ranges are expressed as from one endpoint to another, or between two endpoints. Unless otherwise specified, all numerical ranges disclosed herein encompass endpoints.

[0013] Figure 1 shows a schematic diagram of a semiconductor structure 100 according to one embodiment of the present disclosure. The semiconductor structure 100 may include a substrate 110, logic elements 120, and memory elements 130. The substrate 110 has a first region 110A and a second region 110B, with the first region 110A being laterally adjacent to the second region 110B. The logic elements 120 may be arranged in the first region 110A of the substrate 110, and the memory elements 130 may be arranged in the second region 110B of the substrate 110. In this embodiment, the logic elements 120 located in the first region 110A may include, for example, a plurality of transistors and are operable to perform data writing operations or data reading operations on the memory cells of the memory elements 130 located in the second region 110B.

[0014] In some embodiments, the substrate 110 may include semiconductor materials such as silicon (Si), germanium (Ge), gallium (Ga), any combination thereof, semiconductor on diamond (SOD), silicon on insulator (SOI), or silicon on sapphire (SOS).

[0015] In this embodiment, each transistor of the logic element 120 may include, for example, a complementary metal-oxide-semiconductor field-effect transistor (MOSFET: metal-oxide-semiconductor field-effect transistor), but the present disclosure is not limited to the above example. In some other embodiments, the logic element 120 may also include a multi-bridge channel FET (MBCFET), a stacked nanosheet FET, a fin FET (FINFET), a gate-all-around FET (GAAFET), or other types of FETs. Also, each transistor of the logic element 120 may be an enhancement-mode transistor or a depletion-mode transistor. In some embodiments, by effectively using enhancement-mode transistors and depletion-mode transistors, basic logic gates (e.g., NAND gates or NOR gates) can be implemented with a smaller number of transistors, thus reducing the components required for the entire circuit.

[0016] In this embodiment, the memory element 130 may include memory cells of a dynamic random access memory (DRAM), but the present disclosure is not limited to the above example. In some embodiments, the memory element 130 may also include memory cells of an electrically erasable programmable read-only memory (EEPROM: electrically-erasable programmable read-only memory), a ferroelectric memory, or other types of memories.

[0017] In the semiconductor structure 100, since the manufacturing processes of the logic element 120 and the memory element 130 are compatible, they can be manufactured on the same substrate 110. As a result, the logic element 120 can access the nearby memory element 130 to improve the memory access speed. Also, in some embodiments of the present disclosure, each memory element 130 can be controlled and accessed by an adjacent single transistor. Therefore, the number of required transistors is reduced, and the computing speed is further improved. Compared with the prior art in which the memory element and the logic element are separately manufactured on different dies and then packaged through an interposer (such as silicon) by 2.5D or 3D, the logic element 120 and the memory element 130 of the semiconductor structure 100 of the present disclosure can be manufactured on the same wafer substrate, so that better heat dissipation efficiency and operating performance can be achieved. The semiconductor structure 100 provided by the embodiments of the present disclosure is applicable for attaching a memory cell to a logic circuit or attaching a logic unit to a memory circuit, thereby improving the performance of various circuits.

[0018] In some embodiments, the memory element 130 may include a decoding circuit having bit lines and word lines, but the present disclosure is not limited to the above example. In some embodiments, the memory element 130 may further include a logic circuit for performing calculations. In other words, both the logic circuit and the memory circuit can be manufactured on the substrate of the same chip (for example, forming a computing-in-memory (CIM) structure in a memory chip), so the problem of the "memory wall" in the prior art is alleviated.

[0019] In the semiconductor structure 100, the logic element 120 may include a plurality of transistors, and the memory element 130 may include a plurality of capacitors. However, in this embodiment, for a better understanding of the details of the present disclosure, FIG. 1 shows only one FET of the logic element 120 and one capacitor of the memory element 130 adjacent to the FET.

[0020] As shown in Figure 1, the substrate 110 may include a wafer layer 112, an epitaxial layer 114, and P-wells PW1 and N-wells NW1 formed within the epitaxial layer 114. In this embodiment, the logic element 120 may include an NMOSEFT disposed in the P-well PW1, and the memory element 130 may include a capacitor disposed in the N-well NW1. The P-well PW1 of the logic element 120 includes N-type high-density regions 121A and 121B, which can be used as the source and drain of a transistor, respectively. In this embodiment, in the P-well PW1, N-type low-density regions 122A and 122B may be disposed between and adjacent to the N-type high-density regions 121A and 121B to improve the thermal conductivity and reliability of the transistor. Furthermore, in this embodiment, in the P-well PW1, the indium gallium zinc oxide (IGZO) channel 123 may be located between the N-type low-concentration regions 122A and 122B, and may be doped with trivalent elements, calcium (Ca), magnesium (Mg), or copper (Cu) to adjust the transistor threshold voltage, but this disclosure is not limited to the above examples. In some embodiments, the channel 123 may be made of a silicon germanium material, for example, Si (1-x) Ge x It may be formed by (0 ≤ x ≤ 0.5).

[0021] Furthermore, the logic element 120 may further include a gate structure 124 disposed in the channel 123. In some embodiments, the gate structure 124 may include a high-k dielectric layer 1241 and a polycrystalline silicon layer 1242, and the high-k dielectric layer 1241 is manufactured from a material such as hafnium oxide (HfO2), but is not limited thereto. Also, as shown in Figure 1, the semiconductor structure 100 may further include a dielectric layer 126 disposed on the substrate 110, and the dielectric layer 126 may cover the logic element 120. In some embodiments, the dielectric layer 126 may include, for example, silicate glass, and is not limited to, phosphosilicate glass or borosilicate glass.

[0022] In this embodiment, the logic element 120 may further include conductive plugs 125A, 125B, and 125C that penetrate the dielectric layer 126. The conductive plugs 125A, 125B, and 125C are in contact with the N-type high-density region 121A (i.e., the source of the transistor), the N-type high-density region 121B (i.e., the drain of the transistor), and the gate structure 124, respectively. In some embodiments, a plurality of metal wire layers (not shown in Figure 1) may be arranged in the logic element 120, and the source, drain, and gate of the transistor of the logic element 120 are electrically connected to the wires of the metal wire layers via the conductive plugs 125A, 125B, and 125C.

[0023] In this embodiment, the conductive plugs 125A, 125B, and 125C may have a multilayer structure. For example, the conductive plug 125A may include a barrier layer 1251, a copper-phosphorus alloy layer 1252, and an electrode metal layer 1253. The barrier layer 1251 and the copper-phosphorus alloy layer 1252 may be formed along the contours of the recesses of the dielectric layer 126, and the electrode metal layer 1253 may fill the recesses of the copper-phosphorus alloy layer 1252, thereby sandwiching the copper-phosphorus alloy layer 1252 between the electrode metal layer 1253 and the barrier layer 1251. In some embodiments, for example, the barrier layer 1251 may include titanium nitride (TiN), and the electrode metal layer 1253 may include Cu, tungsten (W), cobalt (Co), or ruthenium (Rh).

[0024] In Figure 1, the memory element 130 may include a lower electrode 132, an upper electrode 133, and dielectric layers 134 and 135 disposed between the lower electrode 132 and the upper electrode 133. The lower electrode 132 may be positioned above the substrate 110, and the upper electrode 133 may be positioned above both the substrate 110 and the lower electrode 132. In this embodiment, the memory element 130 may include, for example, a memory cell of a DRAM, and the upper electrode 133, the lower electrode 132, and the dielectric material within them (including dielectric layers 134 and 135) may form a capacitor for storing charge. In some embodiments, the dielectric layers 134 and 135 may have a high dielectric constant (k) and be manufactured from a material such as hafnium oxide (HfO2).

[0025] As shown in Figure 1, the memory element 130 may be placed in the second region 110B of the substrate 110, on the drain of the transistor of the logic element 120, and the upper electrode 133 of the memory element 130 may cover the conductive plug 125B along the vertical direction (e.g., the Z direction). In other words, the upper electrode 133 of the memory element 130 may be electrically connected to the drain of the transistor of the logic element 120 (i.e., the N-type high-density region 121B).

[0026] Furthermore, in this embodiment, the lower electrode 132 may include a metal layer 1321, a copper-phosphorus alloy layer 1322, and a barrier layer 1323. The copper-phosphorus alloy layer 1322 may extend along the contour of the metal layer 1321 and surround the metal layer 1321, and the barrier layer 1323 may also surround the copper-phosphorus alloy layer 1322 along its contour. Figure 2 shows a partially enlarged schematic view of the barrier layer 1323, copper-phosphorus alloy layer 1322, and metal layer 1321 located in region 110B in Figure 1, according to one embodiment of the present disclosure. As shown in Figure 2, due to the properties of the copper-phosphorus alloy, the surface of the copper-phosphorus alloy layer 1322 has a needle-like structure, thereby increasing the surface area of ​​the lower electrode 132 and increasing the capacitance value of the capacitor formed by the upper electrode 133 and the lower electrode 132. Similarly, the upper electrode 133 may include a metal layer 1331, a copper-phosphorus alloy layer 1332, and a barrier layer 1333. The copper-phosphorus alloy layer 1332 may extend along the contour of the metal layer 1331 and surround the metal layer 1331, and the barrier layer 1333 may also surround the copper-phosphorus alloy layer 1332 along its contour.

[0027] In this embodiment, a shallow trench isolation structure 138, made of a material containing undoped silicate glass (USG), may be formed in the N well NW1 in the second region 110B of the substrate 110. In this way, the lower electrode 132 can be separated from the N well NW1 of the substrate 110 by the shallow trench isolation structure 138.

[0028] As shown in Figure 1, the metal layer 1321 may have a comb-like structure including a plurality of protrusions 1321A, and the metal layer 1331 may also have a comb-like structure including a plurality of protrusions 1331A. The protrusions 1321A extend toward the upper electrode 133, and the protrusions 1331A extend toward the lower electrode 132, and the plurality of protrusions 1321A and the plurality of protrusions 1331A may be interlaced with each other. By designing such an interlacing comb-like structure, the effective overlapping surface area between the metal layer 1321 and the metal layer 1331 can be increased, and the capacitance value of the memory element 130 can be increased. In some embodiments, the plurality of protrusions 1321A may be arranged in an array, and the plurality of protrusions 1331A may also be arranged in an array, but the present disclosure is not limited to the above examples.

[0029] In Figure 1, the substrate 110 may include a first region 110A on which logic elements 120 are formed and a second region 110B on which memory elements 130 are formed. As shown in Figure 1, the N-type high-density regions 121A and 121B may be located in the P-well PW1 of the first region 110A, the N-type low-density regions 122A and 122B may be located between the N-type high-density regions 121A and 121B and may be adjacent to the N-type high-density regions 121A and 121B, and the IGZO channel 123 may be located between the N-type low-density regions 122A and 122B. In some embodiments, the channel 123 may be a silicon-germanium channel containing silicon-germanium material.

[0030] Furthermore, in the semiconductor structure 100, the memory element 130 may be formed in the second region 110B where a P-type transistor is normally formed. More specifically, the shallow trench isolation structure 138 may be formed in the N-well NW1, and the lower electrode 132 may be formed in the shallow trench isolation structure 138. In this embodiment, the shallow trench isolation structure 138 may be, for example, a USG.

[0031] In Figure 1, the gate structure 124 may be formed in the channel 123. After the gate structure 124 is formed, at least one dielectric layer 126 may be further formed, and the dielectric layer 126 may include, for example, silicate glass. The gate structure 124 may also include a high-k dielectric layer 1241 and a polycrystalline silicon layer 1242. In some embodiments, the high-k dielectric layer 1241 includes HfO2 and is manufactured by atomic layer deposition (ALD) to improve its reliability, and may have a thickness of, for example, 5 nm to 10 nm, but this disclosure is not limited to the above examples. In some embodiments, the high-k dielectric layer 1241 may include a two-layer stacked structure of zirconium dioxide (ZrO2) and HfO2.

[0032] In Figure 1, the dielectric layers 126 on the N-type high-concentration regions 121A and 121B and on the gate structure 124 (i.e., the source, drain, and gate of the transistor) are formed to have openings, and the dielectric layer 126 in the second region 110B may be formed to have a deep trench structure (larger openings). In such cases, the lift-off process sequentially deposits the barrier layer 1251 and the copper-phosphorus alloy layer 1252 into the openings of the dielectric layer 126 in the first region 110A, and the barrier layer 1323 and the copper-phosphorus alloy layer 1322 into the deep trenches of the dielectric layer 126 in the second region 110B.

[0033] Next, to form electrodes connected to the source, drain, and gate of the transistor, the electrode metal layer 1253 may be continuously embedded in the openings of the dielectric layer 126 in the first region 110A. In this embodiment, the electrode metal layer 1253 may contain, for example, Cu, W, Co, or Rh. The metal layer 1321 may also be formed in the barrier layer 1323 and copper-phosphorus alloy layer 1322 of the second region 110B, and the metal layer 1321 may be partially removed by a lithography process and a lift-off process, thereby the metal layer 1321 may have a plurality of protrusions 1321A. In some embodiments, the metal layer 1321 may be manufactured from a material such as Cu, W, Co, or Rh, and may be manufactured using the same manufacturing process as the electrode metal layer 1253. Thus, the manufacturing process for the capacitor of the memory element 130 is compatible with the manufacturing process for the transistor of the logic element 120. In this embodiment, the copper-phosphorus alloy layer 1322 and the barrier layer 1323 may be formed sequentially on the metal layer 1321, thereby allowing the copper-phosphorus alloy layer 1322 and the barrier layer 1323 to extend along the contour of the metal layer 1321 and completely protect the metal layer 1321. In some embodiments, the copper-phosphorus alloy layer and the barrier layer (not shown) may be further formed above the electrode metal layer 1253.

[0034] Figure 3 shows a cross-sectional view obtained by cutting the semiconductor structure 100 in Figure 1 along the cutting line A1-A1' in Figure 1.

[0035] In the embodiment shown in Figure 3, the multiple protrusions 1321A may be arranged in an array to increase the surface area of ​​the lower electrode 132, but the disclosure is not limited to the above example.

[0036] In Figure 1, the dielectric layer 134 may be formed in the recesses between the protrusions 1321A to fill the recesses. In some embodiments, the dielectric layer 134 may be formed by depositing HfO2 by ALD. Since the dielectric constant of HfO2 can be increased to 26-30, the memory element 130 can achieve a higher capacitance value in the same area compared to memory elements using conventional materials. Furthermore, the high dielectric constant dielectric layer 134 formed by ALD improves reliability and helps reduce capacitance leakage, thereby further improving the performance of the memory element 130.

[0037] The dielectric layer 135 may be formed on the protrusions 1321A by a lithography process, and may be manufactured from the same material as the dielectric layer 134. Next, the upper electrode 133 (including the barrier layer 1333, the copper-phosphorus alloy layer 1332, and the metal layer 1331) may be formed on the dielectric layers 134 and 135. In this way, the protrusions 1331A of the metal layer 1331 are arranged alternately with the protrusions 1321A of the lower electrode 132.

[0038] The presence of alternating protrusions 1321A and 1331A on the metal layer 1321 of the lower electrode 132 and the metal layer 1331 of the upper electrode 133 increases the effective overlapping surface area between the lower electrode 132 and the upper electrode 133. In this way, compared to conventional structures, the memory element 130 of this disclosure can increase the capacitance value of the capacitor within the same base area, thereby increasing the memory density and capacity within a unit base area of ​​the semiconductor structure 100. Furthermore, since the transistor of the logic element 120 may be electrically connected to the capacitor of the adjacent memory element 130, the parasitic capacitance of the bit line can be more easily reduced, thereby reducing the heat and power loss generated during charging / discharging of the capacitor.

[0039] Figure 4 shows a schematic diagram of a semiconductor structure 300 according to one embodiment of the present disclosure. The semiconductor structure 300 differs from the semiconductor structure 100 in that the memory element 330 of the semiconductor structure 300 may include an EEPROM memory cell. However, the structure of the memory cell differs from the silicon-oxide-nitride-oxide-silicon (SONOS) floating gate used in general EEPROMs. In this embodiment, in the memory cell of the memory element 330, a copper-phosphorus alloy layer having a plurality of protruding structures may be added to the floating gate to enhance the electric field for write and erase operations, thereby making the operation of the memory element 330 more efficient. Also, similar to the semiconductor structure 100, the logic element 320 and the memory element 330 in the semiconductor structure 300 are compatible in terms of their manufacturing processes, and therefore, both can be manufactured on the same wafer substrate using the same manufacturing process.

[0040] The semiconductor structure 300 includes a substrate 310, logic elements 320, and memory elements 330. The substrate 310 has a first region 310A and a second region 310B that is laterally adjacent to the first region 310A. The logic elements 320 may be arranged in the first region 310A of the substrate 310, and the memory elements 330 may be arranged in the second region 310B of the substrate 310.

[0041] In this embodiment, the substrate 310 may include a wafer layer 312, an epitaxial layer 314, and P-wells PW1, PW2, and N-wells NW1 formed within the epitaxial layer 314. The logic element 320 may include a plurality of transistors. For example, as shown in Figure 4, the logic element 320 may include an N-type transistor M1N and a P-type transistor M1P. The N-type transistor M1N may include a P-well PW1, N-type high-density regions 321A, 321B, a gate structure 324A, and conductive plugs 325A, 325B. The P-type transistor M1P may include an N-well NW1, P-type high-density regions 321C, 321D, a gate structure 324B, and conductive plugs 325C, 325D.

[0042] The N-type high-concentration regions 321A and 321B are located on two opposite sides of the P-well PW1 and may function as the source and drain of transistor M1N, respectively. In this embodiment, to improve the reliability of the N-type transistor M1N, the transistor M1N is located between the N-type high-concentration regions 321A and 321B and may further include N-type low-concentration regions 322A and 322B adjacent to the N-type high-concentration regions 321A and 321B. The gate structure 324A of transistor M1N is located in the P-well PW1 and may be located between the N-type high-concentration region 321A and N-type high-concentration region 321B. The gate structure 324A includes an oxide layer 3244 (e.g., a silicon dioxide (SiO2) layer formed by ALD), a polycrystalline silicon layer 3245, a barrier layer 3241 (e.g., containing TiN), a copper-phosphorus alloy layer 3242, and an electrode metal layer 3243 (e.g., containing Cu, W, Co, or Rh). Conductive plugs 325A and 325B may penetrate the SiO2 layer 342 and silicate glass layer 344 (e.g., phosphate silicate glass or borosilicate glass) formed on the substrate 310 and be electrically connected to the source and drain of transistor M1N (i.e., N-type high-concentration regions 321A and 321B). In this embodiment, conductive plugs 325A and 325B may also have a multilayer structure. For example, the conductive plug 325A may include a barrier layer 3251 (e.g., TiN), a copper-phosphorus alloy layer 3252, and an electrode metal layer 3253 (e.g., containing Cu, W, Co, or Rh).

[0043] The P-type transistor M1P may include an N-well NW1, P-type high-concentration regions 321C and 321D, a gate structure 324B, and conductive plugs 325C and 325D. The P-type high-concentration regions 321C and 321D may be located on two opposite sides of the N-well NW1 and function as the source and drain of transistor M1P, respectively. In this embodiment, to improve the reliability of the P-type transistor M1P, transistor M1P may further include P-type low-concentration regions 322C and 322D, located between the P-type high-concentration regions 321C and 321D. The gate structure 324B of transistor M1P is located in the N-well NW1 and may be located between the P-type high-concentration regions 321C and 321D. The gate structure 324B may have the same multilayer structure as the gate structure 324A, and the conductive plugs 325C and 325D may also have the same multilayer structure as the gate structures of the conductive plugs 325A and 325B. Furthermore, the conductive plugs 325C and 325D may penetrate the SiO2 layer 342 and the silicate glass layer 344 on the substrate 310 and be electrically connected to the source and drain of the transistor M1P (i.e., the P-type high-concentration regions 321C and 321D).

[0044] The memory element 330 may include a source 334A, a drain 334B, an oxide layer 331, copper-phosphorus alloy layers 333, 337 (having an array of needle-like structures) capable of rapidly attracting or releasing electrons, a charge storage layer 338, an oxide layer 336, a control gate 332, and conductive plugs 339A, 339B. In this embodiment, the memory element 330 may be arranged in a P-well PW2, and the source 334A and drain 334B may be arranged in an N-type high-concentration region of the P-well PW2. Furthermore, as shown in Figure 4, the memory element 330 may also include N-type low-concentration regions 335A and 335B arranged between the source 334A and drain 334B and adjacent to the source 334A and drain 334B.

[0045] The oxide layer 331 may be located on the substrate 310 between the source 334A and the drain 334B. In some embodiments, the oxide layer 331 may contain SiO2 and be formed by ALD. In such cases, the oxide layer 331 can have higher reliability and thus help prevent charge from escaping from the charge storage layer 338. Also, since the oxide layer 331 formed by ALD can have a smaller thickness, the operating voltage required for the read and write operations performed by the memory element 330 can be further reduced.

[0046] As shown in Figure 4, the copper-phosphorus alloy layer 333 may be located on the oxide layer 331, the charge storage layer 338 may be located on both the copper-phosphorus alloy layer 333 and the oxide layer 331, and the copper-phosphorus alloy layer 337 may be located on the charge storage layer 338. In other words, the copper-phosphorus alloy layers 333 and 337 (which have an array of needle-like structures) that can rapidly attract or release electrons may be located above and below the charge storage layer 338, respectively. The oxide layer 336 may also be located on both the charge storage layer 338 and the copper-phosphorus alloy layer 337. In such cases, the copper-phosphorus alloy layer 333 is sandwiched between the oxide layer 331 and the charge storage layer 338, and the copper-phosphorus alloy layer 337 is sandwiched between the oxide layer 336 and the charge storage layer 338. In some embodiments, the oxide layer 331 may be called the first oxide layer, the oxide layer 336 may be called the second oxide layer, the copper-phosphorus alloy layer 333 may be called the first copper-phosphorus alloy layer, and the copper-phosphorus alloy layer 337 may be called the second copper-phosphorus alloy layer, but the present disclosure is not limited to the above examples.

[0047] In this embodiment, the copper-phosphorus alloy layer 333 has a plurality of protruding structures facing the copper-phosphorus alloy layer 337, and the copper-phosphorus alloy layer 337 has a plurality of protruding structures facing the copper-phosphorus alloy layer 333. Figure 5 shows a top view of the copper-phosphorus alloy layer 333 obtained by cutting along the cutting line A2-A2' in Figure 4.

[0048] In this embodiment, after an oxide layer 331 (e.g., SiO2 with a thickness of 1 nm to 2 nm) is formed between a source 334A and a drain 334B on a substrate 310 by ALD, a SiN layer may be deposited on the oxide layer 331 as a charge storage layer 338. The array of needle-like holes may be formed in the SiN layer by a lithography process, and the copper-phosphorus alloy layer 333 may be formed in the holes of the SiN layer by a lift-off process. In some embodiments, before the copper-phosphorus alloy layer 333 is formed, a barrier layer (not shown) may first be filled into the holes to prevent metal diffusion and contamination. In some embodiments, the barrier layer may be made of a material such as TiN.

[0049] After the copper-phosphorus alloy layer 333 is formed, another SiN layer is deposited on the copper-phosphorus alloy layer 333 and the original SiN layer, and the two sequentially formed upper and lower SiN layers become the charge storage layer 338. Then, multiple holes are formed in the newly formed SiN layer, and subsequently, the copper-phosphorus alloy layer 337 is formed in the holes of the SiN layer by a lift-off process. In this embodiment, the protrusion structures of the copper-phosphorus alloy layer 333 and the protrusion structures of the copper-phosphorus alloy layer 337 may be arranged alternately. For example, the respective protrusion structures of the copper-phosphorus alloy layer 333 and the copper-phosphorus alloy layer 337 do not have to overlap in the X-axis direction. In this embodiment, because the protrusion structures of the copper-phosphorus alloy layer 333 and the copper-phosphorus alloy layer 337 have small radii of curvature, they help to strengthen the electric field for capturing or releasing electrons, thereby improving the efficiency of the write and erase operations of the EEPROM (i.e., memory element 330), respectively.

[0050] In the above embodiments, the charge storage layer 338 may include, for example, SiN, but the disclosure is not limited to the above examples. In some embodiments, the charge storage layer 338 may include SiN, hafnium aluminum oxide (HaAlO), HfO2, aluminum oxide (Al2O3), or a combination thereof. For example, the charge storage layer 338 may include HaAlO. Because the energy band difference between the conduction bands of HaAlO and Si is only 1.63 electron volts, electrons moving within the channel 329 of the memory element 330 are easily tunneled by the conduction band of the charge storage layer 338 under the same gate voltage.

[0051] Furthermore, the charge storage layer 338 may also contain HfO2. The structure of HfO2 helps in electron capture and facilitates the resolution of the problem of excessive erasure, thus improving the performance of the memory element 330. In addition, the copper-phosphorus alloy is used as an oxygen scavenger, creating two positively charged oxygen vacancies at the lattice sites of HfO2. Therefore, the copper-phosphorus alloy layers 333 and 337, positioned above and below the charge storage layer 338, can improve the charge storage capacity of HfO2. On the other hand, the copper-phosphorus alloy layers 333 and 337 can further prevent oxygen atoms from escaping from HfO2 and diffusing into the substrate 310, thereby preventing an increase in the thickness of silicon dioxide (SiO2) and reducing the rate of performance degradation of the memory element 330. In other words, the copper-phosphorus alloy layers 333, 337 and the charge storage layer 338 containing HfO2 enable the memory element 330 of this embodiment to achieve superior performance and reliability.

[0052] In this embodiment, the control gate 332 may also include a multilayer structure. For example, the control gate 332 may include a barrier layer 3321, a copper-phosphorus alloy layer 3322 (e.g., a third copper-phosphorus alloy layer), and a gate electrode layer 3323, which are sequentially formed on the oxide layer 336. The barrier layer 3321 can prevent the metal of the gate electrode layer 3323 from diffusing into the oxide layer 336, and the copper-phosphorus alloy layer 3322 may function as a wetting layer for plating the gate electrode layer 3323. In some embodiments, for example, the barrier layer 3321 may contain TiN, and the gate electrode layer 3323 may contain Cu, W, Co, or Rh. Also in this embodiment, the conductive plugs 339A and 339B may also include a multilayer structure. For example, the conductive plug 339A may include a barrier layer 3391, a copper-phosphorus alloy layer 3392, and an electrode metal layer 3393.

[0053] The details of the operation of the memory element 330, including write operations, erase operations (including two types), and read operations, are described below.

[0054] When a write operation is performed, the control gate 332 and drain 334B receive a positive voltage (e.g., power supply voltage), and the source 334A receives a ground voltage. In such a case, a vertically downward (e.g., negative Z-axis) electric field is generated between the control gate 332 and the substrate 310. When electrons are accelerated along the channel 329 from the source 334A towards the drain 334B and collide with the junction region of the drain 334B, a hot electron injection effect is induced, thereby attracting some electrons in the channel 329 by the vertically downward electric field, passing through the oxide layer 331 and entering the charge storage layer 338. Since the electrons that enter the charge storage layer 338 do not have excess energy, after the write operation, these electrons are stored in the charge storage layer 338, thereby putting the memory element 330 into a written state. In this embodiment, the copper-phosphorus alloy layers 333 and 337 have a needle-like projection structure arranged in an array, which can increase both the charge density at the tip and the vertically downward electric field within the channel 329. As a result, electrons passing through the channel 329 are captured and can quickly pass through the oxide layer 331 into the charge storage layer 338. Therefore, the writing operation time can be shortened and the performance of the memory element 330 is also improved.

[0055] When a first type erase operation is performed, the control gate 332 receives a ground voltage or a negative voltage, and the source 334A and drain 334B receive a positive voltage (e.g., power supply voltage). In this case, a vertically upward (e.g., positive Z-axis) electric field is generated between the control gate 332 and the substrate 310, and electrons present in the charge storage layer 338 are attracted to the copper-phosphorus alloy layer 333 (which can cause a tip effect that can enhance and concentrate the vertically upward electric field), and quickly return to the channel 329 between the source 334A and drain 334B, erasing the write state of the memory element 330.

[0056] In some other embodiments, when a second type of erase operation is performed, the control gate 332 receives a positive voltage, while the source 334A and drain 334B receive a negative voltage. In such cases, a strong vertically downward electric field can further attract electrons present in the charge storage layer 338 to the copper-phosphorus alloy layer 337 (which can cause a tip effect that can enhance and concentrate the vertically downward electric field), thereby allowing the captured electrons to quickly pass through the control gate 332 and erase the written state of the memory element 330. In other words, in a second type of erase operation, the memory element 330 of the present disclosure can attract electrons present in the charge storage layer 338 to the control gate 332, thereby allowing the electrons to pass through another oxide layer 336, reducing the number of times the electrons pass through the oxide layer 331 and extending the durability of the memory element 330.

[0057] When a read operation is performed, the control gate 332 receives a ground voltage, the drain 334B receives a second positive voltage (e.g., a threshold voltage), and the source 334A receives a ground voltage. The current flowing from the drain 334B to the source 334A in the channel is measured under the above conditions. If the measured current is less than a predetermined threshold, it means that electrons are being stored in the charge storage layer 338, and at this point the memory element 330 is determined to be in a write state (e.g., represented by a value of "1"). Conversely, if the measured current is greater than another predetermined threshold, it means that there are not enough electrons stored in the charge storage layer 338, and at this point the memory element 330 is determined to be in an erase or unwritten state (e.g., represented by a value of "0").

[0058] In some embodiments, the memory element 330 may have two or more storage states. That is, the memory element 330 may be a multilevel cell (MLC) capable of storing multiple bits. For example, the memory element 330 may be determined to be in one of multiple storage states depending on the number of electrons in the charge storage layer 338. In such cases, the state of the number of electrons stored in the memory element 330 can be determined according to the magnitude of the current rating read on the channel. In some embodiments, there may be four (or eight) states depending on the number of electrons stored in the memory element 330, and the memory element 330 can be used to store 2-bit (or 3-bit) data.

[0059] Figure 6 shows a schematic diagram of a semiconductor structure 400 according to one embodiment of the present disclosure. The semiconductor structure 400 further includes IGZO or silicon germanium (e.g., Si) in the channels between the source and drain of the transistors of the logic elements and memory elements. (1-x) Ge x Here, 0≦x≦0.5) may be added. For example, transistor M1N' of logic element 420 may further include channel 421A between source 321A and drain 321B, transistor M1P' of logic element 420 may further include channel 421B between source 321C and drain 321D, and memory element 430 may further include channel 431 between source 334A and drain 334B. In this embodiment, channels 421A, 421B and 431 may be IGZO channels or silicon germanium channels.

[0060] Compared to enhancement-mode elements of single-crystal silicon, IGZO is a depletion-mode element, resulting in increased carrier concentration and electron mobility. This not only increases read and write speeds but also improves conductivity, reducing the operating voltage and size of the transistor. Furthermore, generally, the surface of IGZO absorbs oxygen from the environment, allowing electrons (i.e., carriers) within it to bond, enabling the transistor to have a higher threshold voltage. Therefore, in some embodiments, channels 421A, 421B, and 431 may be IGZO channels, and may be further doped with Ca, Mg, or Cu to adjust the threshold voltages of the logic element 320 and memory element 330. In this way, the transistors within can also be configured as enhancement-mode transistors, thereby achieving even better power saving effects.

[0061] In some embodiments, the logic elements and memory elements may include FINFETs. In this embodiment, the memory element may be formed as an EEPROM unit based on the structure of a FINFET. Figure 7 shows a schematic diagram of a memory element 530 according to one embodiment of the present disclosure. The memory element 530 includes N memory cells 530_1 to 530_N connected in parallel, where N is an integer greater than 1. Each of the memory cells 530_1 to 530_N includes a fin structure 532 on a substrate 510 and a control gate 539 that controls the fin structure channel.

[0062] As shown in Figure 7, each of the memory cells 530_1 to 530_N may further include a source 52 and a drain 53 located at two opposite ends of the fin structure 532. In this embodiment, the fin structure 532 between the source 52 and the drain 53 may be designed as a narrow nanoscale transistor channel. In this case, the narrow width of the channel between the source 52 and the drain 53 and the use of an array-like structure of copper-phosphorus alloy (not shown) in the charge storage region can increase the likelihood of collisions between electrons and the crystal lattice in the channel or junction region, thereby increasing the rate of hot electron injection, reducing the operating voltage and operating time required for the memory element 530, and improving the overall performance of the memory element 530.

[0063] Furthermore, the memory cells 530_1 to 530_N within the memory element 530 may be connected in parallel so that the memory element 530 can generate sufficient current to facilitate read operations. For example, as shown in Figure 7, the sources 52 of the memory cells 530_1 to 530_N may be connected to each other by conductive wire 51A, and the drains 53 of the memory cells 530_1 to 530_N may be connected to each other by conductive wire 51B. In other words, since the memory cells 530_1 to 530_N receive the same voltage, write, erase, and read operations can be performed simultaneously. In some embodiments, the conductive wires 51A and 51B may be made of a material such as a multilayer structure including a TiN layer, a copper-phosphorus alloy layer, and a metal layer (Cu, W, Co, or Rh), and the copper-phosphorus alloy layer may be placed between the TiN layer and the metal layer, but the disclosure is not limited thereto.

[0064] In this embodiment, the channels of the logic element and memory element (for example, the channel between the source 52 and the drain 53) are made of silicon germanium material (for example, Si (1-x) Ge xThis may include (0 ≤ x ≤ 0.5). Compared to silicon-based channels, channels made using silicon-germanium material exhibit increased mobility (e.g., a 40% increase), increased operating frequency (e.g., a 10% increase), and a lower threshold voltage. Furthermore, using silicon-germanium as the channel material can improve the negative-bias temperature instability (NBTI) of the threshold voltage in P-type transistors.

[0065] Figure 8 shows a cross-sectional view of the memory element 530 cut along the cutting line A3-A3' in Figure 7. In this embodiment, memory cells 530_1 to 530_N may have the same structure and can operate synchronously. For example, memory cell 530_1 may be sequentially stacked on a fin structure 532 and may include an oxide layer 533 (e.g., containing SiO2), a copper-phosphorus alloy layer 534, a charge storage layer 535 (e.g., containing SiN, HaAlO, HfO2, Al2O3, or a combination thereof), a copper-phosphorus alloy layer 536, an oxide layer 537, and a control gate 539 (e.g., containing Cu, W, Co, or Rh), surrounding the top and side walls of the fin structure 532. In some embodiments, the oxide layer 533 may be a first oxide layer, the copper-phosphorus alloy layer 534 may be a first copper-phosphorus alloy layer, the oxide layer 537 may be a second oxide layer, and the copper-phosphorus alloy layer 536 may be a second copper-phosphorus alloy layer, but the disclosure is not limited thereto.

[0066] In this embodiment, the operational details of the memory element 530 are the same as those of the memory element 330 described above, so a redundant explanation is omitted here.

[0067] In addition to the DRAM unit of the memory element 130 and the EEPROM units of the memory elements 330, 430, and 530 described above, the memory elements may also be implemented by ferroelectric memory cells whose manufacturing process is compatible with the manufacturing process of logic element transistors.

[0068] Figure 9 shows a schematic diagram of a semiconductor structure 600 according to one embodiment of the present disclosure. The memory element 630 of the semiconductor structure 600 is a ferroelectric memory cell.

[0069] The semiconductor structure 600 includes a substrate 610, a logic element 620, and a memory element 630. The logic element 620 may be arranged in a first region 610A of the substrate 610, and the memory element 630 may be arranged in a second region 610B of the substrate 610. The substrate 610 may include a wafer layer 612, an epitaxial layer 614, and P-wells PW1, PW2, and N-wells NW1 formed within the epitaxial layer 614. The logic element 620 may include an N-type transistor M1N and a P-type transistor M1P formed in the P-well PW1 and N-well NW1, respectively. Since the N-type transistor M1N and the P-type transistor M1P have the same structure as the transistors of the logic element 320 of the semiconductor structure 300, a redundant explanation is omitted here.

[0070] The memory element 630 may include a source 634A and a drain 634B located in the P-well PW2, an oxide layer 631, an array-structured ferroelectric material layer 636 (with a thickness of 5 nm to 15 nm), a copper-phosphorus alloy layer 633, and a control gate 632. The source 634A and drain 634B are N-type high-concentration regions of the P-well PW2. In this embodiment, in order to improve the reliability of the memory element 630, N-type low-concentration regions 635A and 635B may be further located between the source 634A and the drain 634B, and may also be adjacent to the source 634A and the drain 634B.

[0071] The oxide layer 631 is located on the substrate 610 between the source 634A and the drain 634B. Figure 10 shows a cross-sectional view of the ferroelectric material layer 636 cut along the cutting line A4-A4' in Figure 9. In this embodiment, the ferroelectric material layer 636 may be located on the oxide layer 631 (with a thickness of 1 nm to 5 nm) and may include an array formed by a plurality of protrusion structures, as shown in Figure 10. The copper-phosphorus alloy layer 633 may be formed on the oxide layer 631 and fill the gaps around the array structure of the ferroelectric material layer 636. The control gate 632 may include an electrode metal (e.g., Cu, W, Co, or Rh) and may be located on the copper-phosphorus alloy layer 633 and embedded in a recess of the copper-phosphorus alloy layer 633. In this case, the copper-phosphorus alloy layer 633 is positioned between the oxide layer 631 and the control gate 632, and the ferroelectric material layer 636 of the array structure is positioned between the copper-phosphorus alloy layer 633 and the oxide layer 631. In another embodiment, the ferroelectric material layer 636 and the copper-phosphorus alloy layer 633 may be a planar structure (not shown) with uniform thickness and sequentially stacked.

[0072] In this embodiment, the ferroelectric material layer 636 may contain HfO2. Compared to conventional perovskite-type ferroelectric materials, HfO2 offers higher compatibility with CMOS manufacturing processes. Furthermore, HfO2 can maintain efficient and high-speed ferroelectricity even at a thickness of 5 nm to 15 nm. In some embodiments, Si, Zr, Al, N, La (lanthanum), or Ti may be added to bond with HfO2 to form electric dipoles when HfO2 is deposited. However, because the crystallization temperature of HfO2 is low, the oxide layer 631 may crystallize during the manufacturing process of the semiconductor structure 600, thereby allowing electrons to easily tunnel and potentially generating a large leakage current. In this embodiment, to avoid the above problem, when forming the oxide layer 631, the generation of leakage current is reduced by forming finer SiO2 by ALD.

[0073] Because the copper-phosphorus alloy layer 633 of the memory element 630 can extend into the holes of the ferroelectric material layer 636, the ferroelectric material layer 636, which has an array of multiple protrusion structures, receives induction of strengthening electric fields in multiple directions during writing operations, thereby accelerating the rate of electric dipole polarization. Furthermore, because the copper-phosphorus alloy layer 633 can function as an oxygen scavenger, the number of lattice sites of HfO2 increases, strengthening the electric dipole effect, thereby lowering the operating voltage required for the memory element 630. On the other hand, the oxygen scavenging performance of the copper-phosphorus alloy layer 633 prevents oxygen atoms of HfO2 from diffusing into the substrate 610, thereby preventing an increase in the thickness of SiO2 and mitigating the rate of performance degradation of the ferroelectric memory cell.

[0074] The details of the operation of the memory element 630, including write and read operations, are described below.

[0075] In this embodiment, the memory element 630 can support two write operation modes corresponding to different memory states. For example, a first type of write operation provides the ferroelectric material layer 636 with a first dipole polarization direction (e.g., the negative direction of the Z axis), and a second type of write operation provides the ferroelectric material layer 636 with a second dipole polarization direction (e.g., the positive direction of the Z axis). In some embodiments, when the ferroelectric material layer 636 has a first dipole polarization direction, it means that the memory element 630 is in a first memory state (e.g., logic "0"), and conversely, when the ferroelectric material layer 636 has a second dipole polarization direction, it means that the memory element 630 is in a second memory state (e.g., logic "1").

[0076] When a first type of write operation is performed, the source 634A and drain 634B receive a ground voltage or a negative voltage, and the control gate 632 receives a positive voltage (e.g., a threshold voltage). In this way, the ferroelectric material layer 636, surrounded on three sides by the copper-phosphorus alloy layer 633, receives downward (i.e., negative Z-axis) electric fields from multiple directions, such as upward (positive Z-axis), left side (negative X-axis), and right side (positive X-axis), thereby enabling the HfO2 to rapidly generate a downward electric dipole. At this point, the memory element 630 is written to have a first memory state (e.g., logical "0").

[0077] When a type 2 write operation is performed, the source 634A and drain 634B receive a positive voltage (e.g., threshold voltage), and the control gate 632 receives a ground voltage or a negative voltage. In this way, the ferroelectric material layer 636, surrounded on three sides by the copper-phosphorus alloy layer 633, receives upward (i.e., Z-axis direction) electric fields from multiple directions, thereby enabling the HfO2 to rapidly generate an upward electric dipole. At this point, the memory element 630 is written to have a second memory state (e.g., logic "1").

[0078] When a read operation is performed, the control gate 632 receives the ground voltage, the drain 634B receives a positive voltage (e.g., a threshold voltage), and the source 634A receives the ground voltage. When the memory element 630 is written to have a first memory state (i.e., the electric dipole of the ferroelectric material layer 636 is oriented downwards), only a very small current (close to zero current) is generated in the channel. However, when the memory element 630 is written to have a second memory state (i.e., the electric dipole of the ferroelectric material layer 636 is oriented upwards), a large current is generated in the channel. Therefore, the memory state of the memory element 630 can be determined by reading the magnitude of the read channel current.

[0079] Figure 11 shows a schematic diagram of a semiconductor structure 700 according to one embodiment of the present disclosure. The semiconductor structure 700 may further include IGZO (or silicon germanium) in the channels between the source and drain of the transistor structure of the logic element and between the source and drain of the memory element. For example, the transistor M1N' of the logic element 720 may further include a channel 721A disposed in the substrate 610 between the source 621A and the drain 621B, the transistor M1P' may further include a channel 721B disposed in the substrate 610 between the source 621C and the drain 621D, and the memory element 730 may further include a channel 731 disposed in the substrate 610 between the source 634A and the drain 634B. In some embodiments, channels 721A, 721B and 731 are IGZO or silicon germanium, for example, Si (1-x) Ge x (Here, 0 ≤ x ≤ 0.5 may be added.)

[0080] Compared to amorphous silicon, IGZO offers increased carrier concentration and electron mobility, resulting in improved conductivity, which in turn reduces the operating voltage and size of the transistors. Furthermore, the IGZO channel 731 can prevent leakage current in the ferroelectric non-volatile memory cell and improve response speed. In some embodiments, the IGZO channel 731 may be doped with trivalent or pentavalent elements to adjust the threshold voltage as required. In some embodiments, transistors M1N' and M1P' may be designed to be enhancement-mode transistors or depletion-mode transistors, as needed. Effective use of enhancement-mode or depletion-mode transistors can reduce the number of transistors required for logic gates (e.g., NAND gates or NOR gates), thereby reducing the total circuit area required.

[0081] Furthermore, the IGZO channel 731 assists the operation of the memory element 730. For example, when a first type of write operation is performed, the source 634A and drain 634B receive a ground voltage or a negative voltage, and the control gate 632 receives a positive voltage. In this way, the ferroelectric material layer 636, surrounded on three sides by the copper-phosphorus alloy layer 633, receives downward (i.e., opposite Z-axis) electric fields from multiple directions, such as upward (Z-axis direction), left side (opposite X-axis direction), and right side (X-axis direction). As a result, the HfO2 rapidly generates downward electric dipoles, allowing the memory element 730 to be written to a first memory state (e.g., logic "0"). Also, due to the influence of the downward electric dipoles, as a result of the induction of the electric field, electron holes are generated on the upper surface of the IGZO channel 731 near the oxide layer 631, forming an NPN transistor. When a first type write operation is performed, the voltages of source 634A and drain 634B are at ground voltage (or negative voltage), so the junction of the P-well PW2 to source 634A and drain 634B is not forward biased, thereby preventing the holes in the channel from moving and indicating an off state. In this embodiment, such an off state may serve as a basis for determining the data state when a subsequent read operation is performed.

[0082] In contrast, when a second type of write operation is performed, the source 634A and drain 634B receive a positive voltage, and the control gate 632 receives a negative voltage. In this way, the ferroelectric material layer 636, surrounded on three sides by the copper-phosphorus alloy layer 633, receives upward (i.e., Z-axis direction) electric fields from multiple directions, thereby enabling HfO2 to rapidly generate upward electric dipoles, and the memory element 630 is rapidly written to a second memory state (e.g., logic "1"). Furthermore, due to the influence of the upward electric dipoles in the ferroelectric material layer 636 and the induction of electric fields within it, more electrons are generated on the upper surface of the IGZO channel 731 near the oxide layer 631 as a result of the induction of electric fields, thereby causing the IGZO channel 731 to exhibit more ON states. In this embodiment, such ON states may serve as a basis for determining the data state when a subsequent read operation is performed.

[0083] When a read operation is performed, the source 634A receives a ground voltage, the drain 634B receives a positive voltage, and the control gate 632 receives a ground voltage. In this case, when the memory element 730 is written to have a first memory state, the current flowing between the source 634A and the drain 634B is close to zero due to the off state indicated by the IGZO channel 731. In contrast, when the memory element 730 is written to have a second memory state, the current flowing between the source 634A and the drain 634B becomes more significant due to the on state indicated by the IGZO channel 731. In this way, the memory state to be written to the memory element 730 can be determined according to the magnitude of the current flowing between the source 634A and the drain 634B. Furthermore, in this embodiment, since a large electric field is not generated between the control gate 632, source 634A, and drain 634B by the read operation, the direction of the electric dipole of the ferroelectric material layer 636 does not change. In other words, during a read operation, the memory state of the memory element 730 is not changed, regardless of whether it is in the first or second memory state.

[0084] In some embodiments, with appropriate design (for example, by applying electric fields of different sizes), the memory element 730 can support more storage states, and the storage state of the memory element 730 can be further determined according to the magnitude of the read channel current during a read operation. In other words, the memory element 730 may be an MLC capable of storing multiple bits. For example, when the memory element 730 is written to four storage states according to the direction and level of the electric dipole polarization of the ferroelectric material layer 636, the memory element 730 is used to store 2 bits of data.

[0085] High-performance computing often involves numerous memory access operations, generating a large amount of thermal energy. In such cases, heat dissipation is essential to maintain normal system operation. For example, high-bandwidth memory (HBM), commonly used in high-performance computing, urgently requires heat dissipation solutions. Similarly, DRAM, which requires frequent charging and discharging, demands highly sophisticated heat dissipation.

[0086] In such cases, to improve heat dissipation efficiency, the circuit board for mounting the memory may be placed in a cooling gas or coolant. In some embodiments of the present disclosure, the organic solderability preservative (OSP) of the circuit board can be partially removed, allowing the conductive wires to come into direct contact with the cooling gas or coolant, thereby achieving a better heat dissipation effect.

[0087] Figure 12 shows a schematic diagram of a circuit board B1 according to one embodiment of the present disclosure. The circuit board B1 may include a plurality of conductive wire layers, but only the surface conductive wire layer C1 of the circuit board B1 (for example, copper foil formed by electroplating) is shown in Figure 12. The wires in the surface conductive wire layer C1 may be used to connect various electronic components. The surface conductive wire layer C1 is also typically coated with OSP P1, i.e., so-called green paint. OSP P1 reduces oxidation of the conductive wires in the surface conductive wire layer C1 and can prevent the conductive wires in the surface conductive wire layer C1 from being damaged during test operation or from short-circuiting during operation.

[0088] The surface conductive wire layer C1 may include a plurality of solder contacts S1 for soldering to electronic components (e.g., chips). The solder contacts S1 (e.g., pads of an SMT) may be exposed from the OSP P1 to better perform subsequent solder printing for soldering to electronic components. For example, an electronic component including a semiconductor structure 100 may have a plurality of pins, and the plurality of pins of the electronic component may be soldered to the corresponding solder contacts S1. In this embodiment, in addition to exposing the solder contacts S1 from the OSP P1, the OSP P1 on a portion of the conductive wires of the surface liner layer C1 may be removed. In this way, when the circuit board B1 operates in a cooling gas or is immersed in a coolant, at least a portion of the conductive wires of the surface conductive wire layer C1 can come into direct contact with the cooling gas or coolant, thereby improving heat dissipation. In some embodiments, the portion of conductive wires exposed from the OSP P1 may include, for example, a ground wire G1 for analog signals, a ground wire G2 for digital signals, and a ground wire G3 for power supplies. In some embodiments, the three grounding wires G1, G2, and G3 may be connected to each other within a grounding layer (not shown). These grounding wires are generally thicker, wider, and longer, which can further improve heat dissipation. Furthermore, since these grounding wires G1, G2, and G3 have zero voltage, their impact on the overall system safety is minimized.

[0089] Furthermore, in the semiconductor structures 100 to 700 of the embodiments of this disclosure, the conductive wires connecting the logic elements and memory elements are covered with a copper-phosphorus alloy, thereby reducing the occurrence of oxidation and corrosion of the conductive wires under high-temperature conditions. Similarly, to reduce the occurrence of oxidation of conductive wires under high-temperature conditions and oxidation and corrosion in air or liquid operating environments, the conductive wires of the circuit board B1 may also be covered with a copper-phosphorus alloy.

[0090] In short, the semiconductor structures provided by embodiments of this disclosure enable the integration of logic elements and memory elements on the same chip using the same manufacturing process, thereby reducing manufacturing time and cost, and shortening the time required to access the memory. Furthermore, methods for improving the overall heat dissipation performance of the PCB are incorporated, thereby facilitating the development of high-performance computing.

[0091] The characteristics of various embodiments are described above so that those skilled in the art may better understand the aspects of this disclosure. Those skilled in the art will readily use the details of this disclosure as a basis for designing or modifying other operations and structures to accomplish the same objectives or achieve the same advantages as the embodiments. Those skilled in the art should understand that these equivalent solutions may be modified, substituted, replaced, and altered in various ways without departing from the spirit or scope of this disclosure.

[0092] Furthermore, the scope of this disclosure is not limited to specific embodiments of the processes, machines, manufactured products, material compositions, means, methods, and steps described in the detailed description. Those skilled in the art will understand from this disclosure that existing or future-developed processes, machines, manufactured products, material compositions, means, methods, or steps that perform the same functions as or achieve substantially the same results as the corresponding embodiments described herein can be used in accordance with this disclosure. Accordingly, such processes, machines, manufactured products, material compositions, apparatus, methods, or steps are included in the appended claims.

Claims

1. A substrate having a first region and a second region laterally adjacent to the first region, A logic element comprising a plurality of transistors is arranged in the first region of the substrate, A memory element arranged in the second region of the substrate, A lower electrode is disposed above the substrate, comprising a first metal layer and a first copper-phosphorus alloy layer extending along the contour of the first metal layer and surrounding the first metal layer, The upper electrode is positioned above the substrate and the lower electrode, and includes a second metal layer and a second copper-phosphorus alloy layer extending along the contour of the second metal layer and surrounding the second metal layer. A memory element including a dielectric layer disposed between the upper electrode and the lower electrode, A semiconductor structure that integrates logic elements and memory elements, including [the specified element].

2. The semiconductor structure according to claim 1, wherein the memory element is a memory cell of a dynamic random access memory (DRAM).

3. The semiconductor structure according to claim 1, wherein the first metal layer has a comb-like structure including a plurality of first protrusions, and the second metal layer has a comb-like structure including a plurality of second protrusions.

4. The semiconductor structure according to claim 3, wherein the plurality of first protrusions extend toward the upper electrode, the plurality of second protrusions extend toward the lower electrode, and the plurality of first protrusions and the plurality of second protrusions are staggered.

5. The semiconductor structure according to claim 1, wherein the lower electrode further includes a first barrier layer that surrounds the first copper-phosphorus alloy layer along the contour of the first copper-phosphorus alloy layer.

6. The semiconductor structure according to claim 1, wherein the upper electrode further includes a second barrier layer that surrounds the second copper-phosphorus alloy layer along the contour of the second copper-phosphorus alloy layer.

7. The semiconductor structure according to claim 1, wherein the first transistor among the plurality of transistors is adjacent to the second region, and the upper electrode is electrically connected to the drain of the first transistor.

8. The semiconductor structure according to claim 7, further comprising a first conductive plug located on the substrate and in contact with the drain of the first transistor, wherein the upper electrode of the memory element covers the first conductive plug along the vertical direction.

9. The dielectric layer is a photoresist material, hafnium oxide (HfO ２ The semiconductor structure according to claim 1, manufactured from a material containing ) or other high dielectric constant materials.

10. The semiconductor structure according to claim 1, wherein the plurality of transistors include at least one of gate-all-around field-effect transistors (GAAFETs), multibridge channel FETs, multilayer nanosheet FETs, fin FETs, or complementary FETs (CFETs).

11. The semiconductor structure according to claim 1, wherein the channel of the logic element comprises indium gallium zinc oxide (IGZO) or silicon germanium.

12. A circuit board comprising multiple conductive wire layers, wherein the surface conductive wire layer among the multiple conductive wire layers comprises multiple solder contacts, An electronic component comprising a semiconductor structure according to claim 1 and a plurality of pins, wherein the plurality of pins are soldered to a plurality of corresponding solder contacts among the plurality of solder contacts, The film comprises an organic solderable preservative (OSP) film that coats the surface conductive wire layer, An electronic device wherein the circuit board is immersed in a cooling fluid or operates in a cooling gas, and the OSP film does not cover any of the solder contacts or at least some of the conductive wires in the surface conductive wire layer so that at least some of the conductive wires are in direct contact with the cooling fluid or the cooling gas.

13. The electronic device according to claim 12, wherein at least some of the conductive wires include a ground wire.

14. A substrate having a first region and a second region laterally adjacent to the first region, A logic element comprising a plurality of transistors is arranged in the first region of the substrate, A memory element arranged in the second region of the substrate, Source and drain located on the substrate, A first oxide layer disposed on the substrate between the source and the drain, A control gate disposed in the first oxide layer, A first copper-phosphorus alloy layer is disposed between the first oxide layer and the control gate, A semiconductor structure that includes a memory element and integrates a logic element and a memory element.

15. The memory element is a memory cell of an electrically erasable programmable read-only memory (EEPROM), and the memory element is A charge storage layer disposed in the first oxide layer and the first copper-phosphorus alloy layer, A second copper-phosphorus alloy layer is disposed in the charge storage layer, The semiconductor structure according to claim 14, further comprising: a second oxide layer disposed between the control gate and the charge storage layer, wherein the first copper-phosphorus alloy layer is disposed between the first oxide layer and the charge storage layer, and the second copper-phosphorus alloy layer is disposed between the second oxide layer and the charge storage layer.

16. The semiconductor structure according to claim 15, wherein the first copper-phosphorus alloy layer has a plurality of first protruding structures facing the second copper-phosphorus alloy layer, and the second copper-phosphorus alloy layer has a plurality of second protruding structures facing the first copper-phosphorus alloy layer.

17. The semiconductor structure according to claim 16, wherein the plurality of first protrusion structures and the plurality of second protrusion structures are staggered.

18. The charge storage layer is made of silicon nitride (SiN), hafnium aluminum oxide (HaAlO), and hafnium oxide (HfO ２ ), aluminum oxide (Al ２ O ３ The semiconductor structure according to claim 15, manufactured from a material comprising ) or a combination thereof.

19. The control gate is The gate electrode layer, A barrier layer is disposed between the gate electrode layer and the first oxide layer, and surrounds the bottom and side walls of the gate electrode layer. The semiconductor structure according to claim 15, further comprising a third copper-phosphorus alloy layer disposed between the gate electrode layer and the barrier layer.

20. The semiconductor structure according to claim 15, wherein the substrate has a plurality of fin structures, and the source and drain of the memory element are located at two opposite ends of the first fin structure among the plurality of fin structures.

21. The semiconductor structure according to claim 20, wherein the first oxide layer, the first copper-phosphorus alloy layer, the charge storage layer, the second copper-phosphorus alloy layer, the second oxide layer, and the control gate are sequentially stacked on the first fin structure, surrounding the top and side walls of the first fin structure.

22. The memory element is a memory cell of a ferroelectric memory, and the memory element is The material includes a ferroelectric material layer disposed between the first copper-phosphorus alloy layer and the first oxide layer, The ferroelectric material layer includes an array formed by a plurality of protruding structures, and the first copper-phosphorus alloy layer fills the gaps around the ferroelectric material layer, or The semiconductor structure according to claim 14, wherein the ferroelectric material layer and the first copper-phosphorus alloy layer are two planar structures with uniform thickness and sequentially stacked.

23. The ferroelectric material layer is made of hafnium oxide (HfO ２ The semiconductor structure according to claim 22, manufactured from a material containing ).

24. The semiconductor structure according to claim 22, wherein the thickness of the first oxide layer is 1 nm to 5 nm, and the thickness of the ferroelectric material layer is 5 nm to 15 nm.

25. The semiconductor structure according to claim 14, wherein the channels of the logic element and the memory element include indium gallium zinc oxide (IGZO) or silicon germanium.

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