Multiplex conversion gain design for CMOS image sensors

Abstract

This invention generally relates to increasing the dynamic range of an image sensor. [Solution] An image sensor having a quad-pixel structure has a quad-pixel circuit that includes four photodetector pixel circuits and a bridge circuit. The bridge circuit selectively couples the floating diffuse nodes corresponding to the four photodetector pixels, allowing the four photodetector pixel circuits to operate selectively in either quad-pixel mode, dual-pixel mode, or single-pixel mode. Each of the photodetector pixel circuits may include a multiplexing gain circuit to provide a wide dynamic range.

Description

[Technical Field]

[0001] This invention generally relates to image sensors. [Background technology]

[0002] Many modern electronic devices (e.g., digital cameras, optical imaging devices) include an image sensor. An image sensor contains an array of photosensitive structures that convert light into electrical charges. Examples of image sensors include charge-coupled device (CCD) image sensors and complementary metal-oxide-semiconductor (CMOS) image sensors. Compared to CCD image sensors, CMOS image sensors are preferred due to their low power consumption, small size, high-speed data processing, direct data output, and lower manufacturing costs. [Overview of the project] [Problems that the invention aims to solve]

[0003] This invention generally relates to increasing the dynamic range of an image sensor. [Means for solving the problem]

[0004] An embodiment of the present invention provides an image sensor comprising a photodiode in a first array within a first semiconductor substrate, a quad pixel circuit, and a bridge circuit. The quad pixel circuit comprises four photodiodes in a 2x2 subarray, four transfer gates, four floating-diffuse regions, and four source followers. The bridge circuit selectively couples the four floating-diffuse regions.

[0005] In an embodiment of the present invention, an image sensor includes a semiconductor substrate, a first photodetector, a second photodetector, a third photodetector, and a fourth photodetector, and a first switch transistor, a second switch transistor, and a third switch transistor. The first photodetector to the fourth photodetector each include a first photodiode to a fourth photodiode, a first transfer gate to a fourth transfer gate, and a first floating diffusion node to a fourth floating diffusion node. The first transistor has a pair of source / drain regions electrically coupled to the first floating diffusion node and the second floating diffusion node, respectively. The second transistor has a pair of source / drain regions electrically coupled to the third floating diffusion node and the fourth floating diffusion node, respectively. The third transistor has a pair of source / drain regions electrically coupled to the first floating diffusion node and the third floating diffusion node, respectively.

[0006] In an embodiment of the present invention, a first chip including a first semiconductor substrate, and four photodetector pixel circuits each including a photodiode, a transfer gate, a floating diffusion node, a source follower, a dual conversion gain transistor, and a lateral overflow integrated capacitor (LOFIC). The photodiode is within the first semiconductor substrate. The photodiodes of the four photodetector pixel circuits are under color filters. The image sensor further includes a bridge circuit that selectively couples the four floating diffusion nodes.

Advantages of the Invention

[0007] Based on the above, a bridge circuit coupled to the floating diffusion node of the image sensor is provided. The bridge circuit enables the four photodetector pixel circuits to selectively operate in different pixel modes. In this way, the dynamic range of the image sensor can be increased.

Brief Description of the Drawings

[0008] Aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. In accordance with standard industry practice, features are not depicted to scale. Furthermore, dimensions of various features within individual drawings may be arbitrarily increased or decreased relative to one another to facilitate illustration or to provide emphasis.

[0009] [Figure 1] This is a circuit diagram illustrating a quad-pixel circuit for an image sensor according to various embodiments of the present invention. [Figure 1A] This is a circuit diagram illustrating a quad-pixel circuit for an image sensor according to various embodiments of the present invention. [Figure 2] This is a circuit diagram illustrating a quad-pixel circuit for an image sensor according to various embodiments of the present invention. [Figure 3] This is a circuit diagram illustrating a quad-pixel circuit for an image sensor according to various embodiments of the present invention. [Figure 4] This is a circuit diagram illustrating a quad-pixel circuit for an image sensor according to various embodiments of the present invention. [Figure 5] This chart illustrates the operation of a triple-conversion gain circuit according to several embodiments. [Figure 6A] This is a circuit diagram of a multiplex conversion gain circuit according to various embodiments. [Figure 6B] This is a circuit diagram of a multiplex conversion gain circuit according to various embodiments. [Figure 7] Cross-sectional views of image sensors corresponding to several embodiments are shown. [Figure 8] The diagram illustrates the mapping of data for forming an image from an image sensor according to several embodiments. [Figure 9] This is a circuit diagram illustrating the distribution of image sensor components between device layers that correspond to various embodiments. [Figure 10] This is a circuit diagram illustrating the distribution of image sensor components between device layers that correspond to various embodiments. [Figure 11]This is a circuit diagram illustrating the distribution of image sensor components between device layers that correspond to various embodiments. [Figure 12] This is a circuit diagram illustrating the distribution of image sensor components between device layers that correspond to various embodiments. [Figure 13] This is a circuit diagram illustrating the distribution of image sensor components between device layers that correspond to various embodiments. [Figure 14] This is a circuit diagram illustrating the distribution of image sensor components between device layers that correspond to various embodiments. [Figure 15] A plan view of a quad pixel group corresponding to the embodiment is shown. [Figure 16] This is a cross-sectional view illustrating an embodiment of a manufacturing process according to the present invention. [Figure 17] This is a cross-sectional view illustrating an embodiment of a manufacturing process according to the present invention. [Figure 18] This is a cross-sectional view illustrating an embodiment of a manufacturing process according to the present invention. [Figure 19] This is a cross-sectional view illustrating an embodiment of a manufacturing process according to the present invention. [Figure 20] This is a cross-sectional view illustrating an embodiment of a manufacturing process according to the present invention. [Figure 21] This is a cross-sectional view illustrating an embodiment of a manufacturing process according to the present invention. [Figure 22] This is a cross-sectional view illustrating an embodiment of a manufacturing process according to the present invention. [Figure 23] This is a flowchart of a manufacturing process according to several embodiments of the present invention. [Figure 24] This is a flowchart illustrating an embodiment of a method for operating a quad pixel group. [Figure 25] This is a flowchart illustrating the reset operation of an image sensor according to several embodiments. [Figure 26] This is a flowchart illustrating the readout operation of an image sensor according to several embodiments. [Figure 27]This is a flowchart illustrating the readout operation of an image sensor according to several embodiments. [Modes for carrying out the invention]

[0010] The present invention provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and arrangements are described below for the sake of brevity of the invention. These are, of course, merely examples and are not intended to limit the invention. For example, forming a first feature on or above a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, or it may include embodiments in which an additional feature is formed between the first and second features so that the first and second features are not in direct contact.

[0011] Spatial relative terms such as “downward,” “below,” “lower,” “upward,” and “top” may be used herein to describe the relationship of one element or feature to another, as illustrated in the figures. These spatial relative terms are intended to encompass different orientations of a device or apparatus in use or operation, in addition to the orientation depicted in the figures. The device or apparatus may have other orientations (90-degree rotation or other orientations), and the spatial relative descriptors used herein may be interpreted accordingly. Terms such as “first,” “second,” “third,” and “fourth” are merely general identifiers and may therefore be interchangeable in different embodiments. For example, an element (e.g., an opening) may be referred to as the “first” element in some embodiments, while that element may be referred to as the “second” element in other embodiments.

[0012] A type of CMOS image sensor has an array of photodetectors, each photodetector containing a photosensitive region, a transfer gate, a floating-diffuse node, a source follower, a row selection transistor, and a reset transistor within a semiconductor substrate. When the reset transistor is closed, the floating-diffuse node is brought to a reference voltage. The photosensitive region is part of a photodiode or other photodetector structure that converts light into electric charge. Upon light exposure, charge accumulates in the photodiode or other photodetector structure until the transfer gate is closed, after which the charge flows to the floating-diffuse node. The charge changes the floating-diffuse node voltage. The floating-diffuse node voltage is applied to the gate electrode of the source follower. When the corresponding row selection transistor is closed, current flows through the source follower at a rate dependent on the floating-diffuse node voltage. The current is detected and used to estimate the amount of charge transferred to the floating-diffuse node, which sequentially reflects the amount of radiation incident on the photosensitive region over the sampling interval.

[0013] Conversion gain is an important parameter for the type of CMOS image sensor described earlier. Conversion gain is related to the capacitance of the stray-diffusion node. If the conversion gain is too high, the photodetector pixel circuit may saturate, making it impossible to distinguish between light intensity levels. If the conversion gain is too low, noise becomes excessive compared to the signal, and variations in light intensity at lower light intensity levels are lost. Low conversion gain is generally desirable for high levels of illumination. High conversion gain is generally desirable for low levels of illumination. The range between the minimum and maximum illumination levels in which a CMOS image sensor is effective is its dynamic range. The dynamic range depends on the stray-diffusion node capacitance.

[0014] The dynamic range can be increased by adding a dual conversion gain circuit to the photodetector pixel circuit. The dual conversion gain circuit allows for higher light intensity levels by selectively adding capacitance to the stray-diffuse node. The source of capacitance may be a lateral overflow integrated capacitor (LOFIC). In high conversion gain mode, the dual conversion gain circuit adds additional capacitance to the stray-diffuse node, reducing the conversion gain. In low conversion gain mode, the dual conversion gain circuit isolates the additional capacitance from the stray-diffuse node. Dual conversion gain primarily corresponds to higher light intensity levels. The concept of dual conversion gain can be generalized to include other multiple conversion gain circuits, such as a triple conversion gain circuit, which allows selection between three possible capacitance levels.

[0015] One approach to extend the dynamic range to accommodate lower light intensity levels is to use a quad-pixel structure. In a quad-pixel structure, a 2x2 subarray of adjacent photodetector pixels is placed beneath each color filter in a color filter / microlens array. At high light intensity levels, the four photodetector pixels operate independently, providing a high-resolution image. At lower light intensity levels, the four photodetector pixels are combined into a single pixel, providing a quarter-resolution image with relatively low noise.

[0016] One way to enable the combination of data from four adjacent photodetector pixels is to have them share a single floating-diffuse node. Four different transfer gates selectively transfer charge from each photodiode to the floating-diffuse node. In high-resolution mode, the photodetector pixels are read sequentially, and the floating-diffuse node is reset between each readout operation. In low-resolution mode, charge from all four photodiodes is transferred to the floating-diffuse node for each readout operation. A drawback of this approach is that reset time becomes a limiting factor, especially in high-resolution mode where pixels are read sequentially, and in low-conversion-gain mode where LOFIC adds additional capacitance to the photodetector pixel circuit.

[0017] Another approach to combining data from four adjacent photodetector pixels is to combine their readings. The photodetector pixels are read by column decoders, and the signals from these column decoders are combined during signal processing. The drawback of this approach is that each read operation introduces noise. When the outputs of four read operations are combined, the resulting data point has four read noise contributions. The four read noise contributions work against the intended benefit of combining the four signals, which is noise reduction. Another disadvantage of combining signals is that four separate read operations are performed to provide each data point, which increases read time.

[0018] According to the present invention, the aforementioned problem is solved by a bridge circuit that selectively couples floating diffusion nodes corresponding to photodetector pixels in a quad-pixel circuit. The quad-pixel circuit includes four photodetector pixel circuits, each of which may include a multiplexing gain circuit. The bridge circuit allows these four photodetector pixel circuits to operate selectively in either quad-pixel mode, dual-pixel mode, or single-pixel mode.

[0019] In single-pixel mode, the bridge circuit separates and holds the four stray-spread nodes of the four photodetector pixel circuits, allowing each photodetector pixel circuit to operate independently of the others. The multiplexing gain circuit operates to vary the capacitance of the stray-spread nodes, so that each photodetector pixel can be in either a high-conversion-gain mode, a low-conversion-gain mode, or some intermediate-conversion-gain mode. In some embodiments, the multiplexing gain circuit is a dual-conversion-gain circuit. In some embodiments, the multiplexing gain circuit is a triple-conversion-gain circuit that can operate to selectively provide either a high, medium, or low-conversion-gain mode by adding a first additional capacitance or both the first and second additional capacitances to the stray-spread mode. Single-pixel mode provides high-resolution images and is suitable for high levels of light and low levels of light where low sampling rates are acceptable.

[0020] In dual-pixel mode, the bridge circuit couples the four stray-spread nodes of the four photodetector pixel circuits into two pairs, causing the four photodetector pixel circuits to operate as two photodetector pixel circuits. A transfer gate operates to mix the charge stored by the photodiodes of the paired photodetector pixels within the coupled stray-spread nodes. The voltage on the coupled stray-spread nodes can be read through one or both of the source followers associated with the coupled photodetector pixel circuits. In either case, a single readout operation provides data from a pair of photodiodes, resulting in lower noise compared to adding the outputs of two separate readout operations. Dual-pixel mode provides an intermediate level of resolution. Dual-pixel mode can be combined with any of the high, intermediate, or low conversion gain modes. All multiplex conversion gain circuits may utilize the same conversion gain switching signal. In some embodiments, some of the multiplexing gain circuits have independent mode-switching signals and additional capacitances from zero, one, or two multiplexing gain circuits can be selectively added to each of the coupled floating-spread nodes to provide a wide range of conversion gain modes.

[0021] In quad-pixel mode, the bridge circuit combines the four stray-spread nodes of four photodetector pixel circuits, causing the four photodetector pixel circuits to operate as a single combined photodetector pixel circuit. A transfer gate is operated to mix the charges accumulated by the four adjacent photodiodes within the single combined stray-spread node. The voltage on the combined stray-spread node can be read through one or more of the four source followers associated with the four photodetector pixel circuits in the quad-pixel circuit. A single readout operation can provide data from all four photodiodes, resulting in lower noise compared to summing the outputs of four separate readout operations. Quad-pixel mode can be combined with any of the high, intermediate, or low conversion gain modes. Optionally, the multiplexing conversion gain circuits have independent mode-switching signals, and additional capacitance from zero, one, two, three, or all of the multiplexing conversion gain circuits can be selectively added to the combined stray-spread node to reduce the conversion gain in quad-pixel mode. Quad-pixel mode offers one-quarter the resolution compared to single-pixel mode. Lower-resolution images may be more accurate and require less memory than equivalent full-resolution images taken under the same lighting conditions.

[0022] The bridge circuit may include transistors or other switching structures. In some embodiments, the bridge circuit includes three transistors. The bridge circuit includes two transistors for coupling the floating diffusion nodes of two adjacent pairs of photodetector pixels and a third transistor for coupling two adjacent pairs. In some embodiments, the bridge circuit includes a fourth transistor for maintaining equivalence between photodetector pixels and simplifying manufacturing. The transistors may be NMOS transistors, PMOS transistors, or other types of transistors.

[0023] Another important performance parameter for CMOS image sensors is resolution. High resolution is achieved by high pixel density. The area occupied by transistors in the photodetector pixel circuit can limit pixel density. One approach to overcome this limitation is to use two or three device layers. The first part of the photodetector pixel circuit, including the photodiode and transfer gate, is located on the first device layer. The second part of the photodetector pixel circuit is located on the second device layer. The application-specific integrated circuit (ASIC) may be located in the peripheral area of ​​the second device layer or on the third device layer.

[0024] The photodetector pixel circuit components on the second device layer may include one or more of the following: row selection transistors, reset transistors, multiplex conversion gain circuits (which may include reset transistors), and source followers. In some embodiments, the bridge circuit is located on the second device layer. In some other embodiments, the bridge circuit is located on the first device layer. Having the bridge circuit on the first device layer can reduce the capacitance of the stray-spread nodes and increase the conversion gain. In some embodiments, the source followers are located on the first device layer along with the bridge circuit, while several other components of the quad pixel circuit are located on the second device layer. This latter configuration can provide a high conversion gain mode in which the stray-spread nodes do not contribute to the capacitance from the wiring extending from the first device layer to the second device layer.

[0025] Unlike conventional quad-pixel structures that have a single shared stray-diffusion node, the quad-pixel structure according to the present invention allows for the existence of a separate multiplexing gain circuit with a separate LOFIC for each photodetector pixel circuit. As pixel density increases, it can become difficult to package a very large number of LOFICs. In some embodiments, this problem is solved by placing the LOFICs on the first device layer along with the photodiodes and transfer gates, while other components of the photodetector pixel circuit are placed on the second device layer. In some embodiments, this problem is solved by placing the LOFICs on the third device layer along with the ASIC.

[0026] Figure 1 is a schematic diagram 100 of a portion of the image sensor including a quad pixel circuit 105. The quad pixel circuit 105 includes four photodetector pixel circuits 101A to 101D and a bridge circuit 107. Each of the photodetector pixel circuits 101A to 101D includes a photodiode PD, a stray-spread node FD, a transfer gate TX, a source follower SF, and a row selection transistor RSL. The photodetector pixel circuits 101A to 101D may further include a reset transistor or a dual conversion gain circuit (not shown).

[0027] The bridge circuit 107 is connected to four floating-diffusion nodes FD and includes circuits for selectively coupling and uncoupling the four floating-diffusion nodes FD to implement various modes. These may include a 1C mode in which the four floating-diffusion nodes FD are uncoupled, a 2C mode in which the floating-diffusion nodes FD of photodetector pixel circuits 101A and 101C are coupled and the floating-diffusion nodes FD of photodetector pixel circuits 101B and 101D are coupled, and a 4C mode in which all four floating-diffusion nodes FD are coupled.

[0028] The row selection transistors RSL of the photodetector pixel circuits 101A and 101C are coupled to the column wiring 103A. The row selection transistors RSL of the photodetector pixel circuits 101B and 101D are coupled to the column wiring 103B. The column wirings 103A and 103B are a wiring structure connected to a column decoder (not shown). One column decoder may exist for each column in the photodetector array.

[0029] The transfer gate TX is selectively activated by the transfer gate signals V TX-A ~V TX-D The transfer gate signals V TX-A ~V TX-D may be independent. The source follower SF is selectively activated by the row selection signals V RS-A and V RS-B The row selection signals V RS-A and V RS-B are each provided by a separate row driver (not shown). In the 1C mode, the row selection signals V RS-A and V RS-B operate in series for each read operation. In the 2C and 4C modes, only one of the row selection signals V RS-A and V RS-B is used for the read operation.

[0030] FIG. 1A is a circuit diagram 110 of a part of an image sensor including the quad pixel circuit 105A. The quad pixel circuit 105A is the same as the quad pixel circuit 105 in FIG. 1, except that all four row selection transistors RSL are coupled to the column wiring 103A. This configuration enables the use of fewer column wirings and can improve the conversion gain by reducing the parasitic capacitance. However, the configuration of FIG. 1A has a trade-off in that it involves the use of four separate row selection signals V RS_A ~V RS_D The configuration of FIG. 1 has the advantage of being able to acquire an image with half the number of sequentially executed row driver operations compared to the configuration of FIG. 1A.

[0031] Figure 2 is a circuit diagram 200 showing the quad pixel circuit 105 when the bridge circuit 107 is realized by the bridge circuit 107A. The bridge circuit 107A receives two control signals V SW1 and V SW2 Includes four switch transistors 201A-201D which may be operated through control signal V. SW1 and V SW2 Setting both to low opens all four switch transistors 201A~201D, implementing 1C mode. Control signal V SW1 Set the control signal V to low. SW2 Setting this to high means closing switch transistors 201B and 201C while keeping switch transistors 201A and 201D open, thereby implementing 2C mode. Control signal V SW1 and V SW2 Setting both to high closes all four switch transistors 201A-201D, implementing 4C mode.

[0032] Figure 3 is a schematic diagram 300 showing the quad pixel circuit 105 when the bridge circuit 107 is implemented by the bridge circuit 107B. The bridge circuit 107B is similar to the bridge circuit 107A in Figure 2, except that it lacks the switch transistor 201D. Removing the switch transistor 201D may simplify the circuit and allow for a reduction in the capacitance of the stray diffusion node FD. Retaining the switch transistor 201D simplifies manufacturing and simplifies maintaining equal capacitance between the four stray diffusion node FDs in the quad pixel circuit 105.

[0033] Figure 4 is a circuit diagram 400 of the quad pixel circuit 405. The quad pixel circuit 405 is the same as the quad pixel circuit 105 in Figure 1, except that the quad pixel circuit 405 has photodetector pixel circuits 401A to 401D instead of photodetector pixel circuits 101A to 101D. The photodetector pixel circuits 401A to 401D have the components of the photodetector pixel circuits 101A to 101D, but each also includes triple conversion gain circuits 409A to 409D.

[0034] The triple conversion gain circuits 409A to 409D may each include a first conversion gain transistor CG1, a second conversion gain transistor CG2, a reset transistor RST, a capacitor control transistor CC, and LOFIC, respectively. The reset transistor RST controls the reset control signal V RT_A ~V RT_D It operates through the capacitor-controlled transistor CC. The capacitor control signal V CC_A ~V CC_D The first conversion gain transistor CG1 and the second conversion gain transistor CG2 are operated via a conversion gain control signal V to implement one of the low, medium, or high conversion gain modes. CG1_A ~V CG1_D and V CG2_A ~V CG2_D It operates through this process.

[0035] Figure 5 is a chart 500 illustrating the operation of the triple conversion gain circuit 409A. Triple conversion gain circuits 409B to 409D may operate in a similar manner. In reset operation, the reset control signal V RT_A and conversion gain control signal V CG1_A and V CG2_A This sets all of the first conversion gain transistor CG1, the second conversion gain transistor CG2, and the reset transistor RST to high so that they are all closed. This causes the floating diffusion node FD to V dd It is set to this, and LOFIC discharges.

[0036] To enter the low conversion gain mode, the conversion gain control signal V CG1_A and V CG2_A While the reset control signal V remains high, RT_A This is set to low. As a result, the floating-diffusion node FD enters a floating state, including the first conversion gain transistor CG1, the second conversion gain transistor CG2, and the capacitance of LOFIC. This state may be maintained until the next read operation involving the floating-diffusion node FD, after which a reset operation may be repeated.

[0037] To enter the intermediate conversion gain mode, the conversion gain control signal V CG1_A While the reset control signal V remains high, RT_A and conversion gain control signal V CG2_A This is set to low. As a result, the stray diffusion node FD includes the capacitance of the source / drain region 411 (see Figure 4) and other capacitances associated with the first conversion gain transistor CG1, but does not include the capacitance of LOFIC. The source / drain region 411 may have a larger or heavier doping than any of the source / drain regions that are always coupled to the stray diffusion node FD, such as the drain region of the transfer gate TX (also called the stray diffusion region), the source region of the first conversion gain transistor CG1, and the source / drain region associated with the bridge circuit 107 (see Figure 4). These other source / drain regions may have the lightest doping to provide functionality and may be kept small in order to keep the capacitance of the stray diffusion node FD low in the high conversion gain mode. On the other hand, the capacitance of the source / drain region 411 may be the same as or greater than all of these other source / drain regions in order to provide a substantial increase in the capacitance of the stray diffusion node FD in the transition from the high conversion gain mode to the medium conversion gain mode. In some embodiments, the capacity of the floating diffusion node FD is at least doubled by adding a source / drain region 411 to the floating diffusion node FD.

[0038] To enter high conversion gain mode, the conversion gain control signal V CG1_A and V CG2_A The reset control signal VRT_A This is set to low. As a result, the floating diffusion node FD becomes floating and is isolated from the source / drain region 411 and the LOFIC capacity. This state may be maintained until the next read operation, after which the reset operation may be repeated again.

[0039] The low, medium, and high conversion gain modes may be used in conjunction with any of the 1C, 2C, or 4C modes. In 4C mode, the reset operations of the four photodetector pixel circuits 401A to 401D may be performed simultaneously. In 1C mode, the reset operations of the four photodetector pixel circuits 401A to 401D may be performed asynchronously. In 4C mode, the transfer gates TX may be opened simultaneously to initiate the read operation. Synchronous operation improves the read operation speed. In 1C mode, the transfer gates TX may be opened asynchronously. Asynchronous operation allows the column wirings 403A and 403B (see Figure 4) to be shared between the photodiodes PD in the quad pixel circuit 405.

[0040] Figures 6A to 6B provide circuit diagrams 600A to 600B of multiplex conversion gain circuits 409E to 409F according to various other embodiments. Multiplex conversion gain circuit 409E is one of the alternatives to the triple conversion gain circuits 409A to 409D in the example of Figure 4. In the multiplex conversion gain circuit 409E of Figure 6A, the capacitor-controlled transistor CC (see Figure 4) is V dd It has been replaced with a direct connection to V ref1 It is connected to ground, rather than to the first conversion gain transistor CG1 in the triple conversion gain circuit 409F of Figure 6B, so the illustrated circuit is simplified to a dual conversion gain circuit that provides only a low conversion gain mode and a high conversion gain mode. In some embodiments, V ref1 is V dd In some embodiments, V ref1 V is ground. In some embodiments, V ref1 This is a negative power supply voltage (V dd(and the polarity is opposite). In some embodiments, V ref1 is an undefined floating voltage. Each of these options provides slightly different operation for the corresponding multiplexing gain circuit, and one of these options may provide the best performance for a particular application. A capacitor-controlled transistor CC may be used to further tune the operation of these multiplexing gain circuits, if provided.

[0041] Figure 7 illustrates cross-sectional views of an image sensor 700 according to several embodiments. The image sensor 700 is an integrated circuit (IC) device and may be a 3D IC in which a first chip 783, a second chip 779, and a third chip 775 are stacked, bonded, and interconnected. The first chip 783 includes a first semiconductor substrate 739 and a first metal interconnect structure 743. The second chip 779 includes a second semiconductor substrate 751 and a second metal interconnect structure 747. The third chip 775 includes a third semiconductor substrate 763 and a third metal interconnect structure 759.

[0042] The photodiodes 711 in the first array 723 are located within the first semiconductor substrate 739. Deep groove isolation (DTI) structures 715 provide electrical isolation between adjacent photodiodes 711. Microlenses 701 and color filters 709 are located within the second array 719, which is above the first array 723. A back metal grid 705 provides optical isolation between adjacent color filters 709. Since the second array 719 has one-quarter the number density of the first array 723, there are four photodiodes 711 for each color filter 709. The four photodiodes 711 below each color filter 709 form a 2x2 subarray within the quad-pixel circuit. The quad-pixel circuit may correspond to the quad-pixel circuit 105 in Figure 1 or any other quad-pixel circuit provided by the present invention.

[0043] Figure 8 illustrates the formation of an image from a quad-pixel structure, such as that used in the image sensor 700 in Figure 7, in 1C and 4C modes. As shown in Figure 8, the color filter 709 may be green (G), red (R), and blue (B) and arranged in a Bayer pattern. In 4C mode, image data from the photodiode 711 is mapped to match the color filter layout. In 1C mode, image data from the photodiode 711 may be mapped to a Bayer pattern image format corresponding to a higher resolution. Interpolation may be used for pixel positions in the mapped image that are offset from the actual pixel positions having the same color.

[0044] Figure 9 provides a schematic diagram 900 (see Figure 7) illustrating how the components of the photodetector pixel circuit 401A (see Figure 4), the components of the bridge circuit 107 (represented by the switch transistor 201A), and the application-specific integrated circuit (ASIC) are distributed within a 3D IC including a first chip 783, a second chip 779, and a third chip 775. As shown in Figure 9, the photodiode PD and transfer gate TX may be located on the first chip 783. Other components of the photodetector pixel circuit 401A (see Figure 4), including the source follower SF, row selection transistor RSL, and triple conversion gain circuit 409A, may be located on the second chip 779, thereby leaving more area on the first chip 783 for the photodiode PD. Components of the bridge circuit 107 (see Figure 4), such as the switch transistor 201A of the bridge circuit 107A (see Figure 2), may also be located on the second chip 779. The floating-diffusion node FD includes several components on the first chip 783, such as the drain region (which may also be called the floating-diffusion region) of the transfer gate TX, several components on the second chip 779, such as the source region of the first conversion gain transistor CG1, and wiring between the first chip 783 and the second chip 779. The ASIC may be located on the third chip 775.

[0045] Figure 10 provides a schematic diagram 1000 illustrating the distribution of components between a first chip 783, a second chip 779, and a third chip 775, corresponding to another embodiment. The distribution of components illustrated by schematic diagram 1000 in Figure 10 differs from the distribution of components illustrated by schematic diagram 900 in Figure 9 in that the LOFIC is located on the third chip 775. This configuration facilitates providing one LOFIC for each photodiode PD. Capacitor-controlled transistors CC, if included, may be kept on the same chip as the LOFIC to reduce wiring.

[0046] Figure 11 provides a schematic diagram 1100 illustrating the distribution of components among the first chip 783, the second chip 779, and the third chip 775, corresponding to another embodiment. The distribution of components illustrated by schematic diagram 1100 in Figure 11 differs from the distribution of components illustrated by schematic diagram 900 in Figure 9 in that the LOFIC is located on the first chip 783. This configuration also facilitates providing one LOFIC for each photodiode PD. The LOFIC is located within the first metal interconnect structure 743 (see Figure 7) and therefore does not reduce the area available for the photodiode PD.

[0047] Figure 12 provides a schematic diagram 1200 illustrating the distribution of components between the first chip 783, the second chip 779, and the third chip 775, corresponding to another embodiment. In the embodiment of Figure 12, the first conversion gain transistor CG1 (or simply the reset transistor if there is no multiplex conversion gain circuit), the source follower SF, and the switch transistor 201A are located on the first chip 783, while the other components of the photodetector pixel circuit 401A (see Figure 4) are located on the second chip 779. In this embodiment, all components that are part of the stray-spread node FD in the high conversion gain mode are located on the first chip 783. The advantage of this configuration is that in the high conversion gain mode, the stray-spread node FD does not have capacitance associated with the wiring extending between the first chip 783 and the second chip 779.

[0048] Figure 13 provides a schematic diagram 1300 illustrating the distribution of components between a first chip 783 and a second chip 779, corresponding to an embodiment suitable for a two-device-layer 3DIC. In the embodiment of Figure 13, all components of the photodetector pixel circuit 401A (see Figure 4) and the bridge circuit 107 (represented by the switch transistor 201A) are located on the first chip 783. The ASIC may be located on the second chip 779.

[0049] Figure 14 provides a schematic diagram 1400 illustrating the distribution of components between the first chip 783 and the second chip 779, which corresponds to another embodiment suitable for a two-device-layer 3DIC. The embodiment in Figure 14 is similar to the embodiment in Figure 13, except that the LOFIC is located on the second chip 779 together with the ASIC.

[0050] Figure 15 provides a plan view 1500 showing a possible transistor layout of a quad pixel circuit on a first chip 783, consistent with the schematic 1300 of Figure 13 and the schematic 1400 of Figure 14. Plan view 1500 illustrates four pixel regions, which are pixel regions 1501A to 1501D. The photodiode PD and source / drain regions have n-type doping. A p-type doped region 1527 provides an isolation structure. A highly concentrated p-type doped region 1511 may be used as a contact to maintain the highly concentrated p-type doped region 1511 at a ground voltage or other fixed bias voltage.

[0051] The wiring structure 1503A connects the source / drain region of the switch transistor 201A to the floating diffusion region 1505B within the pixel region 1501B. The wiring structure 1503A also connects the floating diffusion region 1505B to the gate electrode of the source follower SF within the pixel region 1501B.

[0052] The wiring structure 1503B connects the source / drain region of the switch transistor 201B to the floating diffusion region 1505D within the pixel region 1501D. The wiring structure 1503B also connects the floating diffusion region 1505D to the gate electrode of the source follower SF within the pixel region 1501D.

[0053] The wiring structure 1503C connects the source / drain region of the switch transistor 201D to the floating diffusion region 1505C within the pixel region 1501C. The wiring structure 1503C also connects the floating diffusion region 1505C to the gate electrode of the source follower SF within the pixel region 1501C.

[0054] The wiring structure 1503D connects the source / drain region of the switch transistor 201C to the floating diffusion region 1505A within the pixel region 1501A. The wiring structure 1503D also connects the floating diffusion region 1505A to the gate electrode of the source follower SF within the pixel region 1501A.

[0055] Figures 16-22 illustrate a series of cross-sectional views of the components of an image sensor at various stages of manufacturing according to the process of the present invention. Although Figures 16-22 describe a series of operations, the order of operations may be changed in some cases, and it will be understood that this series of operations is applicable to structures other than those shown. In some embodiments, some of these operations may be omitted entirely or in part. Furthermore, although Figures 16-22 describe a series of operations, it will be understood that the structures shown in Figures 16-22 are not limited to the manufacturing method, but may rather exist independently as structures separated from the method.

[0056] The method may begin with front-end-of-line (FEOL) and back-end-of-line (BEOL) processing for each of the first chip 783, second chip 779, and third chip 775. Although these are referred to as chips, they may also be wafers at this processing stage. Figure 16 illustrates the first chip 783, second chip 779, and third chip 775 after the completion of FEOL and BEOL processing. Up to this point, these three device layers may be processed separately and in any order.

[0057] The first chip 783 includes a photodiode 711 formed in a first semiconductor substrate 739. The semiconductor substrate may be a bulk semiconductor substrate or a semiconductor on an insulator (SOI) substrate. At least the upper part of the semiconductor substrate is semiconductor. The semiconductor may be, for example, silicon (Si), a III-V semiconductor or other binary semiconductor, ternary semiconductor (e.g., AlGaAs), a higher-order semiconductor, or similar. In some embodiments, the semiconductor is or includes silicon (Si). The photodiode 711 may be formed by ion implantation into the first semiconductor substrate 739 during FEOL processing. Additional structures formed during FEOL processing may include, for example, a transfer gate 731, a floating diffusion region 727, and a separation structure 733.

[0058] A first metal interconnect structure 743, including wiring 745 surrounded by interlayer dielectric 749, is formed during BEOL processing. The wiring 745 is arranged in multiple metallized layers. Vias (not shown) connect the wiring 745 between adjacent metallized layers. The wiring and vias in the metal interconnect structure are or may include copper (Cu), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), zirconium (Zi), titanium (Ti), tantalum (Ta), aluminum (Al), conductive carbides, oxides, alloys of these metals, similar materials, or any other suitable conductive material. The wiring and vias may also include a diffusion barrier layer such as titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or similar materials. The interlayer dielectric may include one or more layers of silicon dioxide (SiO2), a low-K dielectric, or an extremely low-K dielectric. A low-K dielectric has a dielectric constant smaller than that of silicon dioxide (SiO2). Examples of low-K dielectrics include carbon-doped silicon dioxide, fluorine-doped silicon dioxide (also called fluorinated silica glass (FSG)), organic polymer low-K dielectrics, and organosilicate glass (OSG), such as porous silicate glass. The metal interconnect structure may also include an etch-stop layer. The etch-stop layer may be aluminum oxide (AlOx), silicon nitride (SiN), silicon carbide (SiC), silicon carbonitride (SiCN), silicon carbide oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), a combination thereof, or similar materials.

[0059] The uppermost layer of the first metal interconnect structure 743 is a bonding layer. The bonding layer includes a contact pad 753 and a dielectric 757. The contact pad 753 may be one of the metals mentioned as suitable for wiring. In some embodiments, the contact pad 753 is a metal suitable for metal-to-metal bonding. In some embodiments, the dielectric 757 is silicon dioxide (SiO2), silicon oxynitride (SiON), similar materials, or other dielectrics suitable for dielectric-to-dielectric bonding.

[0060] The FEOL treatment of the second chip 779 provides a transistor 771. The BEOL treatment provides a second metal interconnect structure 747 including wiring 758 and an interlayer dielectric 760. The uppermost layer of the second metal interconnect structure 747 is a bonding layer. The bonding layer may include contact pads 754 and a bonding dielectric 756.

[0061] The FEOL treatment of the third chip 775 provides the transistor 767 and other components of the ASIC (not shown). The BEOL treatment provides a third metal interconnect structure 759 including wiring 768 and interlayer dielectric 770. The top layer of the third metal interconnect structure 759 is a bonding layer. The bonding layer may include contact pads 764 and bonding dielectric 766.

[0062] A LOFIC (not shown) may be formed during BEOL processing and may be located in any of the first metal interconnect structure 743, the second metal interconnect structure 747, or the third metal interconnect structure 759. In some embodiments, the LOFIC is a metal-insulator-metal capacitor. In some embodiments, the LOFIC is a trench capacitor. In some embodiments, the LOFIC is a metal-oxide-metal capacitor. In some embodiments, the LOFIC includes a comb-shaped metal plate. In some embodiments, the LOFIC is located in the top metallized layer of the metal interconnect structure.

[0063] As shown in the cross-sectional view 1700 of Figure 17, the process may continue by bonding the second chip 779 to the first chip 783. The bonding may be dielectric-to-dielectric bonding between bonding dielectric 756 and bonding dielectric 757, metal-to-metal bonding between contact pad 754 and contact pad 753, or a combination of dielectric-to-dielectric bonding and metal-to-metal bonding. In any case, an electrical connection is formed between contact pad 754 and contact pad 753.

[0064] As shown in the cross-sectional view 1800 of Figure 18, the second semiconductor substrate 751 may be thinned from the back surface. The second semiconductor substrate 751 may be thinned by etching, mechanical grinding, CMP, similar methods, or other suitable processes or groups of processes. In some embodiments, thinning reduces the thickness of the second semiconductor substrate 751 to a range of about 1 μm to about 10 μm. In some embodiments, thinning reduces the thickness of the second semiconductor substrate 751 to about 5 μm or less. In some embodiments, thinning reduces the thickness of the second semiconductor substrate 751 to about 3 μm or less. If the second semiconductor substrate 751 is left too thick, it may not be practical to form a TSV. If the second semiconductor substrate 751 is left too thin, it may be structurally unstable.

[0065] As shown in the cross-sectional view 1900 of Figure 19, the TSV 755 may be formed through the second semiconductor substrate 751. The process may include forming a separation structure on the back surface 1901, etching holes to reach wiring 758 in the second metal interconnect structure 747, lining the holes with a dielectric, performing breakthrough etching to expose the wiring, filling the holes with a conductive material, and planarizing. The conductive material may be doped polysilicon, a metal, or other suitable conductor. If the conductive material is a metal, the metal may be, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), indium (In), nickel (Ni), or similar, or may include these.

[0066] As shown in the cross-sectional view 2000 of Figure 20, a bonding structure may be formed on the back surface 1901. As shown in the cross-sectional view 2100 of Figure 21, the second chip 779 to which the first chip 783 is attached may be bonded to the third chip 775. The bonding may be dielectric-to-dielectric bonding, metal-to-metal bonding, or a combination of dielectric-to-dielectric bonding and metal-to-metal bonding.

[0067] As shown in the cross-sectional view 2200 of Figure 22, the first semiconductor substrate 739 may be thinned from the back surface 2201. The first semiconductor substrate 739 may be thinned by etching, mechanical grinding, CMP, similar methods, or other suitable processes or groups of processes. In some embodiments, thinning reduces the thickness of the second semiconductor substrate 751 to a range of about 1 μm to about 10 μm. In some embodiments, thinning reduces the thickness of the first semiconductor substrate 739 to about 5 μm or less. In some embodiments, thinning reduces the thickness of the second semiconductor substrate 751 to about 3 μm or less. If the first semiconductor substrate 739 is left too thick, light may not penetrate effectively into the photodiode 711. If the first semiconductor substrate 739 is left too thin, light may not be efficiently captured by the photodiode 711. Additional processes provide the DTI structure 715, the back metal grid 705, the color filter 709, the microlens 701, and the contact pad 735 to manufacture the structure shown in Figure 7.

[0068] Figure 23 provides a flowchart of the process 2300 for forming the image sensor of the present invention. Although the process 2300 is illustrated and described below as a series of operations or events, it will be understood that the illustrated order of such operations or events should not be interpreted in an restrictive sense. For example, some operations may occur in a different order and / or simultaneously with other operations or events not illustrated and / or described herein. In addition, not all illustrated operations are required to carry out one or more aspects or embodiments described herein. Furthermore, one or more of the operations depicted herein may be performed in one or more separate operations and / or stages.

[0069] Process 2300 begins with operation 2301, which is FEOL and BEOL processing of the first, second, and third device layers. A cross-sectional view 1600 in Figure 16 provides an example of these device layers after this initial processing. Each device layer may be a separate wafer at this processing stage. The wafers may then be diced to form a chip. FEOL processing forms wells, transistors, diodes, isolation structures, etc., within the substrate. BEOL processing forms metal interconnect structures, capacitors, and bonding structures. The first device layer may include an array of photodiodes or other photodetector structures, transfer gates, etc. The second device layer may include several photodetector pixel circuit components. Either the first or second device layer may include row drivers and column decoders for the photodiode array. The third device layer may include an ASIC.

[0070] Operation 2303 is to align the first device layer and the second device layer and bond them together through their respective bonding layers. A cross-sectional view 1700 in Figure 17 provides an example.

[0071] Operation 2305 involves thinning the semiconductor substrate of the second device layer from the back side. A cross-sectional view 1800 in Figure 18 provides an example.

[0072] Operation 2307 is to form a TSV from the back side through the semiconductor substrate of the second device layer. Cross-sectional view 1900 in Figure 19 provides an example.

[0073] Operation 2311 is to form contact and bonding structures on the back surface of the second device layer. Cross-sectional view 2000 in Figure 20 provides an example.

[0074] Operation 2313 involves aligning the second and third device layers and bonding them together so that the TSV is coupled to the third device layer. A cross-sectional view 2100 in Figure 21 provides an example.

[0075] Operation 2317 involves thinning the semiconductor substrate of the first device layer from the back side. A cross-sectional view 2200 in Figure 22 provides an example.

[0076] Operation 2319 is to form a DTI structure from the back surface of the semiconductor substrate of the first device layer. Operation 2321 is an additional process to form a back surface metal grid, color filter, and microlenses on the back surface of the semiconductor substrate of the first device layer. Operation 2323 is to form contact pads on the back surface of the semiconductor substrate of the first device layer. Figure 7 provides an example of the resulting structure.

[0077] Figure 24 is a flowchart of method 2400 for operating an image sensor having a quad-pixel structure according to the present invention. This method begins with operation 2401, selecting from 1C, 2C, and 4C modes. Operation 2403 is to determine whether 1C mode is selected. If 1C mode is selected, operation 2405 operates the bridge circuit to separate the stray-diffuse nodes in each quad-pixel array. If 1C mode is not selected, operation 2407 determines whether 2C mode is selected. If 2C mode is selected, operation 2409 operates the bridge circuit to couple pairs of stray-diffuse nodes in each quad-pixel array. If 2C mode is selected, operation 2411 operates the bridge circuit to electrically couple all four stray-diffuse nodes in each quad-pixel array.

[0078] Figure 25 is a flowchart of Method 2500 for operating an image sensor having a triple conversion gain circuit and a quad pixel structure according to the present invention. Method 2500 is compatible with Method 2400 in Figure 24. Method 2500 begins with operation 2501, selecting a low, medium, or high conversion gain mode. Operation 2503 is to perform a reset operation, which may include closing all reset and conversion gain transistors in the triple conversion gain circuit. Operation 2505 is to determine whether the low conversion gain mode was selected. If the low conversion gain mode was selected, operation 2507 opens the reset transistor while keeping the conversion gain transistors closed. If the low conversion gain mode was not selected, operation 2509 determines whether the medium conversion gain mode was selected. If the medium conversion gain mode was selected, operation 2511 opens the reset transistor and the second conversion gain transistor, but keeps the first conversion gain transistor closed. If the 2C mode was not selected, operation 2513 opens all reset transistors and all conversion gain transistors.

[0079] Figure 26 is a flowchart of method 2600 for performing a readout operation of an image sensor having a quad-pixel structure according to an embodiment of the present invention. Operation 2601 is to decide to start the readout operation. This decision may be based on a clock. Operation 2603 is to decide whether 1C mode is selected. If 1C mode is selected, operation 2605 operates each row driver of the photodetector array sequentially. If 1C mode is not selected, operation 2607 operates every other row driver of the photodetector array sequentially. In either case, the method continues with operation 2609. Operation 2609 is to decide whether 4C mode is selected. If 4C mode is not selected, operation 2613 operates all column decoders of the photodetector array. If 4C mode is selected, operation 2611 operates only every other column decoder of the photodetector array.

[0080] Figure 27 is a flowchart of method 2700 for performing a readout operation of an image sensor having a quad-pixel structure according to another embodiment of the present invention. Method 2700 includes many of the same steps as method 2600 in Figure 26. However, in method 2700, operation 2613, which operates all column decoders, is performed in all cases, and operation 2609, which determines whether 4C mode is selected, may come after operation 2613. In method 2700, if 4C mode is not selected, operation 2703 outputs data from each column decoder in the conventional manner. If 4C mode is selected, operation 2701 outputs the average value of the values ​​generated by each pair of column decoders.

[0081] Some aspects of the present invention relate to an image sensor comprising a photodiode, a quad-pixel circuit, and a bridge circuit in a first array within a first semiconductor substrate. The quad-pixel circuit comprises four photodiodes, four transfer gates, four floating-diffuse regions, and four source followers in a 2x2 subarray. The bridge circuit selectively couples the four floating-diffuse regions. In some embodiments, the quad-pixel circuit further comprises four multiplexing gain circuits. In some embodiments, each of the four multiplexing gain circuits comprises four lateral overflow integrated capacitors. In some embodiments, each of the four multiplexing gain circuits comprises two transistors connected in series between each lateral overflow integrated capacitor and each floating-diffuse region. In some embodiments, the image sensor further comprises an integrated circuit that generates control signals to selectively operate the two series-connected transistors to independently determine low, medium, and high conversion gain modes.

[0082] In some embodiments, the image sensor further includes an integrated circuit that operates a bridge circuit to generate a control signal that connects groups of one, two, or four of the four floating-diffuse regions. In some embodiments, the image sensor further includes two column decoders, two wiring structures, and an integrated circuit. Each wiring structure connects two of the four source followers to one of the two column decoders. The integrated circuit averages the outputs of the two column decoders when the bridge circuit is connecting the four floating-diffuse regions.

[0083] In some embodiments, the image sensor further includes two column decoders, two wiring structures, and an integrated circuit. Each wiring structure connects two of the four source followers to one of the two column decoders. The integrated circuit deactivates one of the two column decoders when the bridge circuit connects two of the four floating-diffuse regions.

[0084] In some embodiments, the four source follower and bridge circuits are located on a first semiconductor substrate. In some embodiments, the four source follower and bridge circuits are located on a second semiconductor substrate, which is mounted on the first semiconductor substrate. In some embodiments, the image sensor further includes a row driver and a column decoder on the second semiconductor substrate. In some embodiments, the image sensor further includes through-substrate vias and a third semiconductor substrate within the second semiconductor substrate, the third semiconductor substrate containing an integrated circuit. The through-substrate vias connect the integrated circuit to the column decoder. In some embodiments, the image sensor further includes color filters in a second array, the second array having one-quarter the number density of the first array, and therefore there are four photodiodes for each color filter.

[0085] Some aspects of the present invention relate to an image sensor comprising a semiconductor substrate, a first photodetector, a second photodetector, a third photodetector, and a fourth photodetector, as well as a first switch transistor, a second switch transistor, and a third switch transistor. The first to fourth photodetectors each include a first photodiode to a fourth photodiode, a first transfer gate to a fourth transfer gate, and a first to a fourth floating-diffusion node. The first transistor each has a pair of source / drain regions electrically coupled to a first and second floating-diffusion node. The second transistor each has a pair of source / drain regions electrically coupled to a third and fourth floating-diffusion node. The third transistor each has a pair of source / drain regions electrically coupled to a first and third floating-diffusion node. In some embodiments, the image sensor further includes a fourth transistor having a pair of source / drain regions electrically coupled to a second and a fourth floating-diffusion node. In some embodiments, the image sensor further includes first to fourth source followers having first to fourth gate electrodes, with the first to fourth floating-diffusion nodes being coupled to the first to fourth gate electrodes, respectively. The image sensor further includes a column decoder. The wiring structure connects the source regions of the first to fourth source followers to the column decoder.

[0086] Some aspects of the present invention relate to an image sensor comprising a first chip including a first semiconductor substrate, and four photodetector pixel circuits each comprising a photodiode, a transfer gate, a stray-diffusion node, a source follower, a dual-conversion gain transistor, and a lateral overflow integrated capacitor (LOFIC). The photodiode is located within the first semiconductor substrate. The photodiodes of the four photodetector pixel circuits are located beneath a color filter. The image sensor further includes a bridge circuit that selectively couples the four stray-diffusion nodes. In some embodiments, the image sensor further includes a second chip mounted on the first chip. The second chip includes a second semiconductor substrate. The LOFIC is located within the second chip, and the source follower is located within the first chip.

[0087] In some embodiments, the image sensor further includes a second chip comprising a second semiconductor substrate and a third chip comprising a third semiconductor substrate. The second chip is mounted on the first chip, and the third chip is mounted on the second chip. The source follower is located within the second chip. In some embodiments, the LOFIC is located within the third chip. In some embodiments, the LOFIC is located within the first chip.

[0088] The foregoing outlines the features of several embodiments so that those skilled in the art may better understand aspects of the present invention. Those skilled in the art should understand that the present invention can be readily used as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages as the embodiments presented herein. Those skilled in the art should also recognize that such equivalent configurations do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the present invention. [Industrial applicability]

[0089] This invention relates to increasing the dynamic range of an image sensor. [Explanation of Symbols]

[0090] 100 Circuit Diagrams 101A, 101B, 101C, 101D Photodetector Pixel Circuits 105 Quad Pixel Circuit 103A, 103B column wiring 107. BC Bridge Circuit PD photodiode FD (Floating Diffusion) Node TX Transfer Gate SF Source Follower RSL row selection transistor V TX-A , V TX-B , V TX-C , V TX-D Transfer gate signal V RS_A , V RS_B , V RS_C , V RS_D Row selection signal V dd Power supply voltage

Claims

1. A photodiode in the first array within the first semiconductor substrate, A quad pixel circuit comprising four photodiodes, four transfer gates, four floating diffuse regions, and four source followers in a 2x2 subarray, A bridge circuit that selectively connects the four aforementioned floating diffusion regions, Image sensors, including...

2. The image sensor according to claim 1, wherein the quad pixel circuit further includes four multiplexing gain circuits.

3. The image sensor according to claim 2, wherein each of the four multiplexing gain circuits includes a lateral overflow integrated capacitor.

4. The image sensor according to claim 3, wherein each of the four multiplexing gain circuits includes two transistors connected in series between each of the lateral overflow integrated capacitors and each of the floating diffusion regions.

5. Further including integrated circuits, The image sensor according to claim 3, wherein the integrated circuit generates a first control signal that causes the bridge circuit to operate to connect a group that selectively includes one, two, or four of the four floating diffusion regions, and a second control signal that causes the four multiplex conversion gain circuits to selectively operate to independently determine the conversion gain modes.

6. The image sensor according to claim 1, further comprising an integrated circuit, the integrated circuit generating a control signal to operate the bridge circuit to connect a group that selectively includes one, two, or four of the four floating diffusion regions.

7. Two column decoders, Two wiring structures, each of which comprises two wiring structures connecting two of the four source followers to one of the two column decoders, An integrated circuit that averages the outputs of the two column decoders when the bridge circuit is coupling the four floating diffusion regions, The image sensor according to claim 1, further comprising:

8. Two column decoders, Two wiring structures, each of which comprises two wiring structures connecting two of the four source followers to one of the two column decoders, An integrated circuit that deactivates one of the two column decoders when the bridge circuit is coupling the four floating diffusion regions, The image sensor according to claim 1, further comprising:

9. The image sensor according to claim 1, wherein the four source followers and the bridge circuit are located on the first semiconductor substrate.

10. The image sensor according to claim 1, wherein the four source followers and the bridge circuit are located on a second semiconductor substrate, and the second semiconductor substrate is attached to the first semiconductor substrate.

11. The image sensor according to claim 10, further comprising a row driver and a column decoder on the second semiconductor substrate.

12. The image sensor according to claim 1, wherein the quad pixel circuit further includes four dual conversion gain circuits.

13. The image sensor according to claim 1, further comprising a second array containing color filters, wherein the second array has a number density of one-quarter that of the first array, and there are four photodiodes for each of the color filters.

14. Semiconductor substrate and A first photodetector including a first photodiode, a first transfer gate, and a first floating diffusion node in the semiconductor substrate, A second photodetector comprising a second photodiode, a second transfer gate, and a second floating diffusion node within the semiconductor substrate, A third photodetector including a third photodiode, a third transfer gate, and a third floating diffusion node in the semiconductor substrate, A fourth photodetector including a fourth photodiode, a fourth transfer gate, and a fourth floating diffusion node within the semiconductor substrate, A first transistor having a pair of source / drain regions electrically coupled to the first floating diffusion node and the second floating diffusion node, A second transistor having a pair of source / drain regions electrically coupled to the third floating diffusion node and the fourth floating diffusion node, A third transistor having a pair of source / drain regions electrically coupled to the first floating diffusion node and the third floating diffusion node, Image sensors, including...

15. The image sensor according to claim 14, further comprising a fourth transistor having a pair of source / drain regions electrically coupled to the second floating diffusion node and the fourth floating diffusion node, respectively.

16. A first source follower having a first gate electrode, wherein the first floating diffusion node is coupled to the first gate electrode, A second source follower having a second gate electrode, wherein the second floating diffusion node is coupled to the second gate electrode, A third source follower having a third gate electrode, wherein the third floating diffusion node is coupled to the third gate electrode, A fourth source follower having a fourth gate electrode, wherein the fourth floating diffusion node is coupled to the fourth gate electrode, A column decoder wherein the wiring structure connects the source regions of the first source follower, the second source follower, the third source follower, and the fourth source follower to the column decoder, The image sensor according to claim 14, further comprising:

17. A first chip including a first semiconductor substrate, A photodetector pixel circuit comprising four photodetector pixel circuits, each including a photodiode, a transfer gate, a stray diffusion node, a source follower, a multiplexing gain transistor, and a lateral overflow integrated capacitor (LOFIC), wherein the photodiode is located within the first semiconductor substrate, A color filter wherein the photodiodes of the four photodetector pixel circuits are located below the color filter, A bridge circuit that selectively connects the four floating diffusion nodes, Image sensors, including...

18. The image sensor according to claim 17, further comprising a second chip attached to the first chip, wherein the second chip comprises a second semiconductor substrate, the lateral overflow integrated capacitor is located within the second chip, and the source follower is located within the first chip.

19. A second semiconductor substrate is included, and the second chip is attached to the first chip, A third semiconductor substrate is included, and the third chip is attached to the second chip, It further includes, The image sensor according to claim 17, wherein the lateral overflow integrated capacitor is located in the third chip and the source follower is located in the second chip.

20. A second semiconductor substrate is included, and the second chip is attached to the first chip, A third semiconductor substrate is included, and the third chip is attached to the second chip, It further includes, The image sensor according to claim 17, wherein the lateral overflow integrated capacitor is located in the first chip and the source follower is located in the second chip.

Images