Vertical stacked red, green, and blue full-color chip-on-carrier for microLED display panels and method for manufacturing the same.

Abstract

This invention provides a vertically stacked red, green, and blue full-color chip-on-carrier for microLED display panels, which eliminates the need for color filters by utilizing an engineering monolithic epitaxial wafer method and ensuring that each LED stack emits only a specific color. It also provides a method for manufacturing this chip-on-carrier. [Solution] Short-circuits are formed in a portion of a stack of vertically stacked LEDs, and current is passed through the light-emitting portion where the short-circuits are not formed, causing only a specific color to be emitted. Since the chip-on-carrier already has short-circuits formed on a temporary wafer with multiple LED stacks, no separate epitaxial growth or stacking process is required, and a microLED display panel can be easily manufactured by bonding it to a silicon CMOS or glass TFT backplane wafer. This simplifies the manufacturing process, resulting in reduced process time and improved manufacturing yield.

Description

Technical Field

[0001] The present invention relates to a vertical stacked red, green, and blue full-color chip on carrier for a microLED display panel and a manufacturing method thereof. More specifically, by using an engineering monolithic epitaxy wafer method to make each LED stack emit only a specific color, the present invention relates to a vertical stacked red, green, and blue full-color chip on carrier for a microLED display panel that does not require a color filter and a manufacturing method thereof.

Background Art

[0002] The types of Metaverse, which has recently attracted attention, are classified into four forms: VR (virtual reality), AR (augmented reality), MR (mixed reality), and XR (extended reality). It is predicted that the Metaverse ecosystem will develop in the future centering around XR, which is a reality linked with VR, AR, and MR. To effectively implement this, in addition to software for a next-generation computing platform that can provide an innovative user experience, a device (such as smart glasses, head-mounted displays, etc.) that includes a microdisplay with a diagonal length of less than 1 inch as a core component is required. In particular, in order to provide the most immersive experience, visibility, and convenience to XR users and minimize dizziness, the development of high-performance microLED display panel technology is absolutely necessary.

[0003] As shown in Figure 1, the conventional microdisplay panel 10 is a technology that combines a Si CMOS semiconductor wafer process with a high-resolution, high-brightness ultra-small display process. The conventional microdisplay panel 10 can have a structure in which a Si CMOS wafer 11 having a (100) crystal plane of 4 inches or more and equipped with multiple CMOS electrode pads 12, and a transparent wafer 13 of 4 inches or more equipped with microLED electrode pads 14 and multiple microLED chips 15 are bonded together through a conductive bond 16. On the other hand, types of microdisplay panels expected to be applied to XR devices include LCoS (LC on Si) based on liquid crystal (LC), OLEDoS (OLED on Si) based on organic light-emitting diode (OLED), and LEDoS (LED on Si) based on ultra-small microLEDs with pixel sizes of less than 5 μm. However, in the case of VR where displays with low pixel density are applied, LCoS and OLEDoS are the main types being developed and mass-produced.

[0004] However, with the advancement of metaverse implementation technologies, the need for lightweight AR, MR, and XR devices utilizing high-pixel-density microdisplay panels is increasing. This need has led to an urgent need for LEDoS (which employs a microLED pixel light source composed of red, green, and blue subpixels smaller than 5 μm), a theoretically ideal solution based on the advantages of inorganic materials. However, a microdisplay panel platform for this purpose has not yet been established.

[0005] LEDoS, an ultra-small microLED substrate with pixel size less than 5μm, offers advantages when applied to XR devices, including an excellent power-to-performance ratio and short response time. Furthermore, it is composed of inorganic materials, resulting in a long lifespan, efficient power utilization, reduced heat generation, and extended battery life. In particular, because the distance between the display and the eye is extremely short in XR devices, even a slight delay in image conversion can easily cause dizziness and other inconveniences. Therefore, LEDoS, with its nanosecond response time, is considered the most suitable for XR devices compared to LCoS and OLEDoS, which have microsecond response times.

[0006] Furthermore, the biggest reason why LEDoS is attracting attention in AR, MR, and XR devices, unlike VR, is considered to be its brightness and luminous efficiency. Due to the nature of smart glasses that can be worn anywhere, high brightness is an essential condition so that they can operate normally even in outdoor environments such as sunlight. Theoretically, microLEDs can support a brightness of tens to millions of nits, and while OLEDs are organic materials, microLEDs are inorganic materials, so they have the advantage of high luminous efficiency.

[0007] However, despite the aforementioned advantages, the biggest reason why LEDoS, an ultra-small microLED substrate with pixel size less than 5 μm, has not been positioned as a major component of XR devices is that mass production is difficult. In other words, because LEDoS requires fixing millions of ultra-small microLEDs onto a Si CMOS wafer, the process is highly complex and the yield is very low, leading to increased manufacturing costs and a high component price. This is reflected in the final consumer price, resulting in expensive XR devices that are difficult to supply and meet market demand.

[0008] On the other hand, as shown in Figure 2, until recently, the development of LEDoS using group 3-5 compound (GaN, GaP, etc.) microLED light sources has been developed through traditional approaches such as (1) monolithic integration of wafers (or unit dies) composed of microLED arrays on CMOS wafers, or (2) hybridization between wafers (or unit dies) on blue, green, and red light source wafers (or unit dies) on which CMOS wafers or microLED arrays have been fabricated.

[0009] One of the biggest obstacles to LEDoS development using blue, green, and red microLED light sources composed of group 3-5 compounds to date is the difficulty in securing solutions for pixels smaller than 5 μm. However, recently, 5 μm pixels have been successfully demonstrated using monolithic integration technology, and some prototypes developed using hybridization technology have achieved 10 μm pixels by fabricating them via sapphire flip chips. Furthermore, it has been demonstrated that it is possible to reduce the number of 5 μm pixels in the same way by using microtube wiring in hybridization technology. However, both monolithic integration technology and hybridization technology are impractical solutions with considerable difficulties in mass production in terms of quality and yield, making mass production difficult.

[0010] The aforementioned monolithic integration and hybridization technologies share the common characteristic of assembling a front-plane wafer composed of group 3-5 compound microLED arrays and a Si CMOS back-plane wafer composed of numerous IC electrode pad arrays, after separate design and fabrication. However, regardless of the method, the microLED arrays fabricated on the Si CMOS wafer at the unit die-level or wafer-level must be ultra-fine aligned. At this time, the alignment is limited by the precision of the process-related equipment, resulting in a significant impact on the pixel and pitch limitations, making mass production difficult. Therefore, in order to manufacture LEDoSs using high-resolution, high-brightness, and high-speed blue, green, and red microLED light sources with pixels smaller than 5 μm and pitches smaller than 3 μm, a new alternative solution that can circumvent the aforementioned ultra-fine alignment constraints is needed.

[0011] Consequently, several impressive prototypes with 6μm pixels have recently been released using engineering monolithic epitaxy wafers manufactured through a low-temperature metal bonding process between Si CMOS wafers and microLED array wafers. However, it is believed that mass production would be impossible due to low quality and yield issues resulting from low-temperature metal bonding, and the use of small-diameter wafers of 6 inches or less. Above all, when fabricating ultra-fine pixels of less than 3μm for microdisplays using conventional engineering monolithic epitaxy wafers utilizing metal bonding, even greater difficulties arise during pattern etching.

[0012] As yet another example, a novel approach to engineered monolithic epitaxial wafers has recently been proposed, which has achieved significant results in solving the brightness and resolution limitations of LEDoS using group 3-5 compound microLED light sources, while simultaneously providing a mass production and low-cost manufacturing solution through the use of 12-inch large-diameter Si CMOS wafers.

[0013] Referring to Figure 3, the process using an engineering monolithic epitaxial wafer is carried out through the following four steps: (1) First, using an LED epitaxial wafer, LED epitaxies cut to a predetermined size (e.g., 4 mm x 6 mm) are aligned and bonded at the unit die level onto a 12-inch large-diameter Si blanket wafer. Subsequently, the LED epitaxy growth wafer and buffer layer are removed and then planarized to leave only an LED active layer of a predetermined thickness (e.g., approximately 1.5 μm) on the large-diameter Si blanket wafer, completing the LED fab process into a pixel chip form. (2) Next, the Si blanket wafer with the completed pixel chip is bonded to a 12-inch CMOS IC Si wafer at the wafer level through multilayer metal bonding. (3) Next, the Si blanket wafer is removed. (4) Finally, residual processes are performed on the CMOS IC Si wafer for the microLED array that will function as a pixel.

[0014] However, in stage (1), when bonding the LED epitaxy unit die onto the Si blanket wafer, there is a limitation that positional alignment must be performed using a CMOS IC Si wafer of the same size before bonding. In stage (2), when bonding with a multilayer metal containing low-melting-point metals (Sn, In), there is a problem that the low-melting-point metal component can easily overflow, causing a short-circuit failure that electrically connects between or adjacent CMOS IC electrode pad arrays within the microLED subpixel array in the panel. Furthermore, in stage (2), due to the optical opacity of the Si blanket wafer and the multilayer metal bonding layer, ultra-fine alignment wafer bonding (bonding) between the Si blanket wafer (i.e., the front plane wafer) and the CMOS IC Si wafer is difficult, leading to defects. Here, ultra-fine alignment means matching and aligning the microLED array, which is a multi-layer (hundreds to tens of millions) of ultra-small pixel chips on the Si blanket wafer, with the CMOS IC electrode pad array on the CMOS IC Si wafer in a 1:1 ratio.

[0015] In other words, the engineering monolithic epitaxial wafer approach method presented in the aforementioned technology is considered to be a solution that brings us one step closer to realizing LEDoS for ultra-small microLED substrates with pixel sizes of less than 5 μm. However, there are quality and yield issues caused by the use of metal (low temperature, multilayer) in wafer bonding, making it extremely difficult to manufacture high-resolution microdisplays with ultra-fine pixels of less than 3 μm. Furthermore, there are problems with some alignment processes, so a new alternative is needed.

[0016] Furthermore, in conventional microdisplays employing microLED pixel light sources, the vertically stacked tandem structure still requires the application of color filters to achieve full color, resulting in disadvantages in terms of color quality, process complexity, and productivity.

[0017] On the other hand, in a vertically stacked tandem structure, there is a problem in that unwanted sub-pixel emission can occur due to light excitation. Referring to Figure 4, in order to solve this, it is possible to create a structure in which a short passage 180 is formed after etching the remaining part of each LED stack L except for the light-emitting part 120 that emits a specific color. However, in this case, the etching process becomes difficult because the etching must be done deeply up to the light-emitting part 120 located in the intermediate layer, and there is a limitation in that the short passage 180 is difficult to form stably because the conductive material is not sufficiently filled, so improvement is needed. [Prior art documents] [Patent Documents]

[0018] [Patent Document 1] Republic of Korea Patent Publication No. 10-2018-0009116 [Overview of the project] [Problems that the invention aims to solve]

[0019] The objective of the present invention is to solve the aforementioned conventional problems and to provide a vertically stacked red, green, and blue full-color chip-on-carrier for microLED display panels, and a method for manufacturing the same, which does not require a color filter by utilizing an engineering monolithic epitaxy wafer method and causing each LED stack to emit only a specific color. [Means for solving the problem]

[0020] The above object is achieved by a vertical stacked red, green, and blue full-color chip on carrier for a microLED display panel according to the present invention, which includes a temporary wafer; and a plurality of LED stacked bodies vertically stacked through a bonding layer and aligned on the temporary wafer. Each of the plurality of LED stacked bodies has a short circuit formed in a part of the region, so that current is applied to the light-emitting part where the short circuit is not formed, and only a specific color is emitted. The short circuit includes a first short circuit formed to correspond to the width of the light-emitting part and a second short circuit formed to penetrate the light-emitting part.

[0021] In addition, the plurality of LED stacked bodies may include a first LED stacked body including a first light-emitting part that emits a first color, a second LED stacked body including a second light-emitting part that emits a second color, and a third LED stacked body including a third light-emitting part that emits a third color.

[0022] In addition, the first LED stacked body includes the first short circuit formed in the third light-emitting part portion and the second short circuit formed to penetrate the second light-emitting part. The second LED stacked body includes the first short circuit formed in the third light-emitting part portion and the first short circuit formed in the first light-emitting part portion. The third LED stacked body may include the second short circuit formed to penetrate the second light-emitting part and the first short circuit formed in the first light-emitting part portion.

[0023] In addition, a common electrode may be formed on the upper or lower part of the plurality of LED stacked bodies.

[0024] In addition, a sacrificial separation layer may be formed on the temporary wafer.

[0025] The above object is achieved by a method for manufacturing a vertical stacked red, green, and blue full-color chip on carrier for a microLED display panel, which includes: a preparation step of preparing a plurality of front wafers including a support wafer and a light-emitting part according to the present invention; a stacking step of forming a stack in which a plurality of the light-emitting parts are vertically stacked on the support wafer by repeatedly removing the support wafer of another front wafer after bonding the other front wafer on one front wafer through a bonding layer; a first processing step of forming a short path on one surface of the stack; a second processing step of forming the short path on the other surface of the stack after bonding a temporary wafer on one surface of the stack, removing the support wafer, and then forming the short path on the other surface of the stack; and an etching step of etching the stack and separating it in a preset unit, so that a plurality of LED stacks are aligned on the temporary wafer. Each of the plurality of LED stacks has a short path formed in a part of the region, so that current is applied to the light-emitting part where the short path is not formed, and only a specific color is emitted. The short path includes a first short path formed to correspond to the width of the light-emitting part and a second short path formed to penetrate the light-emitting part.

[0026] Also, the plurality of LED stacks may include a first LED stack including a first light-emitting part that emits a first color, a second LED stack including a second light-emitting part that emits a second color, and a third LED stack including a third light-emitting part that emits a third color.

[0027] Also, the first LED stack may include the first short path formed in the third light-emitting part portion and the second short path formed to penetrate the second light-emitting part. The second LED stack may include the first short path formed in the third light-emitting part portion and the first short path formed in the first light-emitting part portion. The third LED stack may include the second short path formed to penetrate the second light-emitting part and the first short path formed in the first light-emitting part portion.

[0028] Furthermore, a common electrode may be formed on the upper or lower part of the multiple LED stacks.

[0029] Furthermore, a sacrificial isolation layer may be formed on the temporary wafer. [Effects of the Invention]

[0030] According to the present invention, the chip-on carrier is a state in which multiple LED stacks are formed on a temporary wafer, with multiple light-emitting units stacked vertically. Since short passages are already formed in each of the multiple LED stacks, the supplier can easily manufacture a microLED display panel by simply bonding it to a silicon (Si) CMOS or glass (Glass) TFT backplane wafer without having to perform separate epitaxial growth or stacking processes. This simplifies the manufacturing process, reduces the burden on manufacturing equipment and infrastructure, shortens process time, and improves manufacturing yield.

[0031] Furthermore, according to the present invention, there is an advantage in that it is easy to form short passages in a vertically stacked tandem structure.

[0032] Furthermore, according to the present invention, since a color filter is not required despite employing a vertically stacked tandem structure, the color quality of the microLED display can be greatly improved, and process complexity and productivity can be greatly improved.

[0033] Furthermore, according to the present invention, when designing and manufacturing a microdisplay panel employing microLED pixel light sources, unlike existing monolithic integration or hybrid integration methods where alignment issues exist, an engineered monolithic epitaxial wafer with multiple LED light-emitting units stacked on it is first fabricated through a bonding process to red, green, and blue LED epitaxial wafers. Then, the stacked structure on the engineered monolithic epitaxial wafer is etched and separated into predetermined units so that the multiple LED stacks are aligned on multiple CMOS electrode pads. This allows the use of not only small-diameter wafers of 6 inches or less, but also large-diameter wafers of 8 inches or more, which can significantly increase product yield.

[0034] Furthermore, according to the present invention, since both the bonding layer and the ohmic contact electrodes are made of transparent ceramic material (unrelated to electrical conductivity), etching is easy in the plasma dry process for aligning the LED stack, and the problem of etching byproducts being re-depositioned does not occur. Moreover, the ease of etching mentioned above provides a significant advantage for the fabrication of high-resolution microLED display panels having ultrafine pixels of less than 10 μm × 10 μm.

[0035] Furthermore, according to the present invention, since a laminate is formed by stacking red, green, and blue LED light-emitting parts on a temporary wafer, and then etching the laminate on a pixel-by-pixel basis, there is an effect of preventing alignment errors between the red, green, and blue LED light-emitting parts.

[0036] Furthermore, according to the present invention, since red light is not absorbed by other light-emitting parts, the luminescence efficiency of red light can be significantly improved in a vertically stacked tandem structure.

[0037] Furthermore, in each LED stack of the present invention, since the light-emitting parts other than the light-emitting part that emits the corresponding color are partially removed, the occurrence of unwanted sub-pixel emission due to light excitation by short-wavelength blue light can be reduced.

[0038] Furthermore, since each LED stack of the present invention has a vertical chip structure that can easily realize a chip size of sub-micrometer or less, rather than a horizontal and flip chip structure manufactured through a mesa etch process, it is possible to achieve cost innovation for microLED display panels by reducing the material cost of the pixel light source.

[0039] On the other hand, the effects of the present invention are not limited to those mentioned above, and a variety of effects may be included within the scope that is obvious to an ordinary person, as described below. [Brief explanation of the drawing]

[0040] [Figure 1] This diagram illustrates the structure of a conventional microdisplay panel. [Figure 2] This diagram illustrates the conventional approach to LEDoS development. [Figure 3] This diagram illustrates an approach method using conventional engineering monolithic epitaxial wafers. [Figure 4] This diagram illustrates an example of a microdisplay panel structure equipped with a short passageway. [Figure 5] This is a flowchart of a method for manufacturing vertically stacked red, green, and blue full-color chip-on carriers for microLED display panels according to one embodiment of the present invention. [Figure 6] This figure illustrates the process of preparing the front wafer in a method for manufacturing vertically stacked red, green, and blue full-color chip-on-carriers for microLED display panels according to one embodiment of the present invention. [Figure 7] This figure illustrates the process of preparing the front wafer in a method for manufacturing vertically stacked red, green, and blue full-color chip-on-carriers for microLED display panels according to one embodiment of the present invention. [Figure 8] This figure illustrates the process of preparing the front wafer in a method for manufacturing vertically stacked red, green, and blue full-color chip-on-carriers for microLED display panels according to one embodiment of the present invention. [Figure 9] This figure illustrates the process of preparing the front wafer in a method for manufacturing vertically stacked red, green, and blue full-color chip-on-carriers for microLED display panels according to one embodiment of the present invention. [Figure 10] This figure illustrates the process by which light-emitting parts are stacked to form a laminate by a method for manufacturing vertically stacked red, green, and blue full-color chip-on-carriers for microLED display panels according to one embodiment of the present invention. [Figure 11] This figure illustrates the process by which light-emitting parts are stacked to form a laminate by a method for manufacturing vertically stacked red, green, and blue full-color chip-on-carriers for microLED display panels according to one embodiment of the present invention. [Figure 12] This figure illustrates the process by which a chip-on carrier is manufactured using a method for manufacturing vertically stacked red, green, and blue full-color chip-on carriers for microLED display panels according to one embodiment of the present invention. [Figure 13] This figure illustrates the process by which a chip-on carrier is manufactured using a method for manufacturing vertically stacked red, green, and blue full-color chip-on carriers for microLED display panels according to one embodiment of the present invention. [Figure 14] This figure illustrates a vertically stacked red, green, and blue full-color chip-on-carrier for a microLED display panel according to one embodiment of the present invention. [Figure 15]This figure illustrates that a common electrode is formed on the upper part of multiple LED stacks in a vertically stacked red, green, and blue full-color chip-on-carrier for a microLED display panel according to one embodiment of the present invention. [Figure 16] This figure illustrates that a common electrode is formed at the bottom of multiple LED stacks in a vertically stacked red, green, and blue full-color chip-on-carrier for a microLED display panel according to one embodiment of the present invention. [Modes for carrying out the invention]

[0041] Some embodiments of the present invention will be described in detail below with reference to illustrative drawings. Note that when assigning reference numerals to the components in each drawing, efforts have been made to ensure that the same component has the same reference numeral whenever possible, even if it is shown in other drawings.

[0042] Furthermore, in describing embodiments of the present invention, if a specific description of a related known configuration or function is deemed to hinder understanding of the embodiments of the present invention, such detailed description will be omitted.

[0043] Furthermore, when describing the components of the embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc., may be used. Such terms are merely used to distinguish a component from other components, and do not limit the essence, order, or sequence of the component in question.

[0044] A method for manufacturing vertically stacked red, green, and blue full-color chip-on-carriers for microLED display panels according to one embodiment of the present invention (S100) will now be described in detail with reference to the attached drawings.

[0045] Figure 5 is a flowchart of a method for manufacturing vertically stacked red, green, and blue full-color chip-on-carriers for microLED display panels according to one embodiment of the present invention; Figures 6 to 9 illustrate the process of preparing the front wafer in the method for manufacturing vertically stacked red, green, and blue full-color chip-on-carriers for microLED display panels according to one embodiment of the present invention; Figures 10 to 11 illustrate the process of stacking light-emitting parts to form a laminate in the method for manufacturing vertically stacked red, green, and blue full-color chip-on-carriers for microLED display panels according to one embodiment of the present invention; and Figures 12 to 13 illustrate the process of manufacturing chip-on-carriers in the method for manufacturing vertically stacked red, green, and blue full-color chip-on-carriers for microLED display panels according to one embodiment of the present invention.

[0046] Referring to Figure 5, a method for manufacturing a vertically stacked red, green, and blue full-color chip-on-carrier for a microLED display panel according to one embodiment of the present invention (S100) includes a preparation step (S110), a stacking step (S120), a first processing step (S130) and a second processing step (S140), a cutting step (S150) and a forming step (S160).

[0047] The preparation stage (S110) is the stage in which multiple front wafers 110 and 210 are prepared.

[0048] The multiple front wafers 110, 210 are each designed to emit different colors from one another. The multiple front wafers 110, 210 may include first front wafers 111, 211 for emitting a first color, second front wafers 112, 212 for emitting a second color different from the first color, and third front wafers 113, 213 for emitting a third color different from the first and second colors. On the other hand, the first, second, and third colors may be, for example, red, green, and blue, respectively, but are not limited to these, and may include a variety of other colors.

[0049] Here, the first front wafers 111, 211 include a support wafer S and a first light-emitting unit 121 positioned on the top of the support wafer S; the second front wafers 112, 212 include a support wafer S and a second light-emitting unit 122 positioned on the top of the support wafer S; and the third front wafers 113, 213 include a support wafer S and a third light-emitting unit 123 positioned on the top of the support wafer S.

[0050] The light-emitting unit 120 generates light and can emit blue, green, or red light. In the present invention, when the light-emitting unit 120 emits blue or green light, binary, ternary, or quaternary compounds such as InN, InGaN, GaN, AlGaN, AlN, and AlGaInN, which are nitride semiconductors of group 3 (Al, Ga, In) among group 3-5 compound semiconductors, can be arranged in appropriate positions and order on the initial growth wafer G and epitaxy-grown.

[0051] In particular, a high-quality InGaN group 3 nitride semiconductor having a high In composition to emit blue or green light must be preferentially formed on top of a group 3 nitride semiconductor composed of GaN, AlGaN, AlN, or AlGaInN, but is not limited thereto.

[0052] Furthermore, in the present invention, when the light-emitting part 120 emits red light, binary, ternary, and quaternary compounds such as InP, InGaP, GaP, AlInP, AlGaP, AlP, and AlGaInP, which are group 3 (Al, Ga, In) phosphide semiconductors among group 3-5 compound semiconductors, can be epitaxy-grown by arranging them in appropriate positions and order on the initial growth wafer G. In addition, in recent developments in equipment and process technology, and in order to further improve the value of display panel products, when emitting red light, high-quality InGaN group 3 nitride semiconductors having a high In composition of 30% or more, in addition to group 3 phosphide semiconductors, can be preferentially formed on top of group 3 nitride semiconductors composed of GaN, AlGaN, AlN, and AlGaInN.

[0053] In particular, to emit red light, a high-quality InGaP group 3 phosphide semiconductor having a high In composition must be preferentially formed on top of a group 3 phosphide semiconductor composed of GaP, AlInP, AlGaP, AlP, and AlGaInP, but is not limited to this, and the following explanation will be based on group 3 nitride semiconductors.

[0054] Each light-emitting portion 120 more specifically includes a first semiconductor region 1201 (e.g., a p-type semiconductor region), an active region 1203 (e.g., multi-quantum wells, MQWs), and a second semiconductor region 1202 (e.g., an n-type semiconductor region). The structure can be formed by sequentially epitaxially growing the second semiconductor region 1202, the active region 1203, and the first semiconductor region 1201 on the growth wafer G. The final structure can consist of many multilayer group 3 nitrides and typically have an overall thickness of about 5.0 to 8.0 μm, but is not limited to this.

[0055] The first semiconductor region 1201, the active region 1203, and the second semiconductor region 1202 may each consist of a single layer or multiple layers. Although not shown, prior to epitaxial growth of the light-emitting portion 120 on the top of the growth wafer G, necessary layers such as a buffer layer may be added to improve the quality of the epitaxially grown light-emitting portion 120. For example, the buffer layer may consist of a nucleation layer (NL) and a compliance layer (CL) composed of an undoped semiconductor region to relieve stress and improve the quality of the thin film, and may have a thickness of approximately 4.0 μm. Also, when removing the growth wafer G using the laser lift-off (LLO) technique, a sacrificial layer may be provided between the nucleation layer and the undoped semiconductor region, and the seed layer may function as the sacrificial layer.

[0056] The second semiconductor region 1202 has second conductivity and is formed on the growth wafer G. Such a second semiconductor region 1202 can have a thickness of 2.0 to 3.5 μm.

[0057] The active region 1203 generates light by utilizing the recombination of electrons and holes, and is formed on the second semiconductor region 1202. Such an active region 1203 can have a multilayer structure with a thickness of several tens of nanometers.

[0058] The first semiconductor region 1201 has first conductivity (p-type) and is formed on the active region 1203. Such a first semiconductor region 1201 can have a thickness of several tens of nanometers to several micrometers in multiple layers, and its surface can have gallium polarity (Ga-polarity).

[0059] In other words, the active region 1203 is interposed between the first semiconductor region 1201 and the second semiconductor region 1202, and when holes in the first semiconductor region 1201, which is a p-type semiconductor region, and electrons in the second semiconductor region 1202, which is an n-type semiconductor region, are recombined in the active region 1203, light can be generated.

[0060] Furthermore, during the preparation of the front wafer 110, an ohmic contact electrode 124, which is optically transparent and electrically conductive, may be formed on at least one of the upper or lower surfaces of the light-emitting portion 120, and which is electrically connected to the light-emitting portion 120 by ohmic contact. This will be described later.

[0061] The support wafer S supports the light-emitting section 120 (first light-emitting section 121, second light-emitting section 122, or third light-emitting section 123) located on top of it. If the initial growth wafer G is not removed, the growth wafer G may be the support wafer S, or it may be a separate wafer bonded to remove the initial growth wafer G.

[0062] The following describes the manufacturing process of the front wafer 110 used for stacking the light-emitting section 120 of the vertically stacked red, green, and blue full-color chip-on-carrier 100 of the present invention in an n-side-up structure.

[0063] Referring to Figure 6, the manufacturing process of the first front wafer 111 is as follows:

[0064] In the case of a first front wafer 111 for emitting red light, a p-side-up front wafer 110 is prepared by sequentially epitaxially growing a second semiconductor region 1202, an active region 1203, and a first semiconductor region 1201 on a GaAs growth wafer G, forming a p-type ohmic contact electrode 124 with transparent conductivity on the upper surface of the first semiconductor region 1201, and then depositing a second bonding layer 130b on the ohmic contact electrode 124. At this time, the growth wafer G acts as a support wafer S, and the structure can have the support wafer S, light-emitting portion 120, ohmic contact electrode 124, and second bonding layer 130b stacked in order.

[0065] Referring to Figure 6, the process by which the second front wafer 112 is manufactured in this embodiment is as follows.

[0066] In the case of a second front wafer 112 for emitting green light, a p-side-up front wafer 110 is prepared by sequentially epitaxially growing a second semiconductor region 1202, an active region 1203, and a first semiconductor region 1201 on a sapphire (α-phase Al2O3) growth wafer G, forming a p-type ohmic contact electrode 124 with transparent conductivity on the upper surface of the first semiconductor region 1201, and then depositing a second junction layer 130b on the ohmic contact electrode 124. At this time, the growth wafer G acts as a support wafer S, and the structure can have the support wafer S, light-emitting portion 120, ohmic contact electrode 124, and second junction layer 130b stacked in order.

[0067] Referring to Figure 7, the process by which the third front wafer 113 is manufactured in this embodiment is as follows.

[0068] In the case of the third front wafer 113 for emitting blue light, a second semiconductor region 1202, an active region 1203, and a first semiconductor region 1201 are epitaxially grown in sequence on a sapphire (α-phase Al2O3) growth wafer G. Then, a p-type ohmic contact electrode 124 with transparent conductivity is formed on the upper surface of the first semiconductor region 1201, and the support wafer S and the ohmic contact electrode 124 are bonded together through a bonding layer B. Subsequently, the growth wafer G is separated from the light-emitting portion 120 using a laser lift-off (LLO) technique, the second semiconductor region 1202 is etched to reduce its thickness, an n-type ohmic contact electrode 124 with transparent conductivity is formed on the surface of the reduced-thickness second semiconductor region 1202, and a second bonding layer 130b is deposited on the n-type ohmic contact electrode 124 to prepare an n-side-up front wafer 110. In this case, the support wafer S may be formed from an optically transparent material other than sapphire or glass, or from a Si material having (111), (110), or (100) crystal planes, but is not limited to these. It may have a structure in which the support wafer S, bonding layer B, ohmic contact electrode 124, light-emitting part 120, ohmic contact electrode 124, and second bonding layer 130b are stacked in order.

[0069] On the other hand, the following describes the manufacturing process of the front wafer 210 used for stacking the light-emitting section 120 of the vertically stacked red, green, and blue full-color chip-on-carrier 100 of the present invention in a p-side-up structure.

[0070] Referring to Figure 8, the process by which the first front wafer 211 is manufactured in this embodiment is as follows:

[0071] In the case of the first front wafer 211 for emitting red light, a second semiconductor region 1202, an active region 1203, and a first semiconductor region 1201 are epitaxially grown in sequence on a GaAs growth wafer G. Then, a p-type ohmic contact electrode 124 with transparent conductivity is formed on the upper surface of the first semiconductor region 1201, and the support wafer S and the ohmic contact electrode 124 are bonded together through a bonding layer B. Subsequently, the growth wafer G is separated from the light-emitting region 120 using a chemical lift-off (CLO) technique, the second semiconductor region 1202 is etched to reduce its thickness, an n-type ohmic contact electrode 124 with transparent conductivity is formed on the surface of the reduced-thickness second semiconductor region 1202, and a second bonding layer 130b is deposited on the n-type ohmic contact electrode 124 to prepare an n-side-up front wafer 210. In this case, the support wafer S may be formed from an optically transparent material other than sapphire or glass, or from a Si material having (111), (110), or (100) crystal planes, but is not limited to these. It may have a structure in which the support wafer S, bonding layer B, ohmic contact electrode 124, light-emitting part 120, ohmic contact electrode 124, and second bonding layer 130b are stacked in order.

[0072] Referring to Figure 8, the process by which the second front wafer 212 is manufactured in this embodiment is as follows.

[0073] In the case of a second front wafer 212 for emitting green light, a second semiconductor region 1202, an active region 1203, and a first semiconductor region 1201 are epitaxially grown sequentially on a sapphire (α-phase Al2O3) growth wafer G. Then, a p-type ohmic contact electrode 124 with transparent conductivity is formed on the upper surface of the first semiconductor region 1201, and the support wafer S and the ohmic contact electrode 124 are bonded through a bonding layer B. Subsequently, the growth wafer G is separated from the light-emitting portion 120 using a laser lift-off (LLO) technique, the second semiconductor region 1202 is etched to reduce its thickness, an n-type ohmic contact electrode 124 with transparent conductivity is formed on the surface of the reduced-thickness second semiconductor region 1202, and a second bonding layer 130b is deposited on the n-type ohmic contact electrode 124 to prepare an n-side-up front wafer 210. In this case, the support wafer S may be formed from an optically transparent material other than sapphire or glass, or from a Si material having (111), (110), or (100) crystal planes, but is not limited to these. It may have a structure in which the support wafer S, bonding layer B, ohmic contact electrode 124, light-emitting part 120, ohmic contact electrode 124, and second bonding layer 130b are stacked in order.

[0074] Referring to Figure 9, the process by which the third front wafer 213 is manufactured in this embodiment is as follows.

[0075] In the case of a third front wafer 213 for emitting blue light, a p-side-up front wafer 210 is prepared by sequentially epitaxially growing a second semiconductor region 1202, an active region 1203, and a first semiconductor region 1201 on a sapphire (α-phase Al2O3) growth wafer G, which is an optically transparent wafer with high temperature resistance that allows 100% transmission (theoretically) of a laser beam (single-wavelength light) without absorption. Then, a p-type ohmic contact electrode 124 with transparent conductivity is formed on the upper surface of the first semiconductor region 1201, and finally, a second junction layer 130b is deposited on the ohmic contact electrode 124. At this time, the growth wafer G acts as a support wafer S, and in addition to being made of an optically transparent material such as sapphire or glass, it can have a structure in which the support wafer S, light-emitting portion 120, ohmic contact electrode 124, and second junction layer 130b are sequentially stacked.

[0076] On the other hand, in the case of green and blue light, the blue or green light emitting portion 120 can be formed on Si having a (111) crystal plane instead of the sapphire (α-phase Al2O3) growth wafer G, in which case the Si growth wafer G can be separated and removed by mechanical polishing or chemical lift-off (CLO) technique.

[0077] Furthermore, in this invention, the growth wafer G, support wafer S, and / or temporary wafer T materials can each be either silicon (Si) or sapphire, but the choice of material can be determined according to the wafer bonding method.

[0078] For example, when bonding at room temperature via a surface activation process, wafers made of different materials such as silicon (Si) or sapphire may be selected regardless of their thermal expansion coefficients. However, when bonding between a growth wafer G, a support wafer S, and a temporary wafer T at a temperature of 50°C or higher, or when annealing is performed at a temperature of 50°C or higher without removing one of the wafers after bonding has been completed, wafers made of the same material must be selected.

[0079] On the other hand, in the manufacturing process of the front wafers 110 and 210 described above, before the ohmic contact electrode 124 is formed on the surface of the first semiconductor region 1201 or the surface of the second semiconductor region 1202, if the surface of the first semiconductor region 1201 is exposed (in a p-side-up configuration) or the surface of the second semiconductor region 1202 is exposed (in an n-side-up configuration), the respective surfaces can be polished and planarized smoothly through mechanical polishing (MP) or chemical-mechanical polishing (CMP), respectively, so that they can have smooth surfaces.

[0080] Furthermore, the ohmic contact electrodes 124 of the front wafers 110 and 210 are formed of a transparent conductive material. When the ohmic contact electrodes 124 are formed in contact with a first semiconductor region 1201 which is a p-type semiconductor, the material of the ohmic contact electrodes 124 can include NiO, PtO, PdO, AgO2, Au, Rh2O3, RuO2, In2O3, SnO2, ZnO, IZO, ITO, and IGZO. When the ohmic contact electrodes 124 are formed in contact with a second semiconductor region 1202 which is an n-type semiconductor, the material of the ohmic contact electrodes 124 can include TiN, CrN, VN, In2O3, SnO2, ZnO, IZO, ITO, and IGZO. Furthermore, since the surface roughness of the second semiconductor region 1202, which has nitrogen polarity (N-polarity), is significantly greater than that of the first semiconductor region 1201, which has gallium polarity (Ga-polarity), it is desirable to introduce a chemical-mechanical polishing (CMP) process to polish and flatten the surface of the second semiconductor region 1202 before forming the transparent conductive ohmic contact electrode 124.

[0081] Furthermore, the surfaces of the ohmic contact electrodes 124 formed on the front wafers 110 and 210 can also be polished and flattened smoothly through mechanical polishing (MP) or chemical-mechanical polishing (CMP), respectively.

[0082] The stacking step (S120) is a step in which a stack is formed in which a plurality of light-emitting units 120 are stacked vertically on a support wafer S by repeatedly bonding one front wafer 110 to another front wafer 110 through a second bonding layer 130b and then removing the support wafer S of the other front wafer 110.

[0083] Here, the second bonding layer 130b can be formed from a transparent insulating material that is optically transparent and electrically insulating (e.g., SiO2, SiNx), or from a transparent conductive material that is optically transparent and electrically conductive (e.g., ITO, IZO, ZnO), and it is desirable to form it from a transparent insulating material in order to ensure bonding strength.

[0084] Here, "optically transparent" means transparent (transmittance of 80% or more) or translucent (transmittance of 50% or more) in the wavelength range of light (including visible light) used in the photolithography process, and "electrically conductive" means having an electrical resistance of less than 10⁻³ Ωcm.

[0085] When the second bonding layer 130b is formed of a transparent insulating material, the transparent insulating material may be, but is not limited to, oxides such as SiO2, Al2O3, HfO2, ZrO2, or Ta2O5, or nitrides such as Si3N4 or AlN.

[0086] Furthermore, when the second bonding layer 130b is formed of a transparent conductive material, the transparent conductive material may be a ceramic material, such as transparent conductive oxide (TCO), transparent conductive nitride (TCN), or transparent conductive oxide nitride (TCON). In this case, if the ceramic material is a transparent conductive oxide, the ceramic material may include In2O3, SnO2, ZnO, IZO, ITO, and IGZO; if the ceramic material is a transparent conductive nitride, the ceramic material may include TiN, CrN, and VN; and if the ceramic material is a transparent conductive oxide nitride, the ceramic material may include InON, SnON, ZnON, IZON, ITON, and IGZON, but is not limited to these.

[0087] On the other hand, the second junction layer 130b can also be formed from an opaque conductive metallic material (e.g., Au, Ag, Cu, Sn, In, Zn).

[0088] The process by which the light-emitting section 120 of the vertically stacked red, green, and blue full-color chip-on-carrier 100 of the present invention is stacked in an n-side-up structure will be explained below with reference to Figure 10.

[0089] Specifically, in the stacking stage (S120), for example, a second front wafer 112 in a p-side-up configuration that emits green light is bonded to a third front wafer 113 in an n-side-up configuration that emits blue light via a second bonding layer 130b. Then, the support wafer S of the second front wafer 112 is removed using a laser lift-off or the like. Subsequently, the second semiconductor region 1202 of the second light-emitting portion 122, which is exposed by the removal of the support wafer S, is etched to reduce its thickness. Then, an n-type ohmic contact electrode 124 is formed on the surface of the second semiconductor region 1202, and the second bonding layer 130b is deposited on the n-type ohmic contact electrode 124.

[0090] Next, the first front wafer 111 in a p-side-up configuration that emits red light is bonded through the second bonding layer 130b, and then the support wafer S of the first front wafer 111 is removed using chemical lift-off or the like. Subsequently, the second semiconductor region 1202 of the first light-emitting portion 121, which is exposed by the removal of the support wafer S, is etched to reduce its thickness, and then an n-type ohmic contact electrode 124 is formed on the surface of the second semiconductor region 1202. At this time, when etching the second semiconductor region 1202 of the first light-emitting portion 121, a surface texturing process may be performed on the surface of the second semiconductor region 1202.

[0091] Through this process, a support wafer S, a bonding layer B, a third light-emitting section 123 with ohmic contact electrodes 124 formed on its upper and lower surfaces, a second bonding layer 130b, a second light-emitting section 122 with ohmic contact electrodes 124 formed on its upper and lower surfaces, and a first light-emitting section 121 with ohmic contact electrodes 124 formed on its upper and lower surfaces are stacked vertically to form a laminate on the support wafer S.

[0092] On the other hand, the lamination stage (S120) does not utilize high pressure or an external electric field, but can utilize the property that smooth surfaces adhere to each other due to van der Waals forces. Accordingly, it is desirable to introduce a chemical-mechanical polishing (CMP) process before joining the front wafers 110 to each other so that the roughness of each bonding surface is very low (Rq, <0.5 nm @ 2 μm × 2 μm) and there are no particles such as impurities between the surfaces. For this reason, in the lamination stage (S120), before joining the front wafers 110 to each other, the surface of the second bonding layer 130b of the front wafers 110 can be polished to a smooth and planar state through mechanical polishing (MP) or chemical-mechanical polishing (CMP).

[0093] On the other hand, in the present invention, after stacking all the RGB light-emitting parts 120 to form a laminate, heat treatment at a high temperature of 200 to 900°C is essential to improve the bonding strength of the second bonding layer 130b, thereby ensuring a strong bonding strength between the RGB light-emitting parts 120.

[0094] At this time, if high-temperature heat treatment is performed after the first processing stage (S130) to strengthen the bonding force between the RGB light-emitting parts 120, there is a risk of damage to the short passage 180. If heat treatment is performed after receiving the vertical stacked red, green, and blue full-color chip-on-carrier 100 of the present invention and bonding it to a silicon (Si) CMOS backplane wafer or the like, there is a risk of damage to the CMOS electrode panel or the like. Therefore, it is desirable to perform the heat treatment at the stacking stage (S120).

[0095] The process by which the light-emitting section 120 of the vertically stacked red, green, and blue full-color chip-on-carrier 100 of the present invention is stacked in a p-side-up structure will be explained below with reference to Figure 11.

[0096] Specifically, in the stacking stage (S220), first, a second front wafer 212 in an n-side-up configuration that emits green light is bonded to a third front wafer 213 in a p-side-up configuration that emits blue light via a second bonding layer 130b. Then, the support wafer S of the second front wafer 212 is removed using a laser lift-off or the like, and the second bonding layer 130b is deposited on the p-type ohmic contact electrode 124.

[0097] Subsequently, the first front wafer 211 in a p-side-up configuration that emits red light is bonded through the second bonding layer 130b. Then, the support wafer S of the first front wafer 211 is removed using chemical lift-off or the like, so that the p-type ohmic contact electrode 124 is exposed to the outside.

[0098] Through this process, a support wafer S, a bonding layer B, a third light-emitting section 123 with ohmic contact electrodes 124 formed on its upper and lower surfaces, a second bonding layer 130b, a second light-emitting section 122 with ohmic contact electrodes 124 formed on its upper and lower surfaces, and a first light-emitting section 121 with ohmic contact electrodes 124 formed on its upper and lower surfaces are stacked vertically to form a laminate on the support wafer S.

[0099] On the other hand, as mentioned above, after stacking all the RGB light-emitting parts 120 to form a laminate, heat treatment at a high temperature of 200 to 900°C is essential to improve the bonding strength of the second bonding layer 130b, thereby ensuring strong bonding strength between the RGB light-emitting parts 120.

[0100] The first processing step (S130) is the step of forming a short passage 180 on one surface of the laminate.

[0101] Referring to Figures 12 to 13, specifically, in the first processing step (S130), the first light-emitting portion 121 in the area where the third LED stack L3 is formed and the area where the second LED stack L2 is formed is first removed by etching along with the upper and lower ohmic contact electrodes 124, and is removed by etching until the second bonding layer 130b is exposed. Subsequently, a through-hole is formed in the area where the third LED stack L3 is formed so as to penetrate the second light-emitting portion 122, and then a conductive transparent material is filled into the through-hole to form a second short passage 182.

[0102] At this time, the through-hole may be formed to penetrate the active region 1203 of the second light-emitting part 122, and in particular, if the second junction layer 130b is formed of a transparent insulating material, it is desirable that the through-hole penetrates all of the second junction layer 130b between the first light-emitting part 121 and the second light-emitting part 122 and the second junction layer 130b between the second light-emitting part 122 and the third light-emitting part 123, until the surface of the ohmic contact electrode 124 of the third light-emitting part 123 is exposed.

[0103] Subsequently, in the first processing stage (S130), a conductive material is filled into the etched portion to form the first short passage 181.

[0104] At this time, after forming the first short passage 181, the substance may remain on the ohmic contact electrode 124 of the first light-emitting part 121 that has not been etched, or it may be removed. However, if the substance is left on the ohmic contact electrode 124 of the first light-emitting part 121, a transparent layer 171 will be formed. It is also possible to fill the etched portion with a conductive material and then form the transparent layer 171 with a different material.

[0105] Furthermore, the short passage 180 and the transparent layer 171 formed on one surface of the laminate are made of a transparent conductive material so that light can be transmitted to the outside.

[0106] When the short passage 180 and the permeable layer 171 are formed from a transparent conductive material, it is desirable that they be formed from a material having low resistance and high permeability characteristics. Such materials may include, but are not limited to, In2O3, SnO2, ZnO, IZO, ITO, and IGZO.

[0107] On the other hand, the short passage 180 in the portion that has been etched and removed or in the through-hole can be formed by filling it with a conductive material through a direct self-alignment method or by filling it with a conductive material through a liquid coating method such as a sol-gel, but is not limited to these methods, and any method for forming the short passage 180 may be used.

[0108] On the other hand, if it is necessary to form a common electrode 160 at the bottom of multiple LED stacks L, the common electrode 160 can be formed on the upper surface of the transparent layer 171 in the first processing step (S130). Here, if the light-emitting part 120 is in an n-side up configuration, the common electrode 160 can be formed as a negative electrode, and if the light-emitting part 120 is in a p-side up configuration, the common electrode 160 can be formed as a positive electrode.

[0109] Here, the common electrode 160 may be formed of a transparent conductive material similar to the ohmic contact electrode 124. When the common electrode 160 is the negative electrode, the material of the common electrode 160 may include TiN, CrN, VN, In2O3, SnO2, ZnO, IZO, ITO, and IGZO. When the common electrode 160 is the positive electrode, the material of the common electrode 160 may include NiO, PtO, PdO, AgO2, Au, Rh2O3, RuO2, In2O3, SnO2, ZnO, IZO, ITO, and IGZO.

[0110] The second processing step (S140) involves bonding a temporary wafer T to one side of the laminate, removing the support wafer S, and then forming a short passage 180 on the other side of the laminate.

[0111] Specifically, in the second processing stage (S140), the temporary wafer T is bonded to one side of the laminate, i.e., the transparent layer 171, through the bonding layer B. Then, the lower support wafer S is separated using laser lift-off or chemical lift-off, and the bonding layer B is removed.

[0112] In this case, if the laminate is stacked in an n-side-up configuration, ohmic contact electrodes 124 are provided on the upper and lower surfaces of the third light-emitting portion 123. However, if the laminate is stacked in a p-side-up configuration, n-type ohmic contact electrodes 124 are not formed on the third light-emitting portion. Therefore, n-type ohmic contact electrodes 124 are additionally formed on the exposed third light-emitting portion 123.

[0113] On the other hand, the temporary wafer T is preferably made of an optically transparent substrate such as sapphire or glass that can be easily separated by a laser lift-off (LLO) technique, and a sacrificial separation layer SL can be formed on the temporary wafer T, which is separated as a sacrifice when the temporary wafer T is removed using a laser lift-off (LLO) technique.

[0114] Such sacrificial isolation layer (SL) materials may include oxides or nitrides that can be deposited using PVD & CVD techniques such as sputtering rings, pulsed laser deposition (PLD), evaporators, MBE, MOCVD, and ALD. Specifically, these may include, but are not limited to, materials such as ITO, GaOx, GaON, GaN, InGaN, ZnO, InGaZnO, InZnO, or InGaO.

[0115] Subsequently, in the second processing stage (S140), first, the third light-emitting portion 123 in the area where the first LED stack L1 is formed and the area where the second LED stack L2 is formed are removed by etching together with the upper and lower ohmic contact electrodes 124, and are removed by etching until the second bonding layer 130b is exposed. Next, a through-hole is formed in the area where the first LED stack L1 is formed so as to penetrate the second light-emitting portion 122, and then a conductive material is filled into the through-hole to form a second short passage 182.

[0116] At this time, the through-hole may be formed to penetrate the active region 1203 of the second light-emitting part 122, and in particular, when the second junction layer 130b is formed of a transparent insulating material, it is desirable that the through-hole penetrates all of the second junction layer 130b between the third light-emitting part 123 and the second light-emitting part 122 and the second junction layer 130b between the second light-emitting part 122 and the first light-emitting part 121, until the surface of the ohmic contact electrode 124 of the first light-emitting part 121 is exposed.

[0117] Subsequently, in the second processing stage (S140), a conductive material is filled into the etched portion to form the first short passage 181.

[0118] At this time, after forming the first short passage 181, the substance may remain on the ohmic contact electrode 124 of the third light-emitting part 123 that has not been etched, or it may be removed. However, if the substance is left on the ohmic contact electrode 124 of the third light-emitting part 123, a residual layer 172 will be formed. It is also possible to fill the etched portion with a conductive material and then form the residual layer 172 with a different material.

[0119] Furthermore, the short passage 180 and the remaining layer 172 formed on the other side of the laminate can be made of a transparent conductive material or a reflective opaque conductive material, respectively.

[0120] When the short passage 180 and the remaining layer 172 are formed of a transparent conductive material, it is desirable that they be formed of a material having low resistance and high permeability. Such materials may include, but are not limited to, In2O3, SnO2, ZnO, IZO, ITO, and IGZO.

[0121] On the other hand, when the short passage 180 and the remaining layer 172 are formed of a transparent reflective material, it is desirable that they be formed of a material having low resistance and high reflectivity characteristics. Such materials can be provided by Ag, Al, Rh, etc., which have high reflectivity in a wide range of wavelengths, or by Cu, Au, etc., which have high reflectivity in a specific wavelength range. Furthermore, a laminated structure is also possible in which a thin adhesion-improving material such as Ti, Ni, Cr, or Pt is formed to improve the adhesion strength of the highly reflective material to a few nanometers or less, and by extension, it may be provided by alloys such as AgCu or AgNi, but is not limited thereto.

[0122] The etching step (S150) is a step in which multiple stacked LED stacks L are aligned on a temporary wafer T by etching the stacked multiple light-emitting parts 120, ohmic contact electrodes 124, and second bonding layer 130b into predetermined units and separating them, and through the etching step (S150), the first short passage 181 is formed to correspond to the width of the light-emitting parts 120.

[0123] On the other hand, the multiple LED stacks L include a first LED stack L1 for emitting only the first color, a second LED stack L2 for emitting only the second color, and a third LED stack L3 for emitting only the third color.

[0124] After the aforementioned etching step (S150), the first LED stack L1 includes a first short passage 181 formed in the third light-emitting part 123 after the third light-emitting part 123 has been removed, a second short passage 182 formed to penetrate the second light-emitting part 122, and the first light-emitting part 121. Current can be supplied only to the first light-emitting part 121 through the short passage 180, causing it to emit only the first color. If a transparent layer 171 is formed on the first light-emitting part 121, the transparent layer 171 can transmit the first color generated by the first light-emitting part 121.

[0125] Furthermore, the second LED stack L2 includes a first short passage 181 formed in the third light-emitting section 123 after the third light-emitting section 123 has been removed, a second light-emitting section 122, and a first short passage 181 formed in the first light-emitting section 121 after the first light-emitting section 121 has been removed. Current is supplied only to the second light-emitting section 122 through the short passage 180, allowing only the second color to be emitted.

[0126] Furthermore, the third LED stack L3 includes a third light-emitting section 123, a second short passage 182 formed to penetrate the second light-emitting section 122, and a first short passage 181 formed in the first light-emitting section 121 after the first light-emitting section 121 has been removed. Current can be supplied only to the third light-emitting section 123 through the short passage 180, causing only the third color to be emitted, and a residual layer 172 can be formed below the third light-emitting section 123.

[0127] Furthermore, the first light-emitting section 121 of the first LED stack L1 can be positioned above the second light-emitting section 122 of the second LED stack L2, and the second light-emitting section 122 of the second LED stack L2 can be positioned above the third light-emitting section 123 of the third LED stack L3.

[0128] The formation step (S160) is a step in which a mold portion 150 is formed to fill the spaces between a plurality of aligned LED stacks L and to serve as a passivation. The material of the mold portion 150 may include, but is not limited to, SiO2, SiNx, Al2O3, SOG, BCB, or organic matter.

[0129] On the other hand, if it is necessary to form a common electrode 160 on the upper part of multiple LED stacks L, the common electrode 160 can be formed on the upper surface of the remaining layer 172 during the formation stage (S160). Here, if the light-emitting part 120 is in an n-side up configuration, the common electrode 160 can be formed as a negative electrode, and if the light-emitting part 120 is in a p-side up configuration, the common electrode 160 can be formed as a positive electrode. Furthermore, the common electrode 160 can be formed from a material having transparent conductivity, similar to the ohmic contact electrode 124. When the common electrode 160 is a negative electrode, the material of the common electrode 160 can include TiN, CrN, VN, In2O3, SnO2, ZnO, IZO, ITO, and IGZO. When the common electrode 160 is a positive electrode, the material of the common electrode 160 can include NiO, PtO, PdO, AgO2, Au, Rh2O3, RuO2, In2O3, SnO2, ZnO, IZO, ITO, and IGZO.

[0130] From here on, with reference to the attached drawings, a vertically stacked red, green, and blue full-color chip-on-carrier 100 for a microLED display panel according to one embodiment of the present invention will be described in detail.

[0131] Figure 14 illustrates a vertically stacked red, green, and blue full-color chip-on-carrier for a microLED display panel according to one embodiment of the present invention; Figure 15 illustrates that a common electrode is formed on the upper part of multiple LED stacks of the vertically stacked red, green, and blue full-color chip-on-carrier for a microLED display panel according to one embodiment of the present invention; and Figure 16 illustrates that a common electrode is formed on the lower part of multiple LED stacks of the vertically stacked red, green, and blue full-color chip-on-carrier for a microLED display panel according to one embodiment of the present invention.

[0132] As shown in Figure 14, a vertically stacked red, green, and blue full-color chip-on-carrier 100 for a microLED display panel according to one embodiment of the present invention includes a temporary wafer T, a plurality of LED stacks L, and a molded portion 150.

[0133] In the following, some explanations will be omitted as they overlap with the method for manufacturing vertically stacked red, green, and blue full-color chip-on carriers for microLED display panels according to one embodiment of the present invention (S100).

[0134] The temporary wafer T has a laminate bonded to its upper surface via a bonding layer B. The material of the temporary wafer T can be either silicon (Si) or sapphire, but the choice of material can be determined by the wafer bonding method.

[0135] On the other hand, the temporary wafer T is preferably made of an optically transparent substrate such as sapphire or glass that can be easily separated by a laser lift-off (LLO) technique, and a sacrificial separation layer SL can be formed on the temporary wafer T, which is separated as a sacrifice when the temporary wafer T is removed using a laser lift-off (LLO) technique.

[0136] Such sacrificial separation layer (SL) materials can include oxides or nitrides that can be deposited using PVD & CVD techniques such as MBE, MOCVD, ALD, sputtering, PLD (pulsed laser deposition), and vaporizers. Specifically, these may include, but are not limited to, materials such as ITO, GaOx, GaON, GaN, InGaN, ZnO, InGaZnO, InZnO, or InGaO.

[0137] Each of the multiple LED stacks L is arranged on a temporary wafer T, with multiple light-emitting parts 120 stacked vertically in an n-side up or p-side up configuration via a second bonding layer 130b. The multiple LED stacks L include a first LED stack L1 for emitting only a first color, a second LED stack L2 for emitting only a second color, and a third LED stack L3 for emitting only a third color.

[0138] The first LED stack L1 includes a first short passage 181 formed to the width corresponding to the third light-emitting portion 123 after the third light-emitting portion 123 has been removed, a second short passage 182 formed to penetrate the second light-emitting portion 122, and the first light-emitting portion 121. Current can be supplied only to the first light-emitting portion 121 through the short passage 180 to cause only the first color to be emitted. If a transparent layer 171 is formed on the first light-emitting portion 121, the transparent layer 171 can transmit the first color generated by the first light-emitting portion 121.

[0139] Furthermore, the second LED stack L2 includes a first short passage 181 formed with a width corresponding to the third light-emitting section 123 after the third light-emitting section 123 has been removed, a second light-emitting section 122, and a first short passage 181 formed with a width corresponding to the first light-emitting section 121 after the first light-emitting section 121 has been removed. Current is supplied only to the second light-emitting section 122 through the short passage 180, allowing only the second color to be emitted.

[0140] Furthermore, the third LED stack L3 includes a third light-emitting section 123, a second short passage 182 formed to penetrate the second light-emitting section 122, and a first short passage 181 formed to a width corresponding to the first light-emitting section 121 after the first light-emitting section 121 has been removed. Current can be supplied only to the third light-emitting section 123 through the short passage 180 to emit only the third color, and a residual layer 172 can be formed below the third light-emitting section 123.

[0141] Furthermore, the first light-emitting section 121 of the first LED stack L1 can be positioned above the second light-emitting section 122 of the second LED stack L2, and the second light-emitting section 122 of the second LED stack L2 can be positioned above the third light-emitting section 123 of the third LED stack L3.

[0142] Furthermore, as shown in Figure 15, a common electrode 160 can be formed on the upper part of multiple LED stacks L, and as shown in Figure 16, a common electrode 160 can also be formed on the lower part of multiple LED stacks L.

[0143] Here, if the light-emitting part 120 is in an n-side-up configuration, the common electrode 160 may be formed as a negative electrode, and if the light-emitting part 120 is in a p-side-up configuration, the common electrode 160 may be formed as a positive electrode. Furthermore, the common electrode 160 may be formed from a material having transparent conductivity, similar to the ohmic contact electrode 124. When the common electrode 160 is the negative electrode, the material of the common electrode 160 can include TiN, CrN, VN, In2O3, SnO2, ZnO, IZO, ITO, and IGZO. When the common electrode 160 is the positive electrode, the material of the common electrode 160 can include NiO, PtO, PdO, AgO2, Au, Rh2O3, RuO2, In2O3, SnO2, ZnO, IZO, ITO, and IGZO.

[0144] The mold portion 150 fills the space between the aligned LED stacks L and acts as a passivation layer. The material of the mold portion 150 may include, but is not limited to, SiO2, SiNx, Al2O3, SOG, BCB, or organic materials.

[0145] According to the vertically stacked red, green, and blue full-color chip-on-carrier 100 of the present invention described above, a microLED display panel can be easily manufactured simply by bonding the vertically stacked red, green, and blue full-color chip-on-carrier 100 to a silicon (Si) CMOS or glass (Glass) TFT backplane wafer or the like.

[0146] Specifically, after bonding the manufactured vertically stacked red, green, and blue full-color chip-on-carrier 100 to the backplane wafer through the first bonding layer, the temporary wafer T is removed using techniques such as laser lift-off, and then the residual sacrificial isolation layer SL and bonding layer B are removed, thereby making it easier to manufacture microLED display panels.

[0147] Although all components constituting the embodiments of the present invention have been described as being either combined into one or operating in combination, the present invention is not necessarily limited to such embodiments. That is, within the scope of the objectives of the present invention, all components may be selectively combined into one or more units and operate in combination.

[0148] Furthermore, unless otherwise stated, terms such as "includes," "constitutes," or "possesses" used above mean that the relevant component may be inherent, and should be interpreted as including other components rather than excluding them. All terms, including technical or scientific terms, have the same meaning as generally understood by a person of ordinary skill in the art to which this invention belongs, unless otherwise defined. Commonly used terms, such as dictionary definitions, should be interpreted as corresponding to their meaning in the context of the relevant technology, and should not be interpreted in an ideal or overly formal sense unless explicitly defined in this invention.

[0149] Furthermore, the above explanation is merely illustrative in describing the technical concept of the present invention, and a person with ordinary skill in the art to which the present invention belongs can make various modifications and variations without departing from the essential characteristics of the present invention.

[0150] Therefore, the embodiments disclosed herein are for illustrative purposes only and not to limit the technical concept of the present invention, and the scope of the technical concept of the present invention is not limited by such embodiments. The scope of protection of the present invention should be interpreted in accordance with the following claims, and all technical concepts within an equivalent scope should be interpreted as being included within the scope of the rights of the present invention. [Explanation of Symbols]

[0151] 10: Conventional Microdisplay Panels 11: Si CMOS wafer 12: CMOS electrode pads 13: Transparent wafer 14: microLED electrode pads 15: microLED chip 16: Conductive junction S100: Method for manufacturing a vertically stacked red, green, and blue full-color chip-on-carrier for a microLED display panel according to one embodiment of the present invention S110: Preparation stage S120: Lamination stage S130: First processing stage S140: Second processing stage S150: Food preparation stage S160: Formation stage 100: Vertical stacked red, green, and blue full-color chip-on-carrier for microLED display panel according to one embodiment of the present invention 110, 210: Front wafer S: Support wafer 120: Light-emitting part 111, 211: First front wafer 121: First light-emitting section 112, 212: Second front wafer 122: Second light-emitting section 113, 213: Third front wafer 123: Third light-emitting section L:LED laminate L1: First LED stack L2: Second LED stack L3: Third LED stack 1201: First Semiconductor Area 1202: Second Semiconductor Area 1203:Active region 124: Ohmic contact electrode G: Growth wafer T: Temporary wafer SL: Sacrificial Separation Layer B: Bonding layer 130b: Second bonding layer 150: Mold part 160: Common electrode 171: Transparent layer 172: Residual layer 180: Short aisle 181: First Short Passage 182: Second Short Passage

Claims

1. Temporary wafers; and Each of the LED stacks includes a light-emitting portion stacked vertically through a bonding layer, and is arranged on the temporary wafer. Each of the multiple LED stacks is, By forming a short-circuit in a certain area, current is passed through the light-emitting part where the short-circuit is not formed, causing it to emit light of a specific color. The aforementioned short passage is A vertically stacked red, green, and blue full-color chip-on-carrier for a microLED display panel, comprising a first short passage formed to correspond to the width of the light-emitting portion and a second short passage formed to penetrate the light-emitting portion.

2. Multiple LED stacks, A vertically stacked red, green, and blue full-color chip-on-carrier for a microLED display panel according to claim 1, comprising a first LED stack including a first light-emitting part that emits a first color, a second LED stack including a second light-emitting part that emits a second color, and a third LED stack including a third light-emitting part that emits a third color.

3. The first LED stack is The first short passage formed in the third light-emitting portion, and the second short passage formed to penetrate the second light-emitting portion, The second LED stack is Including the first short passage formed in the third light-emitting portion and the first short passage formed in the first light-emitting portion, The third LED stack is The vertical stacked red, green, and blue full-color chip-on-carrier for a microLED display panel according to claim 2, comprising a second short passage formed to penetrate the second light-emitting portion and a first short passage formed in the first light-emitting portion.

4. The upper or lower part of the multiple LED stacks is A vertically stacked red, green, and blue full-color chip-on-carrier for a microLED display panel according to claim 1, wherein a common electrode is formed.

5. On the aforementioned temporary wafer, A vertically stacked red, green, and blue full-color chip-on-carrier for a microLED display panel according to claim 1, wherein a sacrificial separation layer is formed.

6. A preparation stage in which multiple front wafers containing a support wafer and a light-emitting section are prepared; A lamination step in which a plurality of light-emitting portions are vertically stacked on a support wafer by repeatedly bonding one front wafer onto one front wafer through a bonding layer and then removing the support wafer of the other front wafer; A first processing step of forming a short passage on one surface of the laminate; A second processing step involves bonding a temporary wafer to one surface of the laminate, removing the support wafer, and then forming the short passage on the other surface of the laminate; and The process includes a cutting step in which the laminate is cut and separated into predetermined units, thereby aligning multiple LED laminates on the temporary wafer. Each of the multiple LED stacks is, By forming a short passage in a certain area, current is passed through the light-emitting part where the short passage is not formed, causing it to emit only a specific color. The aforementioned short passage is A method for manufacturing a vertically stacked red, green, and blue full-color chip-on-carrier for a microLED display panel, comprising a first short passage formed to correspond to the width of the light-emitting portion and a second short passage formed to penetrate the light-emitting portion.

7. Multiple LED stacks, A method for manufacturing a vertically stacked red, green, and blue full-color chip-on-carrier for a microLED display panel according to claim 6, comprising a first LED stack including a first light-emitting part that emits a first color, a second LED stack including a second light-emitting part that emits a second color, and a third LED stack including a third light-emitting part that emits a third color.

8. The first LED stack is The first short passage formed in the third light-emitting portion, and the second short passage formed to penetrate the second light-emitting portion, The second LED stack is Including the first short passage formed in the third light-emitting portion and the first short passage formed in the first light-emitting portion, The third LED stack is A method for manufacturing a vertically stacked red, green, and blue full-color chip-on-carrier for a microLED display panel according to claim 7, comprising a second short passage formed to penetrate the second light-emitting portion and a first short passage formed in the first light-emitting portion.

9. The upper or lower part of the multiple LED stacks is A method for manufacturing vertically stacked red, green, and blue full-color chip-on carriers for microLED display panels according to claim 6, wherein a common electrode is formed.

10. On the aforementioned temporary wafer, A method for manufacturing vertically stacked red, green, and blue full-color chip-on-carriers for microLED display panels according to claim 6, wherein a sacrificial separation layer is formed.

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