Semiconductor module and method for manufacturing the same

Abstract

To improve the performance of semiconductor modules. [Solution] The semiconductor module 100 includes a semiconductor die 10, a semiconductor die 20, a bridge chip 30, a plurality of external terminals 40, a bridge-side sealant 51 that seals the bridge chip 40 and the plurality of external terminals 40, and a conductor layer 60 formed on the bridge-side sealant 51. The conductor layer 60 includes a connection portion 61 electrically connected to the die electrode 11A of the semiconductor die 10 and the bridge electrode 31A of the bridge chip 30, a connection portion 62 electrically connected to the die electrode 21B of the semiconductor die 20 and the bridge electrode 31B of the bridge chip 30, and a bridge wiring 63 electrically connected to the bridge electrode 31C of the bridge chip 30 and a portion of the plurality of external terminals 40.

Description

Technical Field

[0001] The present invention relates to a semiconductor module and a method for manufacturing the same.

Background Art

[0002] There is a technology for connecting a plurality of IC (Integrated Circuit) chips. For example, Patent Document 1 (International Publication No. 2023 / 022179) describes a semiconductor module in which two IC chips are electrically connected via a bridge chip. The semiconductor module is electrically connected to the electrodes of the IC chip via columnar connection portions. Also, for example, Patent Document 2 (U.S. Patent Application Publication No. 2021 / 0210423) describes an example in which two IC chips are electrically connected via an interposer (wiring board) or a TSV (Through Silicon Via). The electrodes of the IC chip are electrically connected to the external terminals of the module via the TSV.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the case of a semiconductor module in which a plurality of external terminals of the semiconductor module are electrically connected only to an IC chip via columnar connection conductors, the region where the external terminals can be arranged is restricted to only the region facing the IC chip and not facing the bridge chip.

[0005] On the other hand, when using a bridge chip with a TSV (Total Slip Differential) or a wiring board acting as an interposer to connect two IC chips, there is the advantage of being able to place external terminals opposite the bridge chip or interposer. However, using a bridge chip with a TSV or a wiring board for an interposer complicates the manufacturing process, which presents challenges from the perspective of manufacturing efficiency or manufacturing cost. [Means for solving the problem]

[0006] A semiconductor module according to one embodiment includes a first semiconductor die having a first die electrode, a second semiconductor die having a second die electrode, a bridge chip having a first bridge electrode electrically connected to the first die electrode, a second bridge electrode electrically connected to the second die electrode, and a third bridge electrode, a plurality of external connection conductors, a first encapsulant that encapsulates the bridge chip and the plurality of external connection conductors, and a conductor layer formed on the first encapsulant. The first semiconductor die and the second semiconductor die are each exposed from the first encapsulant. The conductor layer includes a first connection portion electrically connected to the first die electrode and the first bridge electrode, a second connection portion electrically connected to the second die electrode and the second bridge electrode, and a bridge wiring electrically connected to the third bridge electrode and a portion of the plurality of external connection conductors.

[0007] A method for manufacturing a semiconductor module according to another embodiment includes: (a) forming a conductor layer including a first connection portion, a second connection portion, and bridge wiring on a support; (b) electrically connecting the first die electrode of a first semiconductor die to the first connection portion; (c) electrically connecting the second die electrode of a second semiconductor die to the second connection portion; (d) sealing the first semiconductor die, the second semiconductor die, and the conductor layer with an insulating material to form a die-side seal; (e) peeling the support from the die-side seal; (f) forming an external connection conductor on the exposed surface of the bridge wiring; (g) electrically connecting the conductor layer and the bridge chip; and (h) sealing the external connection conductor and the bridge chip with an insulating material to form a bridge-side seal. The bridge chip has a first bridge electrode, a second bridge electrode, and a third bridge electrode. In step (g), the first connection part and the first bridge electrode, the second connection part and the second bridge electrode, and the bridge wiring and the third bridge electrode are electrically connected, respectively. [Effects of the Invention]

[0008] According to the above embodiment, the performance of the semiconductor module can be improved. [Brief explanation of the drawing]

[0009] [Figure 1] This is an explanatory diagram showing an example configuration of a semiconductor module according to one embodiment. [Figure 2] Figure 1 is a plan view showing an example of the mounting side of a semiconductor module. [Figure 3] This is a cross-sectional view along line AA in Figure 2. [Figure 4] Figure 3 is a plan view showing an example of a conductor layer layout including bridge wiring. [Figure 5] Figure 3 shows an enlarged cross-sectional view of the conductor layer, specifically the connection point that electrically connects the bridge chip to one of the semiconductor dies, and the area around the bridge wiring. [Figure 6]Of the conductor layers shown in FIG. 3, it is an enlarged cross-sectional view of a connection portion that electrically connects a bridge chip and the other semiconductor die, and the periphery of the bridge wiring. [Figure 7] It is a plan view showing an example of the layout of a plurality of bridge-side columnar electrodes shown in FIG. 3. [Figure 8] It is a plan view showing an example of the layout of a plurality of die-side columnar electrodes shown in FIG. 3. [Figure 9] It is a plan view showing an example of the layout of the internal wiring in the first layer among the plurality of wiring layers of the bridge chip shown in FIG. 5. [Figure 10] It is a plan view showing an example of the layout of the internal wiring in the second layer among the plurality of wiring layers of the bridge chip shown in FIG. 5. [Figure 11] It is an explanatory view showing an outline of the manufacturing process of the semiconductor module shown in FIGS. 1 to 4. [Figure 12] It is an enlarged cross-sectional view showing the details of the conductor layer forming process shown in FIG. 11. [Figure 13] It is an enlarged cross-sectional view showing the details of the conductor layer forming process following FIG. 12. [Figure 14] It is an enlarged cross-sectional view showing the details of the conductor layer forming process following FIG. 13. [Figure 15] It is an enlarged cross-sectional view showing the details of the conductor layer forming process following FIG. 14. [Figure 16] It is an enlarged cross-sectional view showing the details of the conductor layer forming process following FIG. 15. [Figure 17] It is an enlarged cross-sectional view showing the details of the semiconductor die mounting process shown in FIG. 11. [Figure 18] It is an enlarged cross-sectional view showing the details of the semiconductor die mounting process following FIG. 17. [Figure 19] It is an enlarged cross-sectional view showing the details of the first encapsulation process shown in FIG. 11. [Figure 20] It is an enlarged cross-sectional view showing the details of the first support removal process shown in FIG. 11. [Figure 21] It is an enlarged cross-sectional view showing a state where the conductor layer shown in FIG. 20 is exposed from the die-side encapsulant. [Figure 22]It is an enlarged cross-sectional view showing details of the second support mounting process shown in FIG. 11. [Figure 23] It is an enlarged cross-sectional view showing details of the external connection conductor forming process shown in FIG. 22. [Figure 24] It is an enlarged cross-sectional view showing details of the external connection conductor forming process following FIG. 23. [Figure 25] It is an enlarged cross-sectional view showing details of the external connection conductor forming process following FIG. 24. [Figure 26] It is an enlarged cross-sectional view showing details of the external connection conductor forming process following FIG. 25. [Figure 27] It is an enlarged cross-sectional view showing details of the external connection conductor forming process following FIG. 26. [Figure 28] It is an enlarged cross-sectional view showing details of the bridge mounting process shown in FIG. 11. [Figure 29] It is an enlarged cross-sectional view showing details of the bridge mounting process following FIG. 28. [Figure 30] It is an enlarged cross-sectional view showing details of the second sealing process shown in FIG. 11. [Figure 31] It is an enlarged cross-sectional view showing the semiconductor module after the second support removal process shown in FIG. 11. [Figure 32] It is an enlarged plan view showing a modified example of the connection structure between the die-side columnar electrode or bridge-side columnar electrode shown in FIG. 5 and the bridge wiring. [Figure 33] It is an enlarged cross-sectional view showing a modified example of the portion where the conductor layer shown in FIG. 3 is connected to the external terminal.

Embodiments for Carrying Out the Invention

[0010] (Explanation of the description format, basic terms, and usage in this application) In this application, descriptions of embodiments are divided into multiple sections for convenience as needed, but unless otherwise explicitly stated, these are not independent or separate entities. Rather, regardless of the order of the descriptions, they are all parts of a single example, or variations of one part or all of the other, such as a detail of the other. Furthermore, as a general rule, repeated explanations of similar parts are omitted. In addition, each component in an embodiment is not essential unless otherwise explicitly stated, such as when its number is theoretically limited or when it is clearly not the case from the context.

[0011] In each figure of the embodiment, identical or similar parts are indicated by the same or similar symbols or reference numbers, and descriptions are generally not repeated.

[0012] In the following explanation, the term "main component" may be used when describing the metallic elements that make up the metal layer. For example, "a metal layer containing copper as the main component" means that the metallic material constituting the metal layer contains at least 90% by weight, preferably 99% by weight or more, of copper.

[0013] Furthermore, when explaining the metallic elements that make up a metal layer, the term "weight percentage" is sometimes used. "Weight percentage of an element" is the value obtained by dividing the weight of the element in question per unit volume by the total weight per unit volume. For example, "weight percentage of silver in component A" is the value obtained by dividing the weight of silver contained in part (or all) of component A by the weight of that part (or all) of component A. Similarly, "weight percentage of silver particles in component A" is the value obtained by dividing the weight of silver particles contained in part (or all) of component A by the weight of that part (or all) of component A.

[0014] Furthermore, the following explanation may use the terms X, Y, and Z directions. For example, Figure 2, described later, shows the X and Y directions. The X and Y directions intersect each other. In the example described below, the X direction is perpendicular to the Y direction. Below, the XY plane, which includes the X and Y directions, will be described as a plane parallel to the main surface of the wiring board.

[0015] Furthermore, surfaces that intersect the XY plane (for example, surfaces parallel to the XZ plane containing the X and Z directions, and surfaces parallel to the YZ plane containing the Y and Z directions) are called sides. In the following explanation, unless otherwise explicitly stated, "planar view" means viewing a surface parallel to the XY plane. Also, the direction normal to the XY plane will be explained as the "Z direction" or thickness direction. "Thickness" and "height" mean the length in the "Z direction" unless otherwise explicitly stated. The X, Y, and Z directions are directions that intersect each other, and more specifically, directions that are orthogonal to each other.

[0016] <Semiconductor Module> Figure 1 is an explanatory diagram showing an example of the configuration of a semiconductor module according to one embodiment. Figure 2 is a plan view showing an example of the mounting side of the semiconductor module shown in Figure 1. In Figure 2, the outlines of the semiconductor die 10, semiconductor die 20, bridge chip 30, and multiple external terminals 40 shown in Figure 1 are shown with dotted lines to indicate their planar positional relationship.

[0017] Figure 3 is a cross-sectional view along line AA in Figure 2. Of the multiple internal wirings 32 shown in Figure 3, internal wiring 32C may exist in a cross-sectional view different from the cross-sectional view along line AA in Figure 2. However, in Figure 3, in order to show that there are multiple types of internal wirings 32 in a single drawing, die electrode 11C, die electrode 21C, and internal wiring 32C are illustrated.

[0018] Figure 4 is a plan view showing an example of the layout of a conductor layer including the bridge wiring shown in Figure 3. In Figure 4, the contours of the semiconductor die 10, semiconductor die 20, bridge chip 30, and multiple external terminals 40 are shown with dotted lines to show the planar positional relationship between the multiple conductor patterns (metal patterns) constituting the conductor layer 60 and the semiconductor die 10, semiconductor die 20, bridge chip 30, and multiple external terminals 40. Also in Figure 4, the contours of the multiple bridge-side columnar electrodes 80 that electrically connect the bridge chip 30 and the conductor layer 60 shown in Figure 3 are shown with dotted lines.

[0019] In this embodiment, for the sake of clarity, we will describe a semiconductor module 100 comprising two semiconductor dies (semiconductor die 10 and semiconductor die 20) and one bridge chip 30. However, as a variation of this embodiment, the semiconductor module may be equipped with three or more semiconductor dies. Also, the semiconductor module may be equipped with two or more bridge chips 30.

[0020] As shown in Figure 1, the semiconductor module 100 includes a semiconductor die 10, a semiconductor die 20, and a bridge chip 30. The semiconductor die 10 and the semiconductor die 20 are electrically connected to each other via the bridge chip 30. In addition, the semiconductor die 10 and the semiconductor die 20 are each electrically connected to an external terminal 40.

[0021] Furthermore, in the semiconductor module 100 according to this embodiment, some of the multiple external terminals 40 are electrically connected to the semiconductor die 10 and the semiconductor die 20 via the bridge chip 30. In other words, the multiple external terminals 40 include an external terminal 41 connected to the semiconductor die 10 without going through the bridge chip 30, an external terminal 42 connected to the semiconductor die 20 without going through the bridge chip 30, and an external terminal 43 connected to the semiconductor die 10 or the semiconductor die 20 via the bridge chip 30.

[0022] Next, the planar positional relationship of the semiconductor die 10, semiconductor die 20, and bridge chip 30 will be explained using Figure 2. As shown in Figure 2, the semiconductor die 10 and semiconductor die 20 are arranged adjacent to each other. The semiconductor die 10 and semiconductor die 20 do not overlap with each other and are separated. A portion of the bridge chip 30 overlaps with the semiconductor die 10. Another portion of the bridge chip 30 overlaps with the semiconductor die 20. The bridge chip 30 is a component for electrically connecting the semiconductor die 10 and the semiconductor die 20, and therefore it overlaps with both the semiconductor die 10 and the semiconductor die 20.

[0023] More specifically, in a plan view, the bridge chip 30 has edge 30s1, edge 30s2 opposite edge 30s1, edge 30s3 intersecting edges 30s1 and 30s2 respectively, and edge 30s4 opposite edge 30s3. Of the multiple edges of the bridge chip 30, edges 30s1 and 30s2 each overlap with both semiconductor die 10 and semiconductor die 20. In other words, edges 30s1 and 30s2 each extend across semiconductor die 10 and semiconductor die 20. On the other hand, edge 30s3 overlaps with semiconductor die 10 but does not overlap with semiconductor die 20. Also, edge 30s4 overlaps with semiconductor die 20 but does not overlap with semiconductor die 10.

[0024] Next, the planar positional relationship between the multiple external terminals 40 and the semiconductor die 10, semiconductor die 20, and bridge chip 30 will be described. Some of the multiple external terminals 40 (external terminals 41) are positioned in a location that overlaps with the semiconductor die 10. Also, some of the multiple external terminals 40 (external terminals 42) are positioned in a location that overlaps with the semiconductor die 20. On the other hand, no external terminals 40 are positioned in a location that overlaps with the bridge chip 30.

[0025] The bridge chip 30 in this embodiment does not have a through-conductor (TSV) that penetrates from one of the upper and lower surfaces of the bridge chip 30 to the other. Furthermore, as will be described later, the bridge chip 30 is a component with internal wiring and electrodes formed on a semiconductor substrate, and is different from a so-called interposer wiring board. For this reason, the multiple external terminals 40 are not arranged in an area that overlaps with the bridge chip 30.

[0026] In this embodiment, as shown in Figure 2, the external terminals 43 connected to the semiconductor die 10 or semiconductor die 20 via the bridge chip 30 are positioned so as not to overlap with either the semiconductor die 10 or the semiconductor die 20. However, if multiple external terminals 43 are formed, some of the multiple external terminals 43 may be positioned so as to overlap with either the semiconductor die 10 or the semiconductor die 20.

[0027] If all of the multiple external terminals 40 are connected to either the semiconductor die 10 or the semiconductor die 20, the area in which the external terminals 40 can be placed is limited to an area that overlaps with either the semiconductor die 10 or the semiconductor die 20, but does not overlap with the bridge chip 30. In other words, the number of external terminals 40 that can be placed is limited by the area of ​​the semiconductor die 10, the area of ​​the semiconductor die 20, and the area of ​​the bridge chip 30.

[0028] On the other hand, in this embodiment, as already described, among the multiple external terminals 40, external terminal 43 can be positioned in a location that does not overlap with the semiconductor die 10 and the semiconductor die 20, respectively. Therefore, the number of external terminals 40 that can be positioned can be increased.

[0029] Next, using Figure 3, we will describe a structure that enables the electrical connection of the semiconductor die 10 or semiconductor die 20 and the external terminal 40 via the bridge chip 30.

[0030] As shown in Figure 3, the semiconductor module 100 includes a semiconductor die 10, a semiconductor die 20, a bridge chip 30, an external terminal (external connection conductor) 40, a encapsulant 51, and a conductor layer 60. In the example shown in Figure 3, the semiconductor module 100 further includes a encapsulant 52.

[0031] The semiconductor die 10 has a plurality of die electrodes 11. The plurality of die electrodes 11 include a die electrode 11A directly connected to an external terminal 40 via a conductor layer 60, a die electrode 11B connected to an external terminal 40 via a conductor layer 60, a bridge chip 30 and bridge wiring 63, and a die electrode 11C connected to a die electrode 21 of the semiconductor die 20 via a conductor layer 60 and a bridge chip 30.

[0032] The semiconductor die 20 has a plurality of die electrodes 21. The plurality of die electrodes 21 include a die electrode 21A directly connected to an external terminal 40 via a conductor layer 60, a die electrode 21B connected to an external terminal 40 via a conductor layer 60, a bridge chip 30 and bridge wiring 63, and a die electrode 21C connected to a die electrode 11 of the semiconductor die 10 via a conductor layer 60 and a bridge chip 30.

[0033] Each of the semiconductor die 10 and semiconductor die 20 includes a semiconductor substrate, such as silicon, and circuit elements such as transistors and diodes. Various integration configurations are possible for the circuit elements of each of the semiconductor die 10 and semiconductor die 20. For example, the circuit elements may be formed two-dimensionally or three-dimensionally on the main surfaces of each of the semiconductor die 10 and semiconductor die 20. Alternatively, a structure may be formed in which multiple semiconductor substrates are stacked, and the circuit elements formed on each of the multiple semiconductor substrates are electrically connected to each other via TSVs.

[0034] The bridge chip 30 has a plurality of bridge electrodes 31. The plurality of bridge electrodes 31 include a bridge electrode 31A electrically connected to the die electrode 11, a bridge electrode 31B electrically connected to the die electrode 21, and a bridge electrode 31C electrically connected to the bridge wiring 63.

[0035] The encapsulant (bridge-side encapsulant) 51 has an upper surface 51t facing the lower surface 52b of the encapsulant (die-side encapsulant) 52, and a lower surface 51b on the opposite side of the upper surface 51t. Each of the bridge chip 30 and the plurality of external terminals 40 is sealed by the encapsulant 51. Each of the semiconductor die 10 and the semiconductor die 20 is exposed from the encapsulant 51.

[0036] In the example shown in Figure 3, the semiconductor die 10, the semiconductor die 20, and the conductive layer 60 are each sealed by a sealant 52. The sealant 52 has an upper surface 52t and a lower surface 52b opposite to the upper surface 52t.

[0037] Each of the sealants 51 and 52 may be made of a resin material, such as a thermosetting resin. Each of the sealants 51 and 52 may contain a large number of inorganic filler particles in the resin.

[0038] In the example shown in Figure 3, the multiple external terminals 40 are through conductors formed to penetrate from one of the upper surface 51t and lower surface 51b of the sealant 51 to the other. Therefore, the upper surface of the external terminals 40 is exposed from the sealant 51 at the upper surface 51t of the sealant 51, and the lower surface of the external terminals 40 is exposed from the sealant 51 at the lower surface 51b of the sealant 51.

[0039] As will be described later, in the manufacturing method of the semiconductor module 100, each of the multiple external terminals 40 is formed in advance before the encapsulation body 51 is formed. In this case, compared to a forming method in which through holes are formed in a substrate (e.g., a silicon substrate) and then conductors are embedded in the through holes, as in the manufacturing method of TSV, the multiple external terminals 40 can be formed more easily.

[0040] Although not shown in Figure 3, there are cases where solder balls are formed on the underside of multiple external terminals 40, exposing them from the sealant 51.

[0041] Furthermore, as shown in Figure 3, the conductive layer 60 is formed on the upper surface 51t of the sealant 51. The conductive layer 60 consists of a metal film formed on the upper surface 51t of the sealant 51 and contains a plurality of conductive patterns (metal patterns). The conductive layer 60 is made of a metal material mainly composed of copper, for example. The conductive layer 60 is formed by, for example, a plating method, as will be described later.

[0042] The conductor layer 60 includes connection parts 61 electrically connected to the die electrode 11 and the bridge electrode 31A, connection parts 62 electrically connected to the die electrode 21 and the bridge electrode 31B, and bridge wiring 63 electrically connected to the bridge electrode 31C and some of the multiple external terminals 40 (external terminals 43 shown in Figures 1 and 2).

[0043] In the example shown in Figure 4, the connection parts 61 and 62 form a circle in plan view. The planar shape of the connection parts 61 and 62 can be modified in various ways, such as to be a polygon with more than four sides, in addition to a circle. The connection parts 61 and 62 are formed together with the bridge wiring 63. Therefore, as shown in Figure 3, the thickness of the connection parts 61 and 62 is equal to the thickness of the bridge wiring 63. Each of the connection parts 61 and 62 is a columnar conductor of μm size (also called a "micropillar").

[0044] Furthermore, the conductor layer 60 has a single-layer structure, with multiple die-side columnar electrodes 70 connected to one side of the conductor layer 60 and multiple bridge-side columnar electrodes 80 connected to the other side of the conductor layer 60. This structure, in which the semiconductor die 10 and the bridge chip 30 are electrically connected via micropillars (e.g., connection parts 61) without the use of an interposer, is called a PSB (Pillar Suspended Bridge) structure.

[0045] The conductor layer 60 is distinguished from a wiring board with multiple wiring layers, known as an interposer substrate, by being a conductor layer consisting of multiple metal patterns formed on the same layer. Since the conductor layer 60 has a single-layer structure, it can be manufactured using a simple process.

[0046] In the simplest PSB structure, no wiring pattern is formed on the conductor layer 60, and all of the multiple conductor patterns provided on the conductor layer 60 form the shapes of the connection parts 61 and 62 shown in Figure 4. This embodiment differs from the simplest PSB structure described above in that the conductor layer 60 further includes bridge wiring 63.

[0047] Furthermore, as shown in Figure 4, the width of each of the multiple bridge wirings 63 (length in the direction perpendicular to the extension direction) is greater than the diameter of each of the multiple connection parts 61. Also, the width of each of the multiple bridge wirings 63 is greater than the diameter of each of the multiple connection parts 62. Because the width of the multiple bridge wirings 63 is wide, the margin that can be allowed when processing the pattern of the multiple bridge wirings 63 can be widened compared to when fine wiring is routed in the conductor layer 60. As a result, the process of forming the conductor layer 60 can be simplified.

[0048] The bridge wiring 63 is a conductor pattern (metal pattern) placed on the encapsulant 51. As shown in Figure 3, the bridge wiring 63 is electrically connected to one or both of the semiconductor die 10 and semiconductor die 20 via the bridge chip 30. The bridge wiring 63 is not directly connected to either the semiconductor die 10 or the semiconductor die 20 (in other words, not via a conductive path through the bridge chip 30).

[0049] As shown in Figure 4, the bridge wiring 63 has a region facing the bridge chip 30 and a region not facing the bridge chip 30, and extends in the Y direction so as to straddle the bridge chip 30. Among the multiple external terminals 40, external terminal 43 is located in the direction of extension of the bridge wiring 63.

[0050] The external terminal 43 is connected to the bridge wiring 63 without going through the semiconductor die 10 and semiconductor die 20. Therefore, as shown in Figures 2 and 4, the external terminal 43 is positioned so as not to overlap with the semiconductor die 10 and semiconductor die 20.

[0051] In other words, according to this embodiment, since some of the multiple external terminals 40 are connected to the bridge wiring 63, the external terminals 40 can be positioned in a location that does not overlap with the semiconductor die 10 and the semiconductor die 20, as shown in Figure 2.

[0052] Furthermore, the bridge wiring 63 is a conductor pattern (metal pattern) arranged on the encapsulant 51. Therefore, the manufacturing process can be simplified compared to a semiconductor module manufacturing method in which an interposer substrate is interposed between the bridge chip 30 and the semiconductor die 10 (or semiconductor die 20), or a semiconductor module manufacturing method that includes a step of forming a TSV on the bridge chip 30.

[0053] As shown in Figure 4, in plan view, the outer edge of the bridge tip 30 includes side 30s1 and side 30s2 opposite to side 30s1. In plan view, the bridge wiring 63 extends across both sides 30s1 and 30s2. The multiple external terminals 40 include external terminals (external connection conductors) 43A located closer to side 30s1 than side 30s2 of the bridge tip 30 and connected to the bridge wiring 63, and external terminals (external connection conductors) 43B located closer to side 30s2 than side 30s1 of the bridge tip 30 and connected to the bridge wiring 63.

[0054] In other words, the bridge wiring 63 extends so as to project outwards from the sides of edge 30s1 and edge 30s2 in a plan view. External terminal 43A is located outside edge 30s1, and external terminal 43B is located outside edge 30s2. External terminals 43A and 43B are electrically connected to each other via the bridge wiring 63.

[0055] Furthermore, in the example shown in Figure 4, external terminals 43A and 43B are positioned so as not to overlap with the semiconductor die 10, semiconductor die 20, and bridge chip 30, respectively. Therefore, the total number of external terminals 40 can be increased compared to the case where external terminals 40 are simply placed only in areas that overlap with the semiconductor die 10 or semiconductor die 20.

[0056] As shown in Figure 4 as an external terminal (external connection conductor) 43C, multiple external terminals 40 may include an external terminal 43C that is connected to the bridge wiring 63 and positioned in a location overlapping with the semiconductor die 20. In this way, even when an external terminal 43C is included, the total number of external terminals 40 can be increased if there is an external terminal 43A or external terminal 43B that is positioned in a location that does not overlap with the semiconductor die 10, semiconductor die 20, and bridge chip 30, and is connected to the bridge wiring 63.

[0057] Incidentally, while the bridge wiring 63 according to this embodiment can be used as wiring for signal transmission, it is particularly preferable to use it as wiring for supplying a reference potential or power supply potential to either one or both of the semiconductor die 10 and the semiconductor die 20.

[0058] More specifically, as shown in Figure 1, semiconductor die 10 has circuit 10C. Semiconductor die 20 has circuit 20C. Power is required to operate circuits 10C and 20C. The power supply potential and reference potential for driving circuit 10C and circuit 20C are supplied from outside the semiconductor module 100, respectively.

[0059] From the viewpoint of stabilizing the operation of circuits 10C and 20C, it is preferable that the cross-sectional area of ​​the power supply potential supply path and the cross-sectional area of ​​the reference potential supply path are both large.

[0060] As shown in Figure 4, in this embodiment, multiple external terminals 43A (and external terminals 43B) are connected to a single bridge wiring 63. By supplying a common potential (power supply potential or reference potential) to these multiple external terminals 43A (and external terminals 43B), the path cross-sectional area of ​​each potential can be increased.

[0061] Furthermore, the reference potential is, for example, the ground potential, and a common (in other words, the same potential) reference potential is supplied to both circuits 10C and 20C shown in Figure 1. Therefore, the bridge wiring 63 for supplying the reference potential may be electrically connected to both semiconductor die 10 and semiconductor die 20.

[0062] In some cases, a common (or in other words, the same) power supply potential may be supplied to both circuit 10C and circuit 20C. In this case, the bridge wiring 63 that supplies the common power supply potential is electrically connected to both semiconductor die 10 and semiconductor die 20.

[0063] On the other hand, if the power supply potential supplied to circuit 10C and the power supply potential supplied to circuit 20C are at different potentials, the bridge wiring 63 for supplying the power supply potential to circuit 10C and the bridge wiring 63 for supplying the power supply potential to circuit 20C must be electrically isolated. In this case, some of the multiple bridge wirings 63 shown in Figure 4 (for example, the bridge wiring 63 that supplies the power supply potential to circuit 10C shown in Figure 1) are electrically connected to the semiconductor die 10 and electrically isolated from the semiconductor die 20. In addition, other parts of the multiple bridge wirings 63 shown in Figure 4 (for example, the bridge wiring 63 that supplies the power supply potential to circuit 20C shown in Figure 1) are electrically connected to the semiconductor die 20 and electrically isolated from the semiconductor die 10.

[0064] Of the multiple external terminals 40, if external terminals 43A and 43B connected to the bridge wiring 63 are external terminals 40 for supplying power potential or reference potential, the other external terminals can be used, for example, as external terminals for signal transmission. For example, the external terminals (external connection conductors) 44 shown in Figures 2 and 4 are connected to the semiconductor die 20 without going through the bridge wiring 63. Since the semiconductor die 20 can be supplied with power potential or reference potential via the bridge wiring 63 and wiring 65 (details will be described later), each of the multiple external terminals 44 can be used as a terminal for signal transmission.

[0065] The bridge chip 30 has a plurality of internal wirings 32, as already described in Figures 1 and 3. The plurality of internal wirings 32 include internal wiring 32A connected to bridge electrodes 31A and 31C respectively, internal wiring 32B connected to bridge electrodes 31B and 31C respectively, and internal wiring 32C connected to bridge electrodes 31A and 31B respectively.

[0066] The primary function of the bridge chip 30 is to electrically connect the semiconductor die 10 and the semiconductor die 20. Of the multiple internal wirings 32 shown in Figure 1, internal wiring 32C is the internal wiring that performs the primary function described above.

[0067] On the other hand, among the multiple internal wirings 32, internal wiring 32A is an internal wiring that has the function of electrically connecting the semiconductor die 10 and the external terminal 43 via the bridge chip 30. Similarly, internal wiring 32B is an internal wiring that has the function of electrically connecting the semiconductor die 20 and the external terminal 43 via the bridge chip 30.

[0068] Because the bridge chip 30 is equipped with internal wiring 32A and internal wiring 32B in addition to internal wiring 32C, the number of external terminals 40 per unit area on the lower surface 51b of the encapsulant 51 shown in Figure 2 can be increased.

[0069] Furthermore, in the examples shown in Figures 3 and 4, the conductor layer 60 further includes wiring 64, which is positioned between the first semiconductor die and the external terminals 41 of the plurality of external terminals 40 and is electrically connected to the die electrode 11 and the external terminals 41 respectively, and wiring 65, which is positioned between the second semiconductor die and the external terminals 42 of the plurality of external terminals 40 and is electrically connected to the second die electrode and the external terminals 42 respectively.

[0070] The wiring 64 is a conductor pattern (metal pattern) placed on the encapsulant 51. The wiring 64 is formed together with the bridge wiring 63. Therefore, the thickness of the wiring 64 is equal to the thickness of the bridge wiring 63. As shown in Figure 3, the wiring 64 is electrically connected to the semiconductor die 10 without going through the bridge chip 30. As shown in Figure 4, the wiring 64 extends in the direction of extension of the bridge wiring 63 (the Y direction in the example of Figure 4). Among the multiple external terminals 40, external terminal 41 is arranged in the direction of extension of the wiring 64.

[0071] The wiring 65 is a conductor pattern (metal pattern) placed on the encapsulant 51. The wiring 65 is formed together with the bridge wiring 63. Therefore, the thickness of the wiring 65 is equal to the thickness of the bridge wiring 63. As shown in Figure 3, the wiring 65 is electrically connected to the semiconductor die 20 without going through the bridge chip 30. As shown in Figure 4, the wiring 65 extends in the direction of extension of the bridge wiring 63 (the Y direction in the example of Figure 4). Among the multiple external terminals 40, external terminal 42 is arranged in the direction of extension of the wiring 65.

[0072] Each of the wires 64 and 65 is connected to a plurality of external terminals 40. Therefore, it is preferable to use wire 64 as a wire to supply power potential or reference potential to circuit 10C shown in Figure 1. It is also preferable to use wire 65 as a wire to supply power potential or reference potential to circuit 20C shown in Figure 1.

[0073] However, as a modification of this embodiment, some of the multiple wirings 64 and multiple wirings 65 may be used as wiring for signal transmission.

[0074] In the example shown in Figure 4, each of the multiple external terminals 41 is connected to one of the multiple wirings 64, and each of the multiple external terminals 42 is connected to one of the multiple wirings 65.

[0075] However, as a modification, an opening may be formed in a part of the wiring 64 or wiring 65, similar to the structure of the connection part 61 shown as an enlarged view in Figure 4, and a circular connection part (not shown) may be provided within the opening. In this case, the connection part provided within the opening of wiring 64 can connect the external terminal 41 to the die electrode 11 of the semiconductor die 10 shown in Figure 3 on a one-to-one basis. Similarly, the connection part provided within the opening of wiring 65 can connect the external terminal 42 to the die electrode 21 of the semiconductor die 20 shown in Figure 3 on a one-to-one basis. Such a structure is effective for application to signal transmission paths.

[0076] As shown in Figure 4, bridge wiring 63 is wiring connected to the bridge chip 30. On the other hand, wiring 64 is wiring connected to the semiconductor die 10, and wiring 65 is wiring connected to the semiconductor die 20. Therefore, in a plan view, bridge wiring 63 is positioned between wiring 64 and wiring 65. This allows the required number of bridge wirings 63, wiring 64, and wiring 65 to be placed without layout constraints.

[0077] <Connection structure around the conductor layer> Next, the detailed structure of the parts that electrically connect the semiconductor die 10, semiconductor die 20, and bridge chip 30 to the conductor layer 60 will be described. Figure 5 is an enlarged cross-sectional view of the connection part and the area around the bridge wiring in the conductor layer shown in Figure 3, which electrically connects the bridge chip to one of the semiconductor dies. Figure 6 is an enlarged cross-sectional view of the connection part and the area around the bridge wiring in the conductor layer shown in Figure 3, which electrically connects the bridge chip to the other semiconductor die.

[0078] Figure 7 is a plan view showing an example of the layout of the multiple bridge-side columnar electrodes shown in Figure 3. In Figure 7, the outlines of the semiconductor die 10, semiconductor die 20, bridge chip 30, external terminal 40, bridge wiring 63, wiring 64, and wiring 65 are shown with dotted lines to indicate the planar positional relationship between each component shown in Figure 4 and the bridge-side columnar electrode 80.

[0079] Figure 8 is a plan view showing an example of the layout of the multiple die-side columnar electrodes shown in Figure 3. In Figure 8, the outlines of the semiconductor die 10, semiconductor die 20, bridge chip 30, external terminal 40, bridge wiring 63, wiring 64, and wiring 65 are shown with dotted lines to indicate the planar positional relationship between each component shown in Figure 4 and the die-side columnar electrode 70.

[0080] As shown in Figure 5, the semiconductor die 10 has a semiconductor substrate 12 having a main surface 12t, and insulating layers 13, 14, and 15 laminated on the main surface 12t of the semiconductor substrate 12. The semiconductor die 10 has internal wiring 16 electrically connected to the semiconductor substrate 12. The semiconductor die 10 also has die electrodes 11 connected to the internal wiring 16. In the example shown in Figure 5, the semiconductor die 10 has three insulating layers 13, 14, and 15. However, the total number of insulating layers on the semiconductor die 10 is not limited to three layers; for example, it may have two layers, or four or more insulating layers.

[0081] As shown in Figure 6, the semiconductor die 20 has a semiconductor substrate 22 having a main surface 22t, and insulating layers 23, 24, and 25 laminated on the main surface 22t of the semiconductor substrate 22. The semiconductor die 20 has internal wiring 26 electrically connected to the semiconductor substrate 22. The semiconductor die 20 also has die electrodes 21 connected to the internal wiring 26. In the example shown in Figure 6, the semiconductor die 20 has three insulating layers 23, 24, and 25. However, the total number of insulating layers on the semiconductor die 20 is not limited to three layers; for example, it may have two layers, or four or more insulating layers.

[0082] As shown in Figures 5 and 6, the bridge chip 30 has a chip 33 having a main surface 33t, and insulating layers 34, 35, and 36 laminated on the main surface 33t of the chip 33. The bridge chip 30 has a plurality of internal wirings 32 formed on the chip 33 or on the insulating layer 34. In the example shown in Figures 5 and 6, the bridge chip 30 has three insulating layers 34, 35, and 36. However, the total number of insulating layers that the bridge chip 30 has is not limited to three layers, and it may have, for example, two layers or four or more insulating layers.

[0083] The bridge chip 30 has a bridge electrode 31A electrically connected to the connection portion 61 shown in Figure 5, and a bridge electrode 31B electrically connected to the connection portion 62 shown in Figure 6. The bridge electrode 31A and the bridge electrode 31B are electrically connected to each other via internal wiring 32.

[0084] The chip 33 is formed from a semiconductor substrate, such as a silicon wafer, but as a modified example, it may be an inorganic substrate formed from an inorganic material such as glass. In the examples shown in Figures 5 and 6, multiple internal wirings 32 are illustrated as internal wirings formed on the semiconductor substrate. However, various modifications can be applied to the wiring for electrically connecting multiple bridge electrodes 31. For example, a redistribution layer (not shown) may be formed on the bridge electrodes 31, and the multiple bridge electrodes 31 may be electrically connected via wiring formed on the redistribution layer.

[0085] Furthermore, as shown in Figure 3, the semiconductor module 100 has a plurality of die-side columnar electrodes 70 positioned between the conductive layer 60 and the semiconductor die 10, or between the conductive layer 60 and the semiconductor die 20. Each of the plurality of die-side columnar electrodes 70 is exposed from the sealant 51 and sealed by the sealant 52.

[0086] As shown in Figure 8, the multiple die-side columnar electrodes 70 are positioned in the region overlapping with the semiconductor die 10 and the region overlapping with the semiconductor die 20, respectively. The multiple die-side columnar electrodes 70 are not positioned in the region that does not overlap with either the semiconductor die 10 or the semiconductor die 20.

[0087] The multiple die-side columnar electrodes 70 include multiple die-side columnar electrodes 70A arranged in regions overlapping with the semiconductor die 10 and the bridge chip 30, respectively, and multiple die-side columnar electrodes 70B arranged in regions overlapping with the semiconductor die 20 and the bridge chip 30, respectively. Furthermore, the multiple die-side columnar electrodes 70 also include multiple die-side columnar electrodes 70C arranged in regions overlapping with the semiconductor die 10 but not with the bridge chip 30, and multiple die-side columnar electrodes 70D arranged in regions overlapping with the semiconductor die 20 but not with the bridge chip 30.

[0088] Multiple die-side columnar electrodes 70C are electrically connected to multiple external terminals 40 via wiring 64 in the conductor layer 60. Multiple die-side columnar electrodes 70D are electrically connected to multiple external terminals 40 via wiring 65 in the conductor layer 60.

[0089] As shown in Figure 5, the connection portion 61 of the conductor layer 60 is electrically connected to the die electrode 11 via die-side columnar electrode 70A, one of the multiple die-side columnar electrodes 70. As shown in Figure 6, the connection portion 62 of the conductor layer 60 is electrically connected to the die electrode 21 via die-side columnar electrode 70B, one of the multiple die-side columnar electrodes 70.

[0090] A connecting layer 60S, for example as shown in Figure 5, is placed at the interface between each of the multiple die-side columnar electrodes 70 and the conductor layer 60, and each of the multiple die-side columnar electrodes 70 and the conductor layer 60 are joined via the connecting layer 60S.

[0091] Similarly, as shown in Figure 3, the semiconductor module 100 has a plurality of bridge-side columnar electrodes 80 positioned between the conductor layer 60 and the bridge chip 30. The plurality of bridge-side columnar electrodes 80 are sealed in a encapsulant 51. However, the tip surface of each of the plurality of bridge-side columnar electrodes 80 (the surface opposite to the surface facing the bridge chip 30) is exposed from the encapsulant 51.

[0092] As shown in Figure 7, the multiple bridge-side columnar electrodes 80 are arranged only in the region that overlaps with the bridge chip 30. The multiple bridge-side columnar electrodes 80 include multiple bridge-side columnar electrodes 80A arranged in a position that overlaps with the semiconductor die 10, and multiple bridge-side columnar electrodes 80B arranged in a position that overlaps with the semiconductor die 20.

[0093] Furthermore, the multiple bridge-side columnar electrodes 80 include multiple bridge-side columnar electrodes 80C. Each of the multiple bridge-side columnar electrodes 80C is positioned so as not to overlap with the semiconductor die 10 and the semiconductor die 20. Each of the multiple bridge-side columnar electrodes 80C is electrically connected to the bridge wiring 63, as shown in Figures 5 and 6.

[0094] As shown in Figure 5, the connection portion 61 of the conductor layer 60 is electrically connected to the bridge electrode 31A via bridge-side columnar electrode 80A, one of the multiple bridge-side columnar electrodes 80. As shown in Figure 6, the connection portion 62 of the conductor layer 60 is electrically connected to the bridge electrode 31B via bridge-side columnar electrode 80B, one of the multiple bridge-side columnar electrodes 80. The bridge wiring 63 of the conductor layer is electrically connected to the bridge electrode 31C via bridge-side columnar electrode 80C, one of the multiple bridge-side columnar electrodes 80.

[0095] Each of the multiple die-side columnar electrodes 70 and the multiple bridge-side columnar electrodes 80 is a columnar conductor of μm size (also called a "micropillar"). The main body of each of the multiple die-side columnar electrodes 70 and the multiple bridge-side columnar electrodes 80 is made of a metallic material, for example, copper as the main component.

[0096] Furthermore, a connecting layer 60S is interposed at the boundary between the die-side columnar electrode 70 and the conductor layer 60, and at the boundary between the bridge-side columnar electrode 80 and the conductor layer 60. The connecting layer 60S is made of, for example, solder. Note that the thickness of the connecting layer 60S is thin, so it is not shown in Figure 3.

[0097] In this embodiment, the die electrode 11 located inside the semiconductor die 10 shown in Figure 5 and the die-side columnar electrode 70A protruding downward from the semiconductor die 10 were described separately. Similarly, the die electrode 21 located inside the semiconductor die 20 shown in Figure 6 and the die-side columnar electrode 70B protruding downward from the semiconductor die 20 were described separately. Similarly, the bridge electrode 31 located inside the bridge chip 30 shown in Figures 5 and 6 and the bridge-side columnar electrode 80 protruding upward from the bridge chip 30 were described separately.

[0098] However, each of the multiple die-side columnar electrodes 70 can also be considered as a die electrode of the semiconductor die 10 or semiconductor die 20. Similarly, each of the multiple bridge-side columnar electrodes 80 can also be considered as a bridge electrode of the bridge chip. In this case, each of the die-side columnar electrodes 70, which are die electrodes, and the bridge-side columnar electrodes 80, which are bridge electrodes, are connected to the conductor layer 60. In this case, the layer on which the die electrode 11 shown in Figure 5 is formed, the layer on which the bridge electrode 31 is formed, and the layer on which the die electrode 21 shown in Figure 6 is formed can each be considered as a layer on which internal wiring is arranged.

[0099] <Internal wiring structure of a bridge chip> Next, an example of the layout of the internal wiring 32 in the bridge chip 30 shown in Figures 1 and 3 will be described. Figure 9 is a plan view showing an example of the layout of the internal wiring in the first layer among the multiple wiring layers in the bridge chip shown in Figure 5. Figure 10 is a plan view showing an example of the layout of the internal wiring in the second layer among the multiple wiring layers in the bridge chip shown in Figure 5.

[0100] In the examples shown in Figures 5 and 6, the bridge chip has, in order from the top layer (the layer closest to the conductor layer 60), a wiring layer (internal wiring layer) 3LT, a wiring layer (internal wiring layer) 3L1, and a wiring layer (internal wiring layer) 3L2. The topmost wiring layer 3LT has multiple bridge electrodes 31. In a plan view, the linearly extending wiring pattern is mainly located in wiring layers 3L1 and 3L2.

[0101] The wiring layer 3L1 shown in Figure 9 has internal wiring 32VD which constitutes the power supply potential supply path and internal wiring 32VS which constitutes the reference potential supply path. The wiring layer 3L1 also has internal wiring 32SG which constitutes the signal transmission path.

[0102] The internal wiring 32VD and internal wiring 32VS of wiring layer 3L1 are linear (strip-shaped) wiring patterns. In the example shown in Figure 9, the internal wiring 32VD and internal wiring 32VS each extend in the X direction.

[0103] On the other hand, the internal wiring 32SG of wiring layer 3L1 has a nonlinear pattern. In the examples shown in Figures 9 and 10, the internal wiring 32SG for signal transmission is mainly routed in wiring layer 3L2 as shown in Figure 10. Therefore, the internal wiring 32SG of wiring layer 3L1 is a land pattern for via wiring (also called plug wiring) that electrically connects wiring layer 3LT and wiring layer 3L2 as shown in Figures 5 and 6. In the example shown in Figure 9, the planar shape of the internal wiring 32SG of wiring layer 3L1 is circular. However, various modifications can be applied to the planar shape of the internal wiring 32SG, such as polygons with four or more sides.

[0104] The wiring layer 3L2 shown in Figure 10 has a plurality of internal wirings 32SG that constitute a signal transmission path. The plurality of internal wirings 32SG extend in the X direction so as to be spaced apart from each other. Each of the plurality of internal wirings 32SG corresponds to an internal wiring 32C for electrically connecting the semiconductor die 10 and the semiconductor die 20 shown in Figure 3.

[0105] In this embodiment, the internal wiring 32VD and internal wiring 32VS formed in the wiring layer 3L1 shown in Figure 9 are not formed in the wiring layer 3L2 shown in Figure 10. However, as a modification, one or both of the internal wiring 32VD and internal wiring 32VS may be formed in the wiring layer 3L2.

[0106] In this embodiment, internal wiring 32VD and internal wiring 32VS are routed in wiring layer 3L1 shown in Figure 9, and internal wiring 32SG is routed in wiring layer 3L2 shown in Figure 10. In this case, as shown in Figure 10, it is possible to realize a layout in wiring layer 3L2 in which the land patterns of internal wiring 32VD (see Figure 9) and internal wiring 32VS (see Figure 9) are not arranged. In this case, a sufficient distance can be secured between adjacent internal wirings 32SG, which is effective from the viewpoint of reducing crosstalk noise between adjacent internal wirings 32SG.

[0107] However, as a modification of this embodiment, internal wiring 32SG may be routed in wiring layer 3L1 shown in Figure 9, and internal wiring 32VD (see Figure 9) and internal wiring 32VS (see Figure 9) may be routed in wiring layer 3L2 shown in Figure 10. In this case, since the linearly extending internal wiring 32SG is arranged to be separated from the land patterns of internal wiring 32VD and internal wiring 32VS, the shape of the wiring pattern becomes more complex compared to the example shown in Figure 10.

[0108] Furthermore, in this embodiment, a semiconductor module 100 having two semiconductor dies (semiconductor die 10 and semiconductor die 20) was used as an example for explanation, but the number of semiconductor dies may be three or more. Also, if the number of semiconductor dies increases, the number of bridge chips 30 may be increased accordingly. Increasing the number of semiconductor dies included in a single semiconductor module 100 has the advantage of enabling the modularization of large-scale circuits.

[0109] <Manufacturing method for semiconductor modules> Next, the semiconductor module manufacturing method described using Figures 1 to 10 will be explained. Figure 11 is an explanatory diagram showing an example of the semiconductor module manufacturing method shown in Figures 1 to 4. As shown in Figure 11, the semiconductor module manufacturing method includes a conductor layer formation step, a semiconductor die mounting step, a first encapsulation step, a support removal step, an external connection conductor formation step, a bridge chip mounting step, and a second encapsulation step. Details of each step will be explained below.

[0110] The conductor layer formation process shown in Figure 11 includes the steps shown in Figures 12 to 16. Each of Figures 12 to 16 is an enlarged cross-sectional view showing details of the conductor layer formation process shown in Figure 11. In the conductor layer formation process, as shown in Figure 16, a conductor layer 60 including a connecting portion 61, a connecting portion 62, and a bridge wiring 63 is formed on the upper surface 90t of the support 90. In this embodiment, the conductor layer 60 formed in the conductor layer formation process also further includes wiring 64 and wiring 65.

[0111] In detail, first, a support 90 having an upper surface 90t is prepared as shown in Figure 12. A release layer 91 and a seed layer 92 are pre-formed on the upper surface 90t of the support 90. The support 90 is, for example, a glass substrate. However, the material of the support 90 is not particularly limited as long as it is a plate with sufficient rigidity so as not to impair workability in each step up to the first support removal step shown in Figure 11. Examples include semiconductor substrates such as silicon wafers, plates made of inorganic materials such as sapphire substrates, and resin plates. However, considering the expansion due to heating during connection, it is desirable that the coefficient of linear expansion of the support 90 be close to that of the semiconductor die.

[0112] The release layer 91 is a functional layer that enables the release of the support 90 in the support removal process shown in Figure 11. Various materials are selected depending on the method used, such as a method of release using an energy beam such as a laser or a mechanical release method. The seed layer 92 is a seed film that serves as a base for forming the conductive members that constitute the conductive layer 60 shown in Figure 14 by a plating method. The seed layer 92 can be formed, for example, by depositing copper on the release layer 91 by a sputtering method.

[0113] Next, as shown in Figure 13, a resist mask 93 is formed on the upper surface 90t of the support 90, more specifically, on the seed layer 92. Multiple openings 93H are formed in the resist mask 93, for example, using photolithography. The multiple openings 93H are formed in the area where the conductive layer 60 shown in Figure 16 is to be formed.

[0114] Next, as shown in Figure 14, a conductor layer 60 including the connection portion 61, the connection portion 62, and the bridge wiring 63 is formed by depositing a metal film within the opening 93H of the resist mask 93 by a plating method or the like. In this embodiment, the connection portion 61, the connection portion 62, the bridge wiring 63, the wiring 64, and the wiring 65 are all formed collectively by a plating method. In other words, the conductor layer 60 is a plated film.

[0115] A seed layer 92 is pre-formed on the upper surface 90t of the support 90. Therefore, each conductor pattern constituting the conductor layer 60 can be formed collectively, for example, by an electrolytic plating method. As shown in Figure 4, which has already been described, each of the bridge wirings 63, wiring 64, and wiring 65 is formed linearly (strip-shaped) so as to extend along the Y direction. In addition, each of the connection parts 61 and 62 is formed in an island shape so as to be separated from the adjacent conductor pattern.

[0116] Next, as shown in Figure 15, the resist mask 93 (see Figure 14) is removed. Removing the resist mask 93 exposes the sides of each of the connection parts 61 and 62, bridge wiring 63, wiring 64, and wiring 65, as well as a portion of the top surface of the seed layer 92.

[0117] Next, as shown in Figure 16, the portion of the seed layer 92 that is exposed from the conductor layer 60 is removed. Etching is an example of a method for removing a portion of the seed layer 92. The thickness of the seed layer 92 is sufficiently thin compared to the conductor layer 60, for example, 10 percent or less. Therefore, even if the conductor layer 60 is not covered with a mask when removing the seed layer 92 by etching, the conductor layer 60 itself functions as a mask, so the portion of the seed layer 92 that is exposed from the conductor layer 60 can be selectively removed.

[0118] In this embodiment, a method for removing the seed layer 92 in the conductor layer formation process has been described. However, as a modified example, the seed layer 92 may be removed after the first support removal process shown in Figure 11 and before the external connection conductor formation process.

[0119] The seed layer 92 and the conductor layer 60 are each made of copper or a copper-based alloy. Furthermore, the seed layer 92 and the conductor layer 60 are made of the same material. Therefore, after a portion of the seed layer 92 is removed, the remaining portion of the seed layer 92 integrates with the conductor layer 60. In the following description, the remaining portion of the seed layer 92 will be described as the conductor layer 60, which is not shown.

[0120] Next, the semiconductor die mounting process shown in Figure 11 includes the steps shown in Figures 17 and 18. Figures 17 and 18 are enlarged cross-sectional views showing details of the semiconductor die mounting process shown in Figure 11. The semiconductor die mounting process includes the step of electrically connecting the die electrode 11 of the semiconductor die 10, as explained using Figure 5, to the connection portion 61 of the conductor layer 60 shown in Figure 16, and the step of electrically connecting the die electrode 21 of the semiconductor die 20, as explained using Figure 6, to the connection portion 62 of the conductor layer 60 shown in Figure 16.

[0121] The mounting order of the semiconductor die 10 and semiconductor die 20 is not particularly limited, but in this embodiment, a method of mounting each of the semiconductor die 10 and semiconductor die 20 together on the conductive layer 60 will be described.

[0122] In the semiconductor die mounting process, first, the semiconductor die 10 (see Figure 5) and semiconductor die 20 (see Figure 6), as described using Figures 5 and 6, are prepared. Each of the multiple die electrodes 11 of the semiconductor die 10 shown in Figure 5 has a die-side columnar electrode 70 pre-formed on it. Similarly, each of the multiple die electrodes 21 of the semiconductor die 20 shown in Figure 6 has a die-side columnar electrode 70 pre-formed on it.

[0123] Furthermore, although not shown in Figure 17, a connecting layer (e.g., a solder layer) 60S, as explained using Figures 5 and 6, is pre-formed at the tip of each of the multiple die-side columnar electrodes 70.

[0124] The detailed structures of semiconductor die 10 and semiconductor die 20 have already been explained using Figures 5 and 6, so a redundant explanation will be omitted.

[0125] Next, as shown in Figure 17, the semiconductor die 10 and semiconductor die 20 are aligned with the support 90 so that the die electrode 11 (specifically, die electrode 11C) is placed on the connection portion 61 of the conductor layer 60, and the die electrode 21 (specifically, die electrode 21C) is placed on the connection portion 62 of the conductor layer 60.

[0126] Of the multiple die electrodes 11, die electrode 11A is positioned opposite the wiring 64. Also, of the multiple die electrodes 21, die electrode 21A is positioned opposite the wiring 65.

[0127] Next, as shown in Figure 18, the die electrode 11 of the semiconductor die 10 is connected to the conductor layer 60 via the die-side columnar electrode 70 and the connecting layer 60S. Similarly, the die electrode 21 of the semiconductor die 20 is connected to the conductor layer 60 via the die-side columnar electrode 70 and the connecting layer 60S. When solder is used as the connecting layer 60S, the connecting layer 60S can be joined to the conductor layer 60 by a reflow process, which involves heating the connecting layer 60S until its temperature exceeds the melting point of the solder constituting the connecting layer 60S, and then cooling it. Alternatively, as a method for joining the connecting layer 60S and the conductor layer 60, for example, a method may be applied in which the layers are temporarily joined by solid-phase diffusion bonding, then heated to the temperature at which the connecting layer 60S melts, and finally joined stably by liquid-phase diffusion bonding.

[0128] Next, in the first sealing step shown in Figure 11, after the semiconductor die mounting step, the semiconductor die 10, the semiconductor die 20, and the conductor layer 60 are sealed with an insulating material to form a sealant 52, as shown in Figure 19. Figure 19 is an enlarged cross-sectional view showing details of the first sealing step shown in Figure 11. In this step, the semiconductor die 10, the semiconductor die 20, and the conductor layer 60 are integrated by the sealant 52. The sealant 52 can be exemplified by a resin material including, for example, a thermosetting resin. As a variation of the sealant 52, the resin may contain a large number of inorganic filler particles.

[0129] In the first support removal step shown in Figure 11, after the first sealing step, the support 90 (see Figure 19) is removed as shown in Figure 20. Figure 20 is an enlarged cross-sectional view showing details of the first support removal step shown in Figure 11. In this step, by applying energy to the release layer 91 with a laser or the like, the release layer 91 is decomposed (ablated), significantly reducing the adhesion of the release layer 91 to the support, and thus the support 90 can be easily removed. In the first support removal step, it is also possible to remove the release layer 91 by mechanical stress.

[0130] In the first support removal step, after removing the support 90, a portion (lower surface) of the conductor layer 60 is exposed from the sealant 52, as shown in Figure 21. Figure 21 is an enlarged cross-sectional view showing the conductor layer 60 shown in Figure 20 exposed from the sealant 52. In this step, the release layer 91 shown in Figure 20 is removed, for example, by etching. If the seed layer removal step explained using Figure 16 is omitted, the seed layer 92 (see Figure 15) is removed together with the release layer 91 in this step.

[0131] After this process is completed, as shown in Figure 21, the lower surface of the connection portion 61, the lower surface of the connection portion 62, and the lower surface of the bridge wiring 63 are exposed from the lower surface 52b of the sealing body 52. ​​In this embodiment, the lower surfaces of the wiring 64 and the wiring 65 are also similarly exposed from the sealing body 52.

[0132] Next, in the second support mounting step shown in Figure 11, the support 95 is attached to the upper surface 52t of the encapsulant 52, as shown in Figure 22. Figure 22 is an enlarged cross-sectional view showing details of the second support mounting step shown in Figure 11. Note that Figure 22 is a cross-section in a different direction from the cross-sections shown in Figures 12 to 21. That is, each of Figures 12 to 21 is a cross-sectional view along the X direction shown in Figure 4. On the other hand, Figure 22 is a cross-sectional view along the extension direction of one of the multiple bridge wirings 63 shown in Figure 4, i.e., the Y direction.

[0133] The support 95 shown in Figure 22 is a plate-shaped member similar to the support 90 described using Figure 12, and is, for example, a glass substrate. There are various variations in the method of attaching the support 95, but in the example shown in Figure 22, the support 95 is attached to the upper surface 52t of the sealant 52 via an adhesive layer 96.

[0134] In this embodiment, each step from the external connection conductor formation step to the second sealing step shown in Figure 11 is performed with the support 95 attached to the sealing body 52. ​​However, if the structure sealed by the sealing body 52 can be handled well, each step from the external connection conductor formation step to the second sealing step can be performed without attaching the support 95. In this case, the second support attachment step and the second support removal step shown in Figure 11 can be omitted.

[0135] Next, the external connection conductor formation process shown in Figure 11 includes the steps shown in Figures 23 to 27. In the external connection conductor formation process, multiple external terminals (external connection conductors) 40 are formed on the exposed surfaces of the bridge wiring 63, wiring 64, and wiring 65 that are exposed from the sealant 52. As shown in Figure 27, the multiple external terminals (external connection conductors) 40 formed on the bridge wiring 63 will be explained as an example.

[0136] In detail, first, as shown in Figure 23, a seed layer 97 is formed on the lower surface 52b of the sealant 52. The seed layer 97 is a seed film that serves as a base for forming the external terminals 40 shown in Figure 27 by a plating method. The seed layer 97 can be formed by depositing copper on the sealant 52. For example, the method for depositing the seed layer 97 can be the sputtering method, similar to that used for the seed layer 92 described using Figure 12.

[0137] Next, as shown in Figure 24, a resist mask 98 is formed on the lower surface 52b of the sealant 52, more specifically, on the seed layer 97. Multiple openings 98H are formed in the resist mask 98, for example, using photolithography. The multiple openings 98H are formed in the region where the external terminals 40 shown in Figure 27 are to be formed.

[0138] Next, as shown in Figure 25, a plurality of external terminals 40 are formed by depositing a metal film within the opening 98H (see Figure 24) of the resist mask 98 using a plating method or the like. In this embodiment, each of the plurality of external terminals 40 is formed collectively by the plating method.

[0139] A seed layer 97 is pre-formed on the lower surface 52b of the sealant 52. Therefore, external terminals 40 can be formed, for example, by electroplating. As shown in Figure 3, which has already been described, the thickness (length in the Z direction) of the multiple external terminals 40 is greater than the thickness of the bridge chip 30. However, by using electroplating, rod-shaped external terminals 40 (also called tall pillars) can be stably formed.

[0140] Next, as shown in Figure 26, the resist mask 98 (see Figure 25) is removed. Removing the resist mask 98 exposes the sides of each of the multiple external terminals 40 and a portion of the top surface of the seed layer 97.

[0141] Next, as shown in Figure 27, the portion of the seed layer 97 that is exposed from multiple external terminals 40 is removed. Etching is an example of a method for removing a portion of the seed layer 97. The thickness of the seed layer 97 is sufficiently thin compared to the thickness of the external terminals 40, for example, less than 1 percent. Therefore, even if the conductive layer 60 is not covered with a mask when removing the seed layer 97 by etching, the external terminals 40 themselves function as a mask, so that the portion of the seed layer 97 that is exposed from the external terminals 40 can be selectively removed.

[0142] The seed layer 97 and the external terminal 40 are each made of copper or a copper-based alloy. Furthermore, the seed layer 97 and the external terminal 40 are made of the same material. Therefore, after a portion of the seed layer 97 is removed, the remaining portion of the seed layer 97 integrates with the external terminal 40. In the following process description, the integrated seed layer 97 and external terminal 40 will be referred to simply as the external terminal 40.

[0143] In this embodiment, since multiple external terminals 40 are formed as described above, no connecting layer 60S, such as the one shown in Figure 5, is interposed between the external terminals 40 and the conductor layer 60. The remaining portion of the seed layer 97 could be considered as a connecting layer, but as described above, the remaining portion of the seed layer 97 is integrated with the external terminals 40, so superficially, no layer corresponding to the connecting layer 60S can be identified, and the external terminals 40 appear to be directly connected to the conductor layer 60.

[0144] Next, the bridge chip mounting process shown in Figure 11 includes the steps shown in Figures 28 and 29. Figures 28 and 29 are enlarged cross-sectional views showing details of the bridge chip mounting process shown in Figure 11. Note that the cross-sections shown in Figures 28 and 29 are the same as the cross-sections shown in Figures 12 to 21.

[0145] In the bridge chip mounting process, the conductor layer 60 and the bridge chip 30 are electrically connected as shown in Figure 29. As previously described, the bridge chip 30 has bridge electrodes 31A, 31B, and 31C.

[0146] For details, first, as shown in Figure 28, a bridge chip 30 is prepared, which includes a plurality of bridge electrodes 31 connected to the conductor layer 60. The bridge chip 30 is placed on the lower surface of the conductor layer 60 such that bridge electrode 31A is located on the connection portion 61 of the conductor layer 60, bridge electrode 31B is located on the connection portion 62 of the conductor layer 60, and bridge electrode 31C is located on the bridge wiring 63 of the conductor layer 60. The detailed structure of the bridge chip 30 has already been explained using Figures 5 and 6, so a redundant explanation will be omitted.

[0147] As shown in Figure 28, a connecting layer (e.g., a solder layer) 60S, as explained using Figures 5 and 6, is pre-formed at the tip of each of the multiple bridge-side columnar electrodes 80.

[0148] Next, as shown in Figure 29, the bridge electrode 31A of the bridge chip 30 is connected to the connection part 61 via the bridge-side columnar electrode 80 and the connecting layer 60S. The bridge electrode 31B of the bridge chip 30 is connected to the connection part 62 via the bridge-side columnar electrode 80 and the connecting layer 60S. In addition, the bridge electrode 31C of the bridge chip 30 is connected to the bridge wiring 63 via the bridge-side columnar electrode 80 and the connecting layer 60S.

[0149] When solder is used as the connecting layer 60S, the connecting layer 60S can be joined to the conductor layer 60 by a reflow process, which involves heating the connecting layer 60S until its temperature exceeds the melting point of the solder constituting the connecting layer 60S, and then cooling it. Alternatively, as a method for joining the connecting layer 60S and the conductor layer 60, a method may be applied in which the layer is temporarily joined by solid-phase diffusion bonding, then heated to the melting point of the connecting layer 60S, and finally joined stably by liquid-phase diffusion bonding.

[0150] Next, in the second sealing step shown in Figure 11, after the bridge chip mounting step, the multiple external terminals 40 and the bridge chip 30 are sealed with a resin material to form a seal 51, as shown in Figure 31. Figure 31 is an enlarged cross-sectional view showing details of the second sealing step shown in Figure 11. In the example shown in Figure 31, the multiple bridge-side columnar electrodes 80 are also sealed by the seal 51. By sealing the multiple bridge-side columnar electrodes 80 exposed from the seal 52 with the seal 51, the multiple bridge-side columnar electrodes 80 can be protected.

[0151] Furthermore, the sealant 51 is formed such that the lower surfaces of the multiple external terminals 40, which are tall pillars, are exposed from the sealant 51 at the lower surface 51b of the sealant 51. If the entire external terminals 40 are covered by the sealant when the sealant 51 is formed, the lower surface 51b is polished after the sealant 51 is formed to expose the lower surfaces of each of the multiple external terminals 40.

[0152] Next, in the second support removal step shown in Figure 11, the support 95 and adhesive layer 96 shown in Figure 30 are peeled off and removed from the upper surface 52t of the encapsulant 52. This yields the semiconductor module 100, as shown in Figure 31. Figure 31 is an enlarged cross-sectional view showing the semiconductor module after the second support removal step shown in Figure 11.

[0153] As shown in Figure 11, in a manufacturing method in which multiple semiconductor dies are integrated by a first encapsulation step and then a bridge chip mounting step is performed, each of the multiple die electrodes and multiple connection parts can be positioned with high positional accuracy, so that the semiconductor dies 10, 20 and the bridge chip 30 can be coupled at a higher density. Furthermore, as explained using Figure 3, the structure in which each of the connection part 61, connection part 62, bridge wiring 63, semiconductor die 10, and semiconductor die 20 is encapsulated by a single encapsulant 52 is a structure obtained by manufacturing using the manufacturing method described using Figures 11 to 31.

[0154] <Variations in the connection structure of the conductor layer> Next, a modified example of the conductor layer connection structure will be described. Figure 32 is an enlarged plan view showing a modified example of the connection structure between the die-side columnar electrode or bridge-side columnar electrode shown in Figure 5 and the bridge wiring. In Figure 32, the outline of the bridge wiring 63 is shown with a solid line, and the outline of either the die-side columnar electrode 70 or the bridge-side columnar electrode 80 connected on the bridge wiring 63 is shown with a dotted line.

[0155] In the example shown in Figure 32, multiple openings 60H are formed in the bridge wiring 63 at positions where at least one of the die-side columnar electrode 70 and the bridge-side columnar electrode 80 is connected. When multiple openings 60H are formed in this way, when the die-side columnar electrode 70 or the bridge-side columnar electrode 80 is connected to the conductor layer 60, the solder component of the connection layer 60S (see Figure 5) wets the openings 60H, thereby defining the position of the connection layer 60S.

[0156] Each of the bridge wirings 63, 64, or 65 has a width wider than the diameter of the die-side columnar electrode 70 and the bridge-side columnar electrode 80, respectively. In this case, if the connecting layer 60S extends excessively around the connection area, the connection state between the columnar electrode and the conductor layer 60 may become unstable. If the conductive layer 60 is considered as a conductive path, this problem is considered to be a problem related to the reliability of the electrical connection state. On the other hand, if the conductive layer 60 is considered as a heat dissipation path, this problem is considered to be a problem related to the reliability of the thermal connection state.

[0157] In this modified example, the multiple openings 60H prevent the connecting layer 60S from excessively wetting a wide area, thereby stabilizing the electrical or thermal connection between the columnar electrode and the conductor layer 60.

[0158] Figure 33 is an enlarged cross-sectional view showing a modified example of the portion where the conductor layer and the external terminal are connected, as shown in Figure 3. In the case of the semiconductor module 100 shown in Figure 3, which has already been described, each of the multiple die electrodes 11 of the semiconductor die 10 and the multiple die electrodes 21 of the semiconductor die 20 are connected somewhere in the conductor layer 60.

[0159] However, considering the versatility of the semiconductor die 10 and semiconductor die 20, layout constraints may result in, for example, the die-side columnar electrode 70 connected to the reference potential supply circuit being placed above the external terminal 40 and wiring 64 for supplying the power potential.

[0160] In this case, since there are many other supply paths for the reference potential, it is sufficient that a specific die-side columnar electrode 70 and the conductor layer 60 directly beneath it are electrically isolated, and that the die-side columnar electrode 70 and the external terminal 40 directly beneath it are electrically isolated.

[0161] In the example shown in Figure 33, an opening 60H2 is formed in the conductive layer 60 at a position overlapping with the die-side columnar electrode 70. The diameter of the opening 60H2 is larger than the diameter of the die-side columnar electrode 70, and the entire die-side columnar electrode 70 overlaps with the opening 60H2.

[0162] In this case, even if a connecting layer 60S is formed at the tip of the die-side columnar electrode 70, the die-side columnar electrode 70 is electrically isolated from the conductor layer 60 and the external terminal 40 located directly beneath it.

[0163] Furthermore, as already explained, the above embodiment described an embodiment in which multiple bridge wirings 63 are used as a transmission path for a reference potential or power supply potential. However, as a modification, the bridge wirings 63 may be used as a signal transmission path.

[0164] Although several representative embodiments have been described above with reference to the drawings, there are various further modifications to the embodiments and modifications described above. Parts of the embodiments can be appropriately modified as long as they do not contradict the above description. Furthermore, for example, parts of the embodiments and modifications described above can be combined with parts of other embodiments. [Explanation of Symbols]

[0165] 3L1,3L2,3LT Wiring layer (internal wiring layer) 10,20 Semiconductor dies 10C,20C circuit 11, 11A, 11B, 11C, 21, 21A, 21B, 21C die electrodes 12,22 Semiconductor substrates 12t,22t,33t main surface 13,14,15,23,24,25,34,35,36 Insulating layer 16,26,32,32A,32B,32C,32SG,32VD,32VS Internal wiring 30 Bridge Tips 30s1, 30s2, 30s3, 30s4 sides 31, 31A, 31B, 31C bridge electrodes 33 chips 40, 41, 42, 43, 43A, 43B, 43C, 44 External terminals (external connection conductors) 51. Sealing body (bridge-side sealing body) 51b,52b Bottom surface 51t,52t top surface 52. Sealing body (die-side sealing body) 60 Conductor layer 60H,60H2 opening 60S Connecting layer (e.g., solder layer) 61, 62 Connection part 63 Bridge Wiring 64,65 Wiring 70, 70A, 70B, 70C, 70D Die-side columnar electrodes 80, 80A, 80B, 80C Bridge-side columnar electrodes 90,95 Support 90t top surface 91 Exfoliation layer 92 Seed Layer 93 Resist Mask 93H,98H opening 96 Adhesive layer 97 Seed Layer 98 Resist Mask 100 semiconductor modules

Claims

1. A first semiconductor die having a first die electrode, A second semiconductor die having a second die electrode, A bridge chip having a first bridge electrode electrically connected to the first die electrode, a second bridge electrode electrically connected to the second die electrode, and a third bridge electrode, Multiple external connection conductors, A first seal that seals the bridge chip and the plurality of external connection conductors, A conductive layer formed on the first seal, It has, Each of the first semiconductor die and the second semiconductor die is exposed from the first encapsulant. The aforementioned conductor layer is The first die electrode and the first bridge electrode are electrically connected to a first connection portion, The second die electrode and the second bridge electrode are electrically connected to a second connection portion, The third bridge electrode and a bridge wiring electrically connected to a portion of the plurality of external connection conductors, A semiconductor module that includes this component.

2. In the semiconductor module according to claim 1, A semiconductor module further comprising the first semiconductor die, the second semiconductor die, and a second encapsulant for sealing the conductor layer.

3. In the semiconductor module according to claim 1, The aforementioned bridge wiring is electrically connected to either one or both of the first semiconductor die and the second semiconductor die, forming a semiconductor module.

4. In the semiconductor module according to claim 3, A semiconductor module in which the bridge wiring is wiring for supplying a reference potential or power supply potential to either one or both of the first semiconductor die and the second semiconductor die.

5. In the semiconductor module according to claim 1, The aforementioned bridge chip is The first internal wiring connected to the first bridge electrode and the third bridge electrode, The second internal wiring connected to the second bridge electrode and the third bridge electrode, A third internal wiring connected to the first bridge electrode and the second bridge electrode, A semiconductor module equipped with these features.

6. In the semiconductor module according to claim 1, In a plan view, the outer edge of the bridge tip includes a first side and a second side opposite to the first side, In a plan view, the bridge wiring extends across the first and second sides, The aforementioned plurality of external connection conductors are A first external connection conductor is positioned closer to the first side than the second side of the bridge chip and is connected to the bridge wiring, A second external connection conductor is positioned closer to the second side of the bridge chip than to the first side and is connected to the bridge wiring, A semiconductor module that includes this component.

7. In the semiconductor module according to claim 6, A semiconductor module in which the first external conductor and the second external conductor are each positioned so as not to overlap with the first semiconductor die, the second semiconductor die, and the bridge chip, respectively.

8. In the semiconductor module according to claim 1, The semiconductor module wherein the conductive layer consists of a metal film formed on the first encapsulant.

9. In the semiconductor module according to claim 1, The first semiconductor die, the second semiconductor die, and the second sealing body for sealing the conductor layer are further comprising The present invention further comprises a plurality of die-side columnar electrodes disposed between the conductor layer and the first semiconductor die, or between the conductor layer and the second semiconductor die. Each of the plurality of die-side columnar electrodes is sealed in the second sealing body. The first connection portion of the conductor layer is electrically connected to the first bridge electrode via the first die-side columnar electrode among the plurality of die-side columnar electrodes, A semiconductor module in which the second connection portion of the conductor layer is electrically connected to the second bridge electrode via a second die-side columnar electrode among the plurality of die-side columnar electrodes.

10. In the semiconductor module according to claim 1, The device further comprises a plurality of bridge-side columnar electrodes disposed between the conductor layer and the bridge chip, Each of the plurality of bridge-side columnar electrodes is sealed in the first sealing body. The first connection portion of the conductor layer is electrically connected to the first bridge electrode via the first bridge-side columnar electrode among the plurality of bridge-side columnar electrodes, The second connection portion of the conductor layer is electrically connected to the second bridge electrode via the second bridge-side columnar electrode among the plurality of bridge-side columnar electrodes. A semiconductor module in which the bridge wiring of the conductor layer is electrically connected to the third bridge electrode via the third bridge-side columnar electrode among the plurality of bridge-side columnar electrodes.

11. In the semiconductor module according to claim 1, The aforementioned conductor layer is A first wiring is disposed between the first semiconductor die and the first external connection conductor of the plurality of external connection conductors, and is electrically connected to the first die electrode and the first external connection conductor, A second wiring is disposed between the second semiconductor die and the second external conductor of the plurality of external conductors, and is electrically connected to the second die electrode and the second external conductor, A semiconductor module that further includes this.

12. In the semiconductor module according to claim 11, In a plan view, the bridge wiring is located between the first wiring and the second wiring in a semiconductor module.

13. (a) A step of forming a conductor layer on a support, including a first connection part, a second connection part, and bridge wiring, (b) A step of electrically connecting the first die electrode of the first semiconductor die to the first connection portion, (c) A step of electrically connecting the second die electrode of the second semiconductor die to the second connection portion, (d) A step of sealing the first semiconductor die, the second semiconductor die, and the conductor layer with an insulating material to form a die-side sealant, (e) A step of peeling the support from the die-side sealant, (f) A step of forming an external connection conductor on the exposed surface of the bridge wiring, (g) A step of electrically connecting the conductor layer and the bridge chip, (h) A step of sealing the external connecting conductor and the bridge tip with an insulating material to form a bridge-side seal, Includes, The bridge tip has a first bridge electrode, a second bridge electrode, and a third bridge electrode. A method for manufacturing a semiconductor module, wherein in step (g), the first connection portion and the first bridge electrode, the second connection portion and the second bridge electrode, and the bridge wiring and the third bridge electrode are electrically connected.

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