Semiconductor equipment

Abstract

The objective is to provide a technology that can suppress leakage current at the collector-side gate. [Solution] The semiconductor device comprises a collector electrode, a collector-side element trench structure, a collector-side gate pad, and a collector-side termination trench structure. In a plan view, the collector electrode surrounds the collector-side gate pad, and in a cross-sectional view, the collector-side termination trench structure penetrates the collector layer on the side of the semiconductor substrate relative to the connection portion between the collector electrode and the collector layer.

Description

[Technical Field]

[0001] This disclosure relates to semiconductor devices. [Background technology]

[0002] A semiconductor device has been proposed that includes an emitter-side gate electrode that forms a channel on the emitter electrode side (front side) and a collector-side gate electrode that forms a channel on the collector electrode side (back side). Various technologies have been proposed for semiconductor devices having such a double-sided gate structure.

[0003] For example, Patent Document 1 proposes a configuration in which a collector-side lead frame for electrical connection to the outside is soldered to a collector-side gate pad provided on the back side of a semiconductor substrate. With such a configuration, it is possible to form a channel on the back side of the semiconductor substrate by applying a voltage to the collector-side gate electrode via the collector-side lead frame and collector-side gate pad from the outside. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2010-123667 [Overview of the project] [Problems that the invention aims to solve]

[0005] However, during the manufacturing process, the solder connecting the collector-side gate pad and the collector-side lead frame sometimes leaked onto the side of the semiconductor substrate. As a result, the collector-side lead frame and the side of the semiconductor substrate became electrically connected by the solder, leading to a problem where the leakage current of the collector-side gate increased.

[0006] Therefore, this disclosure has been made in view of the above-mentioned problems, and aims to provide a technology that can suppress leakage current of the collector-side gate. [Means for solving the problem]

[0007] The semiconductor device according to this disclosure includes a semiconductor substrate having a front surface and a back surface in which an element region and a termination region surrounding the element region are defined; an emitter electrode provided on the front surface side of the semiconductor substrate; an emitter-side element trench structure provided on the front surface side of the element region of the semiconductor substrate and including an emitter-side gate electrode insulated from the emitter electrode; an emitter-side gate pad provided on the front surface side of the termination region of the semiconductor substrate, insulated from the emitter electrode and electrically connected to the emitter-side gate electrode; a collector electrode provided on the back surface side of the semiconductor substrate; a collector-side element trench structure provided on the back surface side of the element region of the semiconductor substrate and including a collector-side gate electrode insulated from the collector electrode; and the semiconductor substrate The semiconductor substrate comprises a collector-side gate pad provided on the back side of the terminal region of the plate, insulated from the collector electrode, and electrically connected to the collector-side gate electrode, and a collector-side termination trench structure provided on the back side of the terminal region of the semiconductor substrate, including the collector-side termination electrode, wherein the semiconductor substrate includes a drift layer of a first conductivity type, a buffer layer of the first conductivity type provided on the back side of the drift layer, and a collector layer of a second conductivity type provided on the back side of the buffer layer, wherein in a plan view the side surface of the semiconductor substrate and the collector electrode surround the collector-side gate pad, and in a cross-sectional view the collector-side termination trench structure penetrates the collector layer on the side surface of the semiconductor substrate with respect to the connection portion between the collector electrode and the collector layer. [Effects of the Invention]

[0008] According to the present disclosure, in a sectional view, the collector-side terminal trench structure penetrates the collector layer on the side surface of the semiconductor substrate with respect to the connection portion between the collector electrode and the collector layer. According to such a configuration, the leakage current of the collector-side gate can be suppressed.

Brief Description of the Drawings

[0009] [Figure 1] It is a plan view showing the front-side configuration of the semiconductor device according to Embodiment 1. [Figure 2] It is a plan view showing the back-side configuration of the semiconductor device according to Embodiment 1. [Figure 3] It is a cross-sectional view showing the configuration of the semiconductor device according to Embodiment 1. [Figure 4] It is a cross-sectional view showing the configuration of the semiconductor device according to Embodiment 2. [Figure 5] It is a cross-sectional view showing the configuration of the semiconductor device according to Embodiment 3. [Figure 6] It is a plan view showing the back-side configuration of the semiconductor device according to Embodiment 4. [Figure 7] It is a cross-sectional view showing the configuration of the semiconductor device according to Embodiment 4. [Figure 8] It is a plan view showing the back-side configuration of the semiconductor device according to Embodiment 4. [Figure 9] It is a cross-sectional view showing the configuration of the semiconductor device according to Embodiment 4. [Figure 10] It is a plan view showing the back-side configuration of the semiconductor device according to Embodiment 4. [Figure 11] It is a cross-sectional view showing the configuration of the semiconductor device according to Embodiment 4. [Figure 12] It is a cross-sectional view showing the configuration of the semiconductor device according to Embodiment 5. [Figure 13] It is a cross-sectional view showing the configuration of the semiconductor device according to Embodiment 6. [Figure 14] It is a plan view showing the back-side configuration of the semiconductor device according to Embodiment 7. [Figure 15] It is a plan view showing the back-side configuration of the semiconductor device according to Embodiment 8. [Figure 16] This is a plan view showing the configuration of the back side of the semiconductor device according to Embodiment 9. [Figure 17] This is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 10. [Figure 18] This is a plan view showing the configuration of the back side of the semiconductor device according to Embodiment 11. [Figure 19] This is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 11. [Figure 20] This is a plan view showing the configuration of the back side of the semiconductor device according to Embodiment 12. [Figure 21] This is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 12. [Figure 22] This is a plan view showing the configuration of the front side of the semiconductor device according to Embodiment 13. [Figure 23] This is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 13. [Figure 24] This is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 13. [Modes for carrying out the invention]

[0010] The embodiments will be described below with reference to the attached drawings. The features described in each of the embodiments below are illustrative, and not all features are necessarily required. In addition, in the descriptions below, the same or similar reference numerals are used for similar components in multiple embodiments, and the different components will be described primarily. Also, in the descriptions below, specific positions and directions such as "top," "bottom," "left," "right," "front," or "back" do not necessarily have to coincide with the positions and directions in actual implementation. Furthermore, although the first conductivity type is described below as n-type and the second conductivity type as p-type, the first conductivity type may be p-type and the second conductivity type as n-type.

[0011] <Embodiment 1> The following describes an example where the semiconductor device according to this embodiment 1 is an IGBT (Insulated Gate Bipolar Transistor). Figures 1 and 2 are plan views showing the front and back configurations of the semiconductor device according to this embodiment 1, respectively. Figure 3 is a cross-sectional view showing the configuration of the semiconductor device according to this embodiment 1, specifically a cross-sectional view along line A and B in Figure 2.

[0012] As shown in Figure 3, the semiconductor device according to this embodiment 1 comprises a semiconductor substrate 25, the semiconductor substrate 25 having a front surface and a back surface defined by an element region 61 and a termination region 62 surrounding the element region 61. The element region 61 forms the path for the main current of the semiconductor device, and the termination region 62 maintains the breakdown voltage in the lateral direction (left-right direction in Figure 3) of the semiconductor device. In the following description, the front surface and back surface refer to the front surface and back surface of the semiconductor substrate 25.

[0013] The semiconductor substrate 25 may be made of ordinary silicon (Si), or of a wide-bandgap semiconductor such as silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), or diamond. When the semiconductor substrate 25 is made of a wide-bandgap semiconductor, stable operation of the semiconductor device at high temperatures and high voltages, and faster switching speeds become possible. The semiconductor substrate 25 may be made of an ordinary semiconductor wafer, or of an epitaxial growth layer. The configurations of the element region 61 and the termination region 62 will be described in detail below.

[0014] <Element area 61> In the element region 61, the semiconductor substrate 25 includes an n-type source layer 1, a p-type contact layer 2, a p-type base layer 3, an emitter-side n-type layer 4, an n-type drift layer 5, an n-type buffer layer 6, a p-type collector layer 7, and a collector-side n-type layer 8.

[0015] On the front surface side of the n-type drift layer 5 which is a pressure-resistant holding part, an emitter-side n-type layer 4 is provided. The n-type impurity concentration of the emitter-side n-type layer 4 is not less than the n-type impurity concentration of the n-type drift layer 5. For example, the n-type impurity concentration of the n-type drift layer 5 is 10 12 cm -3 or more and 10 14 cm -3 or less, and the peak concentration of the n-type impurity in the emitter-side n-type layer 4 is 10 15 cm -3 or more and 10 17 cm -3 or less.

[0016] On the front surface side of the emitter-side n-type layer 4, a p-type base layer 3 is provided. For example, the peak concentration of the p-type impurity in the p-type base layer 3 is 10 17 cm -3 or so. On the front surface side of the p-type base layer 3, an n-type source layer 1 and a p-type contact layer 2 are selectively provided. For example, the peak concentration of the n-type impurity in the n-type source layer 1 is 10 18 cm -3 or more and 10 21 cm -3 or less. The p-type impurity concentration of the p-type contact layer 2 is not less than the p-type impurity concentration of the p-type base layer 3.

[0017] On the back surface side of the n-type drift layer 5 which is a pressure-resistant holding part, an n-type buffer layer 6 is provided. For example, the peak concentration of the n-type impurity in the n-type buffer layer 6 is 10 15 cm -3 or more and 10 18 cm -3 or less. On the back surface side of the n-type buffer layer 6, a p-type collector layer 7 is provided. For example, the peak concentration of the p-type impurity in the p-type collector layer 7 is 10 17 cm -3 or more and 10 19 cm -3 or less. On the back surface side of the p-type collector layer 7, a collector-side n-type layer 8 is selectively provided. For example, the peak concentration of the n-type impurity in the collector-side n-type layer 8 is 10 18 cm -3 or more and 10 21 cm-3 It is approximately as follows.

[0018] In the element region 61, the semiconductor device according to this embodiment 1 includes not only a semiconductor substrate 25, but also an emitter-side element trench structure, an emitter-side interlayer film 11, an emitter electrode 12, a collector-side element trench structure, a collector-side interlayer film 15, and a collector electrode 16.

[0019] The emitter-side element trench structure is provided on the front side of the semiconductor substrate 25 and includes an emitter-side gate insulating film 9 and an emitter-side gate electrode 10. A trench is provided on the front side of the semiconductor substrate 25 that penetrates from the n-type source layer 1 through the p-type base layer 3 and the emitter-side n-type layer 4 to the n-type drift layer 5. The emitter-side gate insulating film 9, which is made of, for example, an oxide film, is provided inside the trench provided on the front side.

[0020] The emitter-side gate electrode 10 is provided on the trench on the front side via the emitter-side gate insulating film 9. Note that in Figure 1, the emitter-side element trench structure (emitter-side gate insulating film 9 and emitter-side gate electrode 10) is shown in a simplified form.

[0021] As shown in Figure 3, the emitter electrode 12, which is the main electrode portion, is provided on the front side of the semiconductor substrate 25. The emitter-side interlayer film 11 is provided between the emitter-side gate electrode 10 and the emitter electrode 12, insulating the emitter-side gate electrode 10 from the emitter electrode 12. As shown in Figure 3, the position of the end of the emitter electrode 12 roughly corresponds to the position of the end of the element region 61, and in the plan view of Figure 1, the region of the emitter electrode 12 roughly corresponds to the element region 61.

[0022] When a voltage positive to the emitter electrode 12 is applied to the emitter-side gate electrode 10 of the emitter-side element trench structure, a channel is formed in the p-type base layer 3 that electrically connects the n-type source layer 1 and the voltage holding portion (n-type drift layer 5). Therefore, the n-type source layer 1, the p-type base layer 3, and the emitter-side element trench structure (emitter-side gate insulating film 9 and emitter-side gate electrode 10) constitute an element region emitter-side MOS channel portion capable of forming a MOS channel on the front surface side of the semiconductor substrate 25.

[0023] The collector-side element trench structure is provided on the back side of the semiconductor substrate 25 and includes the collector-side gate insulating film 13 and the collector-side gate electrode 14 shown in Figure 3. A trench is provided on the back side of the semiconductor substrate 25 that penetrates from the collector-side n-type layer 8 through the p-type collector layer 7 to the n-type buffer layer 6. The collector-side gate insulating film 13, which is made of, for example, an oxide film, is provided inside the trench on the back side.

[0024] The collector-side gate electrode 14 is provided on the trench on the back side via the collector-side gate insulating film 13. Note that in Figure 2, the collector-side element trench structure (collector-side gate insulating film 13 and collector-side gate electrode 14) is shown in a simplified form. The interval at which the emitter-side gate electrode 10 is repeatedly arranged (emitter-side gate pitch) and the interval at which the collector-side gate electrode 14 is repeatedly arranged (collector-side gate pitch) may be the same or different.

[0025] As shown in Figure 3, the collector electrode 16, which is the main electrode portion, is provided on the back side of the semiconductor substrate 25. The collector-side interlayer film 15 is provided between the collector-side gate electrode 14 and the collector electrode 16, and insulates the collector-side gate electrode 14 and the collector electrode 16.

[0026] When a voltage positive to the collector electrode 16 is applied to the collector-side gate electrode 14 of the collector-side element trench structure, a channel is formed in the p-type collector layer 7 that electrically connects the collector-side n-type layer 8 and the n-type buffer layer 6. Therefore, the collector-side n-type layer 8, the p-type collector layer 7, and the collector-side element trench structure (collector-side gate insulating film 13 and collector-side gate electrode 14) constitute a collector-side MOS channel portion of the element region capable of forming a MOS channel on the back surface of the semiconductor substrate 25.

[0027] <Terminal area 62> In the termination region 62, the semiconductor substrate 25 includes an n-type drift layer 5, an n-type buffer layer 6, a p-type collector layer 7, a p-type well layer 17, and an n-type channel stopper layer 18. The n-type drift layer 5, n-type buffer layer 6, and p-type collector layer 7 in the termination region 62 are the same as those in the device region 61.

[0028] A p-type well layer 17 and an n-type channel stopper layer 18 are selectively provided on the front side of the n-type drift layer 5, which is the pressure-resistant holding part. For example, the peak concentration of p-type impurities in the p-type well layer 17 is 10 16 cm -3 The above 10 18 cm -3 The following is an example of the peak concentration of n-type impurities in the n-type channel stopper layer 18. 18 cm -3 The above 10 21 cm -3 It is approximately as follows.

[0029] In the element region 61, the semiconductor device according to this embodiment 1 includes not only a semiconductor substrate 25, but also an emitter-side interlayer film 11, an emitter electrode 12, a collector-side interlayer film 15, a collector electrode 16, a field plate 19, an emitter-side passivation film 20, an emitter-side gate wiring 21, a collector-side gate wiring 22, an emitter-side gate pad 23 and a collector-side gate pad 24 as shown in Figure 1, and a collector-side gate leak suppression unit.

[0030] The emitter-side interlayer film 11 has contact holes that expose the p-type well layer 17 and the n-type channel stopper layer 18. The p-type well layer 17 closest to the device region 61 is connected to the emitter electrode 12 via the contact hole in the emitter-side interlayer film 11. The remaining p-type well layers 17 and the n-type channel stopper layer 18 are each connected to the field plate 19 via the contact holes in the emitter-side interlayer film 11.

[0031] The emitter-side gate wiring 21 is insulated from the emitter electrode 12, p-type well layer 17, and field plate 19 by the emitter-side interlayer film 11 and the emitter-side passivation film 20, but is connected to the emitter-side gate electrode 10 in a different cross-section than that shown in Figure 3. The emitter-side gate pad 23 in Figure 1 is insulated from the emitter electrode 12, but is electrically connected to the emitter-side gate electrode 10 via the emitter-side gate wiring 21 in a different cross-section than that shown in Figure 3. The emitter-side gate pad 23 is connected to a bonding wire (not shown), thereby electrically connecting the emitter-side gate electrode 10 to the outside.

[0032] The collector-side gate wiring 22 is insulated from the p-type collector layer 7 and collector electrode 16 by the collector-side interlayer film 15, but is connected to the collector-side gate electrode 14 in a different cross-section than that shown in Figure 3. The collector-side gate pad 24 in Figure 2 is insulated from the collector electrode 16, but is electrically connected to the collector-side gate electrode 14 via the collector-side gate wiring 22. The collector-side gate pad 24 is connected to a collector-side gate lead frame (not shown) by solder (not shown), thereby electrically connecting the collector-side gate electrode 14 to the outside. As shown in Figure 2, in a plan view, the side surface of the semiconductor substrate 25 and the collector electrode 16 surround the collector-side gate pad 24.

[0033] In this embodiment 1, the collector-side gate leak suppression section is a collector-side termination trench structure. The collector-side termination trench structure is provided on the back side of the semiconductor substrate 25 and includes the collector-side termination insulating film 30 and the collector-side termination electrode 31 shown in Figure 3. A trench that penetrates the p-type collector layer 7 and reaches the n-type buffer layer 6 is provided on the back side of the semiconductor substrate 25. The collector-side termination insulating film 30, which is made of, for example, an oxide film, is provided inside the trench provided on the back side.

[0034] The collector-side termination electrode 31 is provided on the trench on the back side via a collector-side termination insulating film 30. The collector-side termination electrode 31 may be connected to the collector electrode 16 or to a floating electrode (not shown). In Figure 2, the collector-side termination trench structure (collector-side termination insulating film 30 and collector-side termination electrode 31) is shown in a simplified manner, similar to the collector-side element trench structure (collector-side gate insulating film 13 and collector-side gate electrode 14).

[0035] As shown in Figure 3, in a cross-sectional view, the collector-side termination trench structure (collector-side termination insulating film 30 and collector-side termination electrode 31) penetrates the p-type collector layer 7 on the side of the semiconductor substrate 25, relative to the connection portion 16a between the collector electrode 16 and the p-type collector layer 7. In this embodiment 1, in a cross-sectional view, the collector-side termination trench structure penetrates the p-type collector layer 7 on the side of the semiconductor substrate 25.

[0036] <Summary of Embodiment 1> With the above configuration, when a positive voltage is applied to the emitter electrode 12 via the emitter gate pad 23 to the emitter gate electrode 10, the n-type source layer 1 is electrically connected to the breakdown voltage holding section (n-type drift layer 5) by the emitter MOS channel. This turns the IGBT ON. On the other hand, when the application of a positive voltage to the emitter gate pad 23 is stopped, the IGBT turns OFF.

[0037] When a positive voltage is applied to the collector electrode 16 via the collector gate pad 24 during turn-off, the collector-side n-type layer 8 is electrically connected to the n-type buffer layer 6 by the collector-side MOS channel. This reduces the hole injection efficiency of the p-type collector layer 7, allowing for high-speed current interruption.

[0038] However, during the manufacturing process, solder (not shown) provided between the collector-side gate pad 24 and the collector-side gate lead frame (not shown) may seep onto the side surface of the semiconductor substrate 25. In this case, in the conventional technology, an unusual current path is formed between the collector-side gate lead frame and the collector electrode 16, specifically a path from the collector-side gate lead frame through the solder and the p-type collector layer 7 to the collector electrode 16. As a result, there was a problem in that the leakage current of the collector-side gate increased.

[0039] In contrast, in this embodiment 1, the collector-side termination trench structure (collector-side termination insulating film 30 and collector-side termination electrode 31) penetrates the p-type collector layer 7 on the side of the semiconductor substrate 25 at the connection portion 16a between the collector electrode 16 and the p-type collector layer 7. As a result, the collector-side termination trench structure insulates the p-type collector layer 7 around the collector-side gate pad 24 so as to block the current path. Therefore, even if solder between the collector-side gate pad 24 and the collector-side gate lead frame flows around to the side of the semiconductor substrate 25, the increase in leakage current of the collector-side gate can be suppressed.

[0040] <Embodiment 2> Figure 4 is a cross-sectional view showing the configuration of a semiconductor device according to this second embodiment. In the first embodiment, the depth of the collector-side termination trench structure was the same as the depth of the collector-side element trench structure.

[0041] In contrast, in this second embodiment, the depth of the collector-side termination trench structure (collector-side termination insulating film 30 and collector-side termination electrode 31) is greater than the depth of the collector-side element trench structure (collector-side gate insulating film 13 and collector-side gate electrode 14). As an example, Figure 4 shows that the trench of the collector-side termination trench structure penetrates the p-type collector layer 7 and the n-type buffer layer 6 to reach the n-type drift layer 5. With this configuration, the insulation of the p-type collector layer 7 around the collector-side gate pad 24 can be improved, thereby further suppressing the increase in leakage current of the collector-side gate.

[0042] <Embodiment 3> Figure 5 is a cross-sectional view showing the configuration of a semiconductor device according to this third embodiment. In this third embodiment, the width of the collector-side termination trench structure (collector-side termination insulating film 30 and collector-side termination electrode 31) is wider than the width of the collector-side element trench structure (collector-side gate insulating film 13 and collector-side gate electrode 14). With this configuration, the insulation of the p-type collector layer 7 around the collector-side gate pad 24 can be improved by the collector-side termination trench structure, thereby further suppressing the increase in leakage current of the collector-side gate.

[0043] Furthermore, generally speaking, even under the same etching conditions, the wider the trench, the deeper the trench becomes. Therefore, according to this embodiment 3, even if the trench of the collector-side termination trench structure and the trench of the collector-side element trench structure are formed in the same process, the depth of the collector-side termination trench structure will be deeper than the depth of the collector-side element trench structure. For this reason, the configuration of embodiment 2 can be realized without any additional steps.

[0044] <Embodiment 4> Figure 6 is a plan view showing the configuration of the back side of the semiconductor device according to this embodiment 4, and Figure 7 is a cross-sectional view along line A and B in Figure 6. Figure 8 is a plan view showing another configuration of the back side of the semiconductor device according to this embodiment 4, and Figure 9 is a cross-sectional view along line A and B in Figure 8.

[0045] In Embodiment 1, in a cross-sectional view, the collector-side termination trench structure penetrates the p-type collector layer 7 on the side surface of the semiconductor substrate 25. In contrast, in Embodiment 4, in a cross-sectional view, the collector-side termination trench structure penetrates the p-type collector layer 7 on the connection portion 16a side relative to the side surface of the semiconductor substrate 25. In other words, in a cross-sectional view, the collector-side termination trench structure penetrates the p-type collector layer 7 in a portion other than the side surface of the semiconductor substrate 25, insulating the p-type collector layer 7 on the connection portion 16a side from the p-type collector layer 7 on the side surface of the semiconductor substrate 25.

[0046] With this configuration, the collector-side termination trench structure, which suppresses the increase in leakage current of the collector-side gate, can be prevented from being damaged by dicing. As shown in Figures 10 and 11, a collector-side termination trench structure combining Embodiment 1 and Embodiment 4 may be provided on the back side of the semiconductor substrate 25.

[0047] <Embodiment 5> Figure 12 is a cross-sectional view showing the configuration of a semiconductor device according to this embodiment 5. In this embodiment 5, a collector-side passivation film 32, which is a passivation film, is provided on the back side of the semiconductor substrate 25. The collector-side passivation film 32 is provided on the side of the semiconductor substrate 25 of the collector-side gate pad 24.

[0048] With this configuration, the collector-side passivation film 32 prevents solder between the collector-side gate pad 24 and the collector-side gate lead frame from flowing onto the side surface of the semiconductor substrate 25. Therefore, even if an abnormality occurs in either the collector-side termination trench structure or the collector-side passivation film 32, an increase in the leakage current of the collector-side gate can be suppressed.

[0049] <Embodiment 6> Figure 13 is a cross-sectional view showing the configuration of a semiconductor device according to this embodiment 6. In this embodiment 6, similar to embodiment 5, a collector-side passivation film 32, which is a passivation film, is provided on the back side of the semiconductor substrate 25. However, in this embodiment 6, the collector-side passivation film 32 is provided on the collector electrode 16 side of the collector-side gate pad 24.

[0050] With this configuration, the collector-side passivation film 32 can prevent the solder between the collector-side gate pad 24 and the collector-side gate lead frame from reaching the collector electrode 16. Therefore, it is possible to prevent the formation of a current path (a path from the collector-side gate lead frame to the collector electrode 16 via solder) that is different from the current path described in Embodiment 1, which increases the leakage current of the collector-side gate.

[0051] <Embodiment 7> Figure 14 is a plan view showing the configuration of the back side of the semiconductor device according to this embodiment 7. In this embodiment 7, in a plan view, the trench corner portion 26a of the collector-side termination trench structure (collector-side termination insulating film 30 and collector-side termination electrode 31), which corresponds to the corner portion of the semiconductor substrate 25, is rounded. With this configuration, the load applied to the trench corner portion 26a of the collector-side termination trench structure during dicing can be reduced, thereby suppressing damage to the trench corner portion 26a due to dicing.

[0052] <Embodiment 8> Figure 15 is a plan view showing the configuration of the back side of the semiconductor device according to this embodiment 8. In this embodiment 8, in a plan view, the width of the trench corner portion 26a of the collector-side termination trench structure, which corresponds to the corner portion of the semiconductor substrate 25, is wider than the width of the straight portion 26b connected to the trench corner portion 26a of the collector-side termination trench structure. With this configuration, the load applied to the trench corner portion 26a of the collector-side termination trench structure during dicing can be reduced, thereby suppressing damage to the trench corner portion 26a due to dicing.

[0053] <Embodiment 9> Figure 16 is a plan view showing the configuration of the back side of the semiconductor device according to this embodiment 9. In this embodiment 9, in a plan view, the distance D1 between the collector-side gate pad 24 and the collector electrode 16 is greater than the distance D2 between the collector-side gate pad 24 and the side surface of the semiconductor substrate 25.

[0054] With this configuration, in a plan view, the collector-side gate pad 24 is located near the side surface of the semiconductor substrate 25, but the collector-side termination trench structure can suppress an increase in leakage current of the collector-side gate. On the other hand, since the collector-side gate pad 24 is separated from the collector electrode 16, the solder between the collector-side gate pad 24 and the collector-side gate lead frame is prevented from reaching the collector electrode 16. Therefore, it is possible to suppress the formation of a current path that increases the leakage current of the collector-side gate (a path from the collector-side gate lead frame, through the solder, to the collector electrode 16).

[0055] <Embodiment 10> Figure 17 is a cross-sectional view showing the configuration of a semiconductor device according to this embodiment 10. In this embodiment 10, a collector-side termination trench structure is not provided, and a part of the n-type buffer layer 6 functions as a collector-side gate leak suppression section. Specifically, in a cross-sectional view, the n-type buffer layer 6 penetrates the p-type collector layer 7 on the side of the semiconductor substrate 25 with respect to the connection portion 16a between the collector electrode 16 and the p-type collector layer 7. In Figure 17, as an example, the n-type buffer layer 6 is provided in place of the p-type collector layer 7 in almost the entire area on the side of the semiconductor substrate 25 with respect to the connection portion 16a.

[0056] With this configuration, the current path from the side of the semiconductor substrate 25 around the collector-side gate pad 24 to the collector electrode 16 passes through the n-type semiconductor and then the p-type semiconductor, thus including a portion that is reverse-biased at the pn junction. Therefore, even if the solder between the collector-side gate pad 24 and the collector-side gate lead frame wraps around to the side of the semiconductor substrate 25, the increase in leakage current at the collector-side gate can be suppressed.

[0057] <Embodiment 11> Figure 18 is a plan view showing the configuration of the back side of the semiconductor device according to this embodiment 11, and Figure 19 is a cross-sectional view showing the configuration of the semiconductor device according to this embodiment 11. In this embodiment 11, unlike the configurations of embodiments 1 and 10 in which the p-type collector layer 7 is penetrated, the p-type collector layer 7 is not penetrated, and the modified layer 33 is provided.

[0058] The modified layer 33 is provided on a portion of the surface of the collector-side gate pad 24 in a cross-sectional view, and has lower solder wettability than the rest of the surface. In this embodiment 11, the portion on which the modified layer 33 is provided includes the portion of the collector-side gate pad 24 that is on the side of the semiconductor substrate 25.

[0059] The modified layer 33 is at least one of the oxide layer on the surface of the collector-side gate pad 24 and the roughened layer on the surface of the collector-side gate pad 24. In this specification, for example, at least one of A, B, C, ..., and Z means any one of all combinations that can be obtained by selecting one or more from the groups A, B, C, ..., and Z.

[0060] Both the oxide layer and the roughened layer have lower solder wettability than the normal layer. When, for example, laser modification is used as the formation treatment for the modified layer 33, both oxidation and roughening occur, so the modified layer 33 formed by the laser modification treatment will include both the oxide layer and the roughened layer.

[0061] With the above configuration, the modified layer 33, which has low solder wettability, can suppress the solder of the collector-side gate pad 24 from flowing to the side surface of the semiconductor substrate 25, thereby suppressing an increase in leakage current of the collector-side gate.

[0062] <Embodiment 12> Figure 20 is a plan view showing the configuration of the back side of the semiconductor device according to this embodiment 12, and Figure 21 is a cross-sectional view showing the configuration of the semiconductor device according to this embodiment 12. In this embodiment 12, a modified layer 33 is provided, similar to embodiment 11. In this embodiment 12, the modified layer 33 is provided on a part of the surface of at least one of the collector-side gate pad 24 and the collector electrode 16 in a cross-sectional view.

[0063] In the examples shown in Figures 20 and 21, the modified layer 33 is provided on a portion of the surface of the collector-side gate pad 24 in cross-sectional view. This portion includes the portion of the collector-side gate pad 24 that is on the side of the semiconductor substrate 25 and the portion of the collector-side gate pad 24 that is on the collector electrode 16 side.

[0064] With this configuration, the modified layer 33 on the side of the semiconductor substrate 25 of the collector-side gate pad 24 prevents the solder of the collector-side gate pad 24 from flowing onto the side of the semiconductor substrate 25, thereby suppressing an increase in leakage current of the collector-side gate.

[0065] Furthermore, the modified layer 33 on the collector electrode 16 side of the collector-side gate pad 24 prevents the solder on the collector-side gate pad 24 from reaching the collector electrode 16. This prevents the formation of a current path that increases the leakage current of the collector-side gate.

[0066] Furthermore, in the examples shown in Figures 20 and 21, the modified layer 33 is provided on a portion of the surface of the collector electrode 16 in cross-sectional view. This portion includes at least a portion of the outer periphery of the collector electrode 16 in plan view.

[0067] With this configuration, the modified layer 33 provided on at least a portion of the outer periphery of the collector electrode 16 prevents the solder of the collector electrode 16 from flowing around to the side of the semiconductor substrate 25 or reaching the collector-side gate pad 24. Therefore, an increase in leakage current at the collector-side gate can be suppressed.

[0068] <Embodiment 13> Figure 22 is a plan view showing the front side configuration of the semiconductor device according to this embodiment 13, and Figure 23 is a cross-sectional view along line A and B in Figure 22. In this embodiment 13, a modified layer 33 is provided, similar to embodiment 11. In this embodiment 13, the modified layer 33 is provided on a part of the surface of at least one of the emitter-side gate pad 23 and the emitter electrode 12 in a cross-sectional view.

[0069] In the examples shown in Figures 22 and 23, the modified layer 33 is provided on a portion of the surface of the emitter-side gate pad 23 in cross-sectional view. This portion includes the portion of the emitter-side gate pad 23 that is on the side of the semiconductor substrate 25 and the portion of the emitter-side gate pad 23 that is on the side of the emitter electrode 12.

[0070] With this configuration, the modified layer 33 on the side of the semiconductor substrate 25 of the emitter-side gate pad 23 prevents the solder of the emitter-side gate pad 23 from flowing onto the side of the semiconductor substrate 25, thereby suppressing an increase in the leakage current of the emitter-side gate.

[0071] Furthermore, the modified layer 33 on the emitter electrode 12 side of the emitter gate pad 23 prevents the solder on the emitter gate pad 23 from reaching the emitter electrode 12. This prevents the formation of a current path that increases the leakage current of the emitter gate.

[0072] Furthermore, in the examples shown in Figures 22 and 23, the modified layer 33 is provided on a portion of the surface of the emitter electrode 12 in cross-sectional view. This portion includes at least a portion of the outer periphery of the emitter electrode 12 in plan view.

[0073] With this configuration, the modified layer 33 provided on at least a portion of the outer periphery of the emitter electrode 12 prevents the solder of the emitter electrode 12 from wrapping around to the side of the semiconductor substrate 25 or reaching the emitter-side gate pad 23. Therefore, an increase in the leakage current of the emitter-side gate can be suppressed.

[0074] In the configuration shown in Figure 23, a collector-side element trench structure (collector-side gate insulating film 13 and collector-side gate electrode 14) and a collector-side gate pad 24 were provided on the back side of the semiconductor substrate 25. However, the semiconductor device according to this embodiment 13 is not limited to the configuration shown in Figure 23, and as shown in the configuration of Figure 24, the collector-side element trench structure and the collector-side gate pad 24 may not be provided.

[0075] In this disclosure in English, 'a' and 'an' mean one or more. Therefore, 'a', 'an', 'one or more', and 'at least one' can be used interchangeably.

[0076] Furthermore, it is possible to freely combine each embodiment and each variation, and to modify or omit each embodiment and each variation as appropriate.

[0077] The various aspects of this disclosure are summarized below as an appendix.

[0078] (Note 1) A semiconductor substrate having a front surface and a back surface in which an element region and a termination region surrounding the element region are defined, The emitter electrode provided on the front side of the semiconductor substrate, An emitter-side element trench structure is provided on the front side of the element region of the semiconductor substrate and includes an emitter-side gate electrode that is insulated from the emitter electrode, An emitter-side gate pad is provided on the front side of the termination region of the semiconductor substrate, is insulated from the emitter electrode, and is electrically connected to the emitter-side gate electrode, A collector electrode provided on the back side of the semiconductor substrate, A collector-side element trench structure is provided on the back side of the element region of the semiconductor substrate and includes a collector-side gate electrode that is insulated from the collector electrode, A collector-side gate pad is provided on the back side of the terminal region of the semiconductor substrate, is insulated from the collector electrode, and is electrically connected to the collector-side gate electrode, A collector-side termination trench structure is provided on the back side of the termination region of the semiconductor substrate, and includes a collector-side termination electrode. Equipped with, The aforementioned semiconductor substrate is A first conductive drift layer, The first conductive buffer layer provided on the back side of the drift layer, A second conductive collector layer provided on the back side of the buffer layer and Includes, In a plan view, the side surface of the semiconductor substrate and the collector electrode surround the collector-side gate pad. In a cross-sectional view, the collector-side termination trench structure penetrates the collector layer on the side of the semiconductor substrate with respect to the connection portion between the collector electrode and the collector layer, in a semiconductor device.

[0079] (Note 2) The semiconductor device described in Appendix 1, In a cross-sectional view, the collector-side termination trench structure penetrates the collector layer on the side surface of the semiconductor substrate, and is a semiconductor device.

[0080] (Note 3) A semiconductor device as described in Appendix 1 or Appendix 2, A semiconductor device in which the depth of the collector-side termination trench structure is greater than the depth of the collector-side element trench structure.

[0081] (Note 4) A semiconductor device described in any one of the items 1 to 3 of the appendix, A semiconductor device in which the width of the collector-side termination trench structure is wider than the width of the collector-side element trench structure.

[0082] (Note 5) The semiconductor device described in Appendix 1, In a cross-sectional view, the collector-side termination trench structure penetrates the collector layer on the connection portion side of the semiconductor substrate, relating to the semiconductor semiconductor device.

[0083] (Note 6) A semiconductor device described in any one of the items 1 to 5 of the appendix, A semiconductor device further comprising a passivation film provided on the back side of the semiconductor substrate and on the side of the collector-side gate pad of the semiconductor substrate.

[0084] (Note 7) A semiconductor device described in any one of the items 1 to 5 of the appendix, A semiconductor device further comprising a passivation film provided on the back surface of the semiconductor substrate and on the collector electrode side of the collector-side gate pad.

[0085] (Note 8) The semiconductor device described in Appendix 2, A semiconductor device in which, in a plan view, the trench corner portion of the collector-side termination trench structure corresponding to the corner portion of the semiconductor substrate is rounded.

[0086] (Note 9) The semiconductor device described in Appendix 2, A semiconductor device in which, in a plan view, the width of the trench corner portion of the collector-side termination trench structure corresponding to the corner portion of the semiconductor substrate is wider than the width of the straight portion connected to the trench corner portion of the collector-side termination trench structure.

[0087] (Note 10) A semiconductor device described in any one of the items from Appendix 1 to Appendix 9, A semiconductor device wherein, in a plan view, the distance between the collector-side gate pad and the collector electrode is greater than the distance between the collector-side gate pad and the side surface of the semiconductor substrate.

[0088] (Note 11) A semiconductor substrate having a front surface and a back surface in which an element region and a termination region surrounding the element region are defined, The emitter electrode provided on the front side of the semiconductor substrate, An emitter-side element trench structure is provided on the front side of the element region of the semiconductor substrate and includes an emitter-side gate electrode that is insulated from the emitter electrode, An emitter-side gate pad is provided on the front side of the termination region of the semiconductor substrate, is insulated from the emitter electrode, and is electrically connected to the emitter-side gate electrode, A collector electrode provided on the back side of the semiconductor substrate, A collector-side element trench structure is provided on the back side of the element region of the semiconductor substrate and includes a collector-side gate electrode that is insulated from the collector electrode, A collector-side gate pad is provided on the back side of the terminal region of the semiconductor substrate, is insulated from the collector electrode, and is electrically connected to the collector-side gate electrode. Equipped with, The aforementioned semiconductor substrate is A first conductive drift layer, The first conductive buffer layer provided on the back side of the drift layer, A second conductive collector layer provided on the back side of the buffer layer and Includes, In a plan view, the side surface of the semiconductor substrate and the collector electrode surround the collector-side gate pad. In a cross-sectional view, the buffer layer penetrates the collector layer on the side of the semiconductor substrate relative to the connection portion between the collector electrode and the collector layer, in a semiconductor device.

[0089] (Note 12) A semiconductor substrate having a front surface and a back surface in which an element region and a termination region surrounding the element region are defined, The emitter electrode provided on the front side of the semiconductor substrate, An emitter-side element trench structure is provided on the front side of the element region of the semiconductor substrate and includes an emitter-side gate electrode that is insulated from the emitter electrode, An emitter-side gate pad is provided on the front side of the termination region of the semiconductor substrate, is insulated from the emitter electrode, and is electrically connected to the emitter-side gate electrode, A collector electrode provided on the back side of the semiconductor substrate, A collector-side element trench structure is provided on the back side of the element region of the semiconductor substrate and includes a collector-side gate electrode that is insulated from the collector electrode, A collector-side gate pad is provided on the back side of the terminal region of the semiconductor substrate, is insulated from the collector electrode, and is electrically connected to the collector-side gate electrode. Equipped with, The aforementioned semiconductor substrate is A first conductive drift layer, The first conductive buffer layer provided on the back side of the drift layer, A second conductive collector layer provided on the back side of the buffer layer and Includes, A semiconductor device further comprising a modified layer provided on a portion of the surface of at least one of the collector-side gate pad and the collector electrode in a cross-sectional view, the modified layer having lower solder wettability than the rest of the surface.

[0090] (Note 13) The semiconductor device described in Appendix 12, The portion of the semiconductor device on which the modified layer is provided includes the portion of the collector-side gate pad that is on the side surface of the semiconductor substrate.

[0091] (Note 14) A semiconductor device as described in Appendix 12 or Appendix 13, A semiconductor device in which the modified layer is provided in the part of the collector-side gate pad that is on the collector electrode side.

[0092] (Note 15) A semiconductor device described in any one of the appendices 12 to 14, A semiconductor device wherein the portion provided with the modified layer includes at least a portion of the outer periphery of the collector electrode in a plan view.

[0093] (Note 16) A semiconductor substrate having a front surface and a back surface in which an element region and a termination region surrounding the element region are defined, The emitter electrode provided on the front side of the semiconductor substrate, An emitter-side element trench structure is provided on the front side of the element region of the semiconductor substrate and includes an emitter-side gate electrode that is insulated from the emitter electrode, An emitter-side gate pad is provided on the front side of the termination region of the semiconductor substrate, is insulated from the emitter electrode, and is electrically connected to the emitter-side gate electrode. Equipped with, A semiconductor device further comprising a modified layer provided on a portion of the surface of at least one of the emitter-side gate pad and the emitter electrode in a cross-sectional view, the modified layer having lower solder wettability than the rest of the surface.

[0094] (Note 17) The semiconductor device described in Appendix 16, The portion of the semiconductor device on which the modified layer is provided includes the portion of the emitter-side gate pad that is on the side surface of the semiconductor substrate.

[0095] (Note 18) A semiconductor device as described in Appendix 16 or Appendix 17, The portion of the semiconductor device on which the modified layer is provided includes the portion of the emitter-side gate pad that is on the emitter electrode side.

[0096] (Note 19) A semiconductor device described in any one of the appendices 16 to 18, A semiconductor device in which the modified layer is provided in part includes at least a portion of the outer periphery of the emitter electrode in a plan view.

[0097] (Note 20) A semiconductor device described in any one of the appendices 12 to 19, A semiconductor device wherein the modified layer is at least one of the oxide layer on the surface and the roughened layer on the surface. [Explanation of Symbols]

[0098] 5 n-type drift layer, 6 n-type buffer layer, 7 p-type collector layer, 9 emitter-side gate insulating film, 10 emitter-side gate electrode, 12 emitter electrode, 13 collector-side gate insulating film, 14 collector-side gate electrode, 16 collector electrode, 16a connection portion, 23 emitter-side gate pad, 24 collector-side gate pad, 25 semiconductor substrate, 26a trench corner portion, 26b straight portion, 30 collector-side termination insulating film, 31 collector-side termination electrode, 32 collector-side passivation film, 33 modification layer, 61 device region, 62 termination region.

Claims

1. A semiconductor substrate having a front surface and a back surface in which an element region and a termination region surrounding the element region are defined, The emitter electrode provided on the front side of the semiconductor substrate, An emitter-side element trench structure is provided on the front side of the element region of the semiconductor substrate and includes an emitter-side gate electrode that is insulated from the emitter electrode, An emitter-side gate pad is provided on the front side of the termination region of the semiconductor substrate, is insulated from the emitter electrode, and is electrically connected to the emitter-side gate electrode, A collector electrode provided on the back side of the semiconductor substrate, A collector-side element trench structure is provided on the back side of the element region of the semiconductor substrate and includes a collector-side gate electrode that is insulated from the collector electrode, A collector-side gate pad is provided on the back side of the terminal region of the semiconductor substrate, is insulated from the collector electrode, and is electrically connected to the collector-side gate electrode, A collector-side termination trench structure is provided on the back side of the termination region of the semiconductor substrate, and includes a collector-side termination electrode. Equipped with, The aforementioned semiconductor substrate is A first conductive drift layer, The first conductive buffer layer provided on the back side of the drift layer, A second conductive collector layer provided on the back side of the buffer layer and Includes, In a plan view, the side surface of the semiconductor substrate and the collector electrode surround the collector-side gate pad. In a cross-sectional view, the collector-side termination trench structure penetrates the collector layer on the side of the semiconductor substrate with respect to the connection portion between the collector electrode and the collector layer, in a semiconductor device.

2. A semiconductor device according to claim 1, In a cross-sectional view, the collector-side termination trench structure penetrates the collector layer on the side surface of the semiconductor substrate, and is a semiconductor device.

3. A semiconductor device according to claim 1 or claim 2, A semiconductor device in which the depth of the collector-side termination trench structure is greater than the depth of the collector-side element trench structure.

4. A semiconductor device according to claim 1 or claim 2, A semiconductor device in which the width of the collector-side termination trench structure is wider than the width of the collector-side element trench structure.

5. A semiconductor device according to claim 1, In a cross-sectional view, the collector-side termination trench structure penetrates the collector layer on the connection portion side of the semiconductor substrate, relating to the semiconductor semiconductor device.

6. A semiconductor device according to claim 1 or claim 2, A semiconductor device further comprising a passivation film provided on the back side of the semiconductor substrate and on the side of the collector-side gate pad of the semiconductor substrate.

7. A semiconductor device according to claim 1 or claim 2, A semiconductor device further comprising a passivation film provided on the back surface of the semiconductor substrate and on the collector electrode side of the collector-side gate pad.

8. A semiconductor device according to claim 2, A semiconductor device in which, in a plan view, the trench corner portion of the collector-side termination trench structure corresponding to the corner portion of the semiconductor substrate is rounded.

9. A semiconductor device according to claim 2, A semiconductor device in which, in a plan view, the width of the trench corner portion of the collector-side termination trench structure corresponding to the corner portion of the semiconductor substrate is wider than the width of the straight portion connected to the trench corner portion of the collector-side termination trench structure.

10. A semiconductor device according to claim 1 or claim 2, A semiconductor device wherein, in a plan view, the distance between the collector-side gate pad and the collector electrode is greater than the distance between the collector-side gate pad and the side surface of the semiconductor substrate.

11. A semiconductor substrate having a front surface and a back surface in which an element region and a termination region surrounding the element region are defined, The emitter electrode provided on the front side of the semiconductor substrate, An emitter-side element trench structure is provided on the front side of the element region of the semiconductor substrate and includes an emitter-side gate electrode that is insulated from the emitter electrode, An emitter-side gate pad is provided on the front side of the termination region of the semiconductor substrate, is insulated from the emitter electrode, and is electrically connected to the emitter-side gate electrode, A collector electrode provided on the back side of the semiconductor substrate, A collector-side element trench structure is provided on the back side of the element region of the semiconductor substrate and includes a collector-side gate electrode that is insulated from the collector electrode, A collector-side gate pad is provided on the back side of the terminal region of the semiconductor substrate, is insulated from the collector electrode, and is electrically connected to the collector-side gate electrode. Equipped with, The aforementioned semiconductor substrate is A first conductive drift layer, The first conductive buffer layer provided on the back side of the drift layer, A second conductive collector layer provided on the back side of the buffer layer and Includes, In a plan view, the side surface of the semiconductor substrate and the collector electrode surround the collector-side gate pad. In a cross-sectional view, the buffer layer penetrates the collector layer on the side of the semiconductor substrate relative to the connection portion between the collector electrode and the collector layer, in a semiconductor device.

12. A semiconductor substrate having a front surface and a back surface in which an element region and a termination region surrounding the element region are defined, The emitter electrode provided on the front side of the semiconductor substrate, An emitter-side element trench structure is provided on the front side of the element region of the semiconductor substrate and includes an emitter-side gate electrode that is insulated from the emitter electrode, An emitter-side gate pad is provided on the front side of the termination region of the semiconductor substrate, is insulated from the emitter electrode, and is electrically connected to the emitter-side gate electrode, A collector electrode provided on the back side of the semiconductor substrate, A collector-side element trench structure is provided on the back side of the element region of the semiconductor substrate and includes a collector-side gate electrode that is insulated from the collector electrode, A collector-side gate pad is provided on the back side of the terminal region of the semiconductor substrate, is insulated from the collector electrode, and is electrically connected to the collector-side gate electrode. Equipped with, The aforementioned semiconductor substrate is A first conductive drift layer, The first conductive buffer layer provided on the back side of the drift layer, A second conductive collector layer provided on the back side of the buffer layer and Includes, A semiconductor device further comprising a modified layer provided on a portion of the surface of at least one of the collector-side gate pad and the collector electrode in a cross-sectional view, the modified layer having lower solder wettability than the rest of the surface.

13. A semiconductor device according to claim 12, The portion of the semiconductor device on which the modified layer is provided includes the portion of the collector-side gate pad that is on the side surface of the semiconductor substrate.

14. A semiconductor device according to claim 12, A semiconductor device in which the modified layer is provided in the part of the collector-side gate pad that is on the collector electrode side.

15. A semiconductor device according to claim 12, A semiconductor device wherein the portion provided with the modified layer includes at least a portion of the outer periphery of the collector electrode in a plan view.

16. A semiconductor substrate having a front surface and a back surface in which an element region and a termination region surrounding the element region are defined, The emitter electrode provided on the front side of the semiconductor substrate, An emitter-side element trench structure is provided on the front side of the element region of the semiconductor substrate and includes an emitter-side gate electrode that is insulated from the emitter electrode, An emitter-side gate pad is provided on the front side of the termination region of the semiconductor substrate, is insulated from the emitter electrode, and is electrically connected to the emitter-side gate electrode. Equipped with, A semiconductor device further comprising a modified layer provided on a portion of the surface of at least one of the emitter-side gate pad and the emitter electrode in a cross-sectional view, the modified layer having lower solder wettability than the rest of the surface.

17. A semiconductor device according to claim 16, The portion of the semiconductor device on which the modified layer is provided includes the portion of the emitter-side gate pad that is on the side surface of the semiconductor substrate.

18. A semiconductor device according to claim 16, The portion of the semiconductor device on which the modified layer is provided includes the portion of the emitter-side gate pad that is on the emitter electrode side.

19. A semiconductor device according to claim 16, A semiconductor device in which the modified layer is provided in part includes at least a portion of the outer periphery of the emitter electrode in a plan view.

20. A semiconductor device according to any one of claims 12 to 19, A semiconductor device wherein the modified layer is at least one of the oxide layer on the surface and the roughened layer on the surface.

Images